SystemZInstrInfo.td revision 7d0b89bedd5c8a53c71498663046b7e14bb96d6d 
1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Stack allocation
12//===----------------------------------------------------------------------===//
13
14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15                              [(callseq_start timm:$amt)]>;
16def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17                              [(callseq_end timm:$amt1, timm:$amt2)]>;
18
19let neverHasSideEffects = 1 in {
20  // Takes as input the value of the stack pointer after a dynamic allocation
21  // has been made.  Sets the output to the address of the dynamically-
22  // allocated area itself, skipping the outgoing arguments.
23  //
24  // This expands to an LA or LAY instruction.  We restrict the offset
25  // to the range of LA and keep the LAY range in reserve for when
26  // the size of the outgoing arguments is added.
27  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28                           [(set GR64:$dst, dynalloc12only:$src)]>;
29}
30
31//===----------------------------------------------------------------------===//
32// Control flow instructions
33//===----------------------------------------------------------------------===//
34
35// A return instruction (br %r14).
36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37  def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
38
39// Unconditional branches.  R1 is the condition-code mask (all 1s).
40let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41  let isIndirectBranch = 1 in
42    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43                    "br\t$R2", [(brind ADDR64:$R2)]>;
44
45  // An assembler extended mnemonic for BRC.
46  def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
47                 [(br bb:$I2)]>;
48
49  // An assembler extended mnemonic for BRCL.  (The extension is "G"
50  // rather than "L" because "JL" is "Jump if Less".)
51  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
52}
53
54// Conditional branches.  It's easier for LLVM to handle these branches
55// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56// the first operand.  It seems friendlier to use mnemonic forms like
57// JE and JLH when writing out the assembly though.
58let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59  let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60    def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61                                         brtarget16:$I2), "j$R1\t$I2",
62                     [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63    def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64                                           brtarget32:$I2), "jg$R1\t$I2", []>;
65  }
66  def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
67                      "brc\t$R1, $I2", []>;
68  def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
69                        "brcl\t$R1, $I2", []>;
70}
71
72// Fused compare-and-branch instructions.  As for normal branches,
73// we handle these instructions internally in their raw CRJ-like form,
74// but use assembly macros like CRJE when writing them out.
75//
76// These instructions do not use or clobber the condition codes.
77// We nevertheless pretend that they clobber CC, so that we can lower
78// them to separate comparisons and BRCLs if the branch ends up being
79// out of range.
80multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
81  let isBranch = 1, isTerminator = 1, Defs = [CC] in {
82    def RJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
83                                            brtarget16:$RI4),
84                       "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
85    def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
86                                            brtarget16:$RI4),
87                       "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
88    def IJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
89                                            brtarget16:$RI4),
90                       "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
91    def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
92                                            brtarget16:$RI4),
93                       "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
94    def LRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
95                                             brtarget16:$RI4),
96                        "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
97    def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
98                                             brtarget16:$RI4),
99                        "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
100    def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
101                                             brtarget16:$RI4),
102                        "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
103    def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
104                                             brtarget16:$RI4),
105                        "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
106  }
107}
108let isCodeGenOnly = 1 in
109  defm C : CompareBranches<cond4, "$M3", "">;
110defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
111
112// Define AsmParser mnemonics for each general condition-code mask
113// (integer or floating-point)
114multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
115  let R1 = ccmask in {
116    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
117                   "j"##name##"\t$I2", []>;
118    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
119                     "jg"##name##"\t$I2", []>;
120  }
121  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
122  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
123  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
124  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
125  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
126  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
127}
128defm AsmO   : CondExtendedMnemonic<1,  "o">;
129defm AsmH   : CondExtendedMnemonic<2,  "h">;
130defm AsmNLE : CondExtendedMnemonic<3,  "nle">;
131defm AsmL   : CondExtendedMnemonic<4,  "l">;
132defm AsmNHE : CondExtendedMnemonic<5,  "nhe">;
133defm AsmLH  : CondExtendedMnemonic<6,  "lh">;
134defm AsmNE  : CondExtendedMnemonic<7,  "ne">;
135defm AsmE   : CondExtendedMnemonic<8,  "e">;
136defm AsmNLH : CondExtendedMnemonic<9,  "nlh">;
137defm AsmHE  : CondExtendedMnemonic<10, "he">;
138defm AsmNL  : CondExtendedMnemonic<11, "nl">;
139defm AsmLE  : CondExtendedMnemonic<12, "le">;
140defm AsmNH  : CondExtendedMnemonic<13, "nh">;
141defm AsmNO  : CondExtendedMnemonic<14, "no">;
142
143// Define AsmParser mnemonics for each integer condition-code mask.
144// This is like the list above, except that condition 3 is not possible
145// and that the low bit of the mask is therefore always 0.  This means
146// that each condition has two names.  Conditions "o" and "no" are not used.
147//
148// We don't make one of the two names an alias of the other because
149// we need the custom parsing routines to select the correct register class.
150multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
151  let M3 = ccmask in {
152    def CR  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
153                                            brtarget16:$RI4),
154                       "crj"##name##"\t$R1, $R2, $RI4", []>;
155    def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
156                                            brtarget16:$RI4),
157                       "cgrj"##name##"\t$R1, $R2, $RI4", []>;
158    def CI  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
159                                            brtarget16:$RI4),
160                       "cij"##name##"\t$R1, $I2, $RI4", []>;
161    def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
162                                            brtarget16:$RI4),
163                       "cgij"##name##"\t$R1, $I2, $RI4", []>;
164    def CLR  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
165                                            brtarget16:$RI4),
166                        "clrj"##name##"\t$R1, $R2, $RI4", []>;
167    def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
168                                             brtarget16:$RI4),
169                        "clgrj"##name##"\t$R1, $R2, $RI4", []>;
170    def CLI  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
171                                             brtarget16:$RI4),
172                        "clij"##name##"\t$R1, $I2, $RI4", []>;
173    def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
174                                             brtarget16:$RI4),
175                        "clgij"##name##"\t$R1, $I2, $RI4", []>;
176  }
177}
178multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
179  : IntCondExtendedMnemonicA<ccmask, name1> {
180  let isAsmParserOnly = 1 in
181    defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
182}
183defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
184defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
185defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;
186defm AsmJE   : IntCondExtendedMnemonic<8,  "e",  "nlh">;
187defm AsmJHE  : IntCondExtendedMnemonic<10, "he", "nl">;
188defm AsmJLE  : IntCondExtendedMnemonic<12, "le", "nh">;
189
190// Decrement a register and branch if it is nonzero.  These don't clobber CC,
191// but we might need to split long branches into sequences that do.
192let Defs = [CC] in {
193  def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
194  def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
195}
196
197//===----------------------------------------------------------------------===//
198// Select instructions
199//===----------------------------------------------------------------------===//
200
201def Select32 : SelectWrapper<GR32>;
202def Select64 : SelectWrapper<GR64>;
203
204defm CondStore8  : CondStores<GR32, nonvolatile_truncstorei8,
205                              nonvolatile_anyextloadi8, bdxaddr20only>;
206defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
207                              nonvolatile_anyextloadi16, bdxaddr20only>;
208defm CondStore32 : CondStores<GR32, nonvolatile_store,
209                              nonvolatile_load, bdxaddr20only>;
210
211defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
212                    nonvolatile_anyextloadi8, bdxaddr20only>;
213defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
214                    nonvolatile_anyextloadi16, bdxaddr20only>;
215defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
216                    nonvolatile_anyextloadi32, bdxaddr20only>;
217defm CondStore64 : CondStores<GR64, nonvolatile_store,
218                              nonvolatile_load, bdxaddr20only>;
219
220//===----------------------------------------------------------------------===//
221// Call instructions
222//===----------------------------------------------------------------------===//
223
224// The definitions here are for the call-clobbered registers.
225let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
226                        F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC] in {
227  def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
228                        [(z_call pcrel32:$I2)]>;
229  def CallBASR  : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
230                        [(z_call ADDR64:$R2)]>;
231}
232
233// Sibling calls.  Indirect sibling calls must be via R1, since R2 upwards
234// are argument registers and since branching to R0 is a no-op.
235let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
236  def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
237                     [(z_sibcall pcrel32:$I2)]>;
238  let Uses = [R1D] in
239    def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
240}
241
242// Define the general form of the call instructions for the asm parser.
243// These instructions don't hard-code %r14 as the return address register.
244def BRAS  : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
245                   "bras\t$R1, $I2", []>;
246def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
247                    "brasl\t$R1, $I2", []>;
248def BASR  : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
249                   "basr\t$R1, $R2", []>;
250
251//===----------------------------------------------------------------------===//
252// Move instructions
253//===----------------------------------------------------------------------===//
254
255// Register moves.
256let neverHasSideEffects = 1 in {
257  def LR  : UnaryRR <"l",  0x18,   null_frag, GR32, GR32>;
258  def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
259}
260let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
261  def LTR  : UnaryRR <"lt",  0x12,   null_frag, GR32, GR32>;
262  def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
263}
264
265// Move on condition.
266let isCodeGenOnly = 1, Uses = [CC] in {
267  def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
268  def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
269}
270let Uses = [CC] in {
271  def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
272  def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
273}
274
275// Immediate moves.
276let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
277    isReMaterializable = 1 in {
278  // 16-bit sign-extended immediates.
279  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
280  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
281
282  // Other 16-bit immediates.
283  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
284  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
285  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
286  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
287
288  // 32-bit immediates.
289  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
290  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
291  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
292}
293
294// Register loads.
295let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
296  defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
297  def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
298            Requires<[FeatureHighWord]>;
299  def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
300
301  // These instructions are split after register allocation, so we don't
302  // want a custom inserter.
303  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
304    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
305                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
306  }
307}
308let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
309  def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
310  def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
311}
312
313let canFoldAsLoad = 1 in {
314  def LRL  : UnaryRILPC<"lrl",  0xC4D, aligned_load, GR32>;
315  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
316}
317
318// Load on condition.
319let isCodeGenOnly = 1, Uses = [CC] in {
320  def LOC  : CondUnaryRSY<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
321  def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
322}
323let Uses = [CC] in {
324  def AsmLOC  : AsmCondUnaryRSY<"loc",  0xEBF2, GR32, 4>;
325  def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
326}
327
328// Register stores.
329let SimpleBDXStore = 1 in {
330  defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
331  def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
332             Requires<[FeatureHighWord]>;
333  def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
334
335  // These instructions are split after register allocation, so we don't
336  // want a custom inserter.
337  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
338    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
339                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
340  }
341}
342def STRL  : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
343def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
344
345// Store on condition.
346let isCodeGenOnly = 1, Uses = [CC] in {
347  def STOC  : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
348  def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
349}
350let Uses = [CC] in {
351  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
352  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
353}
354
355// 8-bit immediate stores to 8-bit fields.
356defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
357
358// 16-bit immediate stores to 16-, 32- or 64-bit fields.
359def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
360def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
361def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;
362
363// Memory-to-memory moves.
364let mayLoad = 1, mayStore = 1 in
365  defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
366
367// String moves.
368let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
369  defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
370
371//===----------------------------------------------------------------------===//
372// Sign extensions
373//===----------------------------------------------------------------------===//
374//
375// Note that putting these before zero extensions mean that we will prefer
376// them for anyextload*.  There's not really much to choose between the two
377// either way, but signed-extending loads have a short LH and a long LHY,
378// while zero-extending loads have only the long LLH.
379//
380//===----------------------------------------------------------------------===//
381
382// 32-bit extensions from registers.
383let neverHasSideEffects = 1 in {
384  def LBR : UnaryRRE<"lb", 0xB926, sext8,  GR32, GR32>;
385  def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
386}
387
388// 64-bit extensions from registers.
389let neverHasSideEffects = 1 in {
390  def LGBR : UnaryRRE<"lgb", 0xB906, sext8,  GR64, GR64>;
391  def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
392  def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
393}
394let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
395  def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
396
397// Match 32-to-64-bit sign extensions in which the source is already
398// in a 64-bit register.
399def : Pat<(sext_inreg GR64:$src, i32),
400          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
401
402// 32-bit extensions from memory.
403def  LB   : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
404defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
405def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
406
407// 64-bit extensions from memory.
408def LGB   : UnaryRXY<"lgb", 0xE377, asextloadi8,  GR64, 1>;
409def LGH   : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
410def LGF   : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
411def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
412def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
413let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
414  def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
415
416//===----------------------------------------------------------------------===//
417// Zero extensions
418//===----------------------------------------------------------------------===//
419
420// 32-bit extensions from registers.
421let neverHasSideEffects = 1 in {
422  def LLCR : UnaryRRE<"llc", 0xB994, zext8,  GR32, GR32>;
423  def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
424}
425
426// 64-bit extensions from registers.
427let neverHasSideEffects = 1 in {
428  def LLGCR : UnaryRRE<"llgc", 0xB984, zext8,  GR64, GR64>;
429  def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
430  def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
431}
432
433// Match 32-to-64-bit zero extensions in which the source is already
434// in a 64-bit register.
435def : Pat<(and GR64:$src, 0xffffffff),
436          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
437
438// 32-bit extensions from memory.
439def LLC   : UnaryRXY<"llc", 0xE394, azextloadi8,  GR32, 1>;
440def LLH   : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
441def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
442
443// 64-bit extensions from memory.
444def LLGC   : UnaryRXY<"llgc", 0xE390, azextloadi8,  GR64, 1>;
445def LLGH   : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
446def LLGF   : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
447def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
448def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
449
450//===----------------------------------------------------------------------===//
451// Truncations
452//===----------------------------------------------------------------------===//
453
454// Truncations of 64-bit registers to 32-bit registers.
455def : Pat<(i32 (trunc GR64:$src)),
456          (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
457
458// Truncations of 32-bit registers to memory.
459defm STC   : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8,  GR32, 1>;
460defm STH   : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
461def  STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
462
463// Truncations of 64-bit registers to memory.
464defm : StoreGR64Pair<STC, STCY, truncstorei8>;
465defm : StoreGR64Pair<STH, STHY, truncstorei16>;
466def  : StoreGR64PC<STHRL, aligned_truncstorei16>;
467defm : StoreGR64Pair<ST, STY, truncstorei32>;
468def  : StoreGR64PC<STRL, aligned_truncstorei32>;
469
470//===----------------------------------------------------------------------===//
471// Multi-register moves
472//===----------------------------------------------------------------------===//
473
474// Multi-register loads.
475def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
476
477// Multi-register stores.
478def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
479
480//===----------------------------------------------------------------------===//
481// Byte swaps
482//===----------------------------------------------------------------------===//
483
484// Byte-swapping register moves.
485let neverHasSideEffects = 1 in {
486  def LRVR  : UnaryRRE<"lrv",  0xB91F, bswap, GR32, GR32>;
487  def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
488}
489
490// Byte-swapping loads.  Unlike normal loads, these instructions are
491// allowed to access storage more than once.
492def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
493def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
494
495// Likewise byte-swapping stores.
496def STRV  : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
497def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
498                     GR64, 8>;
499
500//===----------------------------------------------------------------------===//
501// Load address instructions
502//===----------------------------------------------------------------------===//
503
504// Load BDX-style addresses.
505let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
506    DispKey = "la" in {
507  let DispSize = "12" in
508    def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
509                    "la\t$R1, $XBD2",
510                    [(set GR64:$R1, laaddr12pair:$XBD2)]>;
511  let DispSize = "20" in
512    def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
513                      "lay\t$R1, $XBD2",
514                      [(set GR64:$R1, laaddr20pair:$XBD2)]>;
515}
516
517// Load a PC-relative address.  There's no version of this instruction
518// with a 16-bit offset, so there's no relaxation.
519let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
520    isReMaterializable = 1 in {
521  def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
522                     "larl\t$R1, $I2",
523                     [(set GR64:$R1, pcrel32:$I2)]>;
524}
525
526//===----------------------------------------------------------------------===//
527// Absolute and Negation
528//===----------------------------------------------------------------------===//
529
530let Defs = [CC] in {
531  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
532    def LPR  : UnaryRR <"lp",  0x10,   z_iabs32, GR32, GR32>;
533    def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs64, GR64, GR64>;
534  }
535  let CCValues = 0xE, CompareZeroCCMask = 0xE in
536    def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
537}
538defm : SXU<z_iabs64, LPGFR>;
539
540let Defs = [CC] in {
541  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
542    def LNR  : UnaryRR <"ln",  0x11,   z_inegabs32, GR32, GR32>;
543    def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs64, GR64, GR64>;
544  }
545  let CCValues = 0xE, CompareZeroCCMask = 0xE in
546    def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
547}
548defm : SXU<z_inegabs64, LNGFR>;
549
550let Defs = [CC] in {
551  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
552    def LCR  : UnaryRR <"lc",  0x13,   ineg, GR32, GR32>;
553    def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
554  }
555  let CCValues = 0xE, CompareZeroCCMask = 0xE in
556    def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
557}
558defm : SXU<ineg, LCGFR>;
559
560//===----------------------------------------------------------------------===//
561// Insertion
562//===----------------------------------------------------------------------===//
563
564let isCodeGenOnly = 1 in
565  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
566defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
567
568defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
569defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
570
571defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
572defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
573
574// Insertions of a 16-bit immediate, leaving other bits unaffected.
575// We don't have or_as_insert equivalents of these operations because
576// OI is available instead.
577def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
578def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
579def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
580def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
581def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
582def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
583
584// ...likewise for 32-bit immediates.  For GR32s this is a general
585// full-width move.  (We use IILF rather than something like LLILF
586// for 32-bit moves because IILF leaves the upper 32 bits of the
587// GR64 unchanged.)
588let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in
589  def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
590def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
591def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
592
593// An alternative model of inserthf, with the first operand being
594// a zero-extended value.
595def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
596          (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
597                imm64hf32:$imm)>;
598
599//===----------------------------------------------------------------------===//
600// Addition
601//===----------------------------------------------------------------------===//
602
603// Plain addition.
604let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
605  // Addition of a register.
606  let isCommutable = 1 in {
607    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
608    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
609  }
610  def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
611
612  // Addition of signed 16-bit immediates.
613  defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
614  defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
615
616  // Addition of signed 32-bit immediates.
617  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
618  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
619
620  // Addition of memory.
621  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
622  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
623  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
624  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
625
626  // Addition to memory.
627  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
628  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
629}
630defm : SXB<add, GR64, AGFR>;
631
632// Addition producing a carry.
633let Defs = [CC] in {
634  // Addition of a register.
635  let isCommutable = 1 in {
636    defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
637    defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
638  }
639  def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
640
641  // Addition of signed 16-bit immediates.
642  def ALHSIK  : BinaryRIE<"alhsik",  0xECDA, addc, GR32, imm32sx16>,
643                Requires<[FeatureDistinctOps]>;
644  def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
645                Requires<[FeatureDistinctOps]>;
646
647  // Addition of unsigned 32-bit immediates.
648  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
649  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
650
651  // Addition of memory.
652  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
653  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
654  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load, 8>;
655}
656defm : ZXB<addc, GR64, ALGFR>;
657
658// Addition producing and using a carry.
659let Defs = [CC], Uses = [CC] in {
660  // Addition of a register.
661  def ALCR  : BinaryRRE<"alc",  0xB998, adde, GR32, GR32>;
662  def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
663
664  // Addition of memory.
665  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load, 4>;
666  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
667}
668
669//===----------------------------------------------------------------------===//
670// Subtraction
671//===----------------------------------------------------------------------===//
672
673// Plain substraction.  Although immediate forms exist, we use the
674// add-immediate instruction instead.
675let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
676  // Subtraction of a register.
677  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
678  def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
679  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
680
681  // Subtraction of memory.
682  defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
683  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
684  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
685  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load, 8>;
686}
687defm : SXB<sub, GR64, SGFR>;
688
689// Subtraction producing a carry.
690let Defs = [CC] in {
691  // Subtraction of a register.
692  defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
693  def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
694  defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
695
696  // Subtraction of unsigned 32-bit immediates.  These don't match
697  // subc because we prefer addc for constants.
698  def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
699  def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
700
701  // Subtraction of memory.
702  defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
703  def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
704  def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
705}
706defm : ZXB<subc, GR64, SLGFR>;
707
708// Subtraction producing and using a carry.
709let Defs = [CC], Uses = [CC] in {
710  // Subtraction of a register.
711  def SLBR  : BinaryRRE<"slb",  0xB999, sube, GR32, GR32>;
712  def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
713
714  // Subtraction of memory.
715  def SLB  : BinaryRXY<"slb",  0xE399, sube, GR32, load, 4>;
716  def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
717}
718
719//===----------------------------------------------------------------------===//
720// AND
721//===----------------------------------------------------------------------===//
722
723let Defs = [CC] in {
724  // ANDs of a register.
725  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
726    defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
727    defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
728  }
729
730  let isConvertibleToThreeAddress = 1 in {
731    // ANDs of a 16-bit immediate, leaving other bits unaffected.
732    // The CC result only reflects the 16-bit field, not the full register.
733    def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
734    def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
735    def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
736    def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
737    def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
738    def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
739
740    // ANDs of a 32-bit immediate, leaving other bits unaffected.
741    // The CC result only reflects the 32-bit field, which means we can
742    // use it as a zero indicator for i32 operations but not otherwise.
743    let CCValues = 0xC, CompareZeroCCMask = 0x8 in
744      def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
745    def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
746    def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
747  }
748
749  // ANDs of memory.
750  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
751    defm N  : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
752    def  NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 
753  }
754
755  // AND to memory
756  defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
757
758  // Block AND.
759  let mayLoad = 1, mayStore = 1 in
760    defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
761}
762defm : RMWIByte<and, bdaddr12pair, NI>;
763defm : RMWIByte<and, bdaddr20pair, NIY>;
764
765//===----------------------------------------------------------------------===//
766// OR
767//===----------------------------------------------------------------------===//
768
769let Defs = [CC] in {
770  // ORs of a register.
771  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
772    defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
773    defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
774  }
775
776  // ORs of a 16-bit immediate, leaving other bits unaffected.
777  // The CC result only reflects the 16-bit field, not the full register.
778  def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
779  def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
780  def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
781  def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
782  def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
783  def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
784
785  // ORs of a 32-bit immediate, leaving other bits unaffected.
786  // The CC result only reflects the 32-bit field, which means we can
787  // use it as a zero indicator for i32 operations but not otherwise.
788  let CCValues = 0xC, CompareZeroCCMask = 0x8 in
789    def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
790  def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
791  def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
792
793  // ORs of memory.
794  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
795    defm O  : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
796    def  OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
797  }
798
799  // OR to memory
800  defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
801
802  // Block OR.
803  let mayLoad = 1, mayStore = 1 in
804    defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
805}
806defm : RMWIByte<or, bdaddr12pair, OI>;
807defm : RMWIByte<or, bdaddr20pair, OIY>;
808
809//===----------------------------------------------------------------------===//
810// XOR
811//===----------------------------------------------------------------------===//
812
813let Defs = [CC] in {
814  // XORs of a register.
815  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
816    defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
817    defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
818  }
819
820  // XORs of a 32-bit immediate, leaving other bits unaffected.
821  // The CC result only reflects the 32-bit field, which means we can
822  // use it as a zero indicator for i32 operations but not otherwise.
823  let CCValues = 0xC, CompareZeroCCMask = 0x8 in
824    def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
825  def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
826  def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
827
828  // XORs of memory.
829  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
830    defm X  : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
831    def  XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
832  }
833
834  // XOR to memory
835  defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
836
837  // Block XOR.
838  let mayLoad = 1, mayStore = 1 in
839    defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
840}
841defm : RMWIByte<xor, bdaddr12pair, XI>;
842defm : RMWIByte<xor, bdaddr20pair, XIY>;
843
844//===----------------------------------------------------------------------===//
845// Multiplication
846//===----------------------------------------------------------------------===//
847
848// Multiplication of a register.
849let isCommutable = 1 in {
850  def MSR  : BinaryRRE<"ms",  0xB252, mul, GR32, GR32>;
851  def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
852}
853def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
854defm : SXB<mul, GR64, MSGFR>;
855
856// Multiplication of a signed 16-bit immediate.
857def MHI  : BinaryRI<"mhi",  0xA7C, mul, GR32, imm32sx16>;
858def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
859
860// Multiplication of a signed 32-bit immediate.
861def MSFI  : BinaryRIL<"msfi",  0xC21, mul, GR32, simm32>;
862def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
863
864// Multiplication of memory.
865defm MH   : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
866defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
867def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
868def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
869
870// Multiplication of a register, producing two results.
871def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
872
873// Multiplication of memory, producing two results.
874def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
875
876//===----------------------------------------------------------------------===//
877// Division and remainder
878//===----------------------------------------------------------------------===//
879
880// Division and remainder, from registers.
881def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
882def DSGR  : BinaryRRE<"dsg",  0xB90D, z_sdivrem64, GR128, GR64>;
883def DLR   : BinaryRRE<"dl",   0xB997, z_udivrem32, GR128, GR32>;
884def DLGR  : BinaryRRE<"dlg",  0xB987, z_udivrem64, GR128, GR64>;
885
886// Division and remainder, from memory.
887def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
888def DSG  : BinaryRXY<"dsg",  0xE30D, z_sdivrem64, GR128, load, 8>;
889def DL   : BinaryRXY<"dl",   0xE397, z_udivrem32, GR128, load, 4>;
890def DLG  : BinaryRXY<"dlg",  0xE387, z_udivrem64, GR128, load, 8>;
891
892//===----------------------------------------------------------------------===//
893// Shifts
894//===----------------------------------------------------------------------===//
895
896// Shift left.
897let neverHasSideEffects = 1 in {
898  defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
899  def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
900}
901
902// Logical shift right.
903let neverHasSideEffects = 1 in {
904  defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
905  def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
906}
907
908// Arithmetic shift right.
909let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
910  defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
911  def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
912}
913
914// Rotate left.
915let neverHasSideEffects = 1 in {
916  def RLL  : ShiftRSY<"rll",  0xEB1D, rotl, GR32>;
917  def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
918}
919
920// Rotate second operand left and inserted selected bits into first operand.
921// These can act like 32-bit operands provided that the constant start and
922// end bits (operands 2 and 3) are in the range [32, 64).
923let Defs = [CC] in {
924  let isCodeGenOnly = 1 in
925    def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
926  let CCValues = 0xE, CompareZeroCCMask = 0xE in
927    def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
928}
929
930// Forms of RISBG that only affect one word of the destination register.
931// They do not set CC.
932let isCodeGenOnly = 1 in
933  def RISBLG32 : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR32>,
934                 Requires<[FeatureHighWord]>;
935def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
936             Requires<[FeatureHighWord]>;
937def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
938             Requires<[FeatureHighWord]>;
939
940// Rotate second operand left and perform a logical operation with selected
941// bits of the first operand.  The CC result only describes the selected bits,
942// so isn't useful for a full comparison against zero.
943let Defs = [CC] in {
944  def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
945  def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
946  def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
947}
948
949//===----------------------------------------------------------------------===//
950// Comparison
951//===----------------------------------------------------------------------===//
952
953// Signed comparisons.  We put these before the unsigned comparisons because
954// some of the signed forms have COMPARE AND BRANCH equivalents whereas none
955// of the unsigned forms do.
956let Defs = [CC], CCValues = 0xE in {
957  // Comparison with a register.
958  def CR   : CompareRR <"c",   0x19,   z_scmp,    GR32, GR32>;
959  def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
960  def CGR  : CompareRRE<"cg",  0xB920, z_scmp,    GR64, GR64>;
961
962  // Comparison with a signed 16-bit immediate.
963  def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
964  def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
965
966  // Comparison with a signed 32-bit immediate.
967  def CFI  : CompareRIL<"cfi",  0xC2D, z_scmp, GR32, simm32>;
968  def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
969
970  // Comparison with memory.
971  defm CH    : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
972  defm C     : CompareRXPair<"c",  0x59, 0xE359, z_scmp, GR32, load, 4>;
973  def  CGH   : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
974  def  CGF   : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
975  def  CG    : CompareRXY<"cg",  0xE320, z_scmp, GR64, load, 8>;
976  def  CHRL  : CompareRILPC<"chrl",  0xC65, z_scmp, GR32, aligned_asextloadi16>;
977  def  CRL   : CompareRILPC<"crl",   0xC6D, z_scmp, GR32, aligned_load>;
978  def  CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
979  def  CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
980  def  CGRL  : CompareRILPC<"cgrl",  0xC68, z_scmp, GR64, aligned_load>;
981
982  // Comparison between memory and a signed 16-bit immediate.
983  def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
984  def CHSI  : CompareSIL<"chsi",  0xE55C, z_scmp, load, imm32sx16>;
985  def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
986}
987defm : SXB<z_scmp, GR64, CGFR>;
988
989// Unsigned comparisons.
990let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
991  // Comparison with a register.
992  def CLR   : CompareRR <"cl",   0x15,   z_ucmp,    GR32, GR32>;
993  def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
994  def CLGR  : CompareRRE<"clg",  0xB921, z_ucmp,    GR64, GR64>;
995
996  // Comparison with a signed 32-bit immediate.
997  def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
998  def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
999
1000  // Comparison with memory.
1001  defm CL     : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1002  def  CLGF   : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1003  def  CLG    : CompareRXY<"clg",  0xE321, z_ucmp, GR64, load, 8>;
1004  def  CLHRL  : CompareRILPC<"clhrl",  0xC67, z_ucmp, GR32,
1005                             aligned_azextloadi16>;
1006  def  CLRL   : CompareRILPC<"clrl",   0xC6F, z_ucmp, GR32,
1007                             aligned_load>;
1008  def  CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1009                             aligned_azextloadi16>;
1010  def  CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1011                             aligned_azextloadi32>;
1012  def  CLGRL  : CompareRILPC<"clgrl",  0xC6A, z_ucmp, GR64,
1013                             aligned_load>;
1014
1015  // Comparison between memory and an unsigned 8-bit immediate.
1016  defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1017
1018  // Comparison between memory and an unsigned 16-bit immediate.
1019  def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1020  def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1021  def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1022}
1023defm : ZXB<z_ucmp, GR64, CLGFR>;
1024
1025// Memory-to-memory comparison.
1026let mayLoad = 1, Defs = [CC] in
1027  defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1028
1029// String comparison.
1030let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1031  defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1032
1033// Test under mask.
1034let Defs = [CC] in {
1035  def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1036  def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1037
1038  def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>;
1039  def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>;
1040
1041  defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1042}
1043def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16>;
1044def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16>;
1045
1046//===----------------------------------------------------------------------===//
1047// Prefetch
1048//===----------------------------------------------------------------------===//
1049
1050def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1051def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1052
1053//===----------------------------------------------------------------------===//
1054// Atomic operations
1055//===----------------------------------------------------------------------===//
1056
1057def ATOMIC_SWAPW        : AtomicLoadWBinaryReg<z_atomic_swapw>;
1058def ATOMIC_SWAP_32      : AtomicLoadBinaryReg32<atomic_swap_32>;
1059def ATOMIC_SWAP_64      : AtomicLoadBinaryReg64<atomic_swap_64>;
1060
1061def ATOMIC_LOADW_AR     : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1062def ATOMIC_LOADW_AFI    : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1063def ATOMIC_LOAD_AR      : AtomicLoadBinaryReg32<atomic_load_add_32>;
1064def ATOMIC_LOAD_AHI     : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1065def ATOMIC_LOAD_AFI     : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1066def ATOMIC_LOAD_AGR     : AtomicLoadBinaryReg64<atomic_load_add_64>;
1067def ATOMIC_LOAD_AGHI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1068def ATOMIC_LOAD_AGFI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1069
1070def ATOMIC_LOADW_SR     : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1071def ATOMIC_LOAD_SR      : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1072def ATOMIC_LOAD_SGR     : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1073
1074def ATOMIC_LOADW_NR     : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1075def ATOMIC_LOADW_NILH   : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1076def ATOMIC_LOAD_NR      : AtomicLoadBinaryReg32<atomic_load_and_32>;
1077def ATOMIC_LOAD_NILL    : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
1078def ATOMIC_LOAD_NILH    : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
1079def ATOMIC_LOAD_NILF    : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1080def ATOMIC_LOAD_NGR     : AtomicLoadBinaryReg64<atomic_load_and_64>;
1081def ATOMIC_LOAD_NILL64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
1082def ATOMIC_LOAD_NILH64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
1083def ATOMIC_LOAD_NIHL    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
1084def ATOMIC_LOAD_NIHH    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
1085def ATOMIC_LOAD_NILF64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
1086def ATOMIC_LOAD_NIHF    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
1087
1088def ATOMIC_LOADW_OR     : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1089def ATOMIC_LOADW_OILH   : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1090def ATOMIC_LOAD_OR      : AtomicLoadBinaryReg32<atomic_load_or_32>;
1091def ATOMIC_LOAD_OILL    : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1092def ATOMIC_LOAD_OILH    : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1093def ATOMIC_LOAD_OILF    : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1094def ATOMIC_LOAD_OGR     : AtomicLoadBinaryReg64<atomic_load_or_64>;
1095def ATOMIC_LOAD_OILL64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1096def ATOMIC_LOAD_OILH64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1097def ATOMIC_LOAD_OIHL    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1098def ATOMIC_LOAD_OIHH    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1099def ATOMIC_LOAD_OILF64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1100def ATOMIC_LOAD_OIHF    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1101
1102def ATOMIC_LOADW_XR     : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1103def ATOMIC_LOADW_XILF   : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1104def ATOMIC_LOAD_XR      : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1105def ATOMIC_LOAD_XILF    : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1106def ATOMIC_LOAD_XGR     : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1107def ATOMIC_LOAD_XILF64  : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1108def ATOMIC_LOAD_XIHF    : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1109
1110def ATOMIC_LOADW_NRi    : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1111def ATOMIC_LOADW_NILHi  : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1112                                               imm32lh16c>;
1113def ATOMIC_LOAD_NRi     : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1114def ATOMIC_LOAD_NILLi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1115                                                imm32ll16c>;
1116def ATOMIC_LOAD_NILHi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1117                                                imm32lh16c>;
1118def ATOMIC_LOAD_NILFi   : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1119def ATOMIC_LOAD_NGRi    : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1120def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1121                                                imm64ll16c>;
1122def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1123                                                imm64lh16c>;
1124def ATOMIC_LOAD_NIHLi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1125                                                imm64hl16c>;
1126def ATOMIC_LOAD_NIHHi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1127                                                imm64hh16c>;
1128def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1129                                                imm64lf32c>;
1130def ATOMIC_LOAD_NIHFi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1131                                                imm64hf32c>;
1132
1133def ATOMIC_LOADW_MIN    : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1134def ATOMIC_LOAD_MIN_32  : AtomicLoadBinaryReg32<atomic_load_min_32>;
1135def ATOMIC_LOAD_MIN_64  : AtomicLoadBinaryReg64<atomic_load_min_64>;
1136
1137def ATOMIC_LOADW_MAX    : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1138def ATOMIC_LOAD_MAX_32  : AtomicLoadBinaryReg32<atomic_load_max_32>;
1139def ATOMIC_LOAD_MAX_64  : AtomicLoadBinaryReg64<atomic_load_max_64>;
1140
1141def ATOMIC_LOADW_UMIN   : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1142def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1143def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1144
1145def ATOMIC_LOADW_UMAX   : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1146def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1147def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1148
1149def ATOMIC_CMP_SWAPW
1150  : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1151                                  ADDR32:$bitshift, ADDR32:$negbitshift,
1152                                  uimm32:$bitsize),
1153           [(set GR32:$dst,
1154                 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1155                                     ADDR32:$bitshift, ADDR32:$negbitshift,
1156                                     uimm32:$bitsize))]> {
1157  let Defs = [CC];
1158  let mayLoad = 1;
1159  let mayStore = 1;
1160  let usesCustomInserter = 1;
1161}
1162
1163let Defs = [CC] in {
1164  defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1165  def  CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1166}
1167
1168//===----------------------------------------------------------------------===//
1169// Miscellaneous Instructions.
1170//===----------------------------------------------------------------------===//
1171
1172// Extract CC into bits 29 and 28 of a register.
1173let Uses = [CC] in
1174  def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1175
1176// Read a 32-bit access register into a GR32.  As with all GR32 operations,
1177// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1178// when a 64-bit address is stored in a pair of access registers.
1179def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1180                  "ear\t$R1, $R2",
1181                  [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1182
1183// Find leftmost one, AKA count leading zeros.  The instruction actually
1184// returns a pair of GR64s, the first giving the number of leading zeros
1185// and the second giving a copy of the source with the leftmost one bit
1186// cleared.  We only use the first result here.
1187let Defs = [CC] in {
1188  def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1189}
1190def : Pat<(ctlz GR64:$src),
1191          (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1192
1193// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1194def : Pat<(i64 (anyext GR32:$src)),
1195          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1196
1197// Extend GR32s and GR64s to GR128s.
1198let usesCustomInserter = 1 in {
1199  def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1200  def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1201  def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1202}
1203
1204// Search a block of memory for a character.
1205let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1206  defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1207
1208//===----------------------------------------------------------------------===//
1209// Peepholes.
1210//===----------------------------------------------------------------------===//
1211
1212// Use AL* for GR64 additions of unsigned 32-bit values.
1213defm : ZXB<add, GR64, ALGFR>;
1214def  : Pat<(add GR64:$src1, imm64zx32:$src2),
1215           (ALGFI GR64:$src1, imm64zx32:$src2)>;
1216def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1217           (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1218
1219// Use SL* for GR64 subtractions of unsigned 32-bit values.
1220defm : ZXB<sub, GR64, SLGFR>;
1221def  : Pat<(add GR64:$src1, imm64zx32n:$src2),
1222           (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1223def  : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1224           (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1225
1226// Optimize sign-extended 1/0 selects to -1/0 selects.  This is important
1227// for vector legalization.
1228def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1229                         (i32 31)),
1230                    (i32 31)),
1231          (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1232def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1233                                                       uimm8zx4:$cc)))),
1234                    (i32 63)),
1235               (i32 63)),
1236          (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1237
1238// Peepholes for turning scalar operations into block operations.
1239defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1240                      XCSequence, 1>;
1241defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1242                      XCSequence, 2>;
1243defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1244                      XCSequence, 4>;
1245defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1246                      OCSequence, XCSequence, 1>;
1247defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1248                      XCSequence, 2>;
1249defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1250                      XCSequence, 4>;
1251defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
1252                      XCSequence, 8>;
1253