SystemZInstrInfo.td revision 9342d3180a4150c3becfda6216bb8ecef2794f44 
1//===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source 
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the SystemZ instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14include "SystemZInstrFormats.td"
15
16//===----------------------------------------------------------------------===//
17// SystemZ Specific Node Definitions.
18//===----------------------------------------------------------------------===//
19def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
20                     [SDNPHasChain, SDNPOptInFlag]>;
21
22let neverHasSideEffects = 1 in
23def NOP : Pseudo<(outs), (ins), "# no-op", []>;
24
25//===----------------------------------------------------------------------===//
26// Instruction Pattern Stuff.
27//===----------------------------------------------------------------------===//
28def LL16 : SDNodeXForm<imm, [{
29  // Transformation function: return low 16 bits.
30  return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
31}]>;
32
33def LH16 : SDNodeXForm<imm, [{
34  // Transformation function: return bits 16-31.
35  return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
36}]>;
37
38def HL16 : SDNodeXForm<imm, [{
39  // Transformation function: return bits 32-47.
40  return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
41}]>;
42
43def HH16 : SDNodeXForm<imm, [{
44  // Transformation function: return bits 48-63.
45  return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
46}]>;
47
48def LO32 : SDNodeXForm<imm, [{
49  // Transformation function: return low 32 bits.
50  return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
51}]>;
52
53def HI32 : SDNodeXForm<imm, [{
54  // Transformation function: return bits 32-63.
55  return getI32Imm(N->getZExtValue() >> 32);
56}]>;
57
58def i64ll16 : PatLeaf<(i64 imm), [{  
59  // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
60  // bits set.
61  return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
62}], LL16>;
63
64def i64lh16 : PatLeaf<(i64 imm), [{  
65  // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
66  return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
67}], LH16>;
68
69def i64hl16 : PatLeaf<(i64 imm), [{  
70  // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
71  return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
72}], HL16>;
73
74def i64hh16 : PatLeaf<(i64 imm), [{  
75  // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
76  return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
77}], HH16>;
78
79def immSExt16 : PatLeaf<(i64 imm), [{
80  // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
81  // field.
82  uint64_t val = N->getZExtValue();
83  return ((int64_t)val == (int16_t)val);
84}]>;
85
86def immSExt32 : PatLeaf<(i64 imm), [{
87  // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
88  // field.
89  uint64_t val = N->getZExtValue();
90  return ((int64_t)val == (int32_t)val);
91}]>;
92
93def i64lo32 : PatLeaf<(i64 imm), [{
94  // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
95  // bits set.
96  return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
97}], LO32>;
98
99def i64hi32 : PatLeaf<(i64 imm), [{
100  // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
101  return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
102}], HI32>;
103
104//===----------------------------------------------------------------------===//
105//  Control Flow Instructions...
106//
107
108// FIXME: Provide proper encoding!
109let isReturn = 1, isTerminator = 1 in {
110  def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
111}
112
113//===----------------------------------------------------------------------===//
114// Move Instructions
115
116// FIXME: Provide proper encoding!
117let neverHasSideEffects = 1 in {
118def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
119                     "lgr\t{$dst, $src}",
120                     []>;
121}
122
123// FIXME: Provide proper encoding!
124let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
125def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
126                       "lghi\t{$dst, $src}",
127                       [(set GR64:$dst, immSExt16:$src)]>;
128
129def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
130                         "llill\t{$dst, $src}",
131                         [(set GR64:$dst, i64ll16:$src)]>;
132def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
133                         "llilh\t{$dst, $src}",
134                         [(set GR64:$dst, i64lh16:$src)]>;
135def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
136                         "llihl\t{$dst, $src}",
137                         [(set GR64:$dst, i64hl16:$src)]>;
138def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
139                         "llihh\t{$dst, $src}",
140                         [(set GR64:$dst, i64hh16:$src)]>;
141// FIXME: these 3 instructions seem to require extimm facility
142def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
143                       "lgfi\t{$dst, $src}",
144                       [(set GR64:$dst, immSExt32:$src)]>;
145def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
146                         "llilf\t{$dst, $src}",
147                         [(set GR64:$dst, i64lo32:$src)]>;
148def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
149                         "llihf\t{$dst, $src}",
150                         [(set GR64:$dst, i64hi32:$src)]>;
151}
152
153//===----------------------------------------------------------------------===//
154// Arithmetic Instructions
155
156let isTwoAddress = 1 in {
157
158let Defs = [PSW] in {
159
160let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
161// FIXME: Provide proper encoding!
162def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
163                     "agr\t{$dst, $src2}",
164                     [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
165                      (implicit PSW)]>;
166}
167
168// FIXME: Provide proper encoding!
169def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
170                       "aghi\t{$dst, $src2}",
171                       [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
172                        (implicit PSW)]>;
173def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
174                       "agfi\t{$dst, $src2}",
175                       [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
176                        (implicit PSW)]>;
177
178let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
179// FIXME: Provide proper encoding!
180def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
181                     "ngr\t{$dst, $src2}",
182                     [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
183}
184
185// FIXME: Provide proper encoding!
186def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
187                         "nill\t{$dst, $src2}",
188                         [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
189def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
190                         "nilh\t{$dst, $src2}",
191                         [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
192def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
193                         "nihl\t{$dst, $src2}",
194                         [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
195def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
196                         "nihh\t{$dst, $src2}",
197                         [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
198// FIXME: these 2 instructions seem to require extimm facility
199def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
200                         "nilf\t{$dst, $src2}",
201                         [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>;
202def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
203                         "nihf\t{$dst, $src2}",
204                         [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>;
205
206let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
207// FIXME: Provide proper encoding!
208def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
209                    "ogr\t{$dst, $src2}",
210                    [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
211}
212
213def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
214                        "oill\t{$dst, $src2}",
215                        [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
216def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
217                        "oilh\t{$dst, $src2}",
218                        [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
219def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
220                        "oihl\t{$dst, $src2}",
221                        [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
222def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
223                        "oihh\t{$dst, $src2}",
224                        [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
225// FIXME: these 2 instructions seem to require extimm facility
226def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
227                        "oilf\t{$dst, $src2}",
228                        [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
229def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
230                        "oihf\t{$dst, $src2}",
231                        [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
232
233// FIXME: Provide proper encoding!
234def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
235                     "sgr\t{$dst, $src2}",
236                     [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
237
238
239let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
240// FIXME: Provide proper encoding!
241def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
242                     "xgr\t{$dst, $src2}",
243                     [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
244}
245
246// FIXME: these 2 instructions seem to require extimm facility
247def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
248                         "xilf\t{$dst, $src2}",
249                         [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>;
250def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
251                         "xihf\t{$dst, $src2}",
252                         [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>;
253
254} // Defs = [PSW]
255} // isTwoAddress = 1
256