SystemZInstrInfo.td revision 9e155d61da39b30bd11956f4f6ee55b8d4db65cd
1//===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SystemZ instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// SystemZ Instruction Predicate Definitions. 16def IsZ10 : Predicate<"Subtarget.isZ10()">; 17 18include "SystemZInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Type Constraints. 22//===----------------------------------------------------------------------===// 23class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; 24class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; 25class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>; 26class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>; 27 28//===----------------------------------------------------------------------===// 29// Type Profiles. 30//===----------------------------------------------------------------------===// 31def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 32def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>; 33def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>; 34def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 35def SDT_BrCond : SDTypeProfile<0, 2, 36 [SDTCisVT<0, OtherVT>, 37 SDTCisI8<1>]>; 38def SDT_SelectCC : SDTypeProfile<1, 3, 39 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 40 SDTCisI8<3>]>; 41def SDT_Address : SDTypeProfile<1, 1, 42 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 43 44//===----------------------------------------------------------------------===// 45// SystemZ Specific Node Definitions. 46//===----------------------------------------------------------------------===// 47def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 48 [SDNPHasChain, SDNPOptInFlag]>; 49def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall, 50 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; 51def SystemZcallseq_start : 52 SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart, 53 [SDNPHasChain, SDNPOutFlag]>; 54def SystemZcallseq_end : 55 SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd, 56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 57def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>; 58def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>; 59def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond, 60 [SDNPHasChain, SDNPInFlag]>; 61def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>; 62def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>; 63 64 65include "SystemZOperands.td" 66 67//===----------------------------------------------------------------------===// 68// Instruction list.. 69 70def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 71 "#ADJCALLSTACKDOWN", 72 [(SystemZcallseq_start timm:$amt)]>; 73def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 74 "#ADJCALLSTACKUP", 75 [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>; 76 77let usesCustomDAGSchedInserter = 1 in { 78 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc), 79 "# Select32 PSEUDO", 80 [(set GR32:$dst, 81 (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>; 82 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc), 83 "# Select64 PSEUDO", 84 [(set GR64:$dst, 85 (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>; 86} 87 88 89//===----------------------------------------------------------------------===// 90// Control Flow Instructions... 91// 92 93// FIXME: Provide proper encoding! 94let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { 95 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>; 96} 97 98let isBranch = 1, isTerminator = 1 in { 99 let isBarrier = 1 in { 100 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>; 101 102 let isIndirectBranch = 1 in 103 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>; 104 } 105 106 let Uses = [PSW] in { 107 def JO : Pseudo<(outs), (ins brtarget:$dst), 108 "jo\t$dst", 109 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>; 110 def JH : Pseudo<(outs), (ins brtarget:$dst), 111 "jh\t$dst", 112 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>; 113 def JNLE: Pseudo<(outs), (ins brtarget:$dst), 114 "jnle\t$dst", 115 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>; 116 def JL : Pseudo<(outs), (ins brtarget:$dst), 117 "jl\t$dst", 118 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>; 119 def JNHE: Pseudo<(outs), (ins brtarget:$dst), 120 "jnhe\t$dst", 121 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>; 122 def JLH : Pseudo<(outs), (ins brtarget:$dst), 123 "jlh\t$dst", 124 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>; 125 def JNE : Pseudo<(outs), (ins brtarget:$dst), 126 "jne\t$dst", 127 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>; 128 def JE : Pseudo<(outs), (ins brtarget:$dst), 129 "je\t$dst", 130 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>; 131 def JNLH: Pseudo<(outs), (ins brtarget:$dst), 132 "jnlh\t$dst", 133 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>; 134 def JHE : Pseudo<(outs), (ins brtarget:$dst), 135 "jhe\t$dst", 136 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>; 137 def JNL : Pseudo<(outs), (ins brtarget:$dst), 138 "jnl\t$dst", 139 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>; 140 def JLE : Pseudo<(outs), (ins brtarget:$dst), 141 "jle\t$dst", 142 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>; 143 def JNH : Pseudo<(outs), (ins brtarget:$dst), 144 "jnh\t$dst", 145 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>; 146 def JNO : Pseudo<(outs), (ins brtarget:$dst), 147 "jno\t$dst", 148 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>; 149 } // Uses = [PSW] 150} // isBranch = 1 151 152//===----------------------------------------------------------------------===// 153// Call Instructions... 154// 155 156let isCall = 1 in 157 // All calls clobber the non-callee saved registers. Uses for argument 158 // registers are added manually. 159 let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D, 160 F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in { 161 def CALLi : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops), 162 "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>; 163 def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops), 164 "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>; 165 } 166 167//===----------------------------------------------------------------------===// 168// Miscellaneous Instructions. 169// 170 171let isReMaterializable = 1 in 172// FIXME: Provide imm12 variant 173// FIXME: Address should be halfword aligned... 174def LA64r : RXI<0x47, 175 (outs GR64:$dst), (ins laaddr:$src), 176 "lay\t{$dst, $src}", 177 [(set GR64:$dst, laaddr:$src)]>; 178def LA64rm : RXYI<0x71E3, 179 (outs GR64:$dst), (ins i64imm:$src), 180 "larl\t{$dst, $src}", 181 [(set GR64:$dst, 182 (SystemZpcrelwrapper tglobaladdr:$src))]>; 183 184let neverHasSideEffects = 1 in 185def NOP : Pseudo<(outs), (ins), "# no-op", []>; 186 187//===----------------------------------------------------------------------===// 188// Move Instructions 189 190let neverHasSideEffects = 1 in { 191def MOV32rr : RRI<0x18, 192 (outs GR32:$dst), (ins GR32:$src), 193 "lr\t{$dst, $src}", 194 []>; 195def MOV64rr : RREI<0xB904, 196 (outs GR64:$dst), (ins GR64:$src), 197 "lgr\t{$dst, $src}", 198 []>; 199def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src), 200 "# MOV128 PSEUDO!\n" 201 "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n" 202 "\tlgr\t${dst:subreg_even}, ${src:subreg_even}", 203 []>; 204def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src), 205 "# MOV64P PSEUDO!\n" 206 "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n" 207 "\tlr\t${dst:subreg_even}, ${src:subreg_even}", 208 []>; 209} 210 211def MOVSX64rr32 : RREI<0xB914, 212 (outs GR64:$dst), (ins GR32:$src), 213 "lgfr\t{$dst, $src}", 214 [(set GR64:$dst, (sext GR32:$src))]>; 215def MOVZX64rr32 : RREI<0xB916, 216 (outs GR64:$dst), (ins GR32:$src), 217 "llgfr\t{$dst, $src}", 218 [(set GR64:$dst, (zext GR32:$src))]>; 219 220let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 221def MOV32ri16 : RII<0x8A7, 222 (outs GR32:$dst), (ins s16imm:$src), 223 "lhi\t{$dst, $src}", 224 [(set GR32:$dst, immSExt16:$src)]>; 225def MOV64ri16 : RII<0x9A7, 226 (outs GR64:$dst), (ins s16imm64:$src), 227 "lghi\t{$dst, $src}", 228 [(set GR64:$dst, immSExt16:$src)]>; 229 230def MOV64rill16 : RII<0xFA5, 231 (outs GR64:$dst), (ins i64imm:$src), 232 "llill\t{$dst, $src}", 233 [(set GR64:$dst, i64ll16:$src)]>; 234def MOV64rilh16 : RII<0xEA5, 235 (outs GR64:$dst), (ins i64imm:$src), 236 "llilh\t{$dst, $src}", 237 [(set GR64:$dst, i64lh16:$src)]>; 238def MOV64rihl16 : RII<0xDA5, 239 (outs GR64:$dst), (ins i64imm:$src), 240 "llihl\t{$dst, $src}", 241 [(set GR64:$dst, i64hl16:$src)]>; 242def MOV64rihh16 : RII<0xCA5, 243 (outs GR64:$dst), (ins i64imm:$src), 244 "llihh\t{$dst, $src}", 245 [(set GR64:$dst, i64hh16:$src)]>; 246 247def MOV64ri32 : RILI<0x1C0, 248 (outs GR64:$dst), (ins s32imm64:$src), 249 "lgfi\t{$dst, $src}", 250 [(set GR64:$dst, immSExt32:$src)]>; 251def MOV64rilo32 : RILI<0xFC0, 252 (outs GR64:$dst), (ins i64imm:$src), 253 "llilf\t{$dst, $src}", 254 [(set GR64:$dst, i64lo32:$src)]>; 255def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins i64imm:$src), 256 "llihf\t{$dst, $src}", 257 [(set GR64:$dst, i64hi32:$src)]>; 258} 259 260let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { 261def MOV32rm : RXI<0x58, 262 (outs GR32:$dst), (ins rriaddr12:$src), 263 "l\t{$dst, $src}", 264 [(set GR32:$dst, (load rriaddr12:$src))]>; 265def MOV32rmy : RXYI<0x58E3, 266 (outs GR32:$dst), (ins rriaddr:$src), 267 "ly\t{$dst, $src}", 268 [(set GR32:$dst, (load rriaddr:$src))]>; 269def MOV64rm : RXYI<0x04E3, 270 (outs GR64:$dst), (ins rriaddr:$src), 271 "lg\t{$dst, $src}", 272 [(set GR64:$dst, (load rriaddr:$src))]>; 273def MOV64Prm : Pseudo<(outs GR64P:$dst), (ins rriaddr12:$src), 274 "# MOV64P PSEUDO!\n" 275 "\tl\t${dst:subreg_odd}, $src\n" 276 "\tl\t${dst:subreg_even}, 4+$src", 277 [(set GR64P:$dst, (load rriaddr12:$src))]>; 278def MOV64Prmy : Pseudo<(outs GR64P:$dst), (ins rriaddr:$src), 279 "# MOV64P PSEUDO!\n" 280 "\tly\t${dst:subreg_odd}, $src\n" 281 "\tly\t${dst:subreg_even}, 4+$src", 282 [(set GR64P:$dst, (load rriaddr:$src))]>; 283def MOV128rm : Pseudo<(outs GR128:$dst), (ins rriaddr:$src), 284 "# MOV128 PSEUDO!\n" 285 "\tlg\t${dst:subreg_odd}, $src\n" 286 "\tlg\t${dst:subreg_even}, 8+$src", 287 [(set GR128:$dst, (load rriaddr:$src))]>; 288} 289 290def MOV32mr : RXI<0x50, 291 (outs), (ins rriaddr12:$dst, GR32:$src), 292 "st\t{$src, $dst}", 293 [(store GR32:$src, rriaddr12:$dst)]>; 294def MOV32mry : RXYI<0x50E3, 295 (outs), (ins rriaddr:$dst, GR32:$src), 296 "sty\t{$src, $dst}", 297 [(store GR32:$src, rriaddr:$dst)]>; 298def MOV64mr : RXYI<0x24E3, 299 (outs), (ins rriaddr:$dst, GR64:$src), 300 "stg\t{$src, $dst}", 301 [(store GR64:$src, rriaddr:$dst)]>; 302def MOV64Pmr : Pseudo<(outs), (ins rriaddr12:$dst, GR64P:$src), 303 "# MOV64P PSEUDO!\n" 304 "\tst\t${src:subreg_odd}, $dst\n" 305 "\tst\t${src:subreg_even}, 4+$dst", 306 [(store GR64P:$src, rriaddr12:$dst)]>; 307def MOV64Pmry : Pseudo<(outs), (ins rriaddr:$dst, GR64P:$src), 308 "# MOV64P PSEUDO!\n" 309 "\tsty\t${src:subreg_odd}, $dst\n" 310 "\tsty\t${src:subreg_even}, 4+$dst", 311 [(store GR64P:$src, rriaddr:$dst)]>; 312def MOV128mr : Pseudo<(outs), (ins rriaddr:$dst, GR128:$src), 313 "# MOV128 PSEUDO!\n" 314 "\tstg\t${src:subreg_odd}, $dst\n" 315 "\tstg\t${src:subreg_even}, 8+$dst", 316 [(store GR128:$src, rriaddr:$dst)]>; 317 318def MOV8mi : SII<0x92, 319 (outs), (ins riaddr12:$dst, i32i8imm:$src), 320 "mvi\t{$dst, $src}", 321 [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>; 322def MOV8miy : SIYI<0x52EB, 323 (outs), (ins riaddr:$dst, i32i8imm:$src), 324 "mviy\t{$dst, $src}", 325 [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>; 326 327def MOV16mi : SILI<0xE544, 328 (outs), (ins riaddr12:$dst, s16imm:$src), 329 "mvhhi\t{$dst, $src}", 330 [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>, 331 Requires<[IsZ10]>; 332def MOV32mi16 : SILI<0xE54C, 333 (outs), (ins riaddr12:$dst, s32imm:$src), 334 "mvhi\t{$dst, $src}", 335 [(store (i32 immSExt16:$src), riaddr12:$dst)]>, 336 Requires<[IsZ10]>; 337def MOV64mi16 : SILI<0xE548, 338 (outs), (ins riaddr12:$dst, s32imm64:$src), 339 "mvghi\t{$dst, $src}", 340 [(store (i64 immSExt16:$src), riaddr12:$dst)]>, 341 Requires<[IsZ10]>; 342 343// sexts 344def MOVSX32rr8 : RREI<0xB926, 345 (outs GR32:$dst), (ins GR32:$src), 346 "lbr\t{$dst, $src}", 347 [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>; 348def MOVSX64rr8 : RREI<0xB906, 349 (outs GR64:$dst), (ins GR64:$src), 350 "lgbr\t{$dst, $src}", 351 [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>; 352def MOVSX32rr16 : RREI<0xB927, 353 (outs GR32:$dst), (ins GR32:$src), 354 "lhr\t{$dst, $src}", 355 [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>; 356def MOVSX64rr16 : RREI<0xB907, 357 (outs GR64:$dst), (ins GR64:$src), 358 "lghr\t{$dst, $src}", 359 [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>; 360 361// extloads 362def MOVSX32rm8 : RXYI<0x76E3, 363 (outs GR32:$dst), (ins rriaddr:$src), 364 "lb\t{$dst, $src}", 365 [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>; 366def MOVSX32rm16 : RXI<0x48, 367 (outs GR32:$dst), (ins rriaddr12:$src), 368 "lh\t{$dst, $src}", 369 [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>; 370def MOVSX32rm16y : RXYI<0x78E3, 371 (outs GR32:$dst), (ins rriaddr:$src), 372 "lhy\t{$dst, $src}", 373 [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>; 374def MOVSX64rm8 : RXYI<0x77E3, 375 (outs GR64:$dst), (ins rriaddr:$src), 376 "lgb\t{$dst, $src}", 377 [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>; 378def MOVSX64rm16 : RXYI<0x15E3, 379 (outs GR64:$dst), (ins rriaddr:$src), 380 "lgh\t{$dst, $src}", 381 [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>; 382def MOVSX64rm32 : RXYI<0x14E3, 383 (outs GR64:$dst), (ins rriaddr:$src), 384 "lgf\t{$dst, $src}", 385 [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>; 386 387def MOVZX32rm8 : RXYI<0x94E3, 388 (outs GR32:$dst), (ins rriaddr:$src), 389 "llc\t{$dst, $src}", 390 [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>; 391def MOVZX32rm16 : RXYI<0x95E3, 392 (outs GR32:$dst), (ins rriaddr:$src), 393 "llh\t{$dst, $src}", 394 [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>; 395def MOVZX64rm8 : RXYI<0x90E3, 396 (outs GR64:$dst), (ins rriaddr:$src), 397 "llgc\t{$dst, $src}", 398 [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>; 399def MOVZX64rm16 : RXYI<0x91E3, 400 (outs GR64:$dst), (ins rriaddr:$src), 401 "llgh\t{$dst, $src}", 402 [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>; 403def MOVZX64rm32 : RXYI<0x16E3, 404 (outs GR64:$dst), (ins rriaddr:$src), 405 "llgf\t{$dst, $src}", 406 [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>; 407 408// truncstores 409def MOV32m8r : RXI<0x42, 410 (outs), (ins rriaddr12:$dst, GR32:$src), 411 "stc\t{$src, $dst}", 412 [(truncstorei8 GR32:$src, rriaddr12:$dst)]>; 413 414def MOV32m8ry : RXYI<0x72E3, 415 (outs), (ins rriaddr:$dst, GR32:$src), 416 "stcy\t{$src, $dst}", 417 [(truncstorei8 GR32:$src, rriaddr:$dst)]>; 418 419def MOV32m16r : RXI<0x40, 420 (outs), (ins rriaddr12:$dst, GR32:$src), 421 "sth\t{$src, $dst}", 422 [(truncstorei16 GR32:$src, rriaddr12:$dst)]>; 423 424def MOV32m16ry : RXYI<0x70E3, 425 (outs), (ins rriaddr:$dst, GR32:$src), 426 "sthy\t{$src, $dst}", 427 [(truncstorei16 GR32:$src, rriaddr:$dst)]>; 428 429def MOV64m8r : RXI<0x42, 430 (outs), (ins rriaddr12:$dst, GR64:$src), 431 "stc\t{$src, $dst}", 432 [(truncstorei8 GR64:$src, rriaddr12:$dst)]>; 433 434def MOV64m8ry : RXYI<0x72E3, 435 (outs), (ins rriaddr:$dst, GR64:$src), 436 "stcy\t{$src, $dst}", 437 [(truncstorei8 GR64:$src, rriaddr:$dst)]>; 438 439def MOV64m16r : RXI<0x40, 440 (outs), (ins rriaddr12:$dst, GR64:$src), 441 "sth\t{$src, $dst}", 442 [(truncstorei16 GR64:$src, rriaddr12:$dst)]>; 443 444def MOV64m16ry : RXYI<0x70E3, 445 (outs), (ins rriaddr:$dst, GR64:$src), 446 "sthy\t{$src, $dst}", 447 [(truncstorei16 GR64:$src, rriaddr:$dst)]>; 448 449def MOV64m32r : RXI<0x50, 450 (outs), (ins rriaddr12:$dst, GR64:$src), 451 "st\t{$src, $dst}", 452 [(truncstorei32 GR64:$src, rriaddr12:$dst)]>; 453 454def MOV64m32ry : RXYI<0x50E3, 455 (outs), (ins rriaddr:$dst, GR64:$src), 456 "sty\t{$src, $dst}", 457 [(truncstorei32 GR64:$src, rriaddr:$dst)]>; 458 459// multiple regs moves 460// FIXME: should we use multiple arg nodes? 461def MOV32mrm : RSYI<0x90EB, 462 (outs), (ins riaddr:$dst, GR32:$from, GR32:$to), 463 "stmy\t{$from, $to, $dst}", 464 []>; 465def MOV64mrm : RSYI<0x24EB, 466 (outs), (ins riaddr:$dst, GR64:$from, GR64:$to), 467 "stmg\t{$from, $to, $dst}", 468 []>; 469def MOV32rmm : RSYI<0x90EB, 470 (outs GR32:$from, GR32:$to), (ins riaddr:$dst), 471 "lmy\t{$from, $to, $dst}", 472 []>; 473def MOV64rmm : RSYI<0x04EB, 474 (outs GR64:$from, GR64:$to), (ins riaddr:$dst), 475 "lmg\t{$from, $to, $dst}", 476 []>; 477 478let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in { 479def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src), 480 "lhi\t${dst:subreg_even}, 0", 481 []>; 482def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src), 483 "lghi\t${dst:subreg_even}, 0", 484 []>; 485} 486 487// Byte swaps 488def BSWAP32rr : RREI<0xB91F, 489 (outs GR32:$dst), (ins GR32:$src), 490 "lrvr\t{$dst, $src}", 491 [(set GR32:$dst, (bswap GR32:$src))]>; 492def BSWAP64rr : RREI<0xB90F, 493 (outs GR64:$dst), (ins GR64:$src), 494 "lrvgr\t{$dst, $src}", 495 [(set GR64:$dst, (bswap GR64:$src))]>; 496 497// FIXME: this is invalid pattern for big-endian 498//def BSWAP16rm : RXYI<0x1FE3, (outs GR32:$dst), (ins rriaddr:$src), 499// "lrvh\t{$dst, $src}", 500// [(set GR32:$dst, (bswap (extloadi32i16 rriaddr:$src)))]>; 501def BSWAP32rm : RXYI<0x1EE3, (outs GR32:$dst), (ins rriaddr:$src), 502 "lrv\t{$dst, $src}", 503 [(set GR32:$dst, (bswap (load rriaddr:$src)))]>; 504def BSWAP64rm : RXYI<0x0FE3, (outs GR64:$dst), (ins rriaddr:$src), 505 "lrvg\t{$dst, $src}", 506 [(set GR64:$dst, (bswap (load rriaddr:$src)))]>; 507 508//def BSWAP16mr : RXYI<0xE33F, (outs), (ins rriaddr:$dst, GR32:$src), 509// "strvh\t{$src, $dst}", 510// [(truncstorei16 (bswap GR32:$src), rriaddr:$dst)]>; 511def BSWAP32mr : RXYI<0xE33E, (outs), (ins rriaddr:$dst, GR32:$src), 512 "strv\t{$src, $dst}", 513 [(store (bswap GR32:$src), rriaddr:$dst)]>; 514def BSWAP64mr : RXYI<0xE32F, (outs), (ins rriaddr:$dst, GR64:$src), 515 "strvg\t{$src, $dst}", 516 [(store (bswap GR64:$src), rriaddr:$dst)]>; 517 518//===----------------------------------------------------------------------===// 519// Arithmetic Instructions 520 521let Defs = [PSW] in { 522def NEG32rr : RRI<0x13, 523 (outs GR32:$dst), (ins GR32:$src), 524 "lcr\t{$dst, $src}", 525 [(set GR32:$dst, (ineg GR32:$src)), 526 (implicit PSW)]>; 527def NEG64rr : RREI<0xB903, (outs GR64:$dst), (ins GR64:$src), 528 "lcgr\t{$dst, $src}", 529 [(set GR64:$dst, (ineg GR64:$src)), 530 (implicit PSW)]>; 531def NEG64rr32 : RREI<0xB913, (outs GR64:$dst), (ins GR32:$src), 532 "lcgfr\t{$dst, $src}", 533 [(set GR64:$dst, (ineg (sext GR32:$src))), 534 (implicit PSW)]>; 535} 536 537let isTwoAddress = 1 in { 538 539let Defs = [PSW] in { 540 541let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y 542def ADD32rr : RRI<0x1A, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 543 "ar\t{$dst, $src2}", 544 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), 545 (implicit PSW)]>; 546def ADD64rr : RREI<0xB908, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 547 "agr\t{$dst, $src2}", 548 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)), 549 (implicit PSW)]>; 550} 551 552def ADD32rm : RXI<0x5A, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2), 553 "a\t{$dst, $src2}", 554 [(set GR32:$dst, (add GR32:$src1, (load rriaddr12:$src2))), 555 (implicit PSW)]>; 556def ADD32rmy : RXYI<0xE35A, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 557 "ay\t{$dst, $src2}", 558 [(set GR32:$dst, (add GR32:$src1, (load rriaddr:$src2))), 559 (implicit PSW)]>; 560def ADD64rm : RXYI<0xE308, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 561 "ag\t{$dst, $src2}", 562 [(set GR64:$dst, (add GR64:$src1, (load rriaddr:$src2))), 563 (implicit PSW)]>; 564 565 566def ADD32ri16 : RII<0xA7A, 567 (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2), 568 "ahi\t{$dst, $src2}", 569 [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)), 570 (implicit PSW)]>; 571def ADD32ri : RILI<0xC29, 572 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 573 "afi\t{$dst, $src2}", 574 [(set GR32:$dst, (add GR32:$src1, imm:$src2)), 575 (implicit PSW)]>; 576def ADD64ri16 : RILI<0xA7B, 577 (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2), 578 "aghi\t{$dst, $src2}", 579 [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)), 580 (implicit PSW)]>; 581def ADD64ri32 : RILI<0xC28, 582 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 583 "agfi\t{$dst, $src2}", 584 [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)), 585 (implicit PSW)]>; 586 587let isCommutable = 1 in { // X = ADC Y, Z == X = ADC Z, Y 588def ADC32rr : RRI<0x1E, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 589 "alr\t{$dst, $src2}", 590 [(set GR32:$dst, (addc GR32:$src1, GR32:$src2))]>; 591def ADC64rr : RREI<0xB90A, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 592 "algr\t{$dst, $src2}", 593 [(set GR64:$dst, (addc GR64:$src1, GR64:$src2))]>; 594} 595 596def ADC32ri : RILI<0xC2B, 597 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 598 "alfi\t{$dst, $src2}", 599 [(set GR32:$dst, (addc GR32:$src1, imm:$src2))]>; 600def ADC64ri32 : RILI<0xC2A, 601 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 602 "algfi\t{$dst, $src2}", 603 [(set GR64:$dst, (addc GR64:$src1, immSExt32:$src2))]>; 604 605let Uses = [PSW] in { 606def ADDE32rr : RREI<0xB998, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 607 "alcr\t{$dst, $src2}", 608 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2)), 609 (implicit PSW)]>; 610def ADDE64rr : RREI<0xB988, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 611 "alcgr\t{$dst, $src2}", 612 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2)), 613 (implicit PSW)]>; 614} 615 616let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y 617def AND32rr : RRI<0x14, 618 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 619 "nr\t{$dst, $src2}", 620 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; 621def AND64rr : RREI<0xB980, 622 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 623 "ngr\t{$dst, $src2}", 624 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>; 625} 626 627def AND32rm : RXI<0x54, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2), 628 "n\t{$dst, $src2}", 629 [(set GR32:$dst, (and GR32:$src1, (load rriaddr12:$src2))), 630 (implicit PSW)]>; 631def AND32rmy : RXYI<0xE354, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 632 "ny\t{$dst, $src2}", 633 [(set GR32:$dst, (and GR32:$src1, (load rriaddr:$src2))), 634 (implicit PSW)]>; 635def AND64rm : RXYI<0xE360, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 636 "ng\t{$dst, $src2}", 637 [(set GR64:$dst, (and GR64:$src1, (load rriaddr:$src2))), 638 (implicit PSW)]>; 639 640def AND32rill16 : RII<0xA57, 641 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 642 "nill\t{$dst, $src2}", 643 [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>; 644def AND64rill16 : RII<0xA57, 645 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 646 "nill\t{$dst, $src2}", 647 [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>; 648 649def AND32rilh16 : RII<0xA56, 650 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 651 "nilh\t{$dst, $src2}", 652 [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>; 653def AND64rilh16 : RII<0xA56, 654 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 655 "nilh\t{$dst, $src2}", 656 [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>; 657 658def AND64rihl16 : RII<0xA55, 659 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 660 "nihl\t{$dst, $src2}", 661 [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>; 662def AND64rihh16 : RII<0xA54, 663 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 664 "nihh\t{$dst, $src2}", 665 [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>; 666 667def AND32ri : RILI<0xC0B, 668 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 669 "nilf\t{$dst, $src2}", 670 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; 671def AND64rilo32 : RILI<0xC0B, 672 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 673 "nilf\t{$dst, $src2}", 674 [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>; 675def AND64rihi32 : RILI<0xC0A, 676 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 677 "nihf\t{$dst, $src2}", 678 [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>; 679 680let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y 681def OR32rr : RRI<0x16, 682 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 683 "or\t{$dst, $src2}", 684 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; 685def OR64rr : RREI<0xB981, 686 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 687 "ogr\t{$dst, $src2}", 688 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; 689} 690 691def OR32rm : RXI<0x56, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2), 692 "o\t{$dst, $src2}", 693 [(set GR32:$dst, (or GR32:$src1, (load rriaddr12:$src2))), 694 (implicit PSW)]>; 695def OR32rmy : RXYI<0xE356, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 696 "oy\t{$dst, $src2}", 697 [(set GR32:$dst, (or GR32:$src1, (load rriaddr:$src2))), 698 (implicit PSW)]>; 699def OR64rm : RXYI<0xE381, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 700 "og\t{$dst, $src2}", 701 [(set GR64:$dst, (or GR64:$src1, (load rriaddr:$src2))), 702 (implicit PSW)]>; 703 704 // FIXME: Provide proper encoding! 705def OR32ri16 : RII<0xA5B, 706 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 707 "oill\t{$dst, $src2}", 708 [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>; 709def OR32ri16h : RII<0xA5A, 710 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 711 "oilh\t{$dst, $src2}", 712 [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>; 713def OR32ri : RILI<0xC0D, 714 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 715 "oilf\t{$dst, $src2}", 716 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; 717 718def OR64rill16 : RII<0xA5B, 719 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 720 "oill\t{$dst, $src2}", 721 [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>; 722def OR64rilh16 : RII<0xA5A, 723 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 724 "oilh\t{$dst, $src2}", 725 [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>; 726def OR64rihl16 : RII<0xA59, 727 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 728 "oihl\t{$dst, $src2}", 729 [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>; 730def OR64rihh16 : RII<0xA58, 731 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 732 "oihh\t{$dst, $src2}", 733 [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>; 734 735def OR64rilo32 : RILI<0xC0D, 736 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 737 "oilf\t{$dst, $src2}", 738 [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>; 739def OR64rihi32 : RILI<0xC0C, 740 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 741 "oihf\t{$dst, $src2}", 742 [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>; 743 744def SUB32rr : RRI<0x1B, 745 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 746 "sr\t{$dst, $src2}", 747 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; 748def SUB64rr : RREI<0xB909, 749 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 750 "sgr\t{$dst, $src2}", 751 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>; 752 753def SUB32rm : RXI<0x5B, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2), 754 "s\t{$dst, $src2}", 755 [(set GR32:$dst, (sub GR32:$src1, (load rriaddr12:$src2))), 756 (implicit PSW)]>; 757def SUB32rmy : RXYI<0xE35B, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 758 "sy\t{$dst, $src2}", 759 [(set GR32:$dst, (sub GR32:$src1, (load rriaddr:$src2))), 760 (implicit PSW)]>; 761def SUB64rm : RXYI<0xE309, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 762 "sg\t{$dst, $src2}", 763 [(set GR64:$dst, (sub GR64:$src1, (load rriaddr:$src2))), 764 (implicit PSW)]>; 765 766def SBC32rr : RRI<0x1F, 767 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 768 "slr\t{$dst, $src2}", 769 [(set GR32:$dst, (subc GR32:$src1, GR32:$src2))]>; 770def SBC64rr : RREI<0xB90B, 771 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 772 "slgr\t{$dst, $src2}", 773 [(set GR64:$dst, (subc GR64:$src1, GR64:$src2))]>; 774 775def SBC32ri : RILI<0xC25, 776 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 777 "sllfi\t{$dst, $src2}", 778 [(set GR32:$dst, (subc GR32:$src1, imm:$src2))]>; 779def SBC64ri32 : RILI<0xC24, 780 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 781 "slgfi\t{$dst, $src2}", 782 [(set GR64:$dst, (subc GR64:$src1, immSExt32:$src2))]>; 783 784let Uses = [PSW] in { 785def SUBE32rr : RREI<0xB999, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 786 "slcr\t{$dst, $src2}", 787 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2)), 788 (implicit PSW)]>; 789def SUBE64rr : RREI<0xB989, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 790 "slcgr\t{$dst, $src2}", 791 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2)), 792 (implicit PSW)]>; 793} 794 795let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y 796def XOR32rr : RRI<0x17, 797 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 798 "xr\t{$dst, $src2}", 799 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; 800def XOR64rr : RREI<0xB982, 801 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 802 "xgr\t{$dst, $src2}", 803 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; 804} 805 806def XOR32rm : RXI<0x57,(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2), 807 "x\t{$dst, $src2}", 808 [(set GR32:$dst, (xor GR32:$src1, (load rriaddr12:$src2))), 809 (implicit PSW)]>; 810def XOR32rmy : RXYI<0xE357, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 811 "xy\t{$dst, $src2}", 812 [(set GR32:$dst, (xor GR32:$src1, (load rriaddr:$src2))), 813 (implicit PSW)]>; 814def XOR64rm : RXYI<0xE382, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 815 "xg\t{$dst, $src2}", 816 [(set GR64:$dst, (xor GR64:$src1, (load rriaddr:$src2))), 817 (implicit PSW)]>; 818 819def XOR32ri : RILI<0xC07, 820 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 821 "xilf\t{$dst, $src2}", 822 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; 823 824} // Defs = [PSW] 825 826let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y 827def MUL32rr : RREI<0xB252, 828 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 829 "msr\t{$dst, $src2}", 830 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>; 831def MUL64rr : RREI<0xB90C, 832 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 833 "msgr\t{$dst, $src2}", 834 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>; 835} 836 837def MUL64rrP : RRI<0x1C, 838 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 839 "mr\t{$dst, $src2}", 840 []>; 841def UMUL64rrP : RREI<0xB996, 842 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 843 "mlr\t{$dst, $src2}", 844 []>; 845def UMUL128rrP : RREI<0xB986, 846 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 847 "mlgr\t{$dst, $src2}", 848 []>; 849 850def MUL32ri16 : RII<0xA7C, 851 (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2), 852 "mhi\t{$dst, $src2}", 853 [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>; 854def MUL64ri16 : RII<0xA7D, 855 (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2), 856 "mghi\t{$dst, $src2}", 857 [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>; 858 859def MUL32ri : RILI<0xC21, 860 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 861 "msfi\t{$dst, $src2}", 862 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>, 863 Requires<[IsZ10]>; 864def MUL64ri32 : RILI<0xC20, 865 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 866 "msgfi\t{$dst, $src2}", 867 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>, 868 Requires<[IsZ10]>; 869 870def MUL32rm : RXI<0x71, 871 (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2), 872 "ms\t{$dst, $src2}", 873 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>; 874def MUL32rmy : RXYI<0xE351, 875 (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 876 "msy\t{$dst, $src2}", 877 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>; 878def MUL64rm : RXYI<0xE30C, 879 (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 880 "msg\t{$dst, $src2}", 881 [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>; 882 883def MULSX64rr32 : RREI<0xB91C, 884 (outs GR64:$dst), (ins GR64:$src1, GR32:$src2), 885 "msgfr\t{$dst, $src2}", 886 [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>; 887 888def SDIVREM32r : RREI<0xB91D, 889 (outs GR128:$dst), (ins GR128:$src1, GR32:$src2), 890 "dsgfr\t{$dst, $src2}", 891 []>; 892def SDIVREM64r : RREI<0xB90D, 893 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 894 "dsgr\t{$dst, $src2}", 895 []>; 896 897def UDIVREM32r : RREI<0xB997, 898 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 899 "dlr\t{$dst, $src2}", 900 []>; 901def UDIVREM64r : RREI<0xB987, 902 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 903 "dlgr\t{$dst, $src2}", 904 []>; 905let mayLoad = 1 in { 906def SDIVREM32m : RXYI<0xE31D, 907 (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2), 908 "dsgf\t{$dst, $src2}", 909 []>; 910def SDIVREM64m : RXYI<0xE30D, 911 (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2), 912 "dsg\t{$dst, $src2}", 913 []>; 914 915def UDIVREM32m : RXYI<0xE397, (outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2), 916 "dl\t{$dst, $src2}", 917 []>; 918def UDIVREM64m : RXYI<0xE387, (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2), 919 "dlg\t{$dst, $src2}", 920 []>; 921} // mayLoad 922} // isTwoAddress = 1 923 924//===----------------------------------------------------------------------===// 925// Shifts 926 927let isTwoAddress = 1 in 928def SRL32rri : RSI<0x88, 929 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 930 "srl\t{$src, $amt}", 931 [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>; 932def SRL64rri : RSYI<0xEB0C, 933 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 934 "srlg\t{$dst, $src, $amt}", 935 [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>; 936 937let isTwoAddress = 1 in 938def SHL32rri : RSI<0x89, 939 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 940 "sll\t{$src, $amt}", 941 [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>; 942def SHL64rri : RSYI<0xEB0D, 943 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 944 "sllg\t{$dst, $src, $amt}", 945 [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>; 946 947let Defs = [PSW] in { 948let isTwoAddress = 1 in 949def SRA32rri : RSI<0x8A, 950 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 951 "sra\t{$src, $amt}", 952 [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)), 953 (implicit PSW)]>; 954 955def SRA64rri : RSYI<0xEB0A, 956 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 957 "srag\t{$dst, $src, $amt}", 958 [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)), 959 (implicit PSW)]>; 960} // Defs = [PSW] 961 962def ROTL32rri : RSYI<0xEB1D, 963 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 964 "rll\t{$dst, $src, $amt}", 965 [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>; 966def ROTL64rri : RSYI<0xEB1C, 967 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 968 "rllg\t{$dst, $src, $amt}", 969 [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>; 970 971//===----------------------------------------------------------------------===// 972// Test instructions (like AND but do not produce any result) 973 974// Integer comparisons 975let Defs = [PSW] in { 976def CMP32rr : RRI<0x19, 977 (outs), (ins GR32:$src1, GR32:$src2), 978 "cr\t$src1, $src2", 979 [(SystemZcmp GR32:$src1, GR32:$src2), 980 (implicit PSW)]>; 981def CMP64rr : RREI<0xB920, 982 (outs), (ins GR64:$src1, GR64:$src2), 983 "cgr\t$src1, $src2", 984 [(SystemZcmp GR64:$src1, GR64:$src2), 985 (implicit PSW)]>; 986 987def CMP32ri : RILI<0xC2D, 988 (outs), (ins GR32:$src1, s32imm:$src2), 989 "cfi\t$src1, $src2", 990 [(SystemZcmp GR32:$src1, imm:$src2), 991 (implicit PSW)]>; 992def CMP64ri32 : RILI<0xC2C, 993 (outs), (ins GR64:$src1, s32imm64:$src2), 994 "cgfi\t$src1, $src2", 995 [(SystemZcmp GR64:$src1, i64immSExt32:$src2), 996 (implicit PSW)]>; 997 998def CMP32rm : RXI<0x59, 999 (outs), (ins GR32:$src1, rriaddr12:$src2), 1000 "c\t$src1, $src2", 1001 [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)), 1002 (implicit PSW)]>; 1003def CMP32rmy : RXYI<0xE359, 1004 (outs), (ins GR32:$src1, rriaddr:$src2), 1005 "cy\t$src1, $src2", 1006 [(SystemZcmp GR32:$src1, (load rriaddr:$src2)), 1007 (implicit PSW)]>; 1008def CMP64rm : RXYI<0xE320, 1009 (outs), (ins GR64:$src1, rriaddr:$src2), 1010 "cg\t$src1, $src2", 1011 [(SystemZcmp GR64:$src1, (load rriaddr:$src2)), 1012 (implicit PSW)]>; 1013 1014def UCMP32rr : RRI<0x15, 1015 (outs), (ins GR32:$src1, GR32:$src2), 1016 "clr\t$src1, $src2", 1017 [(SystemZucmp GR32:$src1, GR32:$src2), 1018 (implicit PSW)]>; 1019def UCMP64rr : RREI<0xB921, 1020 (outs), (ins GR64:$src1, GR64:$src2), 1021 "clgr\t$src1, $src2", 1022 [(SystemZucmp GR64:$src1, GR64:$src2), 1023 (implicit PSW)]>; 1024 1025def UCMP32ri : RILI<0xC2F, 1026 (outs), (ins GR32:$src1, i32imm:$src2), 1027 "clfi\t$src1, $src2", 1028 [(SystemZucmp GR32:$src1, imm:$src2), 1029 (implicit PSW)]>; 1030def UCMP64ri32 : RILI<0xC2E, 1031 (outs), (ins GR64:$src1, i64i32imm:$src2), 1032 "clgfi\t$src1, $src2", 1033 [(SystemZucmp GR64:$src1, i64immZExt32:$src2), 1034 (implicit PSW)]>; 1035 1036def UCMP32rm : RXI<0x55, 1037 (outs), (ins GR32:$src1, rriaddr12:$src2), 1038 "cl\t$src1, $src2", 1039 [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)), 1040 (implicit PSW)]>; 1041def UCMP32rmy : RXYI<0xE355, 1042 (outs), (ins GR32:$src1, rriaddr:$src2), 1043 "cly\t$src1, $src2", 1044 [(SystemZucmp GR32:$src1, (load rriaddr:$src2)), 1045 (implicit PSW)]>; 1046def UCMP64rm : RXYI<0xE351, 1047 (outs), (ins GR64:$src1, rriaddr:$src2), 1048 "clg\t$src1, $src2", 1049 [(SystemZucmp GR64:$src1, (load rriaddr:$src2)), 1050 (implicit PSW)]>; 1051 1052def CMPSX64rr32 : RREI<0xB930, 1053 (outs), (ins GR64:$src1, GR32:$src2), 1054 "cgfr\t$src1, $src2", 1055 [(SystemZucmp GR64:$src1, (sext GR32:$src2)), 1056 (implicit PSW)]>; 1057def UCMPZX64rr32 : RREI<0xB931, 1058 (outs), (ins GR64:$src1, GR32:$src2), 1059 "clgfr\t$src1, $src2", 1060 [(SystemZucmp GR64:$src1, (zext GR32:$src2)), 1061 (implicit PSW)]>; 1062 1063def CMPSX64rm32 : RXYI<0xE330, 1064 (outs), (ins GR64:$src1, rriaddr:$src2), 1065 "cgf\t$src1, $src2", 1066 [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)), 1067 (implicit PSW)]>; 1068def UCMPZX64rm32 : RXYI<0xE331, 1069 (outs), (ins GR64:$src1, rriaddr:$src2), 1070 "clgf\t$src1, $src2", 1071 [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)), 1072 (implicit PSW)]>; 1073 1074// FIXME: Add other crazy ucmp forms 1075 1076} // Defs = [PSW] 1077 1078//===----------------------------------------------------------------------===// 1079// Other crazy stuff 1080let Defs = [PSW] in { 1081def FLOGR64 : RREI<0xB983, 1082 (outs GR128:$dst), (ins GR64:$src), 1083 "flogr\t{$dst, $src}", 1084 []>; 1085} // Defs = [PSW] 1086 1087//===----------------------------------------------------------------------===// 1088// Non-Instruction Patterns. 1089//===----------------------------------------------------------------------===// 1090 1091// ConstPools, JumpTables 1092def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>; 1093def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>; 1094 1095// anyext 1096def : Pat<(i64 (anyext GR32:$src)), 1097 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 1098 1099// calls 1100def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>; 1101def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>; 1102 1103//===----------------------------------------------------------------------===// 1104// Peepholes. 1105//===----------------------------------------------------------------------===// 1106 1107// FIXME: use add/sub tricks with 32678/-32768 1108 1109// Arbitrary immediate support. 1110def : Pat<(i32 imm:$src), 1111 (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>; 1112 1113// Implement in terms of LLIHF/OILF. 1114def : Pat<(i64 imm:$imm), 1115 (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>; 1116 1117// trunc patterns 1118def : Pat<(i32 (trunc GR64:$src)), 1119 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 1120 1121// sext_inreg patterns 1122def : Pat<(sext_inreg GR64:$src, i32), 1123 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 1124 1125// extload patterns 1126def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>; 1127def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>; 1128def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>; 1129def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>; 1130def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>; 1131 1132// muls 1133def : Pat<(mulhs GR32:$src1, GR32:$src2), 1134 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 1135 GR32:$src1, subreg_odd32), 1136 GR32:$src2), 1137 subreg_even32)>; 1138 1139def : Pat<(mulhu GR32:$src1, GR32:$src2), 1140 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 1141 GR32:$src1, subreg_odd32), 1142 GR32:$src2), 1143 subreg_even32)>; 1144def : Pat<(mulhu GR64:$src1, GR64:$src2), 1145 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1146 GR64:$src1, subreg_odd), 1147 GR64:$src2), 1148 subreg_even)>; 1149 1150def : Pat<(ctlz GR64:$src), 1151 (EXTRACT_SUBREG (FLOGR64 GR64:$src), subreg_even)>; 1152