SystemZInstrInfo.td revision bad769f11aadb0b4aef1c998d2cbbfdb47de12da
1//===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SystemZ instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14include "SystemZInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// Type Constraints. 18//===----------------------------------------------------------------------===// 19class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; 20class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; 21class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>; 22class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>; 23 24//===----------------------------------------------------------------------===// 25// Type Profiles. 26//===----------------------------------------------------------------------===// 27def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>; 29def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>; 30def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 31def SDT_BrCond : SDTypeProfile<0, 2, 32 [SDTCisVT<0, OtherVT>, 33 SDTCisI8<1>]>; 34def SDT_SelectCC : SDTypeProfile<1, 3, 35 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 36 SDTCisI8<3>]>; 37def SDT_Address : SDTypeProfile<1, 1, 38 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 39 40//===----------------------------------------------------------------------===// 41// SystemZ Specific Node Definitions. 42//===----------------------------------------------------------------------===// 43def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 44 [SDNPHasChain, SDNPOptInFlag]>; 45def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall, 46 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; 47def SystemZcallseq_start : 48 SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart, 49 [SDNPHasChain, SDNPOutFlag]>; 50def SystemZcallseq_end : 51 SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd, 52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 53def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>; 54def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>; 55def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond, 56 [SDNPHasChain, SDNPInFlag]>; 57def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>; 58def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>; 59 60//===----------------------------------------------------------------------===// 61// Instruction Pattern Stuff. 62//===----------------------------------------------------------------------===// 63 64// SystemZ specific condition code. These correspond to CondCode in 65// SystemZ.h. They must be kept in synch. 66def SYSTEMZ_COND_E : PatLeaf<(i8 0)>; 67def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>; 68def SYSTEMZ_COND_H : PatLeaf<(i8 2)>; 69def SYSTEMZ_COND_L : PatLeaf<(i8 3)>; 70def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>; 71def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>; 72 73def LL16 : SDNodeXForm<imm, [{ 74 // Transformation function: return low 16 bits. 75 return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL); 76}]>; 77 78def LH16 : SDNodeXForm<imm, [{ 79 // Transformation function: return bits 16-31. 80 return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16); 81}]>; 82 83def HL16 : SDNodeXForm<imm, [{ 84 // Transformation function: return bits 32-47. 85 return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32); 86}]>; 87 88def HH16 : SDNodeXForm<imm, [{ 89 // Transformation function: return bits 48-63. 90 return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48); 91}]>; 92 93def LO32 : SDNodeXForm<imm, [{ 94 // Transformation function: return low 32 bits. 95 return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL); 96}]>; 97 98def HI32 : SDNodeXForm<imm, [{ 99 // Transformation function: return bits 32-63. 100 return getI32Imm(N->getZExtValue() >> 32); 101}]>; 102 103def i64ll16 : PatLeaf<(imm), [{ 104 // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16 105 // bits set. 106 return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue()); 107}], LL16>; 108 109def i64lh16 : PatLeaf<(imm), [{ 110 // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set. 111 return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue()); 112}], LH16>; 113 114def i64hl16 : PatLeaf<(i64 imm), [{ 115 // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set. 116 return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue()); 117}], HL16>; 118 119def i64hh16 : PatLeaf<(i64 imm), [{ 120 // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set. 121 return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue()); 122}], HH16>; 123 124def immSExt16 : PatLeaf<(imm), [{ 125 // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended 126 // field. 127 if (N->getValueType(0) == MVT::i64) { 128 uint64_t val = N->getZExtValue(); 129 return ((int64_t)val == (int16_t)val); 130 } else if (N->getValueType(0) == MVT::i32) { 131 uint32_t val = N->getZExtValue(); 132 return ((int32_t)val == (int16_t)val); 133 } 134 135 return false; 136}]>; 137 138def immSExt32 : PatLeaf<(i64 imm), [{ 139 // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended 140 // field. 141 uint64_t val = N->getZExtValue(); 142 return ((int64_t)val == (int32_t)val); 143}]>; 144 145def i64lo32 : PatLeaf<(i64 imm), [{ 146 // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32 147 // bits set. 148 return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue()); 149}], LO32>; 150 151def i64hi32 : PatLeaf<(i64 imm), [{ 152 // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set. 153 return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue()); 154}], HI32>; 155 156def i32immSExt8 : PatLeaf<(i32 imm), [{ 157 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit 158 // sign extended field. 159 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); 160}]>; 161 162def i32immSExt16 : PatLeaf<(i32 imm), [{ 163 // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit 164 // sign extended field. 165 return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue(); 166}]>; 167 168def i64immSExt32 : PatLeaf<(i64 imm), [{ 169 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit 170 // sign extended field. 171 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue(); 172}]>; 173 174def i64immZExt32 : PatLeaf<(i64 imm), [{ 175 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 176 // zero extended field. 177 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue(); 178}]>; 179 180// extloads 181def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 182def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 183def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 184def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 185def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 186 187def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 188def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 189def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 190def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 191def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 192 193def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 194def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 195def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 196def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 197def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 198 199// A couple of more descriptive operand definitions. 200// 32-bits but only 8 bits are significant. 201def i32i8imm : Operand<i32>; 202// 32-bits but only 16 bits are significant. 203def i32i16imm : Operand<i32>; 204// 64-bits but only 32 bits are significant. 205def i64i32imm : Operand<i64>; 206// Branch targets have OtherVT type. 207def brtarget : Operand<OtherVT>; 208 209//===----------------------------------------------------------------------===// 210// SystemZ Operand Definitions. 211//===----------------------------------------------------------------------===// 212 213// Address operands 214 215// riaddr := reg + imm 216def riaddr32 : Operand<i32>, 217 ComplexPattern<i32, 2, "SelectAddrRI", []> { 218 let PrintMethod = "printRIAddrOperand"; 219 let MIOperandInfo = (ops ADDR32:$base, i32imm:$disp); 220} 221 222def riaddr : Operand<i64>, 223 ComplexPattern<i64, 2, "SelectAddrRI", []> { 224 let PrintMethod = "printRIAddrOperand"; 225 let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp); 226} 227 228//===----------------------------------------------------------------------===// 229 230// rriaddr := reg + reg + imm 231def rriaddr : Operand<i64>, 232 ComplexPattern<i64, 3, "SelectAddrRRI", [], []> { 233 let PrintMethod = "printRRIAddrOperand"; 234 let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index); 235} 236def laaddr : Operand<i64>, 237 ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> { 238 let PrintMethod = "printRRIAddrOperand"; 239 let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index); 240} 241 242//===----------------------------------------------------------------------===// 243// Instruction list.. 244 245def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 246 "#ADJCALLSTACKDOWN", 247 [(SystemZcallseq_start timm:$amt)]>; 248def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 249 "#ADJCALLSTACKUP", 250 [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>; 251 252let usesCustomDAGSchedInserter = 1 in { 253 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc), 254 "# Select32 PSEUDO", 255 [(set GR32:$dst, 256 (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>; 257 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc), 258 "# Select64 PSEUDO", 259 [(set GR64:$dst, 260 (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>; 261} 262 263 264//===----------------------------------------------------------------------===// 265// Control Flow Instructions... 266// 267 268// FIXME: Provide proper encoding! 269let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { 270 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>; 271} 272 273let isBranch = 1, isTerminator = 1 in { 274 let Uses = [PSW] in { 275 def JE : Pseudo<(outs), (ins brtarget:$dst), 276 "je\t$dst", 277 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>; 278 def JNE : Pseudo<(outs), (ins brtarget:$dst), 279 "jne\t$dst", 280 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>; 281 def JH : Pseudo<(outs), (ins brtarget:$dst), 282 "jh\t$dst", 283 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>; 284 def JL : Pseudo<(outs), (ins brtarget:$dst), 285 "jl\t$dst", 286 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>; 287 def JHE : Pseudo<(outs), (ins brtarget:$dst), 288 "jhe\t$dst", 289 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>; 290 def JLE : Pseudo<(outs), (ins brtarget:$dst), 291 "jle\t$dst", 292 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>; 293 294 } // Uses = [PSW] 295} // isBranch = 1 296 297//===----------------------------------------------------------------------===// 298// Call Instructions... 299// 300 301let isCall = 1 in 302 // All calls clobber the non-callee saved registers (except R14 which we 303 // handle separately). Uses for argument registers are added manually. 304 let Defs = [R0D, R1D, R3D, R4D, R5D] in { 305 def CALLi : Pseudo<(outs), (ins i64imm:$dst, variable_ops), 306 "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>; 307 def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops), 308 "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>; 309 } 310 311//===----------------------------------------------------------------------===// 312// Miscellaneous Instructions. 313// 314 315let isReMaterializable = 1 in 316// FIXME: Provide imm12 variant 317def LA64r : Pseudo<(outs GR64:$dst), (ins laaddr:$src), 318 "lay\t{$dst, $src}", 319 [(set GR64:$dst, laaddr:$src)]>; 320def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 321 "larl\t{$dst, $src}", 322 [(set GR64:$dst, 323 (SystemZpcrelwrapper tglobaladdr:$src))]>; 324 325let neverHasSideEffects = 1 in 326def NOP : Pseudo<(outs), (ins), "# no-op", []>; 327 328//===----------------------------------------------------------------------===// 329// Move Instructions 330 331// FIXME: Provide proper encoding! 332let neverHasSideEffects = 1 in { 333def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src), 334 "lr\t{$dst, $src}", 335 []>; 336def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src), 337 "lgr\t{$dst, $src}", 338 []>; 339def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src), 340 "# MOV128 PSEUDO!" 341 "lgr\t{$dst:subreg_odd, $src:subreg_odd}\n" 342 "lgr\t{$dst:subreg_even, $src:subreg_even}", 343 []>; 344def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src), 345 "# MOV64P PSEUDO!" 346 "lr\t{$dst:subreg_odd, $src:subreg_odd}\n" 347 "lr\t{$dst:subreg_even, $src:subreg_even}", 348 []>; 349} 350 351def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src), 352 "lgfr\t{$dst, $src}", 353 [(set GR64:$dst, (sext GR32:$src))]>; 354def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src), 355 "llgfr\t{$dst, $src}", 356 [(set GR64:$dst, (zext GR32:$src))]>; 357 358// FIXME: Provide proper encoding! 359let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 360def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins i32imm:$src), 361 "lhi\t{$dst, $src}", 362 [(set GR32:$dst, immSExt16:$src)]>; 363def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 364 "lghi\t{$dst, $src}", 365 [(set GR64:$dst, immSExt16:$src)]>; 366 367def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 368 "llill\t{$dst, $src}", 369 [(set GR64:$dst, i64ll16:$src)]>; 370def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 371 "llilh\t{$dst, $src}", 372 [(set GR64:$dst, i64lh16:$src)]>; 373def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 374 "llihl\t{$dst, $src}", 375 [(set GR64:$dst, i64hl16:$src)]>; 376def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 377 "llihh\t{$dst, $src}", 378 [(set GR64:$dst, i64hh16:$src)]>; 379// FIXME: these 3 instructions seem to require extimm facility 380def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 381 "lgfi\t{$dst, $src}", 382 [(set GR64:$dst, immSExt32:$src)]>; 383def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 384 "llilf\t{$dst, $src}", 385 [(set GR64:$dst, i64lo32:$src)]>; 386def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 387 "llihf\t{$dst, $src}", 388 [(set GR64:$dst, i64hi32:$src)]>; 389} 390 391let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { 392def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 393 "lg\t{$dst, $src}", 394 [(set GR64:$dst, (load rriaddr:$src))]>; 395 396} 397 398def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 399 "stg\t{$src, $dst}", 400 [(store GR64:$src, rriaddr:$dst)]>; 401 402// FIXME: displacements here are really 12 bit, not 20! 403def MOV8mi : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src), 404 "mvi\t{$dst, $src}", 405 [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>; 406def MOV16mi : Pseudo<(outs), (ins riaddr:$dst, i32i16imm:$src), 407 "mvhhi\t{$dst, $src}", 408 [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>; 409def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, i32imm:$src), 410 "mvhi\t{$dst, $src}", 411 [(store (i32 immSExt16:$src), riaddr:$dst)]>; 412def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, i64imm:$src), 413 "mvghi\t{$dst, $src}", 414 [(store (i64 immSExt16:$src), riaddr:$dst)]>; 415 416// extloads 417def MOVSX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 418 "lb\t{$dst, $src}", 419 [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>; 420def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 421 "lhy\t{$dst, $src}", 422 [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>; 423def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 424 "lgb\t{$dst, $src}", 425 [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>; 426def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 427 "lgh\t{$dst, $src}", 428 [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>; 429def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 430 "lgf\t{$dst, $src}", 431 [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>; 432 433def MOVZX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 434 "llc\t{$dst, $src}", 435 [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>; 436def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 437 "llh\t{$dst, $src}", 438 [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>; 439def MOVZX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 440 "llgc\t{$dst, $src}", 441 [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>; 442def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 443 "llgh\t{$dst, $src}", 444 [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>; 445def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 446 "llgf\t{$dst, $src}", 447 [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>; 448 449// truncstores 450// FIXME: Implement 12-bit displacement stuff someday 451def MOV32m8r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 452 "stcy\t{$src, $dst}", 453 [(truncstorei8 GR32:$src, rriaddr:$dst)]>; 454 455def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 456 "sthy\t{$src, $dst}", 457 [(truncstorei16 GR32:$src, rriaddr:$dst)]>; 458 459def MOV64m8r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 460 "stcy\t{$src, $dst}", 461 [(truncstorei8 GR64:$src, rriaddr:$dst)]>; 462 463def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 464 "sthy\t{$src, $dst}", 465 [(truncstorei16 GR64:$src, rriaddr:$dst)]>; 466 467def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 468 "sty\t{$src, $dst}", 469 [(truncstorei32 GR64:$src, rriaddr:$dst)]>; 470 471// multiple regs moves 472// FIXME: should we use multiple arg nodes? 473def MOV32mrm : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to), 474 "stmy\t{$from, $to, $dst}", 475 []>; 476def MOV64mrm : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to), 477 "stmg\t{$from, $to, $dst}", 478 []>; 479def MOV32rmm : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst), 480 "lmy\t{$from, $to, $dst}", 481 []>; 482def MOV64rmm : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst), 483 "lmg\t{$from, $to, $dst}", 484 []>; 485 486 487//===----------------------------------------------------------------------===// 488// Arithmetic Instructions 489 490let isTwoAddress = 1 in { 491 492let Defs = [PSW] in { 493 494let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y 495// FIXME: Provide proper encoding! 496def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 497 "ar\t{$dst, $src2}", 498 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), 499 (implicit PSW)]>; 500def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 501 "agr\t{$dst, $src2}", 502 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)), 503 (implicit PSW)]>; 504} 505 506// FIXME: Provide proper encoding! 507def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 508 "ahi\t{$dst, $src2}", 509 [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)), 510 (implicit PSW)]>; 511def ADD32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 512 "afi\t{$dst, $src2}", 513 [(set GR32:$dst, (add GR32:$src1, imm:$src2)), 514 (implicit PSW)]>; 515def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 516 "aghi\t{$dst, $src2}", 517 [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)), 518 (implicit PSW)]>; 519def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 520 "agfi\t{$dst, $src2}", 521 [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)), 522 (implicit PSW)]>; 523 524let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y 525// FIXME: Provide proper encoding! 526def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 527 "nr\t{$dst, $src2}", 528 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; 529def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 530 "ngr\t{$dst, $src2}", 531 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>; 532} 533 534// FIXME: Provide proper encoding! 535def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 536 "nill\t{$dst, $src2}", 537 [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>; 538def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 539 "nilh\t{$dst, $src2}", 540 [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>; 541def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 542 "nihl\t{$dst, $src2}", 543 [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>; 544def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 545 "nihh\t{$dst, $src2}", 546 [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>; 547// FIXME: these 2 instructions seem to require extimm facility 548def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 549 "nilf\t{$dst, $src2}", 550 [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>; 551def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 552 "nihf\t{$dst, $src2}", 553 [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>; 554 555let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y 556// FIXME: Provide proper encoding! 557def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 558 "or\t{$dst, $src2}", 559 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; 560def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 561 "ogr\t{$dst, $src2}", 562 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; 563} 564 565def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2), 566 "oill\t{$dst, $src2}", 567 [(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>; 568def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2), 569 "oilh\t{$dst, $src2}", 570 [(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>; 571def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 572 "oilf\t{$dst, $src2}", 573 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; 574 575def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 576 "oill\t{$dst, $src2}", 577 [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>; 578def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 579 "oilh\t{$dst, $src2}", 580 [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>; 581def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 582 "oihl\t{$dst, $src2}", 583 [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>; 584def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 585 "oihh\t{$dst, $src2}", 586 [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>; 587// FIXME: these 2 instructions seem to require extimm facility 588def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 589 "oilf\t{$dst, $src2}", 590 [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>; 591def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 592 "oihf\t{$dst, $src2}", 593 [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>; 594 595// FIXME: Provide proper encoding! 596def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 597 "sr\t{$dst, $src2}", 598 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; 599def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 600 "sgr\t{$dst, $src2}", 601 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>; 602 603 604let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y 605// FIXME: Provide proper encoding! 606def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 607 "xr\t{$dst, $src2}", 608 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; 609def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 610 "xgr\t{$dst, $src2}", 611 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; 612} 613 614def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 615 "xilf\t{$dst, $src2}", 616 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; 617 618// FIXME: these 2 instructions seem to require extimm facility 619def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 620 "xilf\t{$dst, $src2}", 621 [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>; 622def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 623 "xihf\t{$dst, $src2}", 624 [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>; 625 626} // Defs = [PSW] 627 628let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y 629def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 630 "msr\t{$dst, $src2}", 631 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>; 632def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 633 "msgr\t{$dst, $src2}", 634 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>; 635 636def MUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 637 "mr\t{$dst, $src2}", 638 []>; 639def UMUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 640 "mlr\t{$dst, $src2}", 641 []>; 642def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 643 "mlgr\t{$dst, $src2}", 644 []>; 645} 646 647 648def MUL32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32i16imm:$src2), 649 "mhi\t{$dst, $src2}", 650 [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>; 651def MUL32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 652 "msfi\t{$dst, $src2}", 653 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>; 654def MUL64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 655 "mghi\t{$dst, $src2}", 656 [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>; 657def MUL64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 658 "msgfi\t{$dst, $src2}", 659 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>; 660 661def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 662 "msy\t{$dst, $src2}", 663 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>; 664def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 665 "msgy\t{$dst, $src2}", 666 [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>; 667 668def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2), 669 "msgfr\t{$dst, $src2}", 670 [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>; 671 672def SDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 673 "dr\t{$dst, $src2}", 674 []>; 675 676def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 677 "dsgr\t{$dst, $src2}", 678 []>; 679 680def UDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 681 "dlr\t{$dst, $src2}", 682 []>; 683 684def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 685 "dlgr\t{$dst, $src2}", 686 []>; 687 688} // isTwoAddress = 1 689 690//===----------------------------------------------------------------------===// 691// Shifts 692 693let isTwoAddress = 1 in 694def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 695 "srl\t{$src, $amt}", 696 [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>; 697def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 698 "srlg\t{$dst, $src, $amt}", 699 [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>; 700def SRLA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 701 "srlg\t{$dst, $src, $amt}", 702 [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>; 703 704let isTwoAddress = 1 in 705def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 706 "sll\t{$src, $amt}", 707 [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>; 708def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 709 "sllg\t{$dst, $src, $amt}", 710 [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>; 711def SHL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 712 "sllg\t{$dst, $src, $amt}", 713 [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>; 714 715 716let Defs = [PSW] in { 717let isTwoAddress = 1 in 718def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 719 "sra\t{$src, $amt}", 720 [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)), 721 (implicit PSW)]>; 722def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 723 "srag\t{$dst, $src, $amt}", 724 [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))), 725 (implicit PSW)]>; 726def SRA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 727 "srag\t{$dst, $src, $amt}", 728 [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))), 729 (implicit PSW)]>; 730} // Defs = [PSW] 731 732//===----------------------------------------------------------------------===// 733// Test instructions (like AND but do not produce any result 734 735// Integer comparisons 736let Defs = [PSW] in { 737def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2), 738 "cr\t$src1, $src2", 739 [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>; 740def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2), 741 "cgr\t$src1, $src2", 742 [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>; 743 744def CMP32ri : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2), 745 "cfi\t$src1, $src2", 746 [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>; 747def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2), 748 "cgfi\t$src1, $src2", 749 [(SystemZcmp GR64:$src1, i64immSExt32:$src2), 750 (implicit PSW)]>; 751 752def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2), 753 "cy\t$src1, $src2", 754 [(SystemZcmp GR32:$src1, (load rriaddr:$src2)), 755 (implicit PSW)]>; 756def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 757 "cg\t$src1, $src2", 758 [(SystemZcmp GR64:$src1, (load rriaddr:$src2)), 759 (implicit PSW)]>; 760 761def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2), 762 "clr\t$src1, $src2", 763 [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>; 764def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2), 765 "clgr\t$src1, $src2", 766 [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>; 767 768def UCMP32ri : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2), 769 "clfi\t$src1, $src2", 770 [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>; 771def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2), 772 "clgfi\t$src1, $src2", 773 [(SystemZucmp GR64:$src1, i64immZExt32:$src2), 774 (implicit PSW)]>; 775 776def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2), 777 "cly\t$src1, $src2", 778 [(SystemZucmp GR32:$src1, (load rriaddr:$src2)), 779 (implicit PSW)]>; 780def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 781 "clg\t$src1, $src2", 782 [(SystemZucmp GR64:$src1, (load rriaddr:$src2)), 783 (implicit PSW)]>; 784 785def CMPSX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2), 786 "cgfr\t$src1, $src2", 787 [(SystemZucmp GR64:$src1, (sext GR32:$src2)), 788 (implicit PSW)]>; 789def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2), 790 "clgfr\t$src1, $src2", 791 [(SystemZucmp GR64:$src1, (zext GR32:$src2)), 792 (implicit PSW)]>; 793 794def CMPSX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 795 "cgf\t$src1, $src2", 796 [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)), 797 (implicit PSW)]>; 798def UCMPZX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 799 "clgf\t$src1, $src2", 800 [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)), 801 (implicit PSW)]>; 802 803// FIXME: Add other crazy ucmp forms 804 805} // Defs = [PSW] 806 807//===----------------------------------------------------------------------===// 808// Non-Instruction Patterns. 809//===----------------------------------------------------------------------===// 810 811// anyext 812def : Pat<(i64 (anyext GR32:$src)), 813 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 814 815//===----------------------------------------------------------------------===// 816// Peepholes. 817//===----------------------------------------------------------------------===// 818 819// FIXME: use add/sub tricks with 32678/-32768 820 821// trunc patterns 822def : Pat<(i32 (trunc GR64:$src)), 823 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 824 825// sext_inreg patterns 826def : Pat<(sext_inreg GR64:$src, i32), 827 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 828 829// extload patterns 830def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>; 831def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>; 832def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>; 833def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>; 834def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>; 835 836// calls 837def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), 838 (CALLi tglobaladdr:$dst)>; 839def : Pat<(SystemZcall (i64 texternalsym:$dst)), 840 (CALLi texternalsym:$dst)>; 841 842// muls 843def : Pat<(mulhs GR32:$src1, GR32:$src2), 844 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 845 GR32:$src1, subreg_odd), 846 GR32:$src2), 847 subreg_even)>; 848 849def : Pat<(mulhu GR32:$src1, GR32:$src2), 850 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 851 GR32:$src1, subreg_odd), 852 GR32:$src2), 853 subreg_even)>; 854def : Pat<(mulhu GR64:$src1, GR64:$src2), 855 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 856 GR64:$src1, subreg_odd), 857 GR64:$src2), 858 subreg_even)>; 859 860// divs 861// FIXME: Add memory versions 862def : Pat<(sdiv GR32:$src1, GR32:$src2), 863 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 864 GR32:$src1, subreg_odd), 865 GR32:$src2), 866 subreg_odd)>; 867def : Pat<(sdiv GR64:$src1, GR64:$src2), 868 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 869 GR64:$src1, subreg_odd), 870 GR64:$src2), 871 subreg_odd)>; 872def : Pat<(udiv GR32:$src1, GR32:$src2), 873 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 874 GR32:$src1, subreg_odd), 875 GR32:$src2), 876 subreg_odd)>; 877def : Pat<(udiv GR64:$src1, GR64:$src2), 878 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 879 GR64:$src1, subreg_odd), 880 GR64:$src2), 881 subreg_odd)>; 882 883// rems 884// FIXME: Add memory versions 885def : Pat<(srem GR32:$src1, GR32:$src2), 886 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 887 GR32:$src1, subreg_odd), 888 GR32:$src2), 889 subreg_even)>; 890def : Pat<(srem GR64:$src1, GR64:$src2), 891 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 892 GR64:$src1, subreg_odd), 893 GR64:$src2), 894 subreg_even)>; 895def : Pat<(urem GR32:$src1, GR32:$src2), 896 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 897 GR32:$src1, subreg_odd), 898 GR32:$src2), 899 subreg_even)>; 900def : Pat<(urem GR64:$src1, GR64:$src2), 901 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 902 GR64:$src1, subreg_odd), 903 GR64:$src2), 904 subreg_even)>; 905