SystemZInstrInfo.td revision c2b840cb7c58e59c68aaa589841c41fb272df66d 
1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Stack allocation
12//===----------------------------------------------------------------------===//
13
14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15                              [(callseq_start timm:$amt)]>;
16def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17                              [(callseq_end timm:$amt1, timm:$amt2)]>;
18
19let neverHasSideEffects = 1 in {
20  // Takes as input the value of the stack pointer after a dynamic allocation
21  // has been made.  Sets the output to the address of the dynamically-
22  // allocated area itself, skipping the outgoing arguments.
23  //
24  // This expands to an LA or LAY instruction.  We restrict the offset
25  // to the range of LA and keep the LAY range in reserve for when
26  // the size of the outgoing arguments is added.
27  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28                           [(set GR64:$dst, dynalloc12only:$src)]>;
29}
30
31//===----------------------------------------------------------------------===//
32// Control flow instructions
33//===----------------------------------------------------------------------===//
34
35// A return instruction.  R1 is the condition-code mask (all 1s)
36// and R2 is the target address, which is always stored in %r14.
37let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
38    R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
39  def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
40}
41
42// Unconditional branches.  R1 is the condition-code mask (all 1s).
43let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
44  let isIndirectBranch = 1 in
45    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
46                    "br\t$R2", [(brind ADDR64:$R2)]>;
47
48  // An assembler extended mnemonic for BRC.
49  def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
50                 [(br bb:$I2)]>;
51
52  // An assembler extended mnemonic for BRCL.  (The extension is "G"
53  // rather than "L" because "JL" is "Jump if Less".)
54  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
55}
56
57// Conditional branches.  It's easier for LLVM to handle these branches
58// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
59// the first operand.  It seems friendlier to use mnemonic forms like
60// JE and JLH when writing out the assembly though.
61let isBranch = 1, isTerminator = 1, Uses = [CC] in {
62  let isCodeGenOnly = 1, CCMaskFirst = 1 in {
63    def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
64                                         brtarget16:$I2), "j$R1\t$I2",
65                     [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
66    def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
67                                           brtarget32:$I2), "jg$R1\t$I2", []>;
68  }
69  def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
70                      "brc\t$R1, $I2", []>;
71  def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
72                        "brcl\t$R1, $I2", []>;
73}
74
75// Fused compare-and-branch instructions.  As for normal branches,
76// we handle these instructions internally in their raw CRJ-like form,
77// but use assembly macros like CRJE when writing them out.
78//
79// These instructions do not use or clobber the condition codes.
80// We nevertheless pretend that they clobber CC, so that we can lower
81// them to separate comparisons and BRCLs if the branch ends up being
82// out of range.
83multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
84  let isBranch = 1, isTerminator = 1, Defs = [CC] in {
85    def RJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
86                                            brtarget16:$RI4),
87                       "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
88    def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
89                                            brtarget16:$RI4),
90                       "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
91    def IJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
92                                            brtarget16:$RI4),
93                       "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
94    def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
95                                            brtarget16:$RI4),
96                       "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
97    def LRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
98                                             brtarget16:$RI4),
99                        "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
100    def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
101                                             brtarget16:$RI4),
102                        "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
103    def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
104                                             brtarget16:$RI4),
105                        "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
106    def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
107                                             brtarget16:$RI4),
108                        "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
109  }
110}
111let isCodeGenOnly = 1 in
112  defm C : CompareBranches<cond4, "$M3", "">;
113defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
114
115// Define AsmParser mnemonics for each general condition-code mask
116// (integer or floating-point)
117multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
118  let R1 = ccmask in {
119    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
120                   "j"##name##"\t$I2", []>;
121    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
122                     "jg"##name##"\t$I2", []>;
123  }
124  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
125  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
126  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
127  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
128  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
129  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
130}
131defm AsmO   : CondExtendedMnemonic<1,  "o">;
132defm AsmH   : CondExtendedMnemonic<2,  "h">;
133defm AsmNLE : CondExtendedMnemonic<3,  "nle">;
134defm AsmL   : CondExtendedMnemonic<4,  "l">;
135defm AsmNHE : CondExtendedMnemonic<5,  "nhe">;
136defm AsmLH  : CondExtendedMnemonic<6,  "lh">;
137defm AsmNE  : CondExtendedMnemonic<7,  "ne">;
138defm AsmE   : CondExtendedMnemonic<8,  "e">;
139defm AsmNLH : CondExtendedMnemonic<9,  "nlh">;
140defm AsmHE  : CondExtendedMnemonic<10, "he">;
141defm AsmNL  : CondExtendedMnemonic<11, "nl">;
142defm AsmLE  : CondExtendedMnemonic<12, "le">;
143defm AsmNH  : CondExtendedMnemonic<13, "nh">;
144defm AsmNO  : CondExtendedMnemonic<14, "no">;
145
146// Define AsmParser mnemonics for each integer condition-code mask.
147// This is like the list above, except that condition 3 is not possible
148// and that the low bit of the mask is therefore always 0.  This means
149// that each condition has two names.  Conditions "o" and "no" are not used.
150//
151// We don't make one of the two names an alias of the other because
152// we need the custom parsing routines to select the correct register class.
153multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
154  let M3 = ccmask in {
155    def CR  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
156                                            brtarget16:$RI4),
157                       "crj"##name##"\t$R1, $R2, $RI4", []>;
158    def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
159                                            brtarget16:$RI4),
160                       "cgrj"##name##"\t$R1, $R2, $RI4", []>;
161    def CI  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
162                                            brtarget16:$RI4),
163                       "cij"##name##"\t$R1, $I2, $RI4", []>;
164    def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
165                                            brtarget16:$RI4),
166                       "cgij"##name##"\t$R1, $I2, $RI4", []>;
167    def CLR  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
168                                            brtarget16:$RI4),
169                        "clrj"##name##"\t$R1, $R2, $RI4", []>;
170    def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
171                                             brtarget16:$RI4),
172                        "clgrj"##name##"\t$R1, $R2, $RI4", []>;
173    def CLI  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
174                                             brtarget16:$RI4),
175                        "clij"##name##"\t$R1, $I2, $RI4", []>;
176    def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
177                                             brtarget16:$RI4),
178                        "clgij"##name##"\t$R1, $I2, $RI4", []>;
179  }
180}
181multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
182  : IntCondExtendedMnemonicA<ccmask, name1> {
183  let isAsmParserOnly = 1 in
184    defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
185}
186defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
187defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
188defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;
189defm AsmJE   : IntCondExtendedMnemonic<8,  "e",  "nlh">;
190defm AsmJHE  : IntCondExtendedMnemonic<10, "he", "nl">;
191defm AsmJLE  : IntCondExtendedMnemonic<12, "le", "nh">;
192
193// Decrement a register and branch if it is nonzero.  These don't clobber CC,
194// but we might need to split long branches into sequences that do.
195let Defs = [CC] in {
196  def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
197  def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
198}
199
200//===----------------------------------------------------------------------===//
201// Select instructions
202//===----------------------------------------------------------------------===//
203
204def Select32 : SelectWrapper<GR32>;
205def Select64 : SelectWrapper<GR64>;
206
207defm CondStore8_32  : CondStores<GR32, nonvolatile_truncstorei8,
208                                 nonvolatile_anyextloadi8, bdxaddr20only>;
209defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16,
210                                 nonvolatile_anyextloadi16, bdxaddr20only>;
211defm CondStore32_32 : CondStores<GR32, nonvolatile_store,
212                                 nonvolatile_load, bdxaddr20only>;
213
214defm CondStore8  : CondStores<GR64, nonvolatile_truncstorei8,
215                              nonvolatile_anyextloadi8, bdxaddr20only>;
216defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16,
217                              nonvolatile_anyextloadi16, bdxaddr20only>;
218defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32,
219                              nonvolatile_anyextloadi32, bdxaddr20only>;
220defm CondStore64 : CondStores<GR64, nonvolatile_store,
221                              nonvolatile_load, bdxaddr20only>;
222
223//===----------------------------------------------------------------------===//
224// Call instructions
225//===----------------------------------------------------------------------===//
226
227// The definitions here are for the call-clobbered registers.
228let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
229                        F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC],
230    R1 = 14, isCodeGenOnly = 1 in {
231  def BRAS  : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
232                     "bras\t%r14, $I2", []>;
233  def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
234                      "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
235  def BASR  : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
236                     "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
237}
238
239// Sibling calls.  Indirect sibling calls must be via R1, since R2 upwards
240// are argument registers and since branching to R0 is a no-op.
241let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
242    isCodeGenOnly = 1, R1 = 15 in {
243  def CallJG : InstRIL<0xC04, (outs), (ins pcrel32call:$I2),
244                       "jg\t$I2", [(z_sibcall pcrel32call:$I2)]>;
245  let R2 = 1, Uses = [R1D] in
246    def CallBR : InstRR<0x07, (outs), (ins), "br\t%r1", [(z_sibcall R1D)]>;
247}
248
249// Define the general form of the call instructions for the asm parser.
250// These instructions don't hard-code %r14 as the return address register.
251def AsmBRAS  : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
252                      "bras\t$R1, $I2", []>;
253def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
254                       "brasl\t$R1, $I2", []>;
255def AsmBASR  : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
256                      "basr\t$R1, $R2", []>;
257
258//===----------------------------------------------------------------------===//
259// Move instructions
260//===----------------------------------------------------------------------===//
261
262// Register moves.
263let neverHasSideEffects = 1 in {
264  def LR  : UnaryRR <"l",  0x18,   null_frag, GR32, GR32>;
265  def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
266}
267let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
268  def LTR  : UnaryRR <"lt",  0x12,   null_frag, GR32, GR32>;
269  def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
270}
271
272// Move on condition.
273let isCodeGenOnly = 1, Uses = [CC] in {
274  def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
275  def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
276}
277let Uses = [CC] in {
278  def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
279  def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
280}
281
282// Immediate moves.
283let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
284    isReMaterializable = 1 in {
285  // 16-bit sign-extended immediates.
286  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
287  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
288
289  // Other 16-bit immediates.
290  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
291  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
292  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
293  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
294
295  // 32-bit immediates.
296  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
297  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
298  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
299}
300
301// Register loads.
302let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
303  defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
304  def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
305
306  // These instructions are split after register allocation, so we don't
307  // want a custom inserter.
308  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
309    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
310                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
311  }
312}
313let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
314  def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
315  def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
316}
317
318let canFoldAsLoad = 1 in {
319  def LRL  : UnaryRILPC<"lrl",  0xC4D, aligned_load, GR32>;
320  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
321}
322
323// Load on condition.
324let isCodeGenOnly = 1, Uses = [CC] in {
325  def LOC  : CondUnaryRSY<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
326  def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
327}
328let Uses = [CC] in {
329  def AsmLOC  : AsmCondUnaryRSY<"loc",  0xEBF2, GR32, 4>;
330  def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
331}
332
333// Register stores.
334let SimpleBDXStore = 1 in {
335  let isCodeGenOnly = 1 in
336    defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
337  def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
338
339  // These instructions are split after register allocation, so we don't
340  // want a custom inserter.
341  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
342    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
343                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
344  }
345}
346let isCodeGenOnly = 1 in
347  def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
348def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
349
350// Store on condition.
351let isCodeGenOnly = 1, Uses = [CC] in {
352  def STOC32 : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
353  def STOC   : CondStoreRSY<"stoc",  0xEBF3, GR64, 4>;
354  def STOCG  : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
355}
356let Uses = [CC] in {
357  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
358  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
359}
360
361// 8-bit immediate stores to 8-bit fields.
362defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
363
364// 16-bit immediate stores to 16-, 32- or 64-bit fields.
365def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
366def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
367def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;
368
369// Memory-to-memory moves.
370let mayLoad = 1, mayStore = 1 in
371  defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
372
373// String moves.
374let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0W] in
375  defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
376
377//===----------------------------------------------------------------------===//
378// Sign extensions
379//===----------------------------------------------------------------------===//
380//
381// Note that putting these before zero extensions mean that we will prefer
382// them for anyextload*.  There's not really much to choose between the two
383// either way, but signed-extending loads have a short LH and a long LHY,
384// while zero-extending loads have only the long LLH.
385//
386//===----------------------------------------------------------------------===//
387
388// 32-bit extensions from registers.
389let neverHasSideEffects = 1 in {
390  def LBR : UnaryRRE<"lb", 0xB926, sext8,  GR32, GR32>;
391  def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
392}
393
394// 64-bit extensions from registers.
395let neverHasSideEffects = 1 in {
396  def LGBR : UnaryRRE<"lgb", 0xB906, sext8,  GR64, GR64>;
397  def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
398  def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
399}
400let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
401  def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
402
403// Match 32-to-64-bit sign extensions in which the source is already
404// in a 64-bit register.
405def : Pat<(sext_inreg GR64:$src, i32),
406          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
407
408// 32-bit extensions from memory.
409def  LB   : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
410defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
411def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
412
413// 64-bit extensions from memory.
414def LGB   : UnaryRXY<"lgb", 0xE377, asextloadi8,  GR64, 1>;
415def LGH   : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
416def LGF   : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
417def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
418def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
419let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
420  def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
421
422//===----------------------------------------------------------------------===//
423// Zero extensions
424//===----------------------------------------------------------------------===//
425
426// 32-bit extensions from registers.
427let neverHasSideEffects = 1 in {
428  def LLCR : UnaryRRE<"llc", 0xB994, zext8,  GR32, GR32>;
429  def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
430}
431
432// 64-bit extensions from registers.
433let neverHasSideEffects = 1 in {
434  def LLGCR : UnaryRRE<"llgc", 0xB984, zext8,  GR64, GR64>;
435  def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
436  def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
437}
438
439// Match 32-to-64-bit zero extensions in which the source is already
440// in a 64-bit register.
441def : Pat<(and GR64:$src, 0xffffffff),
442          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
443
444// 32-bit extensions from memory.
445def LLC   : UnaryRXY<"llc", 0xE394, azextloadi8,  GR32, 1>;
446def LLH   : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
447def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
448
449// 64-bit extensions from memory.
450def LLGC   : UnaryRXY<"llgc", 0xE390, azextloadi8,  GR64, 1>;
451def LLGH   : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
452def LLGF   : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
453def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
454def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
455
456//===----------------------------------------------------------------------===//
457// Truncations
458//===----------------------------------------------------------------------===//
459
460// Truncations of 64-bit registers to 32-bit registers.
461def : Pat<(i32 (trunc GR64:$src)),
462          (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
463
464// Truncations of 32-bit registers to memory.
465let isCodeGenOnly = 1 in {
466  defm STC32   : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8,  GR32, 1>;
467  defm STH32   : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
468  def  STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
469}
470
471// Truncations of 64-bit registers to memory.
472defm STC   : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8,  GR64, 1>;
473defm STH   : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64, 2>;
474def  STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
475defm ST    : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64, 4>;
476def  STRL  : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
477
478//===----------------------------------------------------------------------===//
479// Multi-register moves
480//===----------------------------------------------------------------------===//
481
482// Multi-register loads.
483def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
484
485// Multi-register stores.
486def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
487
488//===----------------------------------------------------------------------===//
489// Byte swaps
490//===----------------------------------------------------------------------===//
491
492// Byte-swapping register moves.
493let neverHasSideEffects = 1 in {
494  def LRVR  : UnaryRRE<"lrv",  0xB91F, bswap, GR32, GR32>;
495  def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
496}
497
498// Byte-swapping loads.  Unlike normal loads, these instructions are
499// allowed to access storage more than once.
500def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
501def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
502
503// Likewise byte-swapping stores.
504def STRV  : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
505def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
506                     GR64, 8>;
507
508//===----------------------------------------------------------------------===//
509// Load address instructions
510//===----------------------------------------------------------------------===//
511
512// Load BDX-style addresses.
513let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
514    DispKey = "la" in {
515  let DispSize = "12" in
516    def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
517                    "la\t$R1, $XBD2",
518                    [(set GR64:$R1, laaddr12pair:$XBD2)]>;
519  let DispSize = "20" in
520    def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
521                      "lay\t$R1, $XBD2",
522                      [(set GR64:$R1, laaddr20pair:$XBD2)]>;
523}
524
525// Load a PC-relative address.  There's no version of this instruction
526// with a 16-bit offset, so there's no relaxation.
527let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
528    isReMaterializable = 1 in {
529  def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
530                     "larl\t$R1, $I2",
531                     [(set GR64:$R1, pcrel32:$I2)]>;
532}
533
534//===----------------------------------------------------------------------===//
535// Absolute and Negation
536//===----------------------------------------------------------------------===//
537
538let Defs = [CC] in {
539  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
540    def LPR  : UnaryRR <"lp",  0x10,   z_iabs32, GR32, GR32>;
541    def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs64, GR64, GR64>;
542  }
543  let CCValues = 0xE, CompareZeroCCMask = 0xE in
544    def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
545}
546defm : SXU<z_iabs64, LPGFR>;
547
548let Defs = [CC] in {
549  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
550    def LNR  : UnaryRR <"ln",  0x11,   z_inegabs32, GR32, GR32>;
551    def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs64, GR64, GR64>;
552  }
553  let CCValues = 0xE, CompareZeroCCMask = 0xE in
554    def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
555}
556defm : SXU<z_inegabs64, LNGFR>;
557
558let Defs = [CC] in {
559  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
560    def LCR  : UnaryRR <"lc",  0x13,   ineg, GR32, GR32>;
561    def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
562  }
563  let CCValues = 0xE, CompareZeroCCMask = 0xE in
564    def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
565}
566defm : SXU<ineg, LCGFR>;
567
568//===----------------------------------------------------------------------===//
569// Insertion
570//===----------------------------------------------------------------------===//
571
572let isCodeGenOnly = 1 in
573  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
574defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
575
576defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
577defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
578
579defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
580defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
581
582// Insertions of a 16-bit immediate, leaving other bits unaffected.
583// We don't have or_as_insert equivalents of these operations because
584// OI is available instead.
585let isCodeGenOnly = 1 in {
586  def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
587  def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
588}
589def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
590def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
591def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
592def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
593
594// ...likewise for 32-bit immediates.  For GR32s this is a general
595// full-width move.  (We use IILF rather than something like LLILF
596// for 32-bit moves because IILF leaves the upper 32 bits of the
597// GR64 unchanged.)
598let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
599    isReMaterializable = 1 in {
600  def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
601}
602def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
603def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
604
605// An alternative model of inserthf, with the first operand being
606// a zero-extended value.
607def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
608          (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
609                imm64hf32:$imm)>;
610
611//===----------------------------------------------------------------------===//
612// Addition
613//===----------------------------------------------------------------------===//
614
615// Plain addition.
616let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
617  // Addition of a register.
618  let isCommutable = 1 in {
619    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
620    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
621  }
622  def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
623
624  // Addition of signed 16-bit immediates.
625  defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
626  defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
627
628  // Addition of signed 32-bit immediates.
629  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
630  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
631
632  // Addition of memory.
633  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
634  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
635  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
636  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
637
638  // Addition to memory.
639  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
640  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
641}
642defm : SXB<add, GR64, AGFR>;
643
644// Addition producing a carry.
645let Defs = [CC] in {
646  // Addition of a register.
647  let isCommutable = 1 in {
648    defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
649    defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
650  }
651  def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
652
653  // Addition of signed 16-bit immediates.
654  def ALHSIK  : BinaryRIE<"alhsik",  0xECDA, addc, GR32, imm32sx16>,
655                Requires<[FeatureDistinctOps]>;
656  def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
657                Requires<[FeatureDistinctOps]>;
658
659  // Addition of unsigned 32-bit immediates.
660  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
661  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
662
663  // Addition of memory.
664  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
665  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
666  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load, 8>;
667}
668defm : ZXB<addc, GR64, ALGFR>;
669
670// Addition producing and using a carry.
671let Defs = [CC], Uses = [CC] in {
672  // Addition of a register.
673  def ALCR  : BinaryRRE<"alc",  0xB998, adde, GR32, GR32>;
674  def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
675
676  // Addition of memory.
677  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load, 4>;
678  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
679}
680
681//===----------------------------------------------------------------------===//
682// Subtraction
683//===----------------------------------------------------------------------===//
684
685// Plain substraction.  Although immediate forms exist, we use the
686// add-immediate instruction instead.
687let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
688  // Subtraction of a register.
689  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
690  def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
691  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
692
693  // Subtraction of memory.
694  defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
695  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
696  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
697  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load, 8>;
698}
699defm : SXB<sub, GR64, SGFR>;
700
701// Subtraction producing a carry.
702let Defs = [CC] in {
703  // Subtraction of a register.
704  defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
705  def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
706  defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
707
708  // Subtraction of unsigned 32-bit immediates.  These don't match
709  // subc because we prefer addc for constants.
710  def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
711  def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
712
713  // Subtraction of memory.
714  defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
715  def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
716  def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
717}
718defm : ZXB<subc, GR64, SLGFR>;
719
720// Subtraction producing and using a carry.
721let Defs = [CC], Uses = [CC] in {
722  // Subtraction of a register.
723  def SLBR  : BinaryRRE<"slb",  0xB999, sube, GR32, GR32>;
724  def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
725
726  // Subtraction of memory.
727  def SLB  : BinaryRXY<"slb",  0xE399, sube, GR32, load, 4>;
728  def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
729}
730
731//===----------------------------------------------------------------------===//
732// AND
733//===----------------------------------------------------------------------===//
734
735let Defs = [CC] in {
736  // ANDs of a register.
737  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
738    defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
739    defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
740  }
741
742  let isConvertibleToThreeAddress = 1 in {
743    // ANDs of a 16-bit immediate, leaving other bits unaffected.
744    // The CC result only reflects the 16-bit field, not the full register.
745    let isCodeGenOnly = 1 in {
746      def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
747      def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
748    }
749    def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
750    def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
751    def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
752    def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
753
754    // ANDs of a 32-bit immediate, leaving other bits unaffected.
755    // The CC result only reflects the 32-bit field, which means we can
756    // use it as a zero indicator for i32 operations but not otherwise.
757    let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in
758      def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
759    def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
760    def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
761  }
762
763  // ANDs of memory.
764  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
765    defm N  : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
766    def  NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 
767  }
768
769  // AND to memory
770  defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
771
772  // Block AND.
773  let mayLoad = 1, mayStore = 1 in
774    defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
775}
776defm : RMWIByte<and, bdaddr12pair, NI>;
777defm : RMWIByte<and, bdaddr20pair, NIY>;
778
779//===----------------------------------------------------------------------===//
780// OR
781//===----------------------------------------------------------------------===//
782
783let Defs = [CC] in {
784  // ORs of a register.
785  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
786    defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
787    defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
788  }
789
790  // ORs of a 16-bit immediate, leaving other bits unaffected.
791  // The CC result only reflects the 16-bit field, not the full register.
792  let isCodeGenOnly = 1 in {
793    def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
794    def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
795  }
796  def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>;
797  def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>;
798  def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
799  def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
800
801  // ORs of a 32-bit immediate, leaving other bits unaffected.
802  // The CC result only reflects the 32-bit field, which means we can
803  // use it as a zero indicator for i32 operations but not otherwise.
804  let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in
805    def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
806  def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
807  def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
808
809  // ORs of memory.
810  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
811    defm O  : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
812    def  OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
813  }
814
815  // OR to memory
816  defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
817
818  // Block OR.
819  let mayLoad = 1, mayStore = 1 in
820    defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
821}
822defm : RMWIByte<or, bdaddr12pair, OI>;
823defm : RMWIByte<or, bdaddr20pair, OIY>;
824
825//===----------------------------------------------------------------------===//
826// XOR
827//===----------------------------------------------------------------------===//
828
829let Defs = [CC] in {
830  // XORs of a register.
831  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
832    defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
833    defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
834  }
835
836  // XORs of a 32-bit immediate, leaving other bits unaffected.
837  // The CC result only reflects the 32-bit field, which means we can
838  // use it as a zero indicator for i32 operations but not otherwise.
839  let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in
840    def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
841  def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
842  def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
843
844  // XORs of memory.
845  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
846    defm X  : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
847    def  XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
848  }
849
850  // XOR to memory
851  defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
852
853  // Block XOR.
854  let mayLoad = 1, mayStore = 1 in
855    defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
856}
857defm : RMWIByte<xor, bdaddr12pair, XI>;
858defm : RMWIByte<xor, bdaddr20pair, XIY>;
859
860//===----------------------------------------------------------------------===//
861// Multiplication
862//===----------------------------------------------------------------------===//
863
864// Multiplication of a register.
865let isCommutable = 1 in {
866  def MSR  : BinaryRRE<"ms",  0xB252, mul, GR32, GR32>;
867  def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
868}
869def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
870defm : SXB<mul, GR64, MSGFR>;
871
872// Multiplication of a signed 16-bit immediate.
873def MHI  : BinaryRI<"mhi",  0xA7C, mul, GR32, imm32sx16>;
874def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
875
876// Multiplication of a signed 32-bit immediate.
877def MSFI  : BinaryRIL<"msfi",  0xC21, mul, GR32, simm32>;
878def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
879
880// Multiplication of memory.
881defm MH   : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
882defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
883def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
884def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
885
886// Multiplication of a register, producing two results.
887def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
888
889// Multiplication of memory, producing two results.
890def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
891
892//===----------------------------------------------------------------------===//
893// Division and remainder
894//===----------------------------------------------------------------------===//
895
896// Division and remainder, from registers.
897def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
898def DSGR  : BinaryRRE<"dsg",  0xB90D, z_sdivrem64, GR128, GR64>;
899def DLR   : BinaryRRE<"dl",   0xB997, z_udivrem32, GR128, GR32>;
900def DLGR  : BinaryRRE<"dlg",  0xB987, z_udivrem64, GR128, GR64>;
901
902// Division and remainder, from memory.
903def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
904def DSG  : BinaryRXY<"dsg",  0xE30D, z_sdivrem64, GR128, load, 8>;
905def DL   : BinaryRXY<"dl",   0xE397, z_udivrem32, GR128, load, 4>;
906def DLG  : BinaryRXY<"dlg",  0xE387, z_udivrem64, GR128, load, 8>;
907
908//===----------------------------------------------------------------------===//
909// Shifts
910//===----------------------------------------------------------------------===//
911
912// Shift left.
913let neverHasSideEffects = 1 in {
914  defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
915  def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
916}
917
918// Logical shift right.
919let neverHasSideEffects = 1 in {
920  defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
921  def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
922}
923
924// Arithmetic shift right.
925let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
926  defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
927  def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
928}
929
930// Rotate left.
931let neverHasSideEffects = 1 in {
932  def RLL  : ShiftRSY<"rll",  0xEB1D, rotl, GR32>;
933  def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
934}
935
936// Rotate second operand left and inserted selected bits into first operand.
937// These can act like 32-bit operands provided that the constant start and
938// end bits (operands 2 and 3) are in the range [32, 64).
939let Defs = [CC] in {
940  let isCodeGenOnly = 1 in
941    def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
942  let CCValues = 0xE, CompareZeroCCMask = 0xE in
943    def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
944}
945
946// Forms of RISBG that only affect one word of the destination register.
947// They do not set CC.
948let isCodeGenOnly = 1 in
949  def RISBLG32 : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR32>,
950                 Requires<[FeatureHighWord]>;
951def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
952             Requires<[FeatureHighWord]>;
953def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
954             Requires<[FeatureHighWord]>;
955
956// Rotate second operand left and perform a logical operation with selected
957// bits of the first operand.  The CC result only describes the selected bits,
958// so isn't useful for a full comparison against zero.
959let Defs = [CC] in {
960  def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
961  def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
962  def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
963}
964
965//===----------------------------------------------------------------------===//
966// Comparison
967//===----------------------------------------------------------------------===//
968
969// Signed comparisons.  We put these before the unsigned comparisons because
970// some of the signed forms have COMPARE AND BRANCH equivalents whereas none
971// of the unsigned forms do.
972let Defs = [CC], CCValues = 0xE in {
973  // Comparison with a register.
974  def CR   : CompareRR <"c",   0x19,   z_scmp,    GR32, GR32>;
975  def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
976  def CGR  : CompareRRE<"cg",  0xB920, z_scmp,    GR64, GR64>;
977
978  // Comparison with a signed 16-bit immediate.
979  def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
980  def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
981
982  // Comparison with a signed 32-bit immediate.
983  def CFI  : CompareRIL<"cfi",  0xC2D, z_scmp, GR32, simm32>;
984  def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
985
986  // Comparison with memory.
987  defm CH    : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
988  defm C     : CompareRXPair<"c",  0x59, 0xE359, z_scmp, GR32, load, 4>;
989  def  CGH   : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
990  def  CGF   : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
991  def  CG    : CompareRXY<"cg",  0xE320, z_scmp, GR64, load, 8>;
992  def  CHRL  : CompareRILPC<"chrl",  0xC65, z_scmp, GR32, aligned_asextloadi16>;
993  def  CRL   : CompareRILPC<"crl",   0xC6D, z_scmp, GR32, aligned_load>;
994  def  CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
995  def  CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
996  def  CGRL  : CompareRILPC<"cgrl",  0xC68, z_scmp, GR64, aligned_load>;
997
998  // Comparison between memory and a signed 16-bit immediate.
999  def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1000  def CHSI  : CompareSIL<"chsi",  0xE55C, z_scmp, load, imm32sx16>;
1001  def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1002}
1003defm : SXB<z_scmp, GR64, CGFR>;
1004
1005// Unsigned comparisons.
1006let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1007  // Comparison with a register.
1008  def CLR   : CompareRR <"cl",   0x15,   z_ucmp,    GR32, GR32>;
1009  def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1010  def CLGR  : CompareRRE<"clg",  0xB921, z_ucmp,    GR64, GR64>;
1011
1012  // Comparison with a signed 32-bit immediate.
1013  def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
1014  def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1015
1016  // Comparison with memory.
1017  defm CL     : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1018  def  CLGF   : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1019  def  CLG    : CompareRXY<"clg",  0xE321, z_ucmp, GR64, load, 8>;
1020  def  CLHRL  : CompareRILPC<"clhrl",  0xC67, z_ucmp, GR32,
1021                             aligned_azextloadi16>;
1022  def  CLRL   : CompareRILPC<"clrl",   0xC6F, z_ucmp, GR32,
1023                             aligned_load>;
1024  def  CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1025                             aligned_azextloadi16>;
1026  def  CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1027                             aligned_azextloadi32>;
1028  def  CLGRL  : CompareRILPC<"clgrl",  0xC6A, z_ucmp, GR64,
1029                             aligned_load>;
1030
1031  // Comparison between memory and an unsigned 8-bit immediate.
1032  defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1033
1034  // Comparison between memory and an unsigned 16-bit immediate.
1035  def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1036  def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1037  def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1038}
1039defm : ZXB<z_ucmp, GR64, CLGFR>;
1040
1041// Memory-to-memory comparison.
1042let mayLoad = 1, Defs = [CC] in
1043  defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1044
1045// String comparison.
1046let mayLoad = 1, Defs = [CC], Uses = [R0W] in
1047  defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1048
1049// Test under mask.
1050let Defs = [CC] in {
1051  let isCodeGenOnly = 1 in {
1052    def TMLL32 : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1053    def TMLH32 : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1054  }
1055
1056  def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR64, imm64ll16>;
1057  def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR64, imm64lh16>;
1058  def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>;
1059  def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>;
1060
1061  defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1062}
1063
1064//===----------------------------------------------------------------------===//
1065// Prefetch
1066//===----------------------------------------------------------------------===//
1067
1068def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1069def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1070
1071//===----------------------------------------------------------------------===//
1072// Atomic operations
1073//===----------------------------------------------------------------------===//
1074
1075def ATOMIC_SWAPW        : AtomicLoadWBinaryReg<z_atomic_swapw>;
1076def ATOMIC_SWAP_32      : AtomicLoadBinaryReg32<atomic_swap_32>;
1077def ATOMIC_SWAP_64      : AtomicLoadBinaryReg64<atomic_swap_64>;
1078
1079def ATOMIC_LOADW_AR     : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1080def ATOMIC_LOADW_AFI    : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1081def ATOMIC_LOAD_AR      : AtomicLoadBinaryReg32<atomic_load_add_32>;
1082def ATOMIC_LOAD_AHI     : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1083def ATOMIC_LOAD_AFI     : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1084def ATOMIC_LOAD_AGR     : AtomicLoadBinaryReg64<atomic_load_add_64>;
1085def ATOMIC_LOAD_AGHI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1086def ATOMIC_LOAD_AGFI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1087
1088def ATOMIC_LOADW_SR     : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1089def ATOMIC_LOAD_SR      : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1090def ATOMIC_LOAD_SGR     : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1091
1092def ATOMIC_LOADW_NR     : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1093def ATOMIC_LOADW_NILH   : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1094def ATOMIC_LOAD_NR      : AtomicLoadBinaryReg32<atomic_load_and_32>;
1095def ATOMIC_LOAD_NILL32  : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
1096def ATOMIC_LOAD_NILH32  : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
1097def ATOMIC_LOAD_NILF32  : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1098def ATOMIC_LOAD_NGR     : AtomicLoadBinaryReg64<atomic_load_and_64>;
1099def ATOMIC_LOAD_NILL    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
1100def ATOMIC_LOAD_NILH    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
1101def ATOMIC_LOAD_NIHL    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
1102def ATOMIC_LOAD_NIHH    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
1103def ATOMIC_LOAD_NILF    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
1104def ATOMIC_LOAD_NIHF    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
1105
1106def ATOMIC_LOADW_OR     : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1107def ATOMIC_LOADW_OILH   : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1108def ATOMIC_LOAD_OR      : AtomicLoadBinaryReg32<atomic_load_or_32>;
1109def ATOMIC_LOAD_OILL32  : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1110def ATOMIC_LOAD_OILH32  : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1111def ATOMIC_LOAD_OILF32  : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1112def ATOMIC_LOAD_OGR     : AtomicLoadBinaryReg64<atomic_load_or_64>;
1113def ATOMIC_LOAD_OILL    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1114def ATOMIC_LOAD_OILH    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1115def ATOMIC_LOAD_OIHL    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1116def ATOMIC_LOAD_OIHH    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1117def ATOMIC_LOAD_OILF    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1118def ATOMIC_LOAD_OIHF    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1119
1120def ATOMIC_LOADW_XR     : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1121def ATOMIC_LOADW_XILF   : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1122def ATOMIC_LOAD_XR      : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1123def ATOMIC_LOAD_XILF32  : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1124def ATOMIC_LOAD_XGR     : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1125def ATOMIC_LOAD_XILF    : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1126def ATOMIC_LOAD_XIHF    : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1127
1128def ATOMIC_LOADW_NRi    : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1129def ATOMIC_LOADW_NILHi  : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1130                                               imm32lh16c>;
1131def ATOMIC_LOAD_NRi     : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1132def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
1133                                                imm32ll16c>;
1134def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
1135                                                imm32lh16c>;
1136def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1137def ATOMIC_LOAD_NGRi    : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1138def ATOMIC_LOAD_NILLi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1139                                                imm64ll16c>;
1140def ATOMIC_LOAD_NILHi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1141                                                imm64lh16c>;
1142def ATOMIC_LOAD_NIHLi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1143                                                imm64hl16c>;
1144def ATOMIC_LOAD_NIHHi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1145                                                imm64hh16c>;
1146def ATOMIC_LOAD_NILFi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1147                                                imm64lf32c>;
1148def ATOMIC_LOAD_NIHFi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1149                                                imm64hf32c>;
1150
1151def ATOMIC_LOADW_MIN    : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1152def ATOMIC_LOAD_MIN_32  : AtomicLoadBinaryReg32<atomic_load_min_32>;
1153def ATOMIC_LOAD_MIN_64  : AtomicLoadBinaryReg64<atomic_load_min_64>;
1154
1155def ATOMIC_LOADW_MAX    : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1156def ATOMIC_LOAD_MAX_32  : AtomicLoadBinaryReg32<atomic_load_max_32>;
1157def ATOMIC_LOAD_MAX_64  : AtomicLoadBinaryReg64<atomic_load_max_64>;
1158
1159def ATOMIC_LOADW_UMIN   : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1160def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1161def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1162
1163def ATOMIC_LOADW_UMAX   : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1164def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1165def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1166
1167def ATOMIC_CMP_SWAPW
1168  : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1169                                  ADDR32:$bitshift, ADDR32:$negbitshift,
1170                                  uimm32:$bitsize),
1171           [(set GR32:$dst,
1172                 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1173                                     ADDR32:$bitshift, ADDR32:$negbitshift,
1174                                     uimm32:$bitsize))]> {
1175  let Defs = [CC];
1176  let mayLoad = 1;
1177  let mayStore = 1;
1178  let usesCustomInserter = 1;
1179}
1180
1181let Defs = [CC] in {
1182  defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1183  def  CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1184}
1185
1186//===----------------------------------------------------------------------===//
1187// Miscellaneous Instructions.
1188//===----------------------------------------------------------------------===//
1189
1190// Extract CC into bits 29 and 28 of a register.
1191let Uses = [CC] in
1192  def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1193
1194// Read a 32-bit access register into a GR32.  As with all GR32 operations,
1195// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1196// when a 64-bit address is stored in a pair of access registers.
1197def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1198                  "ear\t$R1, $R2",
1199                  [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1200
1201// Find leftmost one, AKA count leading zeros.  The instruction actually
1202// returns a pair of GR64s, the first giving the number of leading zeros
1203// and the second giving a copy of the source with the leftmost one bit
1204// cleared.  We only use the first result here.
1205let Defs = [CC] in {
1206  def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1207}
1208def : Pat<(ctlz GR64:$src),
1209          (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
1210
1211// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1212def : Pat<(i64 (anyext GR32:$src)),
1213          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1214
1215// Extend GR32s and GR64s to GR128s.
1216let usesCustomInserter = 1 in {
1217  def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1218  def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1219  def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1220}
1221
1222// Search a block of memory for a character.
1223let mayLoad = 1, Defs = [CC], Uses = [R0W] in
1224  defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1225
1226//===----------------------------------------------------------------------===//
1227// Peepholes.
1228//===----------------------------------------------------------------------===//
1229
1230// Use AL* for GR64 additions of unsigned 32-bit values.
1231defm : ZXB<add, GR64, ALGFR>;
1232def  : Pat<(add GR64:$src1, imm64zx32:$src2),
1233           (ALGFI GR64:$src1, imm64zx32:$src2)>;
1234def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1235           (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1236
1237// Use SL* for GR64 subtractions of unsigned 32-bit values.
1238defm : ZXB<sub, GR64, SLGFR>;
1239def  : Pat<(add GR64:$src1, imm64zx32n:$src2),
1240           (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1241def  : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1242           (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1243
1244// Optimize sign-extended 1/0 selects to -1/0 selects.  This is important
1245// for vector legalization.
1246def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1247                         (i32 31)),
1248                    (i32 31)),
1249          (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1250def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1251                                                       uimm8zx4:$cc)))),
1252                    (i32 63)),
1253               (i32 63)),
1254          (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1255
1256// Peepholes for turning scalar operations into block operations.
1257defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1258                      XCSequence, 1>;
1259defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1260                      XCSequence, 2>;
1261defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1262                      XCSequence, 4>;
1263defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1264                      OCSequence, XCSequence, 1>;
1265defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1266                      XCSequence, 2>;
1267defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1268                      XCSequence, 4>;
1269defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
1270                      XCSequence, 8>;
1271