SystemZInstrInfo.td revision d3ba2f286d15f6725f4c43aba77888cfb5d44ac0
1//===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SystemZ instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14include "SystemZInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// Type Constraints. 18//===----------------------------------------------------------------------===// 19class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; 20class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; 21class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>; 22class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>; 23 24//===----------------------------------------------------------------------===// 25// Type Profiles. 26//===----------------------------------------------------------------------===// 27def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>; 29def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>; 30def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 31def SDT_BrCond : SDTypeProfile<0, 2, 32 [SDTCisVT<0, OtherVT>, 33 SDTCisI8<1>]>; 34def SDT_SelectCC : SDTypeProfile<1, 3, 35 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 36 SDTCisI8<3>]>; 37def SDT_Address : SDTypeProfile<1, 1, 38 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 39 40//===----------------------------------------------------------------------===// 41// SystemZ Specific Node Definitions. 42//===----------------------------------------------------------------------===// 43def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 44 [SDNPHasChain, SDNPOptInFlag]>; 45def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall, 46 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; 47def SystemZcallseq_start : 48 SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart, 49 [SDNPHasChain, SDNPOutFlag]>; 50def SystemZcallseq_end : 51 SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd, 52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 53def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>; 54def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>; 55def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond, 56 [SDNPHasChain, SDNPInFlag]>; 57def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>; 58def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>; 59 60//===----------------------------------------------------------------------===// 61// Instruction Pattern Stuff. 62//===----------------------------------------------------------------------===// 63 64// SystemZ specific condition code. These correspond to CondCode in 65// SystemZ.h. They must be kept in synch. 66def SYSTEMZ_COND_E : PatLeaf<(i8 0)>; 67def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>; 68def SYSTEMZ_COND_H : PatLeaf<(i8 2)>; 69def SYSTEMZ_COND_L : PatLeaf<(i8 3)>; 70def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>; 71def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>; 72 73def LL16 : SDNodeXForm<imm, [{ 74 // Transformation function: return low 16 bits. 75 return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL); 76}]>; 77 78def LH16 : SDNodeXForm<imm, [{ 79 // Transformation function: return bits 16-31. 80 return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16); 81}]>; 82 83def HL16 : SDNodeXForm<imm, [{ 84 // Transformation function: return bits 32-47. 85 return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32); 86}]>; 87 88def HH16 : SDNodeXForm<imm, [{ 89 // Transformation function: return bits 48-63. 90 return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48); 91}]>; 92 93def LO32 : SDNodeXForm<imm, [{ 94 // Transformation function: return low 32 bits. 95 return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL); 96}]>; 97 98def HI32 : SDNodeXForm<imm, [{ 99 // Transformation function: return bits 32-63. 100 return getI32Imm(N->getZExtValue() >> 32); 101}]>; 102 103def i64ll16 : PatLeaf<(imm), [{ 104 // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16 105 // bits set. 106 return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue()); 107}], LL16>; 108 109def i64lh16 : PatLeaf<(imm), [{ 110 // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set. 111 return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue()); 112}], LH16>; 113 114def i64hl16 : PatLeaf<(i64 imm), [{ 115 // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set. 116 return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue()); 117}], HL16>; 118 119def i64hh16 : PatLeaf<(i64 imm), [{ 120 // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set. 121 return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue()); 122}], HH16>; 123 124def immSExt16 : PatLeaf<(imm), [{ 125 // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended 126 // field. 127 if (N->getValueType(0) == MVT::i64) { 128 uint64_t val = N->getZExtValue(); 129 return ((int64_t)val == (int16_t)val); 130 } else if (N->getValueType(0) == MVT::i32) { 131 uint32_t val = N->getZExtValue(); 132 return ((int32_t)val == (int16_t)val); 133 } 134 135 return false; 136}]>; 137 138def immSExt32 : PatLeaf<(i64 imm), [{ 139 // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended 140 // field. 141 uint64_t val = N->getZExtValue(); 142 return ((int64_t)val == (int32_t)val); 143}]>; 144 145def i64lo32 : PatLeaf<(i64 imm), [{ 146 // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32 147 // bits set. 148 return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue()); 149}], LO32>; 150 151def i64hi32 : PatLeaf<(i64 imm), [{ 152 // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set. 153 return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue()); 154}], HI32>; 155 156def i32immSExt8 : PatLeaf<(i32 imm), [{ 157 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit 158 // sign extended field. 159 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); 160}]>; 161 162def i32immSExt16 : PatLeaf<(i32 imm), [{ 163 // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit 164 // sign extended field. 165 return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue(); 166}]>; 167 168def i64immSExt32 : PatLeaf<(i64 imm), [{ 169 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit 170 // sign extended field. 171 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue(); 172}]>; 173 174def i64immZExt32 : PatLeaf<(i64 imm), [{ 175 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 176 // zero extended field. 177 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue(); 178}]>; 179 180// extloads 181def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 182def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 183def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 184def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 185def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 186 187def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 188def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 189def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 190def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 191def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 192 193def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 194def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 195def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 196def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 197def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 198 199// A couple of more descriptive operand definitions. 200// 32-bits but only 8 bits are significant. 201def i32i8imm : Operand<i32>; 202// 32-bits but only 16 bits are significant. 203def i32i16imm : Operand<i32>; 204// 64-bits but only 32 bits are significant. 205def i64i32imm : Operand<i64>; 206// Branch targets have OtherVT type. 207def brtarget : Operand<OtherVT>; 208// Signed i16 209def s16imm : Operand<i32> { 210 let PrintMethod = "printS16ImmOperand"; 211} 212def s16imm64 : Operand<i64> { 213 let PrintMethod = "printS16ImmOperand"; 214} 215// Signed i32 216def s32imm : Operand<i32> { 217 let PrintMethod = "printS32ImmOperand"; 218} 219def s32imm64 : Operand<i64> { 220 let PrintMethod = "printS32ImmOperand"; 221} 222 223//===----------------------------------------------------------------------===// 224// SystemZ Operand Definitions. 225//===----------------------------------------------------------------------===// 226 227// Address operands 228 229// riaddr := reg + imm 230def riaddr32 : Operand<i32>, 231 ComplexPattern<i32, 2, "SelectAddrRI", []> { 232 let PrintMethod = "printRIAddrOperand"; 233 let MIOperandInfo = (ops ADDR32:$base, i32imm:$disp); 234} 235 236def riaddr : Operand<i64>, 237 ComplexPattern<i64, 2, "SelectAddrRI", []> { 238 let PrintMethod = "printRIAddrOperand"; 239 let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp); 240} 241 242//===----------------------------------------------------------------------===// 243 244// rriaddr := reg + reg + imm 245def rriaddr : Operand<i64>, 246 ComplexPattern<i64, 3, "SelectAddrRRI", [], []> { 247 let PrintMethod = "printRRIAddrOperand"; 248 let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index); 249} 250def laaddr : Operand<i64>, 251 ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> { 252 let PrintMethod = "printRRIAddrOperand"; 253 let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index); 254} 255 256//===----------------------------------------------------------------------===// 257// Instruction list.. 258 259def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 260 "#ADJCALLSTACKDOWN", 261 [(SystemZcallseq_start timm:$amt)]>; 262def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 263 "#ADJCALLSTACKUP", 264 [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>; 265 266let usesCustomDAGSchedInserter = 1 in { 267 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc), 268 "# Select32 PSEUDO", 269 [(set GR32:$dst, 270 (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>; 271 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc), 272 "# Select64 PSEUDO", 273 [(set GR64:$dst, 274 (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>; 275} 276 277 278//===----------------------------------------------------------------------===// 279// Control Flow Instructions... 280// 281 282// FIXME: Provide proper encoding! 283let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { 284 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>; 285} 286 287let isBranch = 1, isTerminator = 1 in { 288 let isBarrier = 1 in 289 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>; 290 291 let Uses = [PSW] in { 292 def JE : Pseudo<(outs), (ins brtarget:$dst), 293 "je\t$dst", 294 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>; 295 def JNE : Pseudo<(outs), (ins brtarget:$dst), 296 "jne\t$dst", 297 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>; 298 def JH : Pseudo<(outs), (ins brtarget:$dst), 299 "jh\t$dst", 300 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>; 301 def JL : Pseudo<(outs), (ins brtarget:$dst), 302 "jl\t$dst", 303 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>; 304 def JHE : Pseudo<(outs), (ins brtarget:$dst), 305 "jhe\t$dst", 306 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>; 307 def JLE : Pseudo<(outs), (ins brtarget:$dst), 308 "jle\t$dst", 309 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>; 310 311 } // Uses = [PSW] 312} // isBranch = 1 313 314//===----------------------------------------------------------------------===// 315// Call Instructions... 316// 317 318let isCall = 1 in 319 // All calls clobber the non-callee saved registers (except R14 which we 320 // handle separately). Uses for argument registers are added manually. 321 let Defs = [R0D, R1D, R2D, R3D, R4D, R5D] in { 322 def CALLi : Pseudo<(outs), (ins i64imm:$dst, variable_ops), 323 "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>; 324 def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops), 325 "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>; 326 } 327 328//===----------------------------------------------------------------------===// 329// Miscellaneous Instructions. 330// 331 332let isReMaterializable = 1 in 333// FIXME: Provide imm12 variant 334def LA64r : Pseudo<(outs GR64:$dst), (ins laaddr:$src), 335 "lay\t{$dst, $src}", 336 [(set GR64:$dst, laaddr:$src)]>; 337def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 338 "larl\t{$dst, $src}", 339 [(set GR64:$dst, 340 (SystemZpcrelwrapper tglobaladdr:$src))]>; 341 342let neverHasSideEffects = 1 in 343def NOP : Pseudo<(outs), (ins), "# no-op", []>; 344 345//===----------------------------------------------------------------------===// 346// Move Instructions 347 348// FIXME: Provide proper encoding! 349let neverHasSideEffects = 1 in { 350def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src), 351 "lr\t{$dst, $src}", 352 []>; 353def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src), 354 "lgr\t{$dst, $src}", 355 []>; 356def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src), 357 "# MOV128 PSEUDO!" 358 "lgr\t{$dst:subreg_odd, $src:subreg_odd}\n" 359 "lgr\t{$dst:subreg_even, $src:subreg_even}", 360 []>; 361def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src), 362 "# MOV64P PSEUDO!" 363 "lr\t{$dst:subreg_odd, $src:subreg_odd}\n" 364 "lr\t{$dst:subreg_even, $src:subreg_even}", 365 []>; 366} 367 368def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src), 369 "lgfr\t{$dst, $src}", 370 [(set GR64:$dst, (sext GR32:$src))]>; 371def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src), 372 "llgfr\t{$dst, $src}", 373 [(set GR64:$dst, (zext GR32:$src))]>; 374 375// FIXME: Provide proper encoding! 376let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 377def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src), 378 "lhi\t{$dst, $src}", 379 [(set GR32:$dst, immSExt16:$src)]>; 380def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src), 381 "lghi\t{$dst, $src}", 382 [(set GR64:$dst, immSExt16:$src)]>; 383 384def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 385 "llill\t{$dst, $src}", 386 [(set GR64:$dst, i64ll16:$src)]>; 387def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 388 "llilh\t{$dst, $src}", 389 [(set GR64:$dst, i64lh16:$src)]>; 390def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 391 "llihl\t{$dst, $src}", 392 [(set GR64:$dst, i64hl16:$src)]>; 393def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 394 "llihh\t{$dst, $src}", 395 [(set GR64:$dst, i64hh16:$src)]>; 396// FIXME: these 3 instructions seem to require extimm facility 397def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src), 398 "lgfi\t{$dst, $src}", 399 [(set GR64:$dst, immSExt32:$src)]>; 400def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 401 "llilf\t{$dst, $src}", 402 [(set GR64:$dst, i64lo32:$src)]>; 403def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 404 "llihf\t{$dst, $src}", 405 [(set GR64:$dst, i64hi32:$src)]>; 406} 407 408let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { 409def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 410 "ly\t{$dst, $src}", 411 [(set GR32:$dst, (load rriaddr:$src))]>; 412def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 413 "lg\t{$dst, $src}", 414 [(set GR64:$dst, (load rriaddr:$src))]>; 415 416} 417 418def MOV32mr : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 419 "sty\t{$src, $dst}", 420 [(store GR32:$src, rriaddr:$dst)]>; 421def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 422 "stg\t{$src, $dst}", 423 [(store GR64:$src, rriaddr:$dst)]>; 424 425// FIXME: displacements here are really 12 bit, not 20! 426def MOV8mi : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src), 427 "mviy\t{$dst, $src}", 428 [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>; 429def MOV16mi : Pseudo<(outs), (ins riaddr:$dst, s16imm:$src), 430 "mvhhi\t{$dst, $src}", 431 [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>; 432def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm:$src), 433 "mvhi\t{$dst, $src}", 434 [(store (i32 immSExt16:$src), riaddr:$dst)]>; 435def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm64:$src), 436 "mvghi\t{$dst, $src}", 437 [(store (i64 immSExt16:$src), riaddr:$dst)]>; 438 439// sexts 440def MOVSX32rr8 : Pseudo<(outs GR32:$dst), (ins GR32:$src), 441 "lbr\t{$dst, $src}", 442 [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>; 443def MOVSX64rr8 : Pseudo<(outs GR64:$dst), (ins GR64:$src), 444 "lgbr\t{$dst, $src}", 445 [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>; 446def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src), 447 "lhr\t{$dst, $src}", 448 [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>; 449def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src), 450 "lghr\t{$dst, $src}", 451 [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>; 452 453// extloads 454def MOVSX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 455 "lb\t{$dst, $src}", 456 [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>; 457def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 458 "lhy\t{$dst, $src}", 459 [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>; 460def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 461 "lgb\t{$dst, $src}", 462 [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>; 463def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 464 "lgh\t{$dst, $src}", 465 [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>; 466def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 467 "lgf\t{$dst, $src}", 468 [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>; 469 470def MOVZX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 471 "llc\t{$dst, $src}", 472 [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>; 473def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 474 "llh\t{$dst, $src}", 475 [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>; 476def MOVZX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 477 "llgc\t{$dst, $src}", 478 [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>; 479def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 480 "llgh\t{$dst, $src}", 481 [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>; 482def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 483 "llgf\t{$dst, $src}", 484 [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>; 485 486// truncstores 487// FIXME: Implement 12-bit displacement stuff someday 488def MOV32m8r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 489 "stcy\t{$src, $dst}", 490 [(truncstorei8 GR32:$src, rriaddr:$dst)]>; 491 492def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 493 "sthy\t{$src, $dst}", 494 [(truncstorei16 GR32:$src, rriaddr:$dst)]>; 495 496def MOV64m8r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 497 "stcy\t{$src, $dst}", 498 [(truncstorei8 GR64:$src, rriaddr:$dst)]>; 499 500def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 501 "sthy\t{$src, $dst}", 502 [(truncstorei16 GR64:$src, rriaddr:$dst)]>; 503 504def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 505 "sty\t{$src, $dst}", 506 [(truncstorei32 GR64:$src, rriaddr:$dst)]>; 507 508// multiple regs moves 509// FIXME: should we use multiple arg nodes? 510def MOV32mrm : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to), 511 "stmy\t{$from, $to, $dst}", 512 []>; 513def MOV64mrm : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to), 514 "stmg\t{$from, $to, $dst}", 515 []>; 516def MOV32rmm : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst), 517 "lmy\t{$from, $to, $dst}", 518 []>; 519def MOV64rmm : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst), 520 "lmg\t{$from, $to, $dst}", 521 []>; 522 523 524//===----------------------------------------------------------------------===// 525// Arithmetic Instructions 526 527let isTwoAddress = 1 in { 528 529let Defs = [PSW] in { 530 531let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y 532// FIXME: Provide proper encoding! 533def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 534 "ar\t{$dst, $src2}", 535 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), 536 (implicit PSW)]>; 537def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 538 "agr\t{$dst, $src2}", 539 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)), 540 (implicit PSW)]>; 541} 542 543// FIXME: Provide proper encoding! 544def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2), 545 "ahi\t{$dst, $src2:}", 546 [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)), 547 (implicit PSW)]>; 548def ADD32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 549 "afi\t{$dst, $src2}", 550 [(set GR32:$dst, (add GR32:$src1, imm:$src2)), 551 (implicit PSW)]>; 552def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2), 553 "aghi\t{$dst, $src2}", 554 [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)), 555 (implicit PSW)]>; 556def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 557 "agfi\t{$dst, $src2}", 558 [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)), 559 (implicit PSW)]>; 560 561let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y 562// FIXME: Provide proper encoding! 563def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 564 "nr\t{$dst, $src2}", 565 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; 566def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 567 "ngr\t{$dst, $src2}", 568 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>; 569} 570 571// FIXME: Provide proper encoding! 572def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 573 "nill\t{$dst, $src2}", 574 [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>; 575def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 576 "nilh\t{$dst, $src2}", 577 [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>; 578def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 579 "nihl\t{$dst, $src2}", 580 [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>; 581def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 582 "nihh\t{$dst, $src2}", 583 [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>; 584// FIXME: these 2 instructions seem to require extimm facility 585def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 586 "nilf\t{$dst, $src2}", 587 [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>; 588def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 589 "nihf\t{$dst, $src2}", 590 [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>; 591 592let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y 593// FIXME: Provide proper encoding! 594def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 595 "or\t{$dst, $src2}", 596 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; 597def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 598 "ogr\t{$dst, $src2}", 599 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; 600} 601 602def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2), 603 "oill\t{$dst, $src2}", 604 [(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>; 605def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2), 606 "oilh\t{$dst, $src2}", 607 [(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>; 608def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 609 "oilf\t{$dst, $src2}", 610 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; 611 612def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 613 "oill\t{$dst, $src2}", 614 [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>; 615def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 616 "oilh\t{$dst, $src2}", 617 [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>; 618def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 619 "oihl\t{$dst, $src2}", 620 [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>; 621def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 622 "oihh\t{$dst, $src2}", 623 [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>; 624// FIXME: these 2 instructions seem to require extimm facility 625def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 626 "oilf\t{$dst, $src2}", 627 [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>; 628def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 629 "oihf\t{$dst, $src2}", 630 [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>; 631 632// FIXME: Provide proper encoding! 633def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 634 "sr\t{$dst, $src2}", 635 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; 636def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 637 "sgr\t{$dst, $src2}", 638 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>; 639 640 641let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y 642// FIXME: Provide proper encoding! 643def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 644 "xr\t{$dst, $src2}", 645 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; 646def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 647 "xgr\t{$dst, $src2}", 648 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; 649} 650 651def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 652 "xilf\t{$dst, $src2}", 653 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; 654 655// FIXME: these 2 instructions seem to require extimm facility 656def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 657 "xilf\t{$dst, $src2}", 658 [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>; 659def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 660 "xihf\t{$dst, $src2}", 661 [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>; 662 663} // Defs = [PSW] 664 665let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y 666def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 667 "msr\t{$dst, $src2}", 668 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>; 669def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 670 "msgr\t{$dst, $src2}", 671 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>; 672 673def MUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 674 "mr\t{$dst, $src2}", 675 []>; 676def UMUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 677 "mlr\t{$dst, $src2}", 678 []>; 679def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 680 "mlgr\t{$dst, $src2}", 681 []>; 682} 683 684 685def MUL32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2), 686 "mhi\t{$dst, $src2}", 687 [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>; 688def MUL32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 689 "msfi\t{$dst, $src2}", 690 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>; 691def MUL64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2), 692 "mghi\t{$dst, $src2}", 693 [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>; 694def MUL64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 695 "msgfi\t{$dst, $src2}", 696 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>; 697 698def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 699 "msy\t{$dst, $src2}", 700 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>; 701def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 702 "msgy\t{$dst, $src2}", 703 [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>; 704 705def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2), 706 "msgfr\t{$dst, $src2}", 707 [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>; 708 709def SDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 710 "dr\t{$dst, $src2}", 711 []>; 712 713def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 714 "dsgr\t{$dst, $src2}", 715 []>; 716 717def UDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 718 "dlr\t{$dst, $src2}", 719 []>; 720 721def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 722 "dlgr\t{$dst, $src2}", 723 []>; 724 725} // isTwoAddress = 1 726 727//===----------------------------------------------------------------------===// 728// Shifts 729 730let isTwoAddress = 1 in 731def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 732 "srl\t{$src, $amt}", 733 [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>; 734def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 735 "srlg\t{$dst, $src, $amt}", 736 [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>; 737def SRLA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 738 "srlg\t{$dst, $src, $amt}", 739 [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>; 740 741let isTwoAddress = 1 in 742def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 743 "sll\t{$src, $amt}", 744 [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>; 745def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 746 "sllg\t{$dst, $src, $amt}", 747 [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>; 748def SHL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 749 "sllg\t{$dst, $src, $amt}", 750 [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>; 751 752 753let Defs = [PSW] in { 754let isTwoAddress = 1 in 755def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 756 "sra\t{$src, $amt}", 757 [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)), 758 (implicit PSW)]>; 759def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 760 "srag\t{$dst, $src, $amt}", 761 [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))), 762 (implicit PSW)]>; 763def SRA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 764 "srag\t{$dst, $src, $amt}", 765 [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))), 766 (implicit PSW)]>; 767} // Defs = [PSW] 768 769//===----------------------------------------------------------------------===// 770// Test instructions (like AND but do not produce any result 771 772// Integer comparisons 773let Defs = [PSW] in { 774def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2), 775 "cr\t$src1, $src2", 776 [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>; 777def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2), 778 "cgr\t$src1, $src2", 779 [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>; 780 781def CMP32ri : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2), 782 "cfi\t$src1, $src2", 783 [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>; 784def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2), 785 "cgfi\t$src1, $src2", 786 [(SystemZcmp GR64:$src1, i64immSExt32:$src2), 787 (implicit PSW)]>; 788 789def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2), 790 "cy\t$src1, $src2", 791 [(SystemZcmp GR32:$src1, (load rriaddr:$src2)), 792 (implicit PSW)]>; 793def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 794 "cg\t$src1, $src2", 795 [(SystemZcmp GR64:$src1, (load rriaddr:$src2)), 796 (implicit PSW)]>; 797 798def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2), 799 "clr\t$src1, $src2", 800 [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>; 801def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2), 802 "clgr\t$src1, $src2", 803 [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>; 804 805def UCMP32ri : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2), 806 "clfi\t$src1, $src2", 807 [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>; 808def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2), 809 "clgfi\t$src1, $src2", 810 [(SystemZucmp GR64:$src1, i64immZExt32:$src2), 811 (implicit PSW)]>; 812 813def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2), 814 "cly\t$src1, $src2", 815 [(SystemZucmp GR32:$src1, (load rriaddr:$src2)), 816 (implicit PSW)]>; 817def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 818 "clg\t$src1, $src2", 819 [(SystemZucmp GR64:$src1, (load rriaddr:$src2)), 820 (implicit PSW)]>; 821 822def CMPSX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2), 823 "cgfr\t$src1, $src2", 824 [(SystemZucmp GR64:$src1, (sext GR32:$src2)), 825 (implicit PSW)]>; 826def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2), 827 "clgfr\t$src1, $src2", 828 [(SystemZucmp GR64:$src1, (zext GR32:$src2)), 829 (implicit PSW)]>; 830 831def CMPSX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 832 "cgf\t$src1, $src2", 833 [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)), 834 (implicit PSW)]>; 835def UCMPZX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 836 "clgf\t$src1, $src2", 837 [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)), 838 (implicit PSW)]>; 839 840// FIXME: Add other crazy ucmp forms 841 842} // Defs = [PSW] 843 844//===----------------------------------------------------------------------===// 845// Non-Instruction Patterns. 846//===----------------------------------------------------------------------===// 847 848// anyext 849def : Pat<(i64 (anyext GR32:$src)), 850 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 851 852//===----------------------------------------------------------------------===// 853// Peepholes. 854//===----------------------------------------------------------------------===// 855 856// FIXME: use add/sub tricks with 32678/-32768 857 858// trunc patterns 859def : Pat<(i32 (trunc GR64:$src)), 860 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 861 862// sext_inreg patterns 863def : Pat<(sext_inreg GR64:$src, i32), 864 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 865 866// extload patterns 867def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>; 868def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>; 869def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>; 870def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>; 871def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>; 872 873// calls 874def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), 875 (CALLi tglobaladdr:$dst)>; 876def : Pat<(SystemZcall (i64 texternalsym:$dst)), 877 (CALLi texternalsym:$dst)>; 878 879// muls 880def : Pat<(mulhs GR32:$src1, GR32:$src2), 881 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 882 GR32:$src1, subreg_odd), 883 GR32:$src2), 884 subreg_even)>; 885 886def : Pat<(mulhu GR32:$src1, GR32:$src2), 887 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 888 GR32:$src1, subreg_odd), 889 GR32:$src2), 890 subreg_even)>; 891def : Pat<(mulhu GR64:$src1, GR64:$src2), 892 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 893 GR64:$src1, subreg_odd), 894 GR64:$src2), 895 subreg_even)>; 896 897// divs 898// FIXME: Add memory versions 899def : Pat<(sdiv GR32:$src1, GR32:$src2), 900 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 901 GR32:$src1, subreg_odd), 902 GR32:$src2), 903 subreg_odd)>; 904def : Pat<(sdiv GR64:$src1, GR64:$src2), 905 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 906 GR64:$src1, subreg_odd), 907 GR64:$src2), 908 subreg_odd)>; 909def : Pat<(udiv GR32:$src1, GR32:$src2), 910 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 911 GR32:$src1, subreg_odd), 912 GR32:$src2), 913 subreg_odd)>; 914def : Pat<(udiv GR64:$src1, GR64:$src2), 915 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 916 GR64:$src1, subreg_odd), 917 GR64:$src2), 918 subreg_odd)>; 919 920// rems 921// FIXME: Add memory versions 922def : Pat<(srem GR32:$src1, GR32:$src2), 923 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 924 GR32:$src1, subreg_odd), 925 GR32:$src2), 926 subreg_even)>; 927def : Pat<(srem GR64:$src1, GR64:$src2), 928 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 929 GR64:$src1, subreg_odd), 930 GR64:$src2), 931 subreg_even)>; 932def : Pat<(urem GR32:$src1, GR32:$src2), 933 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 934 GR32:$src1, subreg_odd), 935 GR32:$src2), 936 subreg_even)>; 937def : Pat<(urem GR64:$src1, GR64:$src2), 938 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 939 GR64:$src1, subreg_odd), 940 GR64:$src2), 941 subreg_even)>; 942 943def : Pat<(i32 imm:$src), 944 (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>; 945