SystemZInstrInfo.td revision db92fb07169af6941dfe47439f9849d370f0eb0b
1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 15 [(callseq_start timm:$amt)]>; 16def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_end timm:$amt1, timm:$amt2)]>; 18 19let neverHasSideEffects = 1 in { 20 // Takes as input the value of the stack pointer after a dynamic allocation 21 // has been made. Sets the output to the address of the dynamically- 22 // allocated area itself, skipping the outgoing arguments. 23 // 24 // This expands to an LA or LAY instruction. We restrict the offset 25 // to the range of LA and keep the LAY range in reserve for when 26 // the size of the outgoing arguments is added. 27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 28 [(set GR64:$dst, dynalloc12only:$src)]>; 29} 30 31//===----------------------------------------------------------------------===// 32// Control flow instructions 33//===----------------------------------------------------------------------===// 34 35// A return instruction. R1 is the condition-code mask (all 1s) 36// and R2 is the target address, which is always stored in %r14. 37let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1, 38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in { 39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>; 40} 41 42// Unconditional branches. R1 is the condition-code mask (all 1s). 43let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { 44 let isIndirectBranch = 1 in 45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), 46 "br\t$R2", [(brind ADDR64:$R2)]>; 47 48 // An assembler extended mnemonic for BRC. 49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", 50 [(br bb:$I2)]>; 51 52 // An assembler extended mnemonic for BRCL. (The extension is "G" 53 // rather than "L" because "JL" is "Jump if Less".) 54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>; 55} 56 57// Conditional branches. It's easier for LLVM to handle these branches 58// in their raw BRC/BRCL form, with the 4-bit condition-code mask being 59// the first operand. It seems friendlier to use mnemonic forms like 60// JE and JLH when writing out the assembly though. 61// 62// Using a custom inserter for BRC gives us a chance to convert the BRC 63// and a preceding compare into a single compare-and-branch instruction. 64// The inserter makes no change in cases where a separate branch really 65// is needed. 66multiclass CondBranches<Operand ccmask, string short, string long> { 67 let isBranch = 1, isTerminator = 1, Uses = [CC] in { 68 def "" : InstRI<0xA74, (outs), (ins ccmask:$R1, brtarget16:$I2), short, []>; 69 def L : InstRIL<0xC04, (outs), (ins ccmask:$R1, brtarget32:$I2), long, []>; 70 } 71} 72let isCodeGenOnly = 1, usesCustomInserter = 1 in 73 defm BRC : CondBranches<cond4, "j$R1\t$I2", "jg$R1\t$I2">; 74defm AsmBRC : CondBranches<uimm8zx4, "brc\t$R1, $I2", "brcl\t$R1, $I2">; 75 76def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRC cond4:$cond, bb:$dst)>; 77 78// Fused compare-and-branch instructions. As for normal branches, 79// we handle these instructions internally in their raw CRJ-like form, 80// but use assembly macros like CRJE when writing them out. 81// 82// These instructions do not use or clobber the condition codes. 83// We nevertheless pretend that they clobber CC, so that we can lower 84// them to separate comparisons and BRCLs if the branch ends up being 85// out of range. 86multiclass CompareBranches<Operand ccmask, string pos1, string pos2> { 87 let isBranch = 1, isTerminator = 1, Defs = [CC] in { 88 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 89 brtarget16:$RI4), 90 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 91 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 92 brtarget16:$RI4), 93 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 94 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 95 brtarget16:$RI4), 96 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 97 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 98 brtarget16:$RI4), 99 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 100 } 101} 102let isCodeGenOnly = 1 in 103 defm C : CompareBranches<cond4, "$M3", "">; 104defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">; 105 106// Define AsmParser mnemonics for each general condition-code mask 107// (integer or floating-point) 108multiclass CondExtendedMnemonic<bits<4> ccmask, string name> { 109 let R1 = ccmask in { 110 def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2), 111 "j"##name##"\t$I2", []>; 112 def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2), 113 "jg"##name##"\t$I2", []>; 114 } 115} 116defm AsmJO : CondExtendedMnemonic<1, "o">; 117defm AsmJH : CondExtendedMnemonic<2, "h">; 118defm AsmJNLE : CondExtendedMnemonic<3, "nle">; 119defm AsmJL : CondExtendedMnemonic<4, "l">; 120defm AsmJNHE : CondExtendedMnemonic<5, "nhe">; 121defm AsmJLH : CondExtendedMnemonic<6, "lh">; 122defm AsmJNE : CondExtendedMnemonic<7, "ne">; 123defm AsmJE : CondExtendedMnemonic<8, "e">; 124defm AsmJNLH : CondExtendedMnemonic<9, "nlh">; 125defm AsmJHE : CondExtendedMnemonic<10, "he">; 126defm AsmJNL : CondExtendedMnemonic<11, "nl">; 127defm AsmJLE : CondExtendedMnemonic<12, "le">; 128defm AsmJNH : CondExtendedMnemonic<13, "nh">; 129defm AsmJNO : CondExtendedMnemonic<14, "no">; 130 131// Define AsmParser mnemonics for each integer condition-code mask. 132// This is like the list above, except that condition 3 is not possible 133// and that the low bit of the mask is therefore always 0. This means 134// that each condition has two names. Conditions "o" and "no" are not used. 135// 136// We don't make one of the two names an alias of the other because 137// we need the custom parsing routines to select the correct register class. 138multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> { 139 let M3 = ccmask in { 140 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, 141 brtarget16:$RI4), 142 "crj"##name##"\t$R1, $R2, $RI4", []>; 143 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, 144 brtarget16:$RI4), 145 "cgrj"##name##"\t$R1, $R2, $RI4", []>; 146 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, 147 brtarget16:$RI4), 148 "cij"##name##"\t$R1, $I2, $RI4", []>; 149 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, 150 brtarget16:$RI4), 151 "cgij"##name##"\t$R1, $I2, $RI4", []>; 152 } 153} 154multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 155 : IntCondExtendedMnemonicA<ccmask, name1> { 156 let isAsmParserOnly = 1 in 157 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>; 158} 159defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">; 160defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">; 161defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">; 162defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">; 163defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">; 164defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">; 165 166//===----------------------------------------------------------------------===// 167// Select instructions 168//===----------------------------------------------------------------------===// 169 170def Select32 : SelectWrapper<GR32>; 171def Select64 : SelectWrapper<GR64>; 172 173defm CondStore8_32 : CondStores<GR32, nonvolatile_truncstorei8, 174 nonvolatile_anyextloadi8, bdxaddr20only>; 175defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16, 176 nonvolatile_anyextloadi16, bdxaddr20only>; 177defm CondStore32_32 : CondStores<GR32, nonvolatile_store, 178 nonvolatile_load, bdxaddr20only>; 179 180defm CondStore8 : CondStores<GR64, nonvolatile_truncstorei8, 181 nonvolatile_anyextloadi8, bdxaddr20only>; 182defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16, 183 nonvolatile_anyextloadi16, bdxaddr20only>; 184defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32, 185 nonvolatile_anyextloadi32, bdxaddr20only>; 186defm CondStore64 : CondStores<GR64, nonvolatile_store, 187 nonvolatile_load, bdxaddr20only>; 188 189//===----------------------------------------------------------------------===// 190// Call instructions 191//===----------------------------------------------------------------------===// 192 193// The definitions here are for the call-clobbered registers. 194let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D, 195 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D], 196 R1 = 14, isCodeGenOnly = 1 in { 197 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops), 198 "bras\t%r14, $I2", []>; 199 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops), 200 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>; 201 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops), 202 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>; 203} 204 205// Define the general form of the call instructions for the asm parser. 206// These instructions don't hard-code %r14 as the return address register. 207def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2), 208 "bras\t$R1, $I2", []>; 209def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2), 210 "brasl\t$R1, $I2", []>; 211def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), 212 "basr\t$R1, $R2", []>; 213 214//===----------------------------------------------------------------------===// 215// Move instructions 216//===----------------------------------------------------------------------===// 217 218// Register moves. 219let neverHasSideEffects = 1 in { 220 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>; 221 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>; 222} 223 224// Immediate moves. 225let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 226 isReMaterializable = 1 in { 227 // 16-bit sign-extended immediates. 228 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 229 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 230 231 // Other 16-bit immediates. 232 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 233 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 234 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 235 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 236 237 // 32-bit immediates. 238 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 239 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 240 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 241} 242 243// Register loads. 244let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 245 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 246 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 247 248 // These instructions are split after register allocation, so we don't 249 // want a custom inserter. 250 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 251 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 252 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 253 } 254} 255let canFoldAsLoad = 1 in { 256 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 257 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 258} 259 260// Register stores. 261let SimpleBDXStore = 1 in { 262 let isCodeGenOnly = 1 in 263 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 264 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 265 266 // These instructions are split after register allocation, so we don't 267 // want a custom inserter. 268 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 269 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 270 [(store GR128:$src, bdxaddr20only128:$dst)]>; 271 } 272} 273let isCodeGenOnly = 1 in 274 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 275def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 276 277// 8-bit immediate stores to 8-bit fields. 278defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 279 280// 16-bit immediate stores to 16-, 32- or 64-bit fields. 281def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 282def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 283def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 284 285// Memory-to-memory moves. 286let mayLoad = 1, mayStore = 1 in 287 def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1, 288 bdaddr12only:$BD2), 289 "mvc\t$BDL1, $BD2", []>; 290 291let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in 292 def MVCWrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 293 imm32len8:$length), 294 [(z_mvc bdaddr12only:$dest, bdaddr12only:$src, 295 imm32len8:$length)]>; 296 297defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32, 298 MVCWrapper, 1>; 299defm LoadStore16_32 : MVCLoadStore<anyextloadi16, truncstorei16, i32, 300 MVCWrapper, 2>; 301defm LoadStore32_32 : MVCLoadStore<load, store, i32, MVCWrapper, 4>; 302 303defm LoadStore8 : MVCLoadStore<anyextloadi8, truncstorei8, i64, 304 MVCWrapper, 1>; 305defm LoadStore16 : MVCLoadStore<anyextloadi16, truncstorei16, i64, 306 MVCWrapper, 2>; 307defm LoadStore32 : MVCLoadStore<anyextloadi32, truncstorei32, i64, 308 MVCWrapper, 4>; 309defm LoadStore64 : MVCLoadStore<load, store, i64, MVCWrapper, 8>; 310 311//===----------------------------------------------------------------------===// 312// Sign extensions 313//===----------------------------------------------------------------------===// 314 315// 32-bit extensions from registers. 316let neverHasSideEffects = 1 in { 317 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>; 318 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>; 319} 320 321// 64-bit extensions from registers. 322let neverHasSideEffects = 1 in { 323 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>; 324 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>; 325 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>; 326} 327 328// Match 32-to-64-bit sign extensions in which the source is already 329// in a 64-bit register. 330def : Pat<(sext_inreg GR64:$src, i32), 331 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 332 333// 32-bit extensions from memory. 334def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32, 1>; 335defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32, 2>; 336def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>; 337 338// 64-bit extensions from memory. 339def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64, 1>; 340def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64, 2>; 341def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64, 4>; 342def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>; 343def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>; 344 345// If the sign of a load-extend operation doesn't matter, use the signed ones. 346// There's not really much to choose between the sign and zero extensions, 347// but LH is more compact than LLH for small offsets. 348def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>; 349def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>; 350def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>; 351 352def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>; 353def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>; 354def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>; 355 356// We want PC-relative addresses to be tried ahead of BD and BDX addresses. 357// However, BDXs have two extra operands and are therefore 6 units more 358// complex. 359let AddedComplexity = 7 in { 360 def : Pat<(i32 (extloadi16 pcrel32:$src)), (LHRL pcrel32:$src)>; 361 def : Pat<(i64 (extloadi16 pcrel32:$src)), (LGHRL pcrel32:$src)>; 362} 363 364//===----------------------------------------------------------------------===// 365// Zero extensions 366//===----------------------------------------------------------------------===// 367 368// 32-bit extensions from registers. 369let neverHasSideEffects = 1 in { 370 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>; 371 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>; 372} 373 374// 64-bit extensions from registers. 375let neverHasSideEffects = 1 in { 376 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>; 377 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>; 378 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>; 379} 380 381// Match 32-to-64-bit zero extensions in which the source is already 382// in a 64-bit register. 383def : Pat<(and GR64:$src, 0xffffffff), 384 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 385 386// 32-bit extensions from memory. 387def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32, 1>; 388def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32, 2>; 389def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>; 390 391// 64-bit extensions from memory. 392def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64, 1>; 393def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64, 2>; 394def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64, 4>; 395def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>; 396def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>; 397 398//===----------------------------------------------------------------------===// 399// Truncations 400//===----------------------------------------------------------------------===// 401 402// Truncations of 64-bit registers to 32-bit registers. 403def : Pat<(i32 (trunc GR64:$src)), 404 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 405 406// Truncations of 32-bit registers to memory. 407let isCodeGenOnly = 1 in { 408 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 409 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 410 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 411} 412 413// Truncations of 64-bit registers to memory. 414defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64, 1>; 415defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64, 2>; 416def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>; 417defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64, 4>; 418def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>; 419 420//===----------------------------------------------------------------------===// 421// Multi-register moves 422//===----------------------------------------------------------------------===// 423 424// Multi-register loads. 425def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 426 427// Multi-register stores. 428def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 429 430//===----------------------------------------------------------------------===// 431// Byte swaps 432//===----------------------------------------------------------------------===// 433 434// Byte-swapping register moves. 435let neverHasSideEffects = 1 in { 436 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>; 437 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>; 438} 439 440// Byte-swapping loads. Unlike normal loads, these instructions are 441// allowed to access storage more than once. 442def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>; 443def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>; 444 445// Likewise byte-swapping stores. 446def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>; 447def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>, 448 GR64, 8>; 449 450//===----------------------------------------------------------------------===// 451// Load address instructions 452//===----------------------------------------------------------------------===// 453 454// Load BDX-style addresses. 455let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, 456 DispKey = "la" in { 457 let DispSize = "12" in 458 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2), 459 "la\t$R1, $XBD2", 460 [(set GR64:$R1, laaddr12pair:$XBD2)]>; 461 let DispSize = "20" in 462 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2), 463 "lay\t$R1, $XBD2", 464 [(set GR64:$R1, laaddr20pair:$XBD2)]>; 465} 466 467// Load a PC-relative address. There's no version of this instruction 468// with a 16-bit offset, so there's no relaxation. 469let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 470 isReMaterializable = 1 in { 471 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2), 472 "larl\t$R1, $I2", 473 [(set GR64:$R1, pcrel32:$I2)]>; 474} 475 476//===----------------------------------------------------------------------===// 477// Negation 478//===----------------------------------------------------------------------===// 479 480let Defs = [CC] in { 481 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>; 482 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>; 483 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>; 484} 485defm : SXU<ineg, LCGFR>; 486 487//===----------------------------------------------------------------------===// 488// Insertion 489//===----------------------------------------------------------------------===// 490 491let isCodeGenOnly = 1 in 492 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8, 1>; 493defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8, 1>; 494 495defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>; 496defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>; 497 498defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>; 499defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>; 500 501// Insertions of a 16-bit immediate, leaving other bits unaffected. 502// We don't have or_as_insert equivalents of these operations because 503// OI is available instead. 504let isCodeGenOnly = 1 in { 505 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 506 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 507} 508def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>; 509def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>; 510def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>; 511def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>; 512 513// ...likewise for 32-bit immediates. For GR32s this is a general 514// full-width move. (We use IILF rather than something like LLILF 515// for 32-bit moves because IILF leaves the upper 32 bits of the 516// GR64 unchanged.) 517let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 518 isReMaterializable = 1 in { 519 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 520} 521def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>; 522def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>; 523 524// An alternative model of inserthf, with the first operand being 525// a zero-extended value. 526def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 527 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit), 528 imm64hf32:$imm)>; 529 530//===----------------------------------------------------------------------===// 531// Addition 532//===----------------------------------------------------------------------===// 533 534// Plain addition. 535let Defs = [CC] in { 536 // Addition of a register. 537 let isCommutable = 1 in { 538 def AR : BinaryRR <"a", 0x1A, add, GR32, GR32>; 539 def AGR : BinaryRRE<"ag", 0xB908, add, GR64, GR64>; 540 } 541 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>; 542 543 // Addition of signed 16-bit immediates. 544 def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>; 545 def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>; 546 547 // Addition of signed 32-bit immediates. 548 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 549 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 550 551 // Addition of memory. 552 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16, 2>; 553 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 554 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32, 4>; 555 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 556 557 // Addition to memory. 558 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 559 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 560} 561defm : SXB<add, GR64, AGFR>; 562 563// Addition producing a carry. 564let Defs = [CC] in { 565 // Addition of a register. 566 let isCommutable = 1 in { 567 def ALR : BinaryRR <"al", 0x1E, addc, GR32, GR32>; 568 def ALGR : BinaryRRE<"alg", 0xB90A, addc, GR64, GR64>; 569 } 570 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>; 571 572 // Addition of unsigned 32-bit immediates. 573 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 574 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 575 576 // Addition of memory. 577 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 578 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32, 4>; 579 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 580} 581defm : ZXB<addc, GR64, ALGFR>; 582 583// Addition producing and using a carry. 584let Defs = [CC], Uses = [CC] in { 585 // Addition of a register. 586 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>; 587 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>; 588 589 // Addition of memory. 590 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 591 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 592} 593 594//===----------------------------------------------------------------------===// 595// Subtraction 596//===----------------------------------------------------------------------===// 597 598// Plain substraction. Although immediate forms exist, we use the 599// add-immediate instruction instead. 600let Defs = [CC] in { 601 // Subtraction of a register. 602 def SR : BinaryRR <"s", 0x1B, sub, GR32, GR32>; 603 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>; 604 def SGR : BinaryRRE<"sg", 0xB909, sub, GR64, GR64>; 605 606 // Subtraction of memory. 607 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>; 608 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 609 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32, 4>; 610 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 611} 612defm : SXB<sub, GR64, SGFR>; 613 614// Subtraction producing a carry. 615let Defs = [CC] in { 616 // Subtraction of a register. 617 def SLR : BinaryRR <"sl", 0x1F, subc, GR32, GR32>; 618 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>; 619 def SLGR : BinaryRRE<"slg", 0xB90B, subc, GR64, GR64>; 620 621 // Subtraction of unsigned 32-bit immediates. These don't match 622 // subc because we prefer addc for constants. 623 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 624 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 625 626 // Subtraction of memory. 627 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 628 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32, 4>; 629 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 630} 631defm : ZXB<subc, GR64, SLGFR>; 632 633// Subtraction producing and using a carry. 634let Defs = [CC], Uses = [CC] in { 635 // Subtraction of a register. 636 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>; 637 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>; 638 639 // Subtraction of memory. 640 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 641 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 642} 643 644//===----------------------------------------------------------------------===// 645// AND 646//===----------------------------------------------------------------------===// 647 648let Defs = [CC] in { 649 // ANDs of a register. 650 let isCommutable = 1 in { 651 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>; 652 def NGR : BinaryRRE<"ng", 0xB980, and, GR64, GR64>; 653 } 654 655 // ANDs of a 16-bit immediate, leaving other bits unaffected. 656 let isCodeGenOnly = 1 in { 657 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 658 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 659 } 660 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>; 661 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>; 662 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>; 663 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>; 664 665 // ANDs of a 32-bit immediate, leaving other bits unaffected. 666 let isCodeGenOnly = 1 in 667 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 668 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>; 669 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>; 670 671 // ANDs of memory. 672 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 673 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 674 675 // AND to memory 676 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>; 677} 678defm : RMWIByte<and, bdaddr12pair, NI>; 679defm : RMWIByte<and, bdaddr20pair, NIY>; 680 681//===----------------------------------------------------------------------===// 682// OR 683//===----------------------------------------------------------------------===// 684 685let Defs = [CC] in { 686 // ORs of a register. 687 let isCommutable = 1 in { 688 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>; 689 def OGR : BinaryRRE<"og", 0xB981, or, GR64, GR64>; 690 } 691 692 // ORs of a 16-bit immediate, leaving other bits unaffected. 693 let isCodeGenOnly = 1 in { 694 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 695 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 696 } 697 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>; 698 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>; 699 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>; 700 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>; 701 702 // ORs of a 32-bit immediate, leaving other bits unaffected. 703 let isCodeGenOnly = 1 in 704 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 705 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>; 706 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>; 707 708 // ORs of memory. 709 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 710 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 711 712 // OR to memory 713 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>; 714} 715defm : RMWIByte<or, bdaddr12pair, OI>; 716defm : RMWIByte<or, bdaddr20pair, OIY>; 717 718//===----------------------------------------------------------------------===// 719// XOR 720//===----------------------------------------------------------------------===// 721 722let Defs = [CC] in { 723 // XORs of a register. 724 let isCommutable = 1 in { 725 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>; 726 def XGR : BinaryRRE<"xg", 0xB982, xor, GR64, GR64>; 727 } 728 729 // XORs of a 32-bit immediate, leaving other bits unaffected. 730 let isCodeGenOnly = 1 in 731 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 732 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>; 733 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>; 734 735 // XORs of memory. 736 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 737 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 738 739 // XOR to memory 740 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>; 741} 742defm : RMWIByte<xor, bdaddr12pair, XI>; 743defm : RMWIByte<xor, bdaddr20pair, XIY>; 744 745//===----------------------------------------------------------------------===// 746// Multiplication 747//===----------------------------------------------------------------------===// 748 749// Multiplication of a register. 750let isCommutable = 1 in { 751 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>; 752 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>; 753} 754def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>; 755defm : SXB<mul, GR64, MSGFR>; 756 757// Multiplication of a signed 16-bit immediate. 758def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 759def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 760 761// Multiplication of a signed 32-bit immediate. 762def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 763def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 764 765// Multiplication of memory. 766defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16, 2>; 767defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 768def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32, 4>; 769def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 770 771// Multiplication of a register, producing two results. 772def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>; 773 774// Multiplication of memory, producing two results. 775def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>; 776 777//===----------------------------------------------------------------------===// 778// Division and remainder 779//===----------------------------------------------------------------------===// 780 781// Division and remainder, from registers. 782def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>; 783def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>; 784def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>; 785def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>; 786 787// Division and remainder, from memory. 788def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>; 789def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>; 790def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>; 791def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>; 792 793//===----------------------------------------------------------------------===// 794// Shifts 795//===----------------------------------------------------------------------===// 796 797// Shift left. 798let neverHasSideEffects = 1 in { 799 defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 800 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>; 801} 802 803// Logical shift right. 804let neverHasSideEffects = 1 in { 805 defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 806 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>; 807} 808 809// Arithmetic shift right. 810let Defs = [CC] in { 811 defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 812 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>; 813} 814 815// Rotate left. 816let neverHasSideEffects = 1 in { 817 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>; 818 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>; 819} 820 821// Rotate second operand left and inserted selected bits into first operand. 822// These can act like 32-bit operands provided that the constant start and 823// end bits (operands 2 and 3) are in the range [32, 64) 824let Defs = [CC] in { 825 let isCodeGenOnly = 1 in 826 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 827 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 828} 829 830// Rotate second operand left and perform a logical operation with selected 831// bits of the first operand. 832let Defs = [CC] in { 833 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 834 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 835 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 836} 837 838//===----------------------------------------------------------------------===// 839// Comparison 840//===----------------------------------------------------------------------===// 841 842// Signed comparisons. 843let Defs = [CC] in { 844 // Comparison with a register. 845 def CR : CompareRR <"c", 0x19, z_cmp, GR32, GR32>; 846 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>; 847 def CGR : CompareRRE<"cg", 0xB920, z_cmp, GR64, GR64>; 848 849 // Comparison with a signed 16-bit immediate. 850 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>; 851 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>; 852 853 // Comparison with a signed 32-bit immediate. 854 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>; 855 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>; 856 857 // Comparison with memory. 858 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16, 2>; 859 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load, 4>; 860 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16, 2>; 861 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32, 4>; 862 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load, 8>; 863 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>; 864 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>; 865 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>; 866 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>; 867 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>; 868 869 // Comparison between memory and a signed 16-bit immediate. 870 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>; 871 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>; 872 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>; 873} 874defm : SXB<z_cmp, GR64, CGFR>; 875 876// Unsigned comparisons. 877let Defs = [CC] in { 878 // Comparison with a register. 879 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>; 880 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>; 881 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>; 882 883 // Comparison with a signed 32-bit immediate. 884 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 885 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 886 887 // Comparison with memory. 888 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 889 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32, 4>; 890 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 891 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 892 aligned_zextloadi16>; 893 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 894 aligned_load>; 895 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 896 aligned_zextloadi16>; 897 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 898 aligned_zextloadi32>; 899 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 900 aligned_load>; 901 902 // Comparison between memory and an unsigned 8-bit immediate. 903 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>; 904 905 // Comparison between memory and an unsigned 16-bit immediate. 906 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>; 907 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 908 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 909} 910defm : ZXB<z_ucmp, GR64, CLGFR>; 911 912//===----------------------------------------------------------------------===// 913// Atomic operations 914//===----------------------------------------------------------------------===// 915 916def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 917def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 918def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 919 920def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 921def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 922def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 923def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 924def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 925def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 926def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 927def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 928 929def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 930def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 931def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 932 933def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 934def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 935def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 936def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>; 937def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>; 938def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 939def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 940def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>; 941def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>; 942def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>; 943def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>; 944def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>; 945def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>; 946 947def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 948def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 949def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 950def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 951def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 952def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 953def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 954def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 955def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 956def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 957def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 958def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 959def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 960 961def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 962def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 963def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 964def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 965def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 966def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 967def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 968 969def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 970def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 971 imm32lh16c>; 972def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 973def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 974 imm32ll16c>; 975def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 976 imm32lh16c>; 977def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 978def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 979def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 980 imm64ll16c>; 981def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 982 imm64lh16c>; 983def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 984 imm64hl16c>; 985def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 986 imm64hh16c>; 987def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 988 imm64lf32c>; 989def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 990 imm64hf32c>; 991 992def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 993def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 994def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 995 996def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 997def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 998def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 999 1000def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1001def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1002def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1003 1004def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1005def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1006def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1007 1008def ATOMIC_CMP_SWAPW 1009 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1010 ADDR32:$bitshift, ADDR32:$negbitshift, 1011 uimm32:$bitsize), 1012 [(set GR32:$dst, 1013 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1014 ADDR32:$bitshift, ADDR32:$negbitshift, 1015 uimm32:$bitsize))]> { 1016 let Defs = [CC]; 1017 let mayLoad = 1; 1018 let mayStore = 1; 1019 let usesCustomInserter = 1; 1020} 1021 1022let Defs = [CC] in { 1023 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1024 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1025} 1026 1027//===----------------------------------------------------------------------===// 1028// Miscellaneous Instructions. 1029//===----------------------------------------------------------------------===// 1030 1031// Read a 32-bit access register into a GR32. As with all GR32 operations, 1032// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1033// when a 64-bit address is stored in a pair of access registers. 1034def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2), 1035 "ear\t$R1, $R2", 1036 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>; 1037 1038// Find leftmost one, AKA count leading zeros. The instruction actually 1039// returns a pair of GR64s, the first giving the number of leading zeros 1040// and the second giving a copy of the source with the leftmost one bit 1041// cleared. We only use the first result here. 1042let Defs = [CC] in { 1043 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>; 1044} 1045def : Pat<(ctlz GR64:$src), 1046 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>; 1047 1048// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 1049def : Pat<(i64 (anyext GR32:$src)), 1050 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 1051 1052// There are no 32-bit equivalents of LLILL and LLILH, so use a full 1053// 64-bit move followed by a subreg. This preserves the invariant that 1054// all GR32 operations only modify the low 32 bits. 1055def : Pat<(i32 imm32ll16:$src), 1056 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>; 1057def : Pat<(i32 imm32lh16:$src), 1058 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>; 1059 1060// Extend GR32s and GR64s to GR128s. 1061let usesCustomInserter = 1 in { 1062 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1063 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 1064 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1065} 1066 1067//===----------------------------------------------------------------------===// 1068// Peepholes. 1069//===----------------------------------------------------------------------===// 1070 1071// Use AL* for GR64 additions of unsigned 32-bit values. 1072defm : ZXB<add, GR64, ALGFR>; 1073def : Pat<(add GR64:$src1, imm64zx32:$src2), 1074 (ALGFI GR64:$src1, imm64zx32:$src2)>; 1075def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 1076 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 1077 1078// Use SL* for GR64 subtractions of unsigned 32-bit values. 1079defm : ZXB<sub, GR64, SLGFR>; 1080def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1081 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1082def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 1083 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 1084 1085// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 1086// for vector legalization. 1087def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm:$cc)), (i32 31)), (i32 31)), 1088 (Select32 (LHI -1), (LHI 0), imm:$cc)>; 1089def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm:$cc)))), 1090 (i32 63)), 1091 (i32 63)), 1092 (Select64 (LGHI -1), (LGHI 0), imm:$cc)>; 1093