SystemZInstrInfo.td revision fff1ff91915a613c0c23a5bbf7acb4694654d694 
1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Stack allocation
12//===----------------------------------------------------------------------===//
13
14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15                              [(callseq_start timm:$amt)]>;
16def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17                              [(callseq_end timm:$amt1, timm:$amt2)]>;
18
19let neverHasSideEffects = 1 in {
20  // Takes as input the value of the stack pointer after a dynamic allocation
21  // has been made.  Sets the output to the address of the dynamically-
22  // allocated area itself, skipping the outgoing arguments.
23  //
24  // This expands to an LA or LAY instruction.  We restrict the offset
25  // to the range of LA and keep the LAY range in reserve for when
26  // the size of the outgoing arguments is added.
27  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28                           [(set GR64:$dst, dynalloc12only:$src)]>;
29}
30
31//===----------------------------------------------------------------------===//
32// Control flow instructions
33//===----------------------------------------------------------------------===//
34
35// A return instruction (br %r14).
36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37  def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
38
39// Unconditional branches.  R1 is the condition-code mask (all 1s).
40let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41  let isIndirectBranch = 1 in
42    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43                    "br\t$R2", [(brind ADDR64:$R2)]>;
44
45  // An assembler extended mnemonic for BRC.
46  def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
47                 [(br bb:$I2)]>;
48
49  // An assembler extended mnemonic for BRCL.  (The extension is "G"
50  // rather than "L" because "JL" is "Jump if Less".)
51  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
52}
53
54// Conditional branches.  It's easier for LLVM to handle these branches
55// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56// the first operand.  It seems friendlier to use mnemonic forms like
57// JE and JLH when writing out the assembly though.
58let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59  let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60    def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61                                         brtarget16:$I2), "j$R1\t$I2",
62                     [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63    def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64                                           brtarget32:$I2), "jg$R1\t$I2", []>;
65  }
66  def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
67                      "brc\t$R1, $I2", []>;
68  def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
69                        "brcl\t$R1, $I2", []>;
70  def AsmBCR : InstRR<0x07, (outs), (ins uimm8zx4:$R1, GR64:$R2),
71                      "bcr\t$R1, $R2", []>;
72}
73
74// Fused compare-and-branch instructions.  As for normal branches,
75// we handle these instructions internally in their raw CRJ-like form,
76// but use assembly macros like CRJE when writing them out.
77//
78// These instructions do not use or clobber the condition codes.
79// We nevertheless pretend that they clobber CC, so that we can lower
80// them to separate comparisons and BRCLs if the branch ends up being
81// out of range.
82multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
83  let isBranch = 1, isTerminator = 1, Defs = [CC] in {
84    def RJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
85                                            brtarget16:$RI4),
86                       "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
87    def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
88                                            brtarget16:$RI4),
89                       "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
90    def IJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
91                                            brtarget16:$RI4),
92                       "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
93    def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
94                                            brtarget16:$RI4),
95                       "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
96    def LRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
97                                             brtarget16:$RI4),
98                        "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
99    def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
100                                             brtarget16:$RI4),
101                        "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
102    def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
103                                             brtarget16:$RI4),
104                        "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
105    def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
106                                             brtarget16:$RI4),
107                        "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
108  }
109}
110let isCodeGenOnly = 1 in
111  defm C : CompareBranches<cond4, "$M3", "">;
112defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
113
114// Define AsmParser mnemonics for each general condition-code mask
115// (integer or floating-point)
116multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
117  let R1 = ccmask in {
118    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
119                   "j"##name##"\t$I2", []>;
120    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
121                     "jg"##name##"\t$I2", []>;
122    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>;
123  }
124  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
125  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
126  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
127  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
128  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
129  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
130}
131defm AsmO   : CondExtendedMnemonic<1,  "o">;
132defm AsmH   : CondExtendedMnemonic<2,  "h">;
133defm AsmNLE : CondExtendedMnemonic<3,  "nle">;
134defm AsmL   : CondExtendedMnemonic<4,  "l">;
135defm AsmNHE : CondExtendedMnemonic<5,  "nhe">;
136defm AsmLH  : CondExtendedMnemonic<6,  "lh">;
137defm AsmNE  : CondExtendedMnemonic<7,  "ne">;
138defm AsmE   : CondExtendedMnemonic<8,  "e">;
139defm AsmNLH : CondExtendedMnemonic<9,  "nlh">;
140defm AsmHE  : CondExtendedMnemonic<10, "he">;
141defm AsmNL  : CondExtendedMnemonic<11, "nl">;
142defm AsmLE  : CondExtendedMnemonic<12, "le">;
143defm AsmNH  : CondExtendedMnemonic<13, "nh">;
144defm AsmNO  : CondExtendedMnemonic<14, "no">;
145
146// Define AsmParser mnemonics for each integer condition-code mask.
147// This is like the list above, except that condition 3 is not possible
148// and that the low bit of the mask is therefore always 0.  This means
149// that each condition has two names.  Conditions "o" and "no" are not used.
150//
151// We don't make one of the two names an alias of the other because
152// we need the custom parsing routines to select the correct register class.
153multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
154  let M3 = ccmask in {
155    def CR  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
156                                            brtarget16:$RI4),
157                       "crj"##name##"\t$R1, $R2, $RI4", []>;
158    def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
159                                            brtarget16:$RI4),
160                       "cgrj"##name##"\t$R1, $R2, $RI4", []>;
161    def CI  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
162                                            brtarget16:$RI4),
163                       "cij"##name##"\t$R1, $I2, $RI4", []>;
164    def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
165                                            brtarget16:$RI4),
166                       "cgij"##name##"\t$R1, $I2, $RI4", []>;
167    def CLR  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
168                                            brtarget16:$RI4),
169                        "clrj"##name##"\t$R1, $R2, $RI4", []>;
170    def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
171                                             brtarget16:$RI4),
172                        "clgrj"##name##"\t$R1, $R2, $RI4", []>;
173    def CLI  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
174                                             brtarget16:$RI4),
175                        "clij"##name##"\t$R1, $I2, $RI4", []>;
176    def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
177                                             brtarget16:$RI4),
178                        "clgij"##name##"\t$R1, $I2, $RI4", []>;
179  }
180}
181multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
182  : IntCondExtendedMnemonicA<ccmask, name1> {
183  let isAsmParserOnly = 1 in
184    defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
185}
186defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
187defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
188defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;
189defm AsmJE   : IntCondExtendedMnemonic<8,  "e",  "nlh">;
190defm AsmJHE  : IntCondExtendedMnemonic<10, "he", "nl">;
191defm AsmJLE  : IntCondExtendedMnemonic<12, "le", "nh">;
192
193// Decrement a register and branch if it is nonzero.  These don't clobber CC,
194// but we might need to split long branches into sequences that do.
195let Defs = [CC] in {
196  def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
197  def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
198}
199
200//===----------------------------------------------------------------------===//
201// Select instructions
202//===----------------------------------------------------------------------===//
203
204def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
205def Select32    : SelectWrapper<GR32>;
206def Select64    : SelectWrapper<GR64>;
207
208// We don't define 32-bit Mux stores because the low-only STOC should
209// always be used if possible.
210defm CondStore8Mux  : CondStores<GRX32, nonvolatile_truncstorei8,
211                                 nonvolatile_anyextloadi8, bdxaddr20only>,
212                      Requires<[FeatureHighWord]>;
213defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
214                                 nonvolatile_anyextloadi16, bdxaddr20only>,
215                      Requires<[FeatureHighWord]>;
216defm CondStore8     : CondStores<GR32, nonvolatile_truncstorei8,
217                                 nonvolatile_anyextloadi8, bdxaddr20only>;
218defm CondStore16    : CondStores<GR32, nonvolatile_truncstorei16,
219                                 nonvolatile_anyextloadi16, bdxaddr20only>;
220defm CondStore32    : CondStores<GR32, nonvolatile_store,
221                                 nonvolatile_load, bdxaddr20only>;
222
223defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
224                    nonvolatile_anyextloadi8, bdxaddr20only>;
225defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
226                    nonvolatile_anyextloadi16, bdxaddr20only>;
227defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
228                    nonvolatile_anyextloadi32, bdxaddr20only>;
229defm CondStore64 : CondStores<GR64, nonvolatile_store,
230                              nonvolatile_load, bdxaddr20only>;
231
232//===----------------------------------------------------------------------===//
233// Call instructions
234//===----------------------------------------------------------------------===//
235
236// The definitions here are for the call-clobbered registers.
237let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
238                        F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC] in {
239  def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
240                        [(z_call pcrel32:$I2)]>;
241  def CallBASR  : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
242                        [(z_call ADDR64:$R2)]>;
243}
244
245// Sibling calls.  Indirect sibling calls must be via R1, since R2 upwards
246// are argument registers and since branching to R0 is a no-op.
247let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
248  def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
249                     [(z_sibcall pcrel32:$I2)]>;
250  let Uses = [R1D] in
251    def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
252}
253
254// Define the general form of the call instructions for the asm parser.
255// These instructions don't hard-code %r14 as the return address register.
256def BRAS  : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
257                   "bras\t$R1, $I2", []>;
258def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
259                    "brasl\t$R1, $I2", []>;
260def BASR  : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
261                   "basr\t$R1, $R2", []>;
262
263//===----------------------------------------------------------------------===//
264// Move instructions
265//===----------------------------------------------------------------------===//
266
267// Register moves.
268let neverHasSideEffects = 1 in {
269  // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
270  def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
271              Requires<[FeatureHighWord]>;
272  def LR  : UnaryRR <"l",  0x18,   null_frag, GR32, GR32>;
273  def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
274}
275let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
276  def LTR  : UnaryRR <"lt",  0x12,   null_frag, GR32, GR32>;
277  def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
278}
279
280// Move on condition.
281let isCodeGenOnly = 1, Uses = [CC] in {
282  def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
283  def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
284}
285let Uses = [CC] in {
286  def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
287  def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
288}
289
290// Immediate moves.
291let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
292    isReMaterializable = 1 in {
293  // 16-bit sign-extended immediates.  LHIMux expands to LHI or IIHF,
294  // deopending on the choice of register.
295  def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
296               Requires<[FeatureHighWord]>;
297  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
298  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
299
300  // Other 16-bit immediates.
301  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
302  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
303  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
304  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
305
306  // 32-bit immediates.
307  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
308  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
309  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
310}
311
312// Register loads.
313let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
314  // Expands to L, LY or LFH, depending on the choice of register.
315  def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
316             Requires<[FeatureHighWord]>;
317  defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
318  def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
319            Requires<[FeatureHighWord]>;
320  def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
321
322  // These instructions are split after register allocation, so we don't
323  // want a custom inserter.
324  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
325    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
326                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
327  }
328}
329let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
330  def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
331  def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
332}
333
334let canFoldAsLoad = 1 in {
335  def LRL  : UnaryRILPC<"lrl",  0xC4D, aligned_load, GR32>;
336  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
337}
338
339// Load on condition.
340let isCodeGenOnly = 1, Uses = [CC] in {
341  def LOC  : CondUnaryRSY<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
342  def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
343}
344let Uses = [CC] in {
345  def AsmLOC  : AsmCondUnaryRSY<"loc",  0xEBF2, GR32, 4>;
346  def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
347}
348
349// Register stores.
350let SimpleBDXStore = 1 in {
351  // Expands to ST, STY or STFH, depending on the choice of register.
352  def STMux : StoreRXYPseudo<store, GRX32, 4>,
353              Requires<[FeatureHighWord]>;
354  defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
355  def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
356             Requires<[FeatureHighWord]>;
357  def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
358
359  // These instructions are split after register allocation, so we don't
360  // want a custom inserter.
361  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
362    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
363                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
364  }
365}
366def STRL  : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
367def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
368
369// Store on condition.
370let isCodeGenOnly = 1, Uses = [CC] in {
371  def STOC  : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
372  def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
373}
374let Uses = [CC] in {
375  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
376  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
377}
378
379// 8-bit immediate stores to 8-bit fields.
380defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
381
382// 16-bit immediate stores to 16-, 32- or 64-bit fields.
383def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
384def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
385def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;
386
387// Memory-to-memory moves.
388let mayLoad = 1, mayStore = 1 in
389  defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
390
391// String moves.
392let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
393  defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
394
395//===----------------------------------------------------------------------===//
396// Sign extensions
397//===----------------------------------------------------------------------===//
398//
399// Note that putting these before zero extensions mean that we will prefer
400// them for anyextload*.  There's not really much to choose between the two
401// either way, but signed-extending loads have a short LH and a long LHY,
402// while zero-extending loads have only the long LLH.
403//
404//===----------------------------------------------------------------------===//
405
406// 32-bit extensions from registers.
407let neverHasSideEffects = 1 in {
408  def LBR : UnaryRRE<"lb", 0xB926, sext8,  GR32, GR32>;
409  def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
410}
411
412// 64-bit extensions from registers.
413let neverHasSideEffects = 1 in {
414  def LGBR : UnaryRRE<"lgb", 0xB906, sext8,  GR64, GR64>;
415  def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
416  def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
417}
418let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
419  def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
420
421// Match 32-to-64-bit sign extensions in which the source is already
422// in a 64-bit register.
423def : Pat<(sext_inreg GR64:$src, i32),
424          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
425
426// 32-bit extensions from 8-bit memory.  LBMux expands to LB or LBH,
427// depending on the choice of register.
428def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
429            Requires<[FeatureHighWord]>;
430def LB  : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
431def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
432          Requires<[FeatureHighWord]>;
433
434// 32-bit extensions from 16-bit memory.  LHMux expands to LH or LHH,
435// depending on the choice of register.
436def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
437            Requires<[FeatureHighWord]>;
438defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
439def  LHH  : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
440            Requires<[FeatureHighWord]>;
441def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
442
443// 64-bit extensions from memory.
444def LGB   : UnaryRXY<"lgb", 0xE377, asextloadi8,  GR64, 1>;
445def LGH   : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
446def LGF   : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
447def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
448def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
449let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
450  def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
451
452//===----------------------------------------------------------------------===//
453// Zero extensions
454//===----------------------------------------------------------------------===//
455
456// 32-bit extensions from registers.
457let neverHasSideEffects = 1 in {
458  // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
459  def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
460                Requires<[FeatureHighWord]>;
461  def LLCR    : UnaryRRE<"llc", 0xB994, zext8,  GR32, GR32>;
462  // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
463  def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
464                Requires<[FeatureHighWord]>;
465  def LLHR    : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
466}
467
468// 64-bit extensions from registers.
469let neverHasSideEffects = 1 in {
470  def LLGCR : UnaryRRE<"llgc", 0xB984, zext8,  GR64, GR64>;
471  def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
472  def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
473}
474
475// Match 32-to-64-bit zero extensions in which the source is already
476// in a 64-bit register.
477def : Pat<(and GR64:$src, 0xffffffff),
478          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
479
480// 32-bit extensions from 8-bit memory.  LLCMux expands to LLC or LLCH,
481// depending on the choice of register.
482def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
483             Requires<[FeatureHighWord]>;
484def LLC  : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
485def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>,
486           Requires<[FeatureHighWord]>;
487
488// 32-bit extensions from 16-bit memory.  LLHMux expands to LLH or LLHH,
489// depending on the choice of register.
490def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
491             Requires<[FeatureHighWord]>;
492def LLH   : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
493def LLHH  : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>,
494            Requires<[FeatureHighWord]>;
495def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
496
497// 64-bit extensions from memory.
498def LLGC   : UnaryRXY<"llgc", 0xE390, azextloadi8,  GR64, 1>;
499def LLGH   : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
500def LLGF   : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
501def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
502def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
503
504//===----------------------------------------------------------------------===//
505// Truncations
506//===----------------------------------------------------------------------===//
507
508// Truncations of 64-bit registers to 32-bit registers.
509def : Pat<(i32 (trunc GR64:$src)),
510          (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
511
512// Truncations of 32-bit registers to 8-bit memory.  STCMux expands to
513// STC, STCY or STCH, depending on the choice of register.
514def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
515             Requires<[FeatureHighWord]>;
516defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
517def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
518           Requires<[FeatureHighWord]>;
519
520// Truncations of 32-bit registers to 16-bit memory.  STHMux expands to
521// STH, STHY or STHH, depending on the choice of register.
522def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
523             Requires<[FeatureHighWord]>;
524defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
525def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
526           Requires<[FeatureHighWord]>;
527def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
528
529// Truncations of 64-bit registers to memory.
530defm : StoreGR64Pair<STC, STCY, truncstorei8>;
531defm : StoreGR64Pair<STH, STHY, truncstorei16>;
532def  : StoreGR64PC<STHRL, aligned_truncstorei16>;
533defm : StoreGR64Pair<ST, STY, truncstorei32>;
534def  : StoreGR64PC<STRL, aligned_truncstorei32>;
535
536//===----------------------------------------------------------------------===//
537// Multi-register moves
538//===----------------------------------------------------------------------===//
539
540// Multi-register loads.
541def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
542
543// Multi-register stores.
544def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
545
546//===----------------------------------------------------------------------===//
547// Byte swaps
548//===----------------------------------------------------------------------===//
549
550// Byte-swapping register moves.
551let neverHasSideEffects = 1 in {
552  def LRVR  : UnaryRRE<"lrv",  0xB91F, bswap, GR32, GR32>;
553  def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
554}
555
556// Byte-swapping loads.  Unlike normal loads, these instructions are
557// allowed to access storage more than once.
558def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
559def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
560
561// Likewise byte-swapping stores.
562def STRV  : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
563def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
564                     GR64, 8>;
565
566//===----------------------------------------------------------------------===//
567// Load address instructions
568//===----------------------------------------------------------------------===//
569
570// Load BDX-style addresses.
571let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
572    DispKey = "la" in {
573  let DispSize = "12" in
574    def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
575                    "la\t$R1, $XBD2",
576                    [(set GR64:$R1, laaddr12pair:$XBD2)]>;
577  let DispSize = "20" in
578    def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
579                      "lay\t$R1, $XBD2",
580                      [(set GR64:$R1, laaddr20pair:$XBD2)]>;
581}
582
583// Load a PC-relative address.  There's no version of this instruction
584// with a 16-bit offset, so there's no relaxation.
585let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
586    isReMaterializable = 1 in {
587  def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
588                     "larl\t$R1, $I2",
589                     [(set GR64:$R1, pcrel32:$I2)]>;
590}
591
592//===----------------------------------------------------------------------===//
593// Absolute and Negation
594//===----------------------------------------------------------------------===//
595
596let Defs = [CC] in {
597  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
598    def LPR  : UnaryRR <"lp",  0x10,   z_iabs32, GR32, GR32>;
599    def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs64, GR64, GR64>;
600  }
601  let CCValues = 0xE, CompareZeroCCMask = 0xE in
602    def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
603}
604defm : SXU<z_iabs64, LPGFR>;
605
606let Defs = [CC] in {
607  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
608    def LNR  : UnaryRR <"ln",  0x11,   z_inegabs32, GR32, GR32>;
609    def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs64, GR64, GR64>;
610  }
611  let CCValues = 0xE, CompareZeroCCMask = 0xE in
612    def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
613}
614defm : SXU<z_inegabs64, LNGFR>;
615
616let Defs = [CC] in {
617  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
618    def LCR  : UnaryRR <"lc",  0x13,   ineg, GR32, GR32>;
619    def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
620  }
621  let CCValues = 0xE, CompareZeroCCMask = 0xE in
622    def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
623}
624defm : SXU<ineg, LCGFR>;
625
626//===----------------------------------------------------------------------===//
627// Insertion
628//===----------------------------------------------------------------------===//
629
630let isCodeGenOnly = 1 in
631  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
632defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
633
634defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
635defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
636
637defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
638defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
639
640// Insertions of a 16-bit immediate, leaving other bits unaffected.
641// We don't have or_as_insert equivalents of these operations because
642// OI is available instead.
643//
644// IIxMux expands to II[LH]x, depending on the choice of register.
645def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
646             Requires<[FeatureHighWord]>;
647def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
648             Requires<[FeatureHighWord]>;
649def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
650def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
651def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
652def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
653def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
654def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
655def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
656def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
657
658// ...likewise for 32-bit immediates.  For GR32s this is a general
659// full-width move.  (We use IILF rather than something like LLILF
660// for 32-bit moves because IILF leaves the upper 32 bits of the
661// GR64 unchanged.)
662let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
663  def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
664               Requires<[FeatureHighWord]>;
665  def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
666  def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
667}
668def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
669def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
670
671// An alternative model of inserthf, with the first operand being
672// a zero-extended value.
673def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
674          (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
675                  imm64hf32:$imm)>;
676
677//===----------------------------------------------------------------------===//
678// Addition
679//===----------------------------------------------------------------------===//
680
681// Plain addition.
682let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
683  // Addition of a register.
684  let isCommutable = 1 in {
685    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
686    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
687  }
688  def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
689
690  // Addition of signed 16-bit immediates.
691  defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
692  defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
693  defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
694
695  // Addition of signed 32-bit immediates.
696  def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
697               Requires<[FeatureHighWord]>;
698  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
699  def AIH  : BinaryRIL<"aih",  0xCC8, add, GRH32, simm32>,
700             Requires<[FeatureHighWord]>;
701  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
702
703  // Addition of memory.
704  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
705  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
706  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
707  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
708
709  // Addition to memory.
710  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
711  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
712}
713defm : SXB<add, GR64, AGFR>;
714
715// Addition producing a carry.
716let Defs = [CC] in {
717  // Addition of a register.
718  let isCommutable = 1 in {
719    defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
720    defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
721  }
722  def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
723
724  // Addition of signed 16-bit immediates.
725  def ALHSIK  : BinaryRIE<"alhsik",  0xECDA, addc, GR32, imm32sx16>,
726                Requires<[FeatureDistinctOps]>;
727  def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
728                Requires<[FeatureDistinctOps]>;
729
730  // Addition of unsigned 32-bit immediates.
731  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
732  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
733
734  // Addition of memory.
735  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
736  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
737  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load, 8>;
738}
739defm : ZXB<addc, GR64, ALGFR>;
740
741// Addition producing and using a carry.
742let Defs = [CC], Uses = [CC] in {
743  // Addition of a register.
744  def ALCR  : BinaryRRE<"alc",  0xB998, adde, GR32, GR32>;
745  def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
746
747  // Addition of memory.
748  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load, 4>;
749  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
750}
751
752//===----------------------------------------------------------------------===//
753// Subtraction
754//===----------------------------------------------------------------------===//
755
756// Plain substraction.  Although immediate forms exist, we use the
757// add-immediate instruction instead.
758let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
759  // Subtraction of a register.
760  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
761  def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
762  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
763
764  // Subtraction of memory.
765  defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
766  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
767  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
768  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load, 8>;
769}
770defm : SXB<sub, GR64, SGFR>;
771
772// Subtraction producing a carry.
773let Defs = [CC] in {
774  // Subtraction of a register.
775  defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
776  def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
777  defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
778
779  // Subtraction of unsigned 32-bit immediates.  These don't match
780  // subc because we prefer addc for constants.
781  def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
782  def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
783
784  // Subtraction of memory.
785  defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
786  def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
787  def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
788}
789defm : ZXB<subc, GR64, SLGFR>;
790
791// Subtraction producing and using a carry.
792let Defs = [CC], Uses = [CC] in {
793  // Subtraction of a register.
794  def SLBR  : BinaryRRE<"slb",  0xB999, sube, GR32, GR32>;
795  def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
796
797  // Subtraction of memory.
798  def SLB  : BinaryRXY<"slb",  0xE399, sube, GR32, load, 4>;
799  def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
800}
801
802//===----------------------------------------------------------------------===//
803// AND
804//===----------------------------------------------------------------------===//
805
806let Defs = [CC] in {
807  // ANDs of a register.
808  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
809    defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
810    defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
811  }
812
813  let isConvertibleToThreeAddress = 1 in {
814    // ANDs of a 16-bit immediate, leaving other bits unaffected.
815    // The CC result only reflects the 16-bit field, not the full register.
816    //
817    // NIxMux expands to NI[LH]x, depending on the choice of register.
818    def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
819                 Requires<[FeatureHighWord]>;
820    def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
821                 Requires<[FeatureHighWord]>;
822    def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
823    def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
824    def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
825    def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
826    def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
827    def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
828    def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
829    def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
830
831    // ANDs of a 32-bit immediate, leaving other bits unaffected.
832    // The CC result only reflects the 32-bit field, which means we can
833    // use it as a zero indicator for i32 operations but not otherwise.
834    let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
835      // Expands to NILF or NIHF, depending on the choice of register.
836      def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
837                   Requires<[FeatureHighWord]>;
838      def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
839      def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
840    }
841    def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
842    def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
843  }
844
845  // ANDs of memory.
846  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
847    defm N  : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
848    def  NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 
849  }
850
851  // AND to memory
852  defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
853
854  // Block AND.
855  let mayLoad = 1, mayStore = 1 in
856    defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
857}
858defm : RMWIByte<and, bdaddr12pair, NI>;
859defm : RMWIByte<and, bdaddr20pair, NIY>;
860
861//===----------------------------------------------------------------------===//
862// OR
863//===----------------------------------------------------------------------===//
864
865let Defs = [CC] in {
866  // ORs of a register.
867  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
868    defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
869    defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
870  }
871
872  // ORs of a 16-bit immediate, leaving other bits unaffected.
873  // The CC result only reflects the 16-bit field, not the full register.
874  //
875  // OIxMux expands to OI[LH]x, depending on the choice of register.
876  def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
877               Requires<[FeatureHighWord]>;
878  def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
879               Requires<[FeatureHighWord]>;
880  def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
881  def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
882  def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
883  def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
884  def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
885  def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
886  def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
887  def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
888
889  // ORs of a 32-bit immediate, leaving other bits unaffected.
890  // The CC result only reflects the 32-bit field, which means we can
891  // use it as a zero indicator for i32 operations but not otherwise.
892  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
893    // Expands to OILF or OIHF, depending on the choice of register.
894    def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
895                 Requires<[FeatureHighWord]>;
896    def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
897    def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
898  }
899  def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
900  def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
901
902  // ORs of memory.
903  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
904    defm O  : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
905    def  OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
906  }
907
908  // OR to memory
909  defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
910
911  // Block OR.
912  let mayLoad = 1, mayStore = 1 in
913    defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
914}
915defm : RMWIByte<or, bdaddr12pair, OI>;
916defm : RMWIByte<or, bdaddr20pair, OIY>;
917
918//===----------------------------------------------------------------------===//
919// XOR
920//===----------------------------------------------------------------------===//
921
922let Defs = [CC] in {
923  // XORs of a register.
924  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
925    defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
926    defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
927  }
928
929  // XORs of a 32-bit immediate, leaving other bits unaffected.
930  // The CC result only reflects the 32-bit field, which means we can
931  // use it as a zero indicator for i32 operations but not otherwise.
932  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
933    // Expands to XILF or XIHF, depending on the choice of register.
934    def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
935                 Requires<[FeatureHighWord]>;
936    def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
937    def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
938  }
939  def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
940  def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
941
942  // XORs of memory.
943  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
944    defm X  : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
945    def  XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
946  }
947
948  // XOR to memory
949  defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
950
951  // Block XOR.
952  let mayLoad = 1, mayStore = 1 in
953    defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
954}
955defm : RMWIByte<xor, bdaddr12pair, XI>;
956defm : RMWIByte<xor, bdaddr20pair, XIY>;
957
958//===----------------------------------------------------------------------===//
959// Multiplication
960//===----------------------------------------------------------------------===//
961
962// Multiplication of a register.
963let isCommutable = 1 in {
964  def MSR  : BinaryRRE<"ms",  0xB252, mul, GR32, GR32>;
965  def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
966}
967def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
968defm : SXB<mul, GR64, MSGFR>;
969
970// Multiplication of a signed 16-bit immediate.
971def MHI  : BinaryRI<"mhi",  0xA7C, mul, GR32, imm32sx16>;
972def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
973
974// Multiplication of a signed 32-bit immediate.
975def MSFI  : BinaryRIL<"msfi",  0xC21, mul, GR32, simm32>;
976def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
977
978// Multiplication of memory.
979defm MH   : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
980defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
981def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
982def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
983
984// Multiplication of a register, producing two results.
985def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
986
987// Multiplication of memory, producing two results.
988def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
989
990//===----------------------------------------------------------------------===//
991// Division and remainder
992//===----------------------------------------------------------------------===//
993
994// Division and remainder, from registers.
995def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
996def DSGR  : BinaryRRE<"dsg",  0xB90D, z_sdivrem64, GR128, GR64>;
997def DLR   : BinaryRRE<"dl",   0xB997, z_udivrem32, GR128, GR32>;
998def DLGR  : BinaryRRE<"dlg",  0xB987, z_udivrem64, GR128, GR64>;
999
1000// Division and remainder, from memory.
1001def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
1002def DSG  : BinaryRXY<"dsg",  0xE30D, z_sdivrem64, GR128, load, 8>;
1003def DL   : BinaryRXY<"dl",   0xE397, z_udivrem32, GR128, load, 4>;
1004def DLG  : BinaryRXY<"dlg",  0xE387, z_udivrem64, GR128, load, 8>;
1005
1006//===----------------------------------------------------------------------===//
1007// Shifts
1008//===----------------------------------------------------------------------===//
1009
1010// Shift left.
1011let neverHasSideEffects = 1 in {
1012  defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
1013  def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
1014}
1015
1016// Logical shift right.
1017let neverHasSideEffects = 1 in {
1018  defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
1019  def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
1020}
1021
1022// Arithmetic shift right.
1023let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1024  defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
1025  def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
1026}
1027
1028// Rotate left.
1029let neverHasSideEffects = 1 in {
1030  def RLL  : ShiftRSY<"rll",  0xEB1D, rotl, GR32>;
1031  def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
1032}
1033
1034// Rotate second operand left and inserted selected bits into first operand.
1035// These can act like 32-bit operands provided that the constant start and
1036// end bits (operands 2 and 3) are in the range [32, 64).
1037let Defs = [CC] in {
1038  let isCodeGenOnly = 1 in
1039    def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1040  let CCValues = 0xE, CompareZeroCCMask = 0xE in
1041    def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1042}
1043
1044// Forms of RISBG that only affect one word of the destination register.
1045// They do not set CC.
1046def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>, Requires<[FeatureHighWord]>;
1047def RISBLL  : RotateSelectAliasRIEf<GR32,  GR32>,  Requires<[FeatureHighWord]>;
1048def RISBLH  : RotateSelectAliasRIEf<GR32,  GRH32>, Requires<[FeatureHighWord]>;
1049def RISBHL  : RotateSelectAliasRIEf<GRH32, GR32>,  Requires<[FeatureHighWord]>;
1050def RISBHH  : RotateSelectAliasRIEf<GRH32, GRH32>, Requires<[FeatureHighWord]>;
1051def RISBLG  : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
1052              Requires<[FeatureHighWord]>;
1053def RISBHG  : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
1054              Requires<[FeatureHighWord]>;
1055
1056// Rotate second operand left and perform a logical operation with selected
1057// bits of the first operand.  The CC result only describes the selected bits,
1058// so isn't useful for a full comparison against zero.
1059let Defs = [CC] in {
1060  def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1061  def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1062  def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1063}
1064
1065//===----------------------------------------------------------------------===//
1066// Comparison
1067//===----------------------------------------------------------------------===//
1068
1069// Signed comparisons.  We put these before the unsigned comparisons because
1070// some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1071// of the unsigned forms do.
1072let Defs = [CC], CCValues = 0xE in {
1073  // Comparison with a register.
1074  def CR   : CompareRR <"c",   0x19,   z_scmp,    GR32, GR32>;
1075  def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1076  def CGR  : CompareRRE<"cg",  0xB920, z_scmp,    GR64, GR64>;
1077
1078  // Comparison with a signed 16-bit immediate.
1079  def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
1080  def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1081
1082  // Comparison with a signed 32-bit immediate.  CFIMux expands to CFI or CIH,
1083  // depending on the choice of register.
1084  def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,
1085               Requires<[FeatureHighWord]>;
1086  def CFI  : CompareRIL<"cfi",  0xC2D, z_scmp, GR32, simm32>;
1087  def CIH  : CompareRIL<"cih",  0xCCD, z_scmp, GRH32, simm32>,
1088             Requires<[FeatureHighWord]>;
1089  def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1090
1091  // Comparison with memory.
1092  defm CH    : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1093  def  CMux  : CompareRXYPseudo<z_scmp, GRX32, load, 4>,
1094               Requires<[FeatureHighWord]>;
1095  defm C     : CompareRXPair<"c",  0x59, 0xE359, z_scmp, GR32, load, 4>;
1096  def  CHF   : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>,
1097               Requires<[FeatureHighWord]>;
1098  def  CGH   : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1099  def  CGF   : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1100  def  CG    : CompareRXY<"cg",  0xE320, z_scmp, GR64, load, 8>;
1101  def  CHRL  : CompareRILPC<"chrl",  0xC65, z_scmp, GR32, aligned_asextloadi16>;
1102  def  CRL   : CompareRILPC<"crl",   0xC6D, z_scmp, GR32, aligned_load>;
1103  def  CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1104  def  CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1105  def  CGRL  : CompareRILPC<"cgrl",  0xC68, z_scmp, GR64, aligned_load>;
1106
1107  // Comparison between memory and a signed 16-bit immediate.
1108  def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1109  def CHSI  : CompareSIL<"chsi",  0xE55C, z_scmp, load, imm32sx16>;
1110  def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1111}
1112defm : SXB<z_scmp, GR64, CGFR>;
1113
1114// Unsigned comparisons.
1115let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1116  // Comparison with a register.
1117  def CLR   : CompareRR <"cl",   0x15,   z_ucmp,    GR32, GR32>;
1118  def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1119  def CLGR  : CompareRRE<"clg",  0xB921, z_ucmp,    GR64, GR64>;
1120
1121  // Comparison with an unsigned 32-bit immediate.  CLFIMux expands to CLFI
1122  // or CLIH, depending on the choice of register.
1123  def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
1124                Requires<[FeatureHighWord]>;
1125  def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
1126  def CLIH  : CompareRIL<"clih",  0xCCF, z_ucmp, GR32, uimm32>,
1127              Requires<[FeatureHighWord]>;
1128  def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1129
1130  // Comparison with memory.
1131  def  CLMux  : CompareRXYPseudo<z_ucmp, GRX32, load, 4>,
1132                Requires<[FeatureHighWord]>;
1133  defm CL     : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1134  def  CLHF   : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>,
1135                Requires<[FeatureHighWord]>;
1136  def  CLGF   : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1137  def  CLG    : CompareRXY<"clg",  0xE321, z_ucmp, GR64, load, 8>;
1138  def  CLHRL  : CompareRILPC<"clhrl",  0xC67, z_ucmp, GR32,
1139                             aligned_azextloadi16>;
1140  def  CLRL   : CompareRILPC<"clrl",   0xC6F, z_ucmp, GR32,
1141                             aligned_load>;
1142  def  CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1143                             aligned_azextloadi16>;
1144  def  CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1145                             aligned_azextloadi32>;
1146  def  CLGRL  : CompareRILPC<"clgrl",  0xC6A, z_ucmp, GR64,
1147                             aligned_load>;
1148
1149  // Comparison between memory and an unsigned 8-bit immediate.
1150  defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1151
1152  // Comparison between memory and an unsigned 16-bit immediate.
1153  def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1154  def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1155  def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1156}
1157defm : ZXB<z_ucmp, GR64, CLGFR>;
1158
1159// Memory-to-memory comparison.
1160let mayLoad = 1, Defs = [CC] in
1161  defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1162
1163// String comparison.
1164let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1165  defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1166
1167// Test under mask.
1168let Defs = [CC] in {
1169  // TMxMux expands to TM[LH]x, depending on the choice of register.
1170  def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
1171               Requires<[FeatureHighWord]>;
1172  def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
1173               Requires<[FeatureHighWord]>;
1174  def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1175  def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1176  def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
1177  def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
1178
1179  def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;
1180  def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;
1181  def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;
1182  def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;
1183
1184  defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1185}
1186
1187//===----------------------------------------------------------------------===//
1188// Prefetch
1189//===----------------------------------------------------------------------===//
1190
1191def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1192def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1193
1194//===----------------------------------------------------------------------===//
1195// Atomic operations
1196//===----------------------------------------------------------------------===//
1197
1198def ATOMIC_SWAPW        : AtomicLoadWBinaryReg<z_atomic_swapw>;
1199def ATOMIC_SWAP_32      : AtomicLoadBinaryReg32<atomic_swap_32>;
1200def ATOMIC_SWAP_64      : AtomicLoadBinaryReg64<atomic_swap_64>;
1201
1202def ATOMIC_LOADW_AR     : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1203def ATOMIC_LOADW_AFI    : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1204def ATOMIC_LOAD_AR      : AtomicLoadBinaryReg32<atomic_load_add_32>;
1205def ATOMIC_LOAD_AHI     : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1206def ATOMIC_LOAD_AFI     : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1207def ATOMIC_LOAD_AGR     : AtomicLoadBinaryReg64<atomic_load_add_64>;
1208def ATOMIC_LOAD_AGHI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1209def ATOMIC_LOAD_AGFI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1210
1211def ATOMIC_LOADW_SR     : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1212def ATOMIC_LOAD_SR      : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1213def ATOMIC_LOAD_SGR     : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1214
1215def ATOMIC_LOADW_NR     : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1216def ATOMIC_LOADW_NILH   : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1217def ATOMIC_LOAD_NR      : AtomicLoadBinaryReg32<atomic_load_and_32>;
1218def ATOMIC_LOAD_NILL    : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
1219def ATOMIC_LOAD_NILH    : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
1220def ATOMIC_LOAD_NILF    : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1221def ATOMIC_LOAD_NGR     : AtomicLoadBinaryReg64<atomic_load_and_64>;
1222def ATOMIC_LOAD_NILL64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
1223def ATOMIC_LOAD_NILH64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
1224def ATOMIC_LOAD_NIHL64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
1225def ATOMIC_LOAD_NIHH64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
1226def ATOMIC_LOAD_NILF64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
1227def ATOMIC_LOAD_NIHF64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
1228
1229def ATOMIC_LOADW_OR     : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1230def ATOMIC_LOADW_OILH   : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1231def ATOMIC_LOAD_OR      : AtomicLoadBinaryReg32<atomic_load_or_32>;
1232def ATOMIC_LOAD_OILL    : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1233def ATOMIC_LOAD_OILH    : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1234def ATOMIC_LOAD_OILF    : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1235def ATOMIC_LOAD_OGR     : AtomicLoadBinaryReg64<atomic_load_or_64>;
1236def ATOMIC_LOAD_OILL64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1237def ATOMIC_LOAD_OILH64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1238def ATOMIC_LOAD_OIHL64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1239def ATOMIC_LOAD_OIHH64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1240def ATOMIC_LOAD_OILF64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1241def ATOMIC_LOAD_OIHF64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1242
1243def ATOMIC_LOADW_XR     : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1244def ATOMIC_LOADW_XILF   : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1245def ATOMIC_LOAD_XR      : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1246def ATOMIC_LOAD_XILF    : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1247def ATOMIC_LOAD_XGR     : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1248def ATOMIC_LOAD_XILF64  : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1249def ATOMIC_LOAD_XIHF64  : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1250
1251def ATOMIC_LOADW_NRi    : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1252def ATOMIC_LOADW_NILHi  : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1253                                               imm32lh16c>;
1254def ATOMIC_LOAD_NRi     : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1255def ATOMIC_LOAD_NILLi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1256                                                imm32ll16c>;
1257def ATOMIC_LOAD_NILHi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1258                                                imm32lh16c>;
1259def ATOMIC_LOAD_NILFi   : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1260def ATOMIC_LOAD_NGRi    : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1261def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1262                                                imm64ll16c>;
1263def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1264                                                imm64lh16c>;
1265def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1266                                                imm64hl16c>;
1267def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1268                                                imm64hh16c>;
1269def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1270                                                imm64lf32c>;
1271def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1272                                                imm64hf32c>;
1273
1274def ATOMIC_LOADW_MIN    : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1275def ATOMIC_LOAD_MIN_32  : AtomicLoadBinaryReg32<atomic_load_min_32>;
1276def ATOMIC_LOAD_MIN_64  : AtomicLoadBinaryReg64<atomic_load_min_64>;
1277
1278def ATOMIC_LOADW_MAX    : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1279def ATOMIC_LOAD_MAX_32  : AtomicLoadBinaryReg32<atomic_load_max_32>;
1280def ATOMIC_LOAD_MAX_64  : AtomicLoadBinaryReg64<atomic_load_max_64>;
1281
1282def ATOMIC_LOADW_UMIN   : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1283def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1284def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1285
1286def ATOMIC_LOADW_UMAX   : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1287def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1288def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1289
1290def ATOMIC_CMP_SWAPW
1291  : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1292                                  ADDR32:$bitshift, ADDR32:$negbitshift,
1293                                  uimm32:$bitsize),
1294           [(set GR32:$dst,
1295                 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1296                                     ADDR32:$bitshift, ADDR32:$negbitshift,
1297                                     uimm32:$bitsize))]> {
1298  let Defs = [CC];
1299  let mayLoad = 1;
1300  let mayStore = 1;
1301  let usesCustomInserter = 1;
1302}
1303
1304let Defs = [CC] in {
1305  defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1306  def  CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1307}
1308
1309//===----------------------------------------------------------------------===//
1310// Miscellaneous Instructions.
1311//===----------------------------------------------------------------------===//
1312
1313// Extract CC into bits 29 and 28 of a register.
1314let Uses = [CC] in
1315  def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1316
1317// Read a 32-bit access register into a GR32.  As with all GR32 operations,
1318// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1319// when a 64-bit address is stored in a pair of access registers.
1320def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1321                  "ear\t$R1, $R2",
1322                  [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1323
1324// Find leftmost one, AKA count leading zeros.  The instruction actually
1325// returns a pair of GR64s, the first giving the number of leading zeros
1326// and the second giving a copy of the source with the leftmost one bit
1327// cleared.  We only use the first result here.
1328let Defs = [CC] in {
1329  def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1330}
1331def : Pat<(ctlz GR64:$src),
1332          (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1333
1334// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1335def : Pat<(i64 (anyext GR32:$src)),
1336          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1337
1338// Extend GR32s and GR64s to GR128s.
1339let usesCustomInserter = 1 in {
1340  def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1341  def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1342  def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1343}
1344
1345// Search a block of memory for a character.
1346let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1347  defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1348
1349//===----------------------------------------------------------------------===//
1350// Peepholes.
1351//===----------------------------------------------------------------------===//
1352
1353// Use AL* for GR64 additions of unsigned 32-bit values.
1354defm : ZXB<add, GR64, ALGFR>;
1355def  : Pat<(add GR64:$src1, imm64zx32:$src2),
1356           (ALGFI GR64:$src1, imm64zx32:$src2)>;
1357def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1358           (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1359
1360// Use SL* for GR64 subtractions of unsigned 32-bit values.
1361defm : ZXB<sub, GR64, SLGFR>;
1362def  : Pat<(add GR64:$src1, imm64zx32n:$src2),
1363           (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1364def  : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1365           (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1366
1367// Optimize sign-extended 1/0 selects to -1/0 selects.  This is important
1368// for vector legalization.
1369def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1370                         (i32 31)),
1371                    (i32 31)),
1372          (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1373def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1374                                                       uimm8zx4:$cc)))),
1375                    (i32 63)),
1376               (i32 63)),
1377          (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1378
1379// Peepholes for turning scalar operations into block operations.
1380defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1381                      XCSequence, 1>;
1382defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1383                      XCSequence, 2>;
1384defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1385                      XCSequence, 4>;
1386defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1387                      OCSequence, XCSequence, 1>;
1388defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1389                      XCSequence, 2>;
1390defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1391                      XCSequence, 4>;
1392defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
1393                      XCSequence, 8>;
1394