SystemZRegisterInfo.cpp revision 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 
1//===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZ.h"
15#include "SystemZInstrInfo.h"
16#include "SystemZMachineFunctionInfo.h"
17#include "SystemZRegisterInfo.h"
18#include "SystemZSubtarget.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/Target/TargetFrameLowering.h"
24#include "llvm/Target/TargetInstrInfo.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Target/TargetOptions.h"
27#include "llvm/ADT/BitVector.h"
28
29#define GET_REGINFO_MC_DESC
30#define GET_REGINFO_TARGET_DESC
31#include "SystemZGenRegisterInfo.inc"
32
33using namespace llvm;
34
35SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
36                                         const SystemZInstrInfo &tii)
37  : SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
38                           SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
39    TM(tm), TII(tii) {
40}
41
42const unsigned*
43SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
44  static const unsigned CalleeSavedRegs[] = {
45    SystemZ::R6D,  SystemZ::R7D,  SystemZ::R8D,  SystemZ::R9D,
46    SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
47    SystemZ::R14D, SystemZ::R15D,
48    SystemZ::F8L,  SystemZ::F9L,  SystemZ::F10L, SystemZ::F11L,
49    SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L,
50    0
51  };
52
53  return CalleeSavedRegs;
54}
55
56BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
57  BitVector Reserved(getNumRegs());
58  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
59
60  if (TFI->hasFP(MF)) {
61    // R11D is the frame pointer. Reserve all aliases.
62    Reserved.set(SystemZ::R11D);
63    Reserved.set(SystemZ::R11W);
64    Reserved.set(SystemZ::R10P);
65    Reserved.set(SystemZ::R10Q);
66  }
67
68  Reserved.set(SystemZ::R14D);
69  Reserved.set(SystemZ::R15D);
70  Reserved.set(SystemZ::R14W);
71  Reserved.set(SystemZ::R15W);
72  Reserved.set(SystemZ::R14P);
73  Reserved.set(SystemZ::R14Q);
74  return Reserved;
75}
76
77const TargetRegisterClass*
78SystemZRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
79                                              const TargetRegisterClass *B,
80                                              unsigned Idx) const {
81  switch(Idx) {
82  // Exact sub-classes don't exist for the other sub-register indexes.
83  default: return 0;
84  case SystemZ::subreg_32bit:
85    if (B == SystemZ::ADDR32RegisterClass)
86      return A->getSize() == 8 ? SystemZ::ADDR64RegisterClass : 0;
87    return A;
88  }
89}
90
91void SystemZRegisterInfo::
92eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
93                              MachineBasicBlock::iterator I) const {
94  MBB.erase(I);
95}
96
97void
98SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
99                                         int SPAdj, RegScavenger *RS) const {
100  assert(SPAdj == 0 && "Unxpected");
101
102  unsigned i = 0;
103  MachineInstr &MI = *II;
104  MachineFunction &MF = *MI.getParent()->getParent();
105  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
106
107  while (!MI.getOperand(i).isFI()) {
108    ++i;
109    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
110  }
111
112  int FrameIndex = MI.getOperand(i).getIndex();
113
114  unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
115
116  // This must be part of a rri or ri operand memory reference.  Replace the
117  // FrameIndex with base register with BasePtr.  Add an offset to the
118  // displacement field.
119  MI.getOperand(i).ChangeToRegister(BasePtr, false);
120
121  // Offset is a either 12-bit unsigned or 20-bit signed integer.
122  // FIXME: handle "too long" displacements.
123  int Offset =
124    TFI->getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
125
126  // Check whether displacement is too long to fit into 12 bit zext field.
127  MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
128
129  MI.getOperand(i+1).ChangeToImmediate(Offset);
130}
131
132unsigned SystemZRegisterInfo::getRARegister() const {
133  assert(0 && "What is the return address register");
134  return 0;
135}
136
137unsigned
138SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
139  assert(0 && "What is the frame register");
140  return 0;
141}
142
143unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
144  assert(0 && "What is the exception register");
145  return 0;
146}
147
148unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
149  assert(0 && "What is the exception handler register");
150  return 0;
151}
152
153int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
154  assert(0 && "What is the dwarf register number");
155  return -1;
156}
157
158int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
159  assert(0 && "What is the dwarf register number");
160  return -1;
161}
162