X86InstrControl.td revision 31d157ae1ac2cd9c787dc3c1d28e64c682803844
1//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 jump, return, call, and related instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Control Flow Instructions. 16// 17 18// Return instructions. 19let isTerminator = 1, isReturn = 1, isBarrier = 1, 20 hasCtrlDep = 1, FPForm = SpecialFP in { 21 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops), 22 "ret", 23 [(X86retflag 0)], IIC_RET>; 24 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 25 "ret\t$amt", 26 [(X86retflag timm:$amt)], IIC_RET_IMM>; 27 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 28 "retw\t$amt", 29 [], IIC_RET_IMM>, OpSize; 30 def LRETL : I <0xCB, RawFrm, (outs), (ins), 31 "lretl", [], IIC_RET>; 32 def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 33 "lretq", [], IIC_RET>; 34 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 35 "lret\t$amt", [], IIC_RET>; 36 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 37 "lretw\t$amt", [], IIC_RET>, OpSize; 38} 39 40// Unconditional branches. 41let isBarrier = 1, isBranch = 1, isTerminator = 1 in { 42 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst), 43 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>; 44 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 45 "jmp\t$dst", [], IIC_JMP_REL>; 46 // FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious 47 // with JMP_1. 48 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), 49 "jmpq\t$dst", [], IIC_JMP_REL>; 50} 51 52// Conditional Branches. 53let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in { 54 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { 55 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [], 56 IIC_Jcc>; 57 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm, 58 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB; 59 } 60} 61 62defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; 63defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>; 64defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; 65defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; 66defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; 67defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; 68defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; 69defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; 70defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; 71defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; 72defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; 73defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; 74defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; 75defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; 76defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; 77defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; 78 79// jcx/jecx/jrcx instructions. 80let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in { 81 // These are the 32-bit versions of this instruction for the asmparser. In 82 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 83 // jecxz. 84 let Uses = [CX] in 85 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 86 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In32BitMode]>; 87 let Uses = [ECX] in 88 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 89 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[In32BitMode]>; 90 91 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser. 92 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version 93 // is jrcxz. 94 let Uses = [ECX] in 95 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 96 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>; 97 let Uses = [RCX] in 98 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 99 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>; 100} 101 102// Indirect branches 103let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 104 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 105 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>; 106 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 107 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode]>; 108 109 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 110 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>; 111 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 112 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, Requires<[In64BitMode]>; 113 114 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 115 (ins i16imm:$off, i16imm:$seg), 116 "ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize; 117 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 118 (ins i32imm:$off, i16imm:$seg), 119 "ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>; 120 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), 121 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>; 122 123 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), 124 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize; 125 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), 126 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>; 127} 128 129 130// Loop instructions 131 132def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>; 133def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>; 134def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>; 135 136//===----------------------------------------------------------------------===// 137// Call Instructions... 138// 139let isCall = 1 in 140 // All calls clobber the non-callee saved registers. ESP is marked as 141 // a use to prevent stack-pointer assignments that appear immediately 142 // before calls from potentially appearing dead. Uses for argument 143 // registers are added manually. 144 let Uses = [ESP] in { 145 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 146 (outs), (ins i32imm_pcrel:$dst,variable_ops), 147 "call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>; 148 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), 149 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>, 150 Requires<[In32BitMode]>; 151 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), 152 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>, 153 Requires<[In32BitMode]>; 154 155 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 156 (ins i16imm:$off, i16imm:$seg), 157 "lcall{w}\t{$seg, $off|$off, $seg}", [], 158 IIC_CALL_FAR_PTR>, OpSize; 159 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 160 (ins i32imm:$off, i16imm:$seg), 161 "lcall{l}\t{$seg, $off|$off, $seg}", [], 162 IIC_CALL_FAR_PTR>; 163 164 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), 165 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize; 166 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), 167 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>; 168 169 // callw for 16 bit code for the assembler. 170 let isAsmParserOnly = 1 in 171 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 172 (outs), (ins i16imm_pcrel:$dst, variable_ops), 173 "callw\t$dst", []>, OpSize; 174 } 175 176 177// Tail call stuff. 178 179let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 180 isCodeGenOnly = 1 in 181 let Uses = [ESP] in { 182 def TCRETURNdi : PseudoI<(outs), 183 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops), []>; 184 def TCRETURNri : PseudoI<(outs), 185 (ins GR32_TC:$dst, i32imm:$offset, variable_ops), []>; 186 let mayLoad = 1 in 187 def TCRETURNmi : PseudoI<(outs), 188 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops), []>; 189 190 // FIXME: The should be pseudo instructions that are lowered when going to 191 // mcinst. 192 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), 193 (ins i32imm_pcrel:$dst, variable_ops), 194 "jmp\t$dst # TAILCALL", 195 [], IIC_JMP_REL>; 196 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops), 197 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead. 198 let mayLoad = 1 in 199 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops), 200 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 201} 202 203 204//===----------------------------------------------------------------------===// 205// Call Instructions... 206// 207 208// RSP is marked as a use to prevent stack-pointer assignments that appear 209// immediately before calls from potentially appearing dead. Uses for argument 210// registers are added manually. 211let isCall = 1, Uses = [RSP] in { 212 // NOTE: this pattern doesn't match "X86call imm", because we do not know 213 // that the offset between an arbitrary immediate and the call will fit in 214 // the 32-bit pcrel field that we have. 215 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 216 (outs), (ins i64i32imm_pcrel:$dst, variable_ops), 217 "call{q}\t$dst", [], IIC_CALL_RI>, 218 Requires<[In64BitMode]>; 219 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops), 220 "call{q}\t{*}$dst", [(X86call GR64:$dst)], 221 IIC_CALL_RI>, 222 Requires<[In64BitMode]>; 223 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops), 224 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))], 225 IIC_CALL_MEM>, 226 Requires<[In64BitMode]>; 227 228 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), 229 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>; 230} 231 232let isCall = 1, isCodeGenOnly = 1 in 233 // __chkstk(MSVC): clobber R10, R11 and EFLAGS. 234 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP. 235 let Defs = [RAX, R10, R11, RSP, EFLAGS], 236 Uses = [RSP] in { 237 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm, 238 (outs), (ins i64i32imm_pcrel:$dst, variable_ops), 239 "call{q}\t$dst", [], IIC_CALL_RI>, 240 Requires<[IsWin64]>; 241 } 242 243let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 244 isCodeGenOnly = 1 in 245 let Uses = [RSP], 246 usesCustomInserter = 1 in { 247 def TCRETURNdi64 : PseudoI<(outs), 248 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops), 249 []>; 250 def TCRETURNri64 : PseudoI<(outs), 251 (ins ptr_rc_tailcall:$dst, i32imm:$offset, variable_ops), []>; 252 let mayLoad = 1 in 253 def TCRETURNmi64 : PseudoI<(outs), 254 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops), []>; 255 256 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), 257 (ins i64i32imm_pcrel:$dst, variable_ops), 258 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>; 259 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst, variable_ops), 260 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 261 262 let mayLoad = 1 in 263 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops), 264 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 265} 266