| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 4ccfbedaedc35920dc437aec501ec2bc4f8a4a2a |
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03-Sep-2013 |
Craig Topper <craig.topper@gmail.com> |
Add hadSideEffects=0 to some instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 816f6d0ac76c0ffb2ea9ecb72349d5d7d0fa8d1a |
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29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Skip moving call address loading into callseq when targets prefer register indirect call.
To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.
To prevent that, such moving is disabled when target favors register
indirect call.
Previous workaround disabling CALL32m/CALL64m insn selection is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 2bb3fcd490fd420f913f80d0753a4da61fd4a750 |
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26-Mar-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Annotate control instructions with SchedRW lists.
This could definitely be more granular. I am not sure if it makes a
difference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 9511a460d8dc2f5979365ad863e9e6c514043101 |
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24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Mark X86::RET and RETI instructions as variadic.
There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 85dccf18ea0e0b7258d1c5f186b616e022dbebf1 |
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05-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make X86 call and return instructions non-variadic.
Function argument and return value registers aren't part of the
encoding, so they should be implicit operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| cf661a040c2cdc490277c8cb6b51f486e68a9625 |
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09-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use ptr_rc_tailcall instead of GR32_TC.
The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 0d82fe77f2b6f48b5fab131c1671169d154f8c69 |
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11-Apr-2012 |
Charles Davis <cdavis@mines.edu> |
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
ret instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 930a1ebd929aa0ab4c2610e7f7a721c18dcfe052 |
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27-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 527a08b253795cf09de41c289c9dc071f00b1d4a |
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16-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the same CALL instructions for Windows as for everything else.
The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 8bcde2aa66415ba2e63b22d2a3c1750bfb25b550 |
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16-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Enable register mask operands for x86 calls.
Call instructions no longer have a list of 43 call-clobbered registers.
Instead, they get a single register mask operand with a bit vector of
call-preserved registers.
This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call
instruction, and it speeds up building call instructions because those
43 imp-def operands no longer need to be added to use-def lists. (And
removed and shifted and re-added for every explicit call operand).
Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and
BranchFolding are significantly faster because they can deal with call
clobbers in bulk.
Overall, clang -O2 is between 0% and 8% faster, uniformly distributed
depending on call density in the compiled code. Debug builds using
clang -O0 are 0% - 3% faster.
I have verified that this patch doesn't change the assembly generated
for the LLVM nightly test suite when building with -disable-copyprop
and -disable-branch-fold.
Branch folding behaves slightly differently in a few cases because call
instructions have different hash values now.
Copy propagation flushes its data structures when it crosses a register
mask operand. This causes it to leave a few dead copies behind, on the
order of 20 instruction across the entire nightly test suite, including
SPEC. Fixing this properly would require the pass to use different data
structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 922d314e8f9f0d8e447c055485a2969ee9cf2dd2 |
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02-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 53fa56e8dc60c8b594f22b888b4fb3c3b0567d82 |
|
26-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle call-clobbered ymm registers on Win64.
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| cf0e269d16f3d784b428c9b1b1e22d1f9e8bb91d |
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20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| a2e0762fae050464494a50c8b5d53ac2f4ba738c |
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24-Mar-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
FIXME: Some cleanups would be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 7754f85885f8a961cb403ef13ab39583492d2b1e |
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26-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Tweak win64's tailcall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| e5fffe9c3fa402cb5d5167327783f82b86f52b8f |
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26-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 7158e08b8e619f4dcac9834c57f5f8afd6eea2eb |
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03-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack in
prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if
the adjustment is 4 in 32-bit mode.
In the epilogue, takes care to pop to a caller-saved register that's not live
at the exit (either return or tailcall instruction).
rdar://8771137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 6bac79deb39c0c1fcd526f1a087bf6013b2826e9 |
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30-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violations
while I'm in there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 269f10b316b41fde5c9bf3f6e5c471f371862834 |
|
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
accept lret as an alias for lretl, fixing the reopened part of PR8592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 6b5e3978e3f720f6d2828068157b9d9687aee711 |
|
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
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| 7aef62ff8c72506cc9b77333d25f4aa8aa9cf9fe |
|
18-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added a handful of x86-32 instructions that were missing so that llvm-mc would
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
|
| 87be16a9e1a08b2f761023f3f01d1574c58f5b6f |
|
05-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
continue moving stuff out to X86InstrSystem.td. Move
control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrControl.td
|