X86InstrInfo.cpp revision 5446274bd242e1f23547ce57aa4d411e46e9acb8
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/LiveVariables.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/Target/TargetAsmInfo.h" 31 32using namespace llvm; 33 34namespace { 35 cl::opt<bool> 36 NoFusing("disable-spill-fusing", 37 cl::desc("Disable fusing of spill code into instructions")); 38 cl::opt<bool> 39 PrintFailedFusing("print-failed-fuse-candidates", 40 cl::desc("Print instructions that the allocator wants to" 41 " fuse, but the X86 backend currently can't"), 42 cl::Hidden); 43 cl::opt<bool> 44 ReMatPICStubLoad("remat-pic-stub-load", 45 cl::desc("Re-materialize load from stub in PIC mode"), 46 cl::init(false), cl::Hidden); 47} 48 49X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 50 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 51 TM(tm), RI(tm, *this) { 52 SmallVector<unsigned,16> AmbEntries; 53 static const unsigned OpTbl2Addr[][2] = { 54 { X86::ADC32ri, X86::ADC32mi }, 55 { X86::ADC32ri8, X86::ADC32mi8 }, 56 { X86::ADC32rr, X86::ADC32mr }, 57 { X86::ADC64ri32, X86::ADC64mi32 }, 58 { X86::ADC64ri8, X86::ADC64mi8 }, 59 { X86::ADC64rr, X86::ADC64mr }, 60 { X86::ADD16ri, X86::ADD16mi }, 61 { X86::ADD16ri8, X86::ADD16mi8 }, 62 { X86::ADD16rr, X86::ADD16mr }, 63 { X86::ADD32ri, X86::ADD32mi }, 64 { X86::ADD32ri8, X86::ADD32mi8 }, 65 { X86::ADD32rr, X86::ADD32mr }, 66 { X86::ADD64ri32, X86::ADD64mi32 }, 67 { X86::ADD64ri8, X86::ADD64mi8 }, 68 { X86::ADD64rr, X86::ADD64mr }, 69 { X86::ADD8ri, X86::ADD8mi }, 70 { X86::ADD8rr, X86::ADD8mr }, 71 { X86::AND16ri, X86::AND16mi }, 72 { X86::AND16ri8, X86::AND16mi8 }, 73 { X86::AND16rr, X86::AND16mr }, 74 { X86::AND32ri, X86::AND32mi }, 75 { X86::AND32ri8, X86::AND32mi8 }, 76 { X86::AND32rr, X86::AND32mr }, 77 { X86::AND64ri32, X86::AND64mi32 }, 78 { X86::AND64ri8, X86::AND64mi8 }, 79 { X86::AND64rr, X86::AND64mr }, 80 { X86::AND8ri, X86::AND8mi }, 81 { X86::AND8rr, X86::AND8mr }, 82 { X86::DEC16r, X86::DEC16m }, 83 { X86::DEC32r, X86::DEC32m }, 84 { X86::DEC64_16r, X86::DEC64_16m }, 85 { X86::DEC64_32r, X86::DEC64_32m }, 86 { X86::DEC64r, X86::DEC64m }, 87 { X86::DEC8r, X86::DEC8m }, 88 { X86::INC16r, X86::INC16m }, 89 { X86::INC32r, X86::INC32m }, 90 { X86::INC64_16r, X86::INC64_16m }, 91 { X86::INC64_32r, X86::INC64_32m }, 92 { X86::INC64r, X86::INC64m }, 93 { X86::INC8r, X86::INC8m }, 94 { X86::NEG16r, X86::NEG16m }, 95 { X86::NEG32r, X86::NEG32m }, 96 { X86::NEG64r, X86::NEG64m }, 97 { X86::NEG8r, X86::NEG8m }, 98 { X86::NOT16r, X86::NOT16m }, 99 { X86::NOT32r, X86::NOT32m }, 100 { X86::NOT64r, X86::NOT64m }, 101 { X86::NOT8r, X86::NOT8m }, 102 { X86::OR16ri, X86::OR16mi }, 103 { X86::OR16ri8, X86::OR16mi8 }, 104 { X86::OR16rr, X86::OR16mr }, 105 { X86::OR32ri, X86::OR32mi }, 106 { X86::OR32ri8, X86::OR32mi8 }, 107 { X86::OR32rr, X86::OR32mr }, 108 { X86::OR64ri32, X86::OR64mi32 }, 109 { X86::OR64ri8, X86::OR64mi8 }, 110 { X86::OR64rr, X86::OR64mr }, 111 { X86::OR8ri, X86::OR8mi }, 112 { X86::OR8rr, X86::OR8mr }, 113 { X86::ROL16r1, X86::ROL16m1 }, 114 { X86::ROL16rCL, X86::ROL16mCL }, 115 { X86::ROL16ri, X86::ROL16mi }, 116 { X86::ROL32r1, X86::ROL32m1 }, 117 { X86::ROL32rCL, X86::ROL32mCL }, 118 { X86::ROL32ri, X86::ROL32mi }, 119 { X86::ROL64r1, X86::ROL64m1 }, 120 { X86::ROL64rCL, X86::ROL64mCL }, 121 { X86::ROL64ri, X86::ROL64mi }, 122 { X86::ROL8r1, X86::ROL8m1 }, 123 { X86::ROL8rCL, X86::ROL8mCL }, 124 { X86::ROL8ri, X86::ROL8mi }, 125 { X86::ROR16r1, X86::ROR16m1 }, 126 { X86::ROR16rCL, X86::ROR16mCL }, 127 { X86::ROR16ri, X86::ROR16mi }, 128 { X86::ROR32r1, X86::ROR32m1 }, 129 { X86::ROR32rCL, X86::ROR32mCL }, 130 { X86::ROR32ri, X86::ROR32mi }, 131 { X86::ROR64r1, X86::ROR64m1 }, 132 { X86::ROR64rCL, X86::ROR64mCL }, 133 { X86::ROR64ri, X86::ROR64mi }, 134 { X86::ROR8r1, X86::ROR8m1 }, 135 { X86::ROR8rCL, X86::ROR8mCL }, 136 { X86::ROR8ri, X86::ROR8mi }, 137 { X86::SAR16r1, X86::SAR16m1 }, 138 { X86::SAR16rCL, X86::SAR16mCL }, 139 { X86::SAR16ri, X86::SAR16mi }, 140 { X86::SAR32r1, X86::SAR32m1 }, 141 { X86::SAR32rCL, X86::SAR32mCL }, 142 { X86::SAR32ri, X86::SAR32mi }, 143 { X86::SAR64r1, X86::SAR64m1 }, 144 { X86::SAR64rCL, X86::SAR64mCL }, 145 { X86::SAR64ri, X86::SAR64mi }, 146 { X86::SAR8r1, X86::SAR8m1 }, 147 { X86::SAR8rCL, X86::SAR8mCL }, 148 { X86::SAR8ri, X86::SAR8mi }, 149 { X86::SBB32ri, X86::SBB32mi }, 150 { X86::SBB32ri8, X86::SBB32mi8 }, 151 { X86::SBB32rr, X86::SBB32mr }, 152 { X86::SBB64ri32, X86::SBB64mi32 }, 153 { X86::SBB64ri8, X86::SBB64mi8 }, 154 { X86::SBB64rr, X86::SBB64mr }, 155 { X86::SHL16rCL, X86::SHL16mCL }, 156 { X86::SHL16ri, X86::SHL16mi }, 157 { X86::SHL32rCL, X86::SHL32mCL }, 158 { X86::SHL32ri, X86::SHL32mi }, 159 { X86::SHL64rCL, X86::SHL64mCL }, 160 { X86::SHL64ri, X86::SHL64mi }, 161 { X86::SHL8rCL, X86::SHL8mCL }, 162 { X86::SHL8ri, X86::SHL8mi }, 163 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 164 { X86::SHLD16rri8, X86::SHLD16mri8 }, 165 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 166 { X86::SHLD32rri8, X86::SHLD32mri8 }, 167 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 168 { X86::SHLD64rri8, X86::SHLD64mri8 }, 169 { X86::SHR16r1, X86::SHR16m1 }, 170 { X86::SHR16rCL, X86::SHR16mCL }, 171 { X86::SHR16ri, X86::SHR16mi }, 172 { X86::SHR32r1, X86::SHR32m1 }, 173 { X86::SHR32rCL, X86::SHR32mCL }, 174 { X86::SHR32ri, X86::SHR32mi }, 175 { X86::SHR64r1, X86::SHR64m1 }, 176 { X86::SHR64rCL, X86::SHR64mCL }, 177 { X86::SHR64ri, X86::SHR64mi }, 178 { X86::SHR8r1, X86::SHR8m1 }, 179 { X86::SHR8rCL, X86::SHR8mCL }, 180 { X86::SHR8ri, X86::SHR8mi }, 181 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 182 { X86::SHRD16rri8, X86::SHRD16mri8 }, 183 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 184 { X86::SHRD32rri8, X86::SHRD32mri8 }, 185 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 186 { X86::SHRD64rri8, X86::SHRD64mri8 }, 187 { X86::SUB16ri, X86::SUB16mi }, 188 { X86::SUB16ri8, X86::SUB16mi8 }, 189 { X86::SUB16rr, X86::SUB16mr }, 190 { X86::SUB32ri, X86::SUB32mi }, 191 { X86::SUB32ri8, X86::SUB32mi8 }, 192 { X86::SUB32rr, X86::SUB32mr }, 193 { X86::SUB64ri32, X86::SUB64mi32 }, 194 { X86::SUB64ri8, X86::SUB64mi8 }, 195 { X86::SUB64rr, X86::SUB64mr }, 196 { X86::SUB8ri, X86::SUB8mi }, 197 { X86::SUB8rr, X86::SUB8mr }, 198 { X86::XOR16ri, X86::XOR16mi }, 199 { X86::XOR16ri8, X86::XOR16mi8 }, 200 { X86::XOR16rr, X86::XOR16mr }, 201 { X86::XOR32ri, X86::XOR32mi }, 202 { X86::XOR32ri8, X86::XOR32mi8 }, 203 { X86::XOR32rr, X86::XOR32mr }, 204 { X86::XOR64ri32, X86::XOR64mi32 }, 205 { X86::XOR64ri8, X86::XOR64mi8 }, 206 { X86::XOR64rr, X86::XOR64mr }, 207 { X86::XOR8ri, X86::XOR8mi }, 208 { X86::XOR8rr, X86::XOR8mr } 209 }; 210 211 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 212 unsigned RegOp = OpTbl2Addr[i][0]; 213 unsigned MemOp = OpTbl2Addr[i][1]; 214 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 215 MemOp)).second) 216 assert(false && "Duplicated entries?"); 217 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store 218 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 219 std::make_pair(RegOp, 220 AuxInfo))).second) 221 AmbEntries.push_back(MemOp); 222 } 223 224 // If the third value is 1, then it's folding either a load or a store. 225 static const unsigned OpTbl0[][3] = { 226 { X86::CALL32r, X86::CALL32m, 1 }, 227 { X86::CALL64r, X86::CALL64m, 1 }, 228 { X86::CMP16ri, X86::CMP16mi, 1 }, 229 { X86::CMP16ri8, X86::CMP16mi8, 1 }, 230 { X86::CMP16rr, X86::CMP16mr, 1 }, 231 { X86::CMP32ri, X86::CMP32mi, 1 }, 232 { X86::CMP32ri8, X86::CMP32mi8, 1 }, 233 { X86::CMP32rr, X86::CMP32mr, 1 }, 234 { X86::CMP64ri32, X86::CMP64mi32, 1 }, 235 { X86::CMP64ri8, X86::CMP64mi8, 1 }, 236 { X86::CMP64rr, X86::CMP64mr, 1 }, 237 { X86::CMP8ri, X86::CMP8mi, 1 }, 238 { X86::CMP8rr, X86::CMP8mr, 1 }, 239 { X86::DIV16r, X86::DIV16m, 1 }, 240 { X86::DIV32r, X86::DIV32m, 1 }, 241 { X86::DIV64r, X86::DIV64m, 1 }, 242 { X86::DIV8r, X86::DIV8m, 1 }, 243 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 }, 244 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 }, 245 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 }, 246 { X86::IDIV16r, X86::IDIV16m, 1 }, 247 { X86::IDIV32r, X86::IDIV32m, 1 }, 248 { X86::IDIV64r, X86::IDIV64m, 1 }, 249 { X86::IDIV8r, X86::IDIV8m, 1 }, 250 { X86::IMUL16r, X86::IMUL16m, 1 }, 251 { X86::IMUL32r, X86::IMUL32m, 1 }, 252 { X86::IMUL64r, X86::IMUL64m, 1 }, 253 { X86::IMUL8r, X86::IMUL8m, 1 }, 254 { X86::JMP32r, X86::JMP32m, 1 }, 255 { X86::JMP64r, X86::JMP64m, 1 }, 256 { X86::MOV16ri, X86::MOV16mi, 0 }, 257 { X86::MOV16rr, X86::MOV16mr, 0 }, 258 { X86::MOV16to16_, X86::MOV16_mr, 0 }, 259 { X86::MOV32ri, X86::MOV32mi, 0 }, 260 { X86::MOV32rr, X86::MOV32mr, 0 }, 261 { X86::MOV32to32_, X86::MOV32_mr, 0 }, 262 { X86::MOV64ri32, X86::MOV64mi32, 0 }, 263 { X86::MOV64rr, X86::MOV64mr, 0 }, 264 { X86::MOV8ri, X86::MOV8mi, 0 }, 265 { X86::MOV8rr, X86::MOV8mr, 0 }, 266 { X86::MOVAPDrr, X86::MOVAPDmr, 0 }, 267 { X86::MOVAPSrr, X86::MOVAPSmr, 0 }, 268 { X86::MOVDQArr, X86::MOVDQAmr, 0 }, 269 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 }, 270 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 }, 271 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 }, 272 { X86::MOVSDrr, X86::MOVSDmr, 0 }, 273 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 }, 274 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 }, 275 { X86::MOVSSrr, X86::MOVSSmr, 0 }, 276 { X86::MOVUPDrr, X86::MOVUPDmr, 0 }, 277 { X86::MOVUPSrr, X86::MOVUPSmr, 0 }, 278 { X86::MUL16r, X86::MUL16m, 1 }, 279 { X86::MUL32r, X86::MUL32m, 1 }, 280 { X86::MUL64r, X86::MUL64m, 1 }, 281 { X86::MUL8r, X86::MUL8m, 1 }, 282 { X86::SETAEr, X86::SETAEm, 0 }, 283 { X86::SETAr, X86::SETAm, 0 }, 284 { X86::SETBEr, X86::SETBEm, 0 }, 285 { X86::SETBr, X86::SETBm, 0 }, 286 { X86::SETEr, X86::SETEm, 0 }, 287 { X86::SETGEr, X86::SETGEm, 0 }, 288 { X86::SETGr, X86::SETGm, 0 }, 289 { X86::SETLEr, X86::SETLEm, 0 }, 290 { X86::SETLr, X86::SETLm, 0 }, 291 { X86::SETNEr, X86::SETNEm, 0 }, 292 { X86::SETNOr, X86::SETNOm, 0 }, 293 { X86::SETNPr, X86::SETNPm, 0 }, 294 { X86::SETNSr, X86::SETNSm, 0 }, 295 { X86::SETOr, X86::SETOm, 0 }, 296 { X86::SETPr, X86::SETPm, 0 }, 297 { X86::SETSr, X86::SETSm, 0 }, 298 { X86::TAILJMPr, X86::TAILJMPm, 1 }, 299 { X86::TEST16ri, X86::TEST16mi, 1 }, 300 { X86::TEST32ri, X86::TEST32mi, 1 }, 301 { X86::TEST64ri32, X86::TEST64mi32, 1 }, 302 { X86::TEST8ri, X86::TEST8mi, 1 } 303 }; 304 305 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 306 unsigned RegOp = OpTbl0[i][0]; 307 unsigned MemOp = OpTbl0[i][1]; 308 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 309 MemOp)).second) 310 assert(false && "Duplicated entries?"); 311 unsigned FoldedLoad = OpTbl0[i][2]; 312 // Index 0, folded load or store. 313 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 314 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 315 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 316 std::make_pair(RegOp, AuxInfo))).second) 317 AmbEntries.push_back(MemOp); 318 } 319 320 static const unsigned OpTbl1[][2] = { 321 { X86::CMP16rr, X86::CMP16rm }, 322 { X86::CMP32rr, X86::CMP32rm }, 323 { X86::CMP64rr, X86::CMP64rm }, 324 { X86::CMP8rr, X86::CMP8rm }, 325 { X86::CVTSD2SSrr, X86::CVTSD2SSrm }, 326 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm }, 327 { X86::CVTSI2SDrr, X86::CVTSI2SDrm }, 328 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm }, 329 { X86::CVTSI2SSrr, X86::CVTSI2SSrm }, 330 { X86::CVTSS2SDrr, X86::CVTSS2SDrm }, 331 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm }, 332 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm }, 333 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm }, 334 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm }, 335 { X86::FsMOVAPDrr, X86::MOVSDrm }, 336 { X86::FsMOVAPSrr, X86::MOVSSrm }, 337 { X86::IMUL16rri, X86::IMUL16rmi }, 338 { X86::IMUL16rri8, X86::IMUL16rmi8 }, 339 { X86::IMUL32rri, X86::IMUL32rmi }, 340 { X86::IMUL32rri8, X86::IMUL32rmi8 }, 341 { X86::IMUL64rri32, X86::IMUL64rmi32 }, 342 { X86::IMUL64rri8, X86::IMUL64rmi8 }, 343 { X86::Int_CMPSDrr, X86::Int_CMPSDrm }, 344 { X86::Int_CMPSSrr, X86::Int_CMPSSrm }, 345 { X86::Int_COMISDrr, X86::Int_COMISDrm }, 346 { X86::Int_COMISSrr, X86::Int_COMISSrm }, 347 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm }, 348 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm }, 349 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm }, 350 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm }, 351 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm }, 352 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm }, 353 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm }, 354 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm }, 355 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm }, 356 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm }, 357 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm }, 358 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm }, 359 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm }, 360 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm }, 361 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm }, 362 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm }, 363 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm }, 364 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm }, 365 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm }, 366 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm }, 367 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm }, 368 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm }, 369 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm }, 370 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm }, 371 { X86::MOV16rr, X86::MOV16rm }, 372 { X86::MOV16to16_, X86::MOV16_rm }, 373 { X86::MOV32rr, X86::MOV32rm }, 374 { X86::MOV32to32_, X86::MOV32_rm }, 375 { X86::MOV64rr, X86::MOV64rm }, 376 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm }, 377 { X86::MOV64toSDrr, X86::MOV64toSDrm }, 378 { X86::MOV8rr, X86::MOV8rm }, 379 { X86::MOVAPDrr, X86::MOVAPDrm }, 380 { X86::MOVAPSrr, X86::MOVAPSrm }, 381 { X86::MOVDDUPrr, X86::MOVDDUPrm }, 382 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, 383 { X86::MOVDI2SSrr, X86::MOVDI2SSrm }, 384 { X86::MOVDQArr, X86::MOVDQArm }, 385 { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, 386 { X86::MOVSDrr, X86::MOVSDrm }, 387 { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, 388 { X86::MOVSLDUPrr, X86::MOVSLDUPrm }, 389 { X86::MOVSS2PSrr, X86::MOVSS2PSrm }, 390 { X86::MOVSSrr, X86::MOVSSrm }, 391 { X86::MOVSX16rr8, X86::MOVSX16rm8 }, 392 { X86::MOVSX32rr16, X86::MOVSX32rm16 }, 393 { X86::MOVSX32rr8, X86::MOVSX32rm8 }, 394 { X86::MOVSX64rr16, X86::MOVSX64rm16 }, 395 { X86::MOVSX64rr32, X86::MOVSX64rm32 }, 396 { X86::MOVSX64rr8, X86::MOVSX64rm8 }, 397 { X86::MOVUPDrr, X86::MOVUPDrm }, 398 { X86::MOVUPSrr, X86::MOVUPSrm }, 399 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm }, 400 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm }, 401 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm }, 402 { X86::MOVZX16rr8, X86::MOVZX16rm8 }, 403 { X86::MOVZX32rr16, X86::MOVZX32rm16 }, 404 { X86::MOVZX32rr8, X86::MOVZX32rm8 }, 405 { X86::MOVZX64rr16, X86::MOVZX64rm16 }, 406 { X86::MOVZX64rr32, X86::MOVZX64rm32 }, 407 { X86::MOVZX64rr8, X86::MOVZX64rm8 }, 408 { X86::PSHUFDri, X86::PSHUFDmi }, 409 { X86::PSHUFHWri, X86::PSHUFHWmi }, 410 { X86::PSHUFLWri, X86::PSHUFLWmi }, 411 { X86::RCPPSr, X86::RCPPSm }, 412 { X86::RCPPSr_Int, X86::RCPPSm_Int }, 413 { X86::RSQRTPSr, X86::RSQRTPSm }, 414 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int }, 415 { X86::RSQRTSSr, X86::RSQRTSSm }, 416 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int }, 417 { X86::SQRTPDr, X86::SQRTPDm }, 418 { X86::SQRTPDr_Int, X86::SQRTPDm_Int }, 419 { X86::SQRTPSr, X86::SQRTPSm }, 420 { X86::SQRTPSr_Int, X86::SQRTPSm_Int }, 421 { X86::SQRTSDr, X86::SQRTSDm }, 422 { X86::SQRTSDr_Int, X86::SQRTSDm_Int }, 423 { X86::SQRTSSr, X86::SQRTSSm }, 424 { X86::SQRTSSr_Int, X86::SQRTSSm_Int }, 425 { X86::TEST16rr, X86::TEST16rm }, 426 { X86::TEST32rr, X86::TEST32rm }, 427 { X86::TEST64rr, X86::TEST64rm }, 428 { X86::TEST8rr, X86::TEST8rm }, 429 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 430 { X86::UCOMISDrr, X86::UCOMISDrm }, 431 { X86::UCOMISSrr, X86::UCOMISSrm } 432 }; 433 434 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 435 unsigned RegOp = OpTbl1[i][0]; 436 unsigned MemOp = OpTbl1[i][1]; 437 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 438 MemOp)).second) 439 assert(false && "Duplicated entries?"); 440 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load 441 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 442 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 443 std::make_pair(RegOp, AuxInfo))).second) 444 AmbEntries.push_back(MemOp); 445 } 446 447 static const unsigned OpTbl2[][2] = { 448 { X86::ADC32rr, X86::ADC32rm }, 449 { X86::ADC64rr, X86::ADC64rm }, 450 { X86::ADD16rr, X86::ADD16rm }, 451 { X86::ADD32rr, X86::ADD32rm }, 452 { X86::ADD64rr, X86::ADD64rm }, 453 { X86::ADD8rr, X86::ADD8rm }, 454 { X86::ADDPDrr, X86::ADDPDrm }, 455 { X86::ADDPSrr, X86::ADDPSrm }, 456 { X86::ADDSDrr, X86::ADDSDrm }, 457 { X86::ADDSSrr, X86::ADDSSrm }, 458 { X86::ADDSUBPDrr, X86::ADDSUBPDrm }, 459 { X86::ADDSUBPSrr, X86::ADDSUBPSrm }, 460 { X86::AND16rr, X86::AND16rm }, 461 { X86::AND32rr, X86::AND32rm }, 462 { X86::AND64rr, X86::AND64rm }, 463 { X86::AND8rr, X86::AND8rm }, 464 { X86::ANDNPDrr, X86::ANDNPDrm }, 465 { X86::ANDNPSrr, X86::ANDNPSrm }, 466 { X86::ANDPDrr, X86::ANDPDrm }, 467 { X86::ANDPSrr, X86::ANDPSrm }, 468 { X86::CMOVA16rr, X86::CMOVA16rm }, 469 { X86::CMOVA32rr, X86::CMOVA32rm }, 470 { X86::CMOVA64rr, X86::CMOVA64rm }, 471 { X86::CMOVAE16rr, X86::CMOVAE16rm }, 472 { X86::CMOVAE32rr, X86::CMOVAE32rm }, 473 { X86::CMOVAE64rr, X86::CMOVAE64rm }, 474 { X86::CMOVB16rr, X86::CMOVB16rm }, 475 { X86::CMOVB32rr, X86::CMOVB32rm }, 476 { X86::CMOVB64rr, X86::CMOVB64rm }, 477 { X86::CMOVBE16rr, X86::CMOVBE16rm }, 478 { X86::CMOVBE32rr, X86::CMOVBE32rm }, 479 { X86::CMOVBE64rr, X86::CMOVBE64rm }, 480 { X86::CMOVE16rr, X86::CMOVE16rm }, 481 { X86::CMOVE32rr, X86::CMOVE32rm }, 482 { X86::CMOVE64rr, X86::CMOVE64rm }, 483 { X86::CMOVG16rr, X86::CMOVG16rm }, 484 { X86::CMOVG32rr, X86::CMOVG32rm }, 485 { X86::CMOVG64rr, X86::CMOVG64rm }, 486 { X86::CMOVGE16rr, X86::CMOVGE16rm }, 487 { X86::CMOVGE32rr, X86::CMOVGE32rm }, 488 { X86::CMOVGE64rr, X86::CMOVGE64rm }, 489 { X86::CMOVL16rr, X86::CMOVL16rm }, 490 { X86::CMOVL32rr, X86::CMOVL32rm }, 491 { X86::CMOVL64rr, X86::CMOVL64rm }, 492 { X86::CMOVLE16rr, X86::CMOVLE16rm }, 493 { X86::CMOVLE32rr, X86::CMOVLE32rm }, 494 { X86::CMOVLE64rr, X86::CMOVLE64rm }, 495 { X86::CMOVNE16rr, X86::CMOVNE16rm }, 496 { X86::CMOVNE32rr, X86::CMOVNE32rm }, 497 { X86::CMOVNE64rr, X86::CMOVNE64rm }, 498 { X86::CMOVNO16rr, X86::CMOVNO16rm }, 499 { X86::CMOVNO32rr, X86::CMOVNO32rm }, 500 { X86::CMOVNO64rr, X86::CMOVNO64rm }, 501 { X86::CMOVNP16rr, X86::CMOVNP16rm }, 502 { X86::CMOVNP32rr, X86::CMOVNP32rm }, 503 { X86::CMOVNP64rr, X86::CMOVNP64rm }, 504 { X86::CMOVNS16rr, X86::CMOVNS16rm }, 505 { X86::CMOVNS32rr, X86::CMOVNS32rm }, 506 { X86::CMOVNS64rr, X86::CMOVNS64rm }, 507 { X86::CMOVO16rr, X86::CMOVO16rm }, 508 { X86::CMOVO32rr, X86::CMOVO32rm }, 509 { X86::CMOVO64rr, X86::CMOVO64rm }, 510 { X86::CMOVP16rr, X86::CMOVP16rm }, 511 { X86::CMOVP32rr, X86::CMOVP32rm }, 512 { X86::CMOVP64rr, X86::CMOVP64rm }, 513 { X86::CMOVS16rr, X86::CMOVS16rm }, 514 { X86::CMOVS32rr, X86::CMOVS32rm }, 515 { X86::CMOVS64rr, X86::CMOVS64rm }, 516 { X86::CMPPDrri, X86::CMPPDrmi }, 517 { X86::CMPPSrri, X86::CMPPSrmi }, 518 { X86::CMPSDrr, X86::CMPSDrm }, 519 { X86::CMPSSrr, X86::CMPSSrm }, 520 { X86::DIVPDrr, X86::DIVPDrm }, 521 { X86::DIVPSrr, X86::DIVPSrm }, 522 { X86::DIVSDrr, X86::DIVSDrm }, 523 { X86::DIVSSrr, X86::DIVSSrm }, 524 { X86::FsANDNPDrr, X86::FsANDNPDrm }, 525 { X86::FsANDNPSrr, X86::FsANDNPSrm }, 526 { X86::FsANDPDrr, X86::FsANDPDrm }, 527 { X86::FsANDPSrr, X86::FsANDPSrm }, 528 { X86::FsORPDrr, X86::FsORPDrm }, 529 { X86::FsORPSrr, X86::FsORPSrm }, 530 { X86::FsXORPDrr, X86::FsXORPDrm }, 531 { X86::FsXORPSrr, X86::FsXORPSrm }, 532 { X86::HADDPDrr, X86::HADDPDrm }, 533 { X86::HADDPSrr, X86::HADDPSrm }, 534 { X86::HSUBPDrr, X86::HSUBPDrm }, 535 { X86::HSUBPSrr, X86::HSUBPSrm }, 536 { X86::IMUL16rr, X86::IMUL16rm }, 537 { X86::IMUL32rr, X86::IMUL32rm }, 538 { X86::IMUL64rr, X86::IMUL64rm }, 539 { X86::MAXPDrr, X86::MAXPDrm }, 540 { X86::MAXPDrr_Int, X86::MAXPDrm_Int }, 541 { X86::MAXPSrr, X86::MAXPSrm }, 542 { X86::MAXPSrr_Int, X86::MAXPSrm_Int }, 543 { X86::MAXSDrr, X86::MAXSDrm }, 544 { X86::MAXSDrr_Int, X86::MAXSDrm_Int }, 545 { X86::MAXSSrr, X86::MAXSSrm }, 546 { X86::MAXSSrr_Int, X86::MAXSSrm_Int }, 547 { X86::MINPDrr, X86::MINPDrm }, 548 { X86::MINPDrr_Int, X86::MINPDrm_Int }, 549 { X86::MINPSrr, X86::MINPSrm }, 550 { X86::MINPSrr_Int, X86::MINPSrm_Int }, 551 { X86::MINSDrr, X86::MINSDrm }, 552 { X86::MINSDrr_Int, X86::MINSDrm_Int }, 553 { X86::MINSSrr, X86::MINSSrm }, 554 { X86::MINSSrr_Int, X86::MINSSrm_Int }, 555 { X86::MULPDrr, X86::MULPDrm }, 556 { X86::MULPSrr, X86::MULPSrm }, 557 { X86::MULSDrr, X86::MULSDrm }, 558 { X86::MULSSrr, X86::MULSSrm }, 559 { X86::OR16rr, X86::OR16rm }, 560 { X86::OR32rr, X86::OR32rm }, 561 { X86::OR64rr, X86::OR64rm }, 562 { X86::OR8rr, X86::OR8rm }, 563 { X86::ORPDrr, X86::ORPDrm }, 564 { X86::ORPSrr, X86::ORPSrm }, 565 { X86::PACKSSDWrr, X86::PACKSSDWrm }, 566 { X86::PACKSSWBrr, X86::PACKSSWBrm }, 567 { X86::PACKUSWBrr, X86::PACKUSWBrm }, 568 { X86::PADDBrr, X86::PADDBrm }, 569 { X86::PADDDrr, X86::PADDDrm }, 570 { X86::PADDQrr, X86::PADDQrm }, 571 { X86::PADDSBrr, X86::PADDSBrm }, 572 { X86::PADDSWrr, X86::PADDSWrm }, 573 { X86::PADDWrr, X86::PADDWrm }, 574 { X86::PANDNrr, X86::PANDNrm }, 575 { X86::PANDrr, X86::PANDrm }, 576 { X86::PAVGBrr, X86::PAVGBrm }, 577 { X86::PAVGWrr, X86::PAVGWrm }, 578 { X86::PCMPEQBrr, X86::PCMPEQBrm }, 579 { X86::PCMPEQDrr, X86::PCMPEQDrm }, 580 { X86::PCMPEQWrr, X86::PCMPEQWrm }, 581 { X86::PCMPGTBrr, X86::PCMPGTBrm }, 582 { X86::PCMPGTDrr, X86::PCMPGTDrm }, 583 { X86::PCMPGTWrr, X86::PCMPGTWrm }, 584 { X86::PINSRWrri, X86::PINSRWrmi }, 585 { X86::PMADDWDrr, X86::PMADDWDrm }, 586 { X86::PMAXSWrr, X86::PMAXSWrm }, 587 { X86::PMAXUBrr, X86::PMAXUBrm }, 588 { X86::PMINSWrr, X86::PMINSWrm }, 589 { X86::PMINUBrr, X86::PMINUBrm }, 590 { X86::PMULDQrr, X86::PMULDQrm }, 591 { X86::PMULHUWrr, X86::PMULHUWrm }, 592 { X86::PMULHWrr, X86::PMULHWrm }, 593 { X86::PMULLDrr, X86::PMULLDrm }, 594 { X86::PMULLDrr_int, X86::PMULLDrm_int }, 595 { X86::PMULLWrr, X86::PMULLWrm }, 596 { X86::PMULUDQrr, X86::PMULUDQrm }, 597 { X86::PORrr, X86::PORrm }, 598 { X86::PSADBWrr, X86::PSADBWrm }, 599 { X86::PSLLDrr, X86::PSLLDrm }, 600 { X86::PSLLQrr, X86::PSLLQrm }, 601 { X86::PSLLWrr, X86::PSLLWrm }, 602 { X86::PSRADrr, X86::PSRADrm }, 603 { X86::PSRAWrr, X86::PSRAWrm }, 604 { X86::PSRLDrr, X86::PSRLDrm }, 605 { X86::PSRLQrr, X86::PSRLQrm }, 606 { X86::PSRLWrr, X86::PSRLWrm }, 607 { X86::PSUBBrr, X86::PSUBBrm }, 608 { X86::PSUBDrr, X86::PSUBDrm }, 609 { X86::PSUBSBrr, X86::PSUBSBrm }, 610 { X86::PSUBSWrr, X86::PSUBSWrm }, 611 { X86::PSUBWrr, X86::PSUBWrm }, 612 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm }, 613 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm }, 614 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm }, 615 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm }, 616 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm }, 617 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm }, 618 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm }, 619 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm }, 620 { X86::PXORrr, X86::PXORrm }, 621 { X86::SBB32rr, X86::SBB32rm }, 622 { X86::SBB64rr, X86::SBB64rm }, 623 { X86::SHUFPDrri, X86::SHUFPDrmi }, 624 { X86::SHUFPSrri, X86::SHUFPSrmi }, 625 { X86::SUB16rr, X86::SUB16rm }, 626 { X86::SUB32rr, X86::SUB32rm }, 627 { X86::SUB64rr, X86::SUB64rm }, 628 { X86::SUB8rr, X86::SUB8rm }, 629 { X86::SUBPDrr, X86::SUBPDrm }, 630 { X86::SUBPSrr, X86::SUBPSrm }, 631 { X86::SUBSDrr, X86::SUBSDrm }, 632 { X86::SUBSSrr, X86::SUBSSrm }, 633 // FIXME: TEST*rr -> swapped operand of TEST*mr. 634 { X86::UNPCKHPDrr, X86::UNPCKHPDrm }, 635 { X86::UNPCKHPSrr, X86::UNPCKHPSrm }, 636 { X86::UNPCKLPDrr, X86::UNPCKLPDrm }, 637 { X86::UNPCKLPSrr, X86::UNPCKLPSrm }, 638 { X86::XOR16rr, X86::XOR16rm }, 639 { X86::XOR32rr, X86::XOR32rm }, 640 { X86::XOR64rr, X86::XOR64rm }, 641 { X86::XOR8rr, X86::XOR8rm }, 642 { X86::XORPDrr, X86::XORPDrm }, 643 { X86::XORPSrr, X86::XORPSrm } 644 }; 645 646 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 647 unsigned RegOp = OpTbl2[i][0]; 648 unsigned MemOp = OpTbl2[i][1]; 649 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 650 MemOp)).second) 651 assert(false && "Duplicated entries?"); 652 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load 653 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 654 std::make_pair(RegOp, AuxInfo))).second) 655 AmbEntries.push_back(MemOp); 656 } 657 658 // Remove ambiguous entries. 659 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 660} 661 662bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 663 unsigned& sourceReg, 664 unsigned& destReg) const { 665 switch (MI.getOpcode()) { 666 default: 667 return false; 668 case X86::MOV8rr: 669 case X86::MOV16rr: 670 case X86::MOV32rr: 671 case X86::MOV64rr: 672 case X86::MOV16to16_: 673 case X86::MOV32to32_: 674 case X86::MOVSSrr: 675 case X86::MOVSDrr: 676 677 // FP Stack register class copies 678 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: 679 case X86::MOV_Fp3264: case X86::MOV_Fp3280: 680 case X86::MOV_Fp6432: case X86::MOV_Fp8032: 681 682 case X86::FsMOVAPSrr: 683 case X86::FsMOVAPDrr: 684 case X86::MOVAPSrr: 685 case X86::MOVAPDrr: 686 case X86::MOVDQArr: 687 case X86::MOVSS2PSrr: 688 case X86::MOVSD2PDrr: 689 case X86::MOVPS2SSrr: 690 case X86::MOVPD2SDrr: 691 case X86::MMX_MOVD64rr: 692 case X86::MMX_MOVQ64rr: 693 assert(MI.getNumOperands() >= 2 && 694 MI.getOperand(0).isReg() && 695 MI.getOperand(1).isReg() && 696 "invalid register-register move instruction"); 697 sourceReg = MI.getOperand(1).getReg(); 698 destReg = MI.getOperand(0).getReg(); 699 return true; 700 } 701} 702 703unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 704 int &FrameIndex) const { 705 switch (MI->getOpcode()) { 706 default: break; 707 case X86::MOV8rm: 708 case X86::MOV16rm: 709 case X86::MOV16_rm: 710 case X86::MOV32rm: 711 case X86::MOV32_rm: 712 case X86::MOV64rm: 713 case X86::LD_Fp64m: 714 case X86::MOVSSrm: 715 case X86::MOVSDrm: 716 case X86::MOVAPSrm: 717 case X86::MOVAPDrm: 718 case X86::MOVDQArm: 719 case X86::MMX_MOVD64rm: 720 case X86::MMX_MOVQ64rm: 721 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 722 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() && 723 MI->getOperand(2).getImm() == 1 && 724 MI->getOperand(3).getReg() == 0 && 725 MI->getOperand(4).getImm() == 0) { 726 FrameIndex = MI->getOperand(1).getIndex(); 727 return MI->getOperand(0).getReg(); 728 } 729 break; 730 } 731 return 0; 732} 733 734unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 735 int &FrameIndex) const { 736 switch (MI->getOpcode()) { 737 default: break; 738 case X86::MOV8mr: 739 case X86::MOV16mr: 740 case X86::MOV16_mr: 741 case X86::MOV32mr: 742 case X86::MOV32_mr: 743 case X86::MOV64mr: 744 case X86::ST_FpP64m: 745 case X86::MOVSSmr: 746 case X86::MOVSDmr: 747 case X86::MOVAPSmr: 748 case X86::MOVAPDmr: 749 case X86::MOVDQAmr: 750 case X86::MMX_MOVD64mr: 751 case X86::MMX_MOVQ64mr: 752 case X86::MMX_MOVNTQmr: 753 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 754 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() && 755 MI->getOperand(1).getImm() == 1 && 756 MI->getOperand(2).getReg() == 0 && 757 MI->getOperand(3).getImm() == 0) { 758 FrameIndex = MI->getOperand(0).getIndex(); 759 return MI->getOperand(4).getReg(); 760 } 761 break; 762 } 763 return 0; 764} 765 766 767/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 768/// X86::MOVPC32r. 769static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 770 bool isPICBase = false; 771 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 772 E = MRI.def_end(); I != E; ++I) { 773 MachineInstr *DefMI = I.getOperand().getParent(); 774 if (DefMI->getOpcode() != X86::MOVPC32r) 775 return false; 776 assert(!isPICBase && "More than one PIC base?"); 777 isPICBase = true; 778 } 779 return isPICBase; 780} 781 782/// isGVStub - Return true if the GV requires an extra load to get the 783/// real address. 784static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) { 785 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false); 786} 787 788bool 789X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 790 switch (MI->getOpcode()) { 791 default: break; 792 case X86::MOV8rm: 793 case X86::MOV16rm: 794 case X86::MOV16_rm: 795 case X86::MOV32rm: 796 case X86::MOV32_rm: 797 case X86::MOV64rm: 798 case X86::LD_Fp64m: 799 case X86::MOVSSrm: 800 case X86::MOVSDrm: 801 case X86::MOVAPSrm: 802 case X86::MOVAPDrm: 803 case X86::MOVDQArm: 804 case X86::MMX_MOVD64rm: 805 case X86::MMX_MOVQ64rm: { 806 // Loads from constant pools are trivially rematerializable. 807 if (MI->getOperand(1).isReg() && 808 MI->getOperand(2).isImm() && 809 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 810 (MI->getOperand(4).isCPI() || 811 (MI->getOperand(4).isGlobal() && 812 isGVStub(MI->getOperand(4).getGlobal(), TM)))) { 813 unsigned BaseReg = MI->getOperand(1).getReg(); 814 if (BaseReg == 0) 815 return true; 816 // Allow re-materialization of PIC load. 817 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 818 return false; 819 const MachineFunction &MF = *MI->getParent()->getParent(); 820 const MachineRegisterInfo &MRI = MF.getRegInfo(); 821 bool isPICBase = false; 822 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 823 E = MRI.def_end(); I != E; ++I) { 824 MachineInstr *DefMI = I.getOperand().getParent(); 825 if (DefMI->getOpcode() != X86::MOVPC32r) 826 return false; 827 assert(!isPICBase && "More than one PIC base?"); 828 isPICBase = true; 829 } 830 return isPICBase; 831 } 832 return false; 833 } 834 835 case X86::LEA32r: 836 case X86::LEA64r: { 837 if (MI->getOperand(2).isImm() && 838 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 839 !MI->getOperand(4).isReg()) { 840 // lea fi#, lea GV, etc. are all rematerializable. 841 if (!MI->getOperand(1).isReg()) 842 return true; 843 unsigned BaseReg = MI->getOperand(1).getReg(); 844 if (BaseReg == 0) 845 return true; 846 // Allow re-materialization of lea PICBase + x. 847 const MachineFunction &MF = *MI->getParent()->getParent(); 848 const MachineRegisterInfo &MRI = MF.getRegInfo(); 849 return regIsPICBase(BaseReg, MRI); 850 } 851 return false; 852 } 853 } 854 855 // All other instructions marked M_REMATERIALIZABLE are always trivially 856 // rematerializable. 857 return true; 858} 859 860/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 861/// would clobber the EFLAGS condition register. Note the result may be 862/// conservative. If it cannot definitely determine the safety after visiting 863/// two instructions it assumes it's not safe. 864static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 865 MachineBasicBlock::iterator I) { 866 // It's always safe to clobber EFLAGS at the end of a block. 867 if (I == MBB.end()) 868 return true; 869 870 // For compile time consideration, if we are not able to determine the 871 // safety after visiting 2 instructions, we will assume it's not safe. 872 for (unsigned i = 0; i < 2; ++i) { 873 bool SeenDef = false; 874 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) { 875 MachineOperand &MO = I->getOperand(j); 876 if (!MO.isReg()) 877 continue; 878 if (MO.getReg() == X86::EFLAGS) { 879 if (MO.isUse()) 880 return false; 881 SeenDef = true; 882 } 883 } 884 885 if (SeenDef) 886 // This instruction defines EFLAGS, no need to look any further. 887 return true; 888 ++I; 889 890 // If we make it to the end of the block, it's safe to clobber EFLAGS. 891 if (I == MBB.end()) 892 return true; 893 } 894 895 // Conservative answer. 896 return false; 897} 898 899void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 900 MachineBasicBlock::iterator I, 901 unsigned DestReg, 902 const MachineInstr *Orig) const { 903 unsigned SubIdx = Orig->getOperand(0).isReg() 904 ? Orig->getOperand(0).getSubReg() : 0; 905 bool ChangeSubIdx = SubIdx != 0; 906 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) { 907 DestReg = RI.getSubReg(DestReg, SubIdx); 908 SubIdx = 0; 909 } 910 911 // MOV32r0 etc. are implemented with xor which clobbers condition code. 912 // Re-materialize them as movri instructions to avoid side effects. 913 bool Emitted = false; 914 switch (Orig->getOpcode()) { 915 default: break; 916 case X86::MOV8r0: 917 case X86::MOV16r0: 918 case X86::MOV32r0: 919 case X86::MOV64r0: { 920 if (!isSafeToClobberEFLAGS(MBB, I)) { 921 unsigned Opc = 0; 922 switch (Orig->getOpcode()) { 923 default: break; 924 case X86::MOV8r0: Opc = X86::MOV8ri; break; 925 case X86::MOV16r0: Opc = X86::MOV16ri; break; 926 case X86::MOV32r0: Opc = X86::MOV32ri; break; 927 case X86::MOV64r0: Opc = X86::MOV64ri32; break; 928 } 929 BuildMI(MBB, I, get(Opc), DestReg).addImm(0); 930 Emitted = true; 931 } 932 break; 933 } 934 } 935 936 if (!Emitted) { 937 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 938 MI->getOperand(0).setReg(DestReg); 939 MBB.insert(I, MI); 940 } 941 942 if (ChangeSubIdx) { 943 MachineInstr *NewMI = prior(I); 944 NewMI->getOperand(0).setSubReg(SubIdx); 945 } 946} 947 948/// isInvariantLoad - Return true if the specified instruction (which is marked 949/// mayLoad) is loading from a location whose value is invariant across the 950/// function. For example, loading a value from the constant pool or from 951/// from the argument area of a function if it does not change. This should 952/// only return true of *all* loads the instruction does are invariant (if it 953/// does multiple loads). 954bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const { 955 // This code cares about loads from three cases: constant pool entries, 956 // invariant argument slots, and global stubs. In order to handle these cases 957 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV 958 // operand and base our analysis on it. This is safe because the address of 959 // none of these three cases is ever used as anything other than a load base 960 // and X86 doesn't have any instructions that load from multiple places. 961 962 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 963 const MachineOperand &MO = MI->getOperand(i); 964 // Loads from constant pools are trivially invariant. 965 if (MO.isCPI()) 966 return true; 967 968 if (MO.isGlobal()) 969 return isGVStub(MO.getGlobal(), TM); 970 971 // If this is a load from an invariant stack slot, the load is a constant. 972 if (MO.isFI()) { 973 const MachineFrameInfo &MFI = 974 *MI->getParent()->getParent()->getFrameInfo(); 975 int Idx = MO.getIndex(); 976 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx); 977 } 978 } 979 980 // All other instances of these instructions are presumed to have other 981 // issues. 982 return false; 983} 984 985/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 986/// is not marked dead. 987static bool hasLiveCondCodeDef(MachineInstr *MI) { 988 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 989 MachineOperand &MO = MI->getOperand(i); 990 if (MO.isReg() && MO.isDef() && 991 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 992 return true; 993 } 994 } 995 return false; 996} 997 998/// convertToThreeAddress - This method must be implemented by targets that 999/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1000/// may be able to convert a two-address instruction into a true 1001/// three-address instruction on demand. This allows the X86 target (for 1002/// example) to convert ADD and SHL instructions into LEA instructions if they 1003/// would require register copies due to two-addressness. 1004/// 1005/// This method returns a null pointer if the transformation cannot be 1006/// performed, otherwise it returns the new instruction. 1007/// 1008MachineInstr * 1009X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1010 MachineBasicBlock::iterator &MBBI, 1011 LiveVariables *LV) const { 1012 MachineInstr *MI = MBBI; 1013 MachineFunction &MF = *MI->getParent()->getParent(); 1014 // All instructions input are two-addr instructions. Get the known operands. 1015 unsigned Dest = MI->getOperand(0).getReg(); 1016 unsigned Src = MI->getOperand(1).getReg(); 1017 bool isDead = MI->getOperand(0).isDead(); 1018 bool isKill = MI->getOperand(1).isKill(); 1019 1020 MachineInstr *NewMI = NULL; 1021 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1022 // we have better subtarget support, enable the 16-bit LEA generation here. 1023 bool DisableLEA16 = true; 1024 1025 unsigned MIOpc = MI->getOpcode(); 1026 switch (MIOpc) { 1027 case X86::SHUFPSrri: { 1028 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1029 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1030 1031 unsigned B = MI->getOperand(1).getReg(); 1032 unsigned C = MI->getOperand(2).getReg(); 1033 if (B != C) return 0; 1034 unsigned A = MI->getOperand(0).getReg(); 1035 unsigned M = MI->getOperand(3).getImm(); 1036 NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead) 1037 .addReg(B, false, false, isKill).addImm(M); 1038 break; 1039 } 1040 case X86::SHL64ri: { 1041 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1042 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1043 // the flags produced by a shift yet, so this is safe. 1044 unsigned ShAmt = MI->getOperand(2).getImm(); 1045 if (ShAmt == 0 || ShAmt >= 4) return 0; 1046 1047 NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead) 1048 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0); 1049 break; 1050 } 1051 case X86::SHL32ri: { 1052 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1053 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1054 // the flags produced by a shift yet, so this is safe. 1055 unsigned ShAmt = MI->getOperand(2).getImm(); 1056 if (ShAmt == 0 || ShAmt >= 4) return 0; 1057 1058 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? 1059 X86::LEA64_32r : X86::LEA32r; 1060 NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead) 1061 .addReg(0).addImm(1 << ShAmt) 1062 .addReg(Src, false, false, isKill).addImm(0); 1063 break; 1064 } 1065 case X86::SHL16ri: { 1066 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1067 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1068 // the flags produced by a shift yet, so this is safe. 1069 unsigned ShAmt = MI->getOperand(2).getImm(); 1070 if (ShAmt == 0 || ShAmt >= 4) return 0; 1071 1072 if (DisableLEA16) { 1073 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. 1074 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1075 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1076 ? X86::LEA64_32r : X86::LEA32r; 1077 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1078 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1079 1080 // Build and insert into an implicit UNDEF value. This is OK because 1081 // well be shifting and then extracting the lower 16-bits. 1082 BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg); 1083 MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg) 1084 .addReg(leaInReg).addReg(Src, false, false, isKill) 1085 .addImm(X86::SUBREG_16BIT); 1086 1087 NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt) 1088 .addReg(leaInReg, false, false, true).addImm(0); 1089 1090 MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG)) 1091 .addReg(Dest, true, false, false, isDead) 1092 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT); 1093 if (LV) { 1094 // Update live variables 1095 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1096 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1097 if (isKill) 1098 LV->replaceKillInstruction(Src, MI, InsMI); 1099 if (isDead) 1100 LV->replaceKillInstruction(Dest, MI, ExtMI); 1101 } 1102 return ExtMI; 1103 } else { 1104 NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead) 1105 .addReg(0).addImm(1 << ShAmt) 1106 .addReg(Src, false, false, isKill).addImm(0); 1107 } 1108 break; 1109 } 1110 default: { 1111 // The following opcodes also sets the condition code register(s). Only 1112 // convert them to equivalent lea if the condition code register def's 1113 // are dead! 1114 if (hasLiveCondCodeDef(MI)) 1115 return 0; 1116 1117 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1118 switch (MIOpc) { 1119 default: return 0; 1120 case X86::INC64r: 1121 case X86::INC32r: 1122 case X86::INC64_32r: { 1123 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1124 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1125 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1126 NewMI = addRegOffset(BuildMI(MF, get(Opc)) 1127 .addReg(Dest, true, false, false, isDead), 1128 Src, isKill, 1); 1129 break; 1130 } 1131 case X86::INC16r: 1132 case X86::INC64_16r: 1133 if (DisableLEA16) return 0; 1134 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1135 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) 1136 .addReg(Dest, true, false, false, isDead), 1137 Src, isKill, 1); 1138 break; 1139 case X86::DEC64r: 1140 case X86::DEC32r: 1141 case X86::DEC64_32r: { 1142 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1143 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1144 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1145 NewMI = addRegOffset(BuildMI(MF, get(Opc)) 1146 .addReg(Dest, true, false, false, isDead), 1147 Src, isKill, -1); 1148 break; 1149 } 1150 case X86::DEC16r: 1151 case X86::DEC64_16r: 1152 if (DisableLEA16) return 0; 1153 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1154 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) 1155 .addReg(Dest, true, false, false, isDead), 1156 Src, isKill, -1); 1157 break; 1158 case X86::ADD64rr: 1159 case X86::ADD32rr: { 1160 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1161 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1162 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1163 unsigned Src2 = MI->getOperand(2).getReg(); 1164 bool isKill2 = MI->getOperand(2).isKill(); 1165 NewMI = addRegReg(BuildMI(MF, get(Opc)) 1166 .addReg(Dest, true, false, false, isDead), 1167 Src, isKill, Src2, isKill2); 1168 if (LV && isKill2) 1169 LV->replaceKillInstruction(Src2, MI, NewMI); 1170 break; 1171 } 1172 case X86::ADD16rr: { 1173 if (DisableLEA16) return 0; 1174 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1175 unsigned Src2 = MI->getOperand(2).getReg(); 1176 bool isKill2 = MI->getOperand(2).isKill(); 1177 NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r)) 1178 .addReg(Dest, true, false, false, isDead), 1179 Src, isKill, Src2, isKill2); 1180 if (LV && isKill2) 1181 LV->replaceKillInstruction(Src2, MI, NewMI); 1182 break; 1183 } 1184 case X86::ADD64ri32: 1185 case X86::ADD64ri8: 1186 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1187 if (MI->getOperand(2).isImm()) 1188 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r)) 1189 .addReg(Dest, true, false, false, isDead), 1190 Src, isKill, MI->getOperand(2).getImm()); 1191 break; 1192 case X86::ADD32ri: 1193 case X86::ADD32ri8: 1194 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1195 if (MI->getOperand(2).isImm()) { 1196 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1197 NewMI = addRegOffset(BuildMI(MF, get(Opc)) 1198 .addReg(Dest, true, false, false, isDead), 1199 Src, isKill, MI->getOperand(2).getImm()); 1200 } 1201 break; 1202 case X86::ADD16ri: 1203 case X86::ADD16ri8: 1204 if (DisableLEA16) return 0; 1205 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1206 if (MI->getOperand(2).isImm()) 1207 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) 1208 .addReg(Dest, true, false, false, isDead), 1209 Src, isKill, MI->getOperand(2).getImm()); 1210 break; 1211 case X86::SHL16ri: 1212 if (DisableLEA16) return 0; 1213 case X86::SHL32ri: 1214 case X86::SHL64ri: { 1215 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() && 1216 "Unknown shl instruction!"); 1217 unsigned ShAmt = MI->getOperand(2).getImm(); 1218 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { 1219 X86AddressMode AM; 1220 AM.Scale = 1 << ShAmt; 1221 AM.IndexReg = Src; 1222 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r 1223 : (MIOpc == X86::SHL32ri 1224 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); 1225 NewMI = addFullAddress(BuildMI(MF, get(Opc)) 1226 .addReg(Dest, true, false, false, isDead), AM); 1227 if (isKill) 1228 NewMI->getOperand(3).setIsKill(true); 1229 } 1230 break; 1231 } 1232 } 1233 } 1234 } 1235 1236 if (!NewMI) return 0; 1237 1238 if (LV) { // Update live variables 1239 if (isKill) 1240 LV->replaceKillInstruction(Src, MI, NewMI); 1241 if (isDead) 1242 LV->replaceKillInstruction(Dest, MI, NewMI); 1243 } 1244 1245 MFI->insert(MBBI, NewMI); // Insert the new inst 1246 return NewMI; 1247} 1248 1249/// commuteInstruction - We have a few instructions that must be hacked on to 1250/// commute them. 1251/// 1252MachineInstr * 1253X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1254 switch (MI->getOpcode()) { 1255 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1256 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1257 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1258 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1259 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1260 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1261 unsigned Opc; 1262 unsigned Size; 1263 switch (MI->getOpcode()) { 1264 default: assert(0 && "Unreachable!"); 1265 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1266 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1267 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1268 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1269 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1270 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1271 } 1272 unsigned Amt = MI->getOperand(3).getImm(); 1273 if (NewMI) { 1274 MachineFunction &MF = *MI->getParent()->getParent(); 1275 MI = MF.CloneMachineInstr(MI); 1276 NewMI = false; 1277 } 1278 MI->setDesc(get(Opc)); 1279 MI->getOperand(3).setImm(Size-Amt); 1280 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1281 } 1282 case X86::CMOVB16rr: 1283 case X86::CMOVB32rr: 1284 case X86::CMOVB64rr: 1285 case X86::CMOVAE16rr: 1286 case X86::CMOVAE32rr: 1287 case X86::CMOVAE64rr: 1288 case X86::CMOVE16rr: 1289 case X86::CMOVE32rr: 1290 case X86::CMOVE64rr: 1291 case X86::CMOVNE16rr: 1292 case X86::CMOVNE32rr: 1293 case X86::CMOVNE64rr: 1294 case X86::CMOVBE16rr: 1295 case X86::CMOVBE32rr: 1296 case X86::CMOVBE64rr: 1297 case X86::CMOVA16rr: 1298 case X86::CMOVA32rr: 1299 case X86::CMOVA64rr: 1300 case X86::CMOVL16rr: 1301 case X86::CMOVL32rr: 1302 case X86::CMOVL64rr: 1303 case X86::CMOVGE16rr: 1304 case X86::CMOVGE32rr: 1305 case X86::CMOVGE64rr: 1306 case X86::CMOVLE16rr: 1307 case X86::CMOVLE32rr: 1308 case X86::CMOVLE64rr: 1309 case X86::CMOVG16rr: 1310 case X86::CMOVG32rr: 1311 case X86::CMOVG64rr: 1312 case X86::CMOVS16rr: 1313 case X86::CMOVS32rr: 1314 case X86::CMOVS64rr: 1315 case X86::CMOVNS16rr: 1316 case X86::CMOVNS32rr: 1317 case X86::CMOVNS64rr: 1318 case X86::CMOVP16rr: 1319 case X86::CMOVP32rr: 1320 case X86::CMOVP64rr: 1321 case X86::CMOVNP16rr: 1322 case X86::CMOVNP32rr: 1323 case X86::CMOVNP64rr: 1324 case X86::CMOVO16rr: 1325 case X86::CMOVO32rr: 1326 case X86::CMOVO64rr: 1327 case X86::CMOVNO16rr: 1328 case X86::CMOVNO32rr: 1329 case X86::CMOVNO64rr: { 1330 unsigned Opc = 0; 1331 switch (MI->getOpcode()) { 1332 default: break; 1333 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1334 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1335 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1336 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1337 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1338 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1339 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1340 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1341 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1342 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1343 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1344 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1345 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1346 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1347 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1348 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1349 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1350 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1351 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1352 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1353 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1354 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1355 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1356 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1357 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1358 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1359 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1360 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1361 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1362 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1363 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1364 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1365 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break; 1366 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1367 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1368 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1369 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1370 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1371 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break; 1372 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1373 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1374 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1375 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1376 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1377 case X86::CMOVO64rr: Opc = X86::CMOVNO32rr; break; 1378 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1379 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1380 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1381 } 1382 if (NewMI) { 1383 MachineFunction &MF = *MI->getParent()->getParent(); 1384 MI = MF.CloneMachineInstr(MI); 1385 NewMI = false; 1386 } 1387 MI->setDesc(get(Opc)); 1388 // Fallthrough intended. 1389 } 1390 default: 1391 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1392 } 1393} 1394 1395static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1396 switch (BrOpc) { 1397 default: return X86::COND_INVALID; 1398 case X86::JE: return X86::COND_E; 1399 case X86::JNE: return X86::COND_NE; 1400 case X86::JL: return X86::COND_L; 1401 case X86::JLE: return X86::COND_LE; 1402 case X86::JG: return X86::COND_G; 1403 case X86::JGE: return X86::COND_GE; 1404 case X86::JB: return X86::COND_B; 1405 case X86::JBE: return X86::COND_BE; 1406 case X86::JA: return X86::COND_A; 1407 case X86::JAE: return X86::COND_AE; 1408 case X86::JS: return X86::COND_S; 1409 case X86::JNS: return X86::COND_NS; 1410 case X86::JP: return X86::COND_P; 1411 case X86::JNP: return X86::COND_NP; 1412 case X86::JO: return X86::COND_O; 1413 case X86::JNO: return X86::COND_NO; 1414 } 1415} 1416 1417unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1418 switch (CC) { 1419 default: assert(0 && "Illegal condition code!"); 1420 case X86::COND_E: return X86::JE; 1421 case X86::COND_NE: return X86::JNE; 1422 case X86::COND_L: return X86::JL; 1423 case X86::COND_LE: return X86::JLE; 1424 case X86::COND_G: return X86::JG; 1425 case X86::COND_GE: return X86::JGE; 1426 case X86::COND_B: return X86::JB; 1427 case X86::COND_BE: return X86::JBE; 1428 case X86::COND_A: return X86::JA; 1429 case X86::COND_AE: return X86::JAE; 1430 case X86::COND_S: return X86::JS; 1431 case X86::COND_NS: return X86::JNS; 1432 case X86::COND_P: return X86::JP; 1433 case X86::COND_NP: return X86::JNP; 1434 case X86::COND_O: return X86::JO; 1435 case X86::COND_NO: return X86::JNO; 1436 } 1437} 1438 1439/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1440/// e.g. turning COND_E to COND_NE. 1441X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1442 switch (CC) { 1443 default: assert(0 && "Illegal condition code!"); 1444 case X86::COND_E: return X86::COND_NE; 1445 case X86::COND_NE: return X86::COND_E; 1446 case X86::COND_L: return X86::COND_GE; 1447 case X86::COND_LE: return X86::COND_G; 1448 case X86::COND_G: return X86::COND_LE; 1449 case X86::COND_GE: return X86::COND_L; 1450 case X86::COND_B: return X86::COND_AE; 1451 case X86::COND_BE: return X86::COND_A; 1452 case X86::COND_A: return X86::COND_BE; 1453 case X86::COND_AE: return X86::COND_B; 1454 case X86::COND_S: return X86::COND_NS; 1455 case X86::COND_NS: return X86::COND_S; 1456 case X86::COND_P: return X86::COND_NP; 1457 case X86::COND_NP: return X86::COND_P; 1458 case X86::COND_O: return X86::COND_NO; 1459 case X86::COND_NO: return X86::COND_O; 1460 } 1461} 1462 1463bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1464 const TargetInstrDesc &TID = MI->getDesc(); 1465 if (!TID.isTerminator()) return false; 1466 1467 // Conditional branch is a special case. 1468 if (TID.isBranch() && !TID.isBarrier()) 1469 return true; 1470 if (!TID.isPredicable()) 1471 return true; 1472 return !isPredicated(MI); 1473} 1474 1475// For purposes of branch analysis do not count FP_REG_KILL as a terminator. 1476static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, 1477 const X86InstrInfo &TII) { 1478 if (MI->getOpcode() == X86::FP_REG_KILL) 1479 return false; 1480 return TII.isUnpredicatedTerminator(MI); 1481} 1482 1483bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1484 MachineBasicBlock *&TBB, 1485 MachineBasicBlock *&FBB, 1486 SmallVectorImpl<MachineOperand> &Cond) const { 1487 // Start from the bottom of the block and work up, examining the 1488 // terminator instructions. 1489 MachineBasicBlock::iterator I = MBB.end(); 1490 while (I != MBB.begin()) { 1491 --I; 1492 // Working from the bottom, when we see a non-terminator 1493 // instruction, we're done. 1494 if (!isBrAnalysisUnpredicatedTerminator(I, *this)) 1495 break; 1496 // A terminator that isn't a branch can't easily be handled 1497 // by this analysis. 1498 if (!I->getDesc().isBranch()) 1499 return true; 1500 // Handle unconditional branches. 1501 if (I->getOpcode() == X86::JMP) { 1502 // If the block has any instructions after a JMP, delete them. 1503 while (next(I) != MBB.end()) 1504 next(I)->eraseFromParent(); 1505 Cond.clear(); 1506 FBB = 0; 1507 // Delete the JMP if it's equivalent to a fall-through. 1508 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1509 TBB = 0; 1510 I->eraseFromParent(); 1511 I = MBB.end(); 1512 continue; 1513 } 1514 // TBB is used to indicate the unconditinal destination. 1515 TBB = I->getOperand(0).getMBB(); 1516 continue; 1517 } 1518 // Handle conditional branches. 1519 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1520 if (BranchCode == X86::COND_INVALID) 1521 return true; // Can't handle indirect branch. 1522 // Working from the bottom, handle the first conditional branch. 1523 if (Cond.empty()) { 1524 FBB = TBB; 1525 TBB = I->getOperand(0).getMBB(); 1526 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1527 continue; 1528 } 1529 // Handle subsequent conditional branches. Only handle the case 1530 // where all conditional branches branch to the same destination 1531 // and their condition opcodes fit one of the special 1532 // multi-branch idioms. 1533 assert(Cond.size() == 1); 1534 assert(TBB); 1535 // Only handle the case where all conditional branches branch to 1536 // the same destination. 1537 if (TBB != I->getOperand(0).getMBB()) 1538 return true; 1539 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1540 // If the conditions are the same, we can leave them alone. 1541 if (OldBranchCode == BranchCode) 1542 continue; 1543 // If they differ, see if they fit one of the known patterns. 1544 // Theoretically we could handle more patterns here, but 1545 // we shouldn't expect to see them if instruction selection 1546 // has done a reasonable job. 1547 if ((OldBranchCode == X86::COND_NP && 1548 BranchCode == X86::COND_E) || 1549 (OldBranchCode == X86::COND_E && 1550 BranchCode == X86::COND_NP)) 1551 BranchCode = X86::COND_NP_OR_E; 1552 else if ((OldBranchCode == X86::COND_P && 1553 BranchCode == X86::COND_NE) || 1554 (OldBranchCode == X86::COND_NE && 1555 BranchCode == X86::COND_P)) 1556 BranchCode = X86::COND_NE_OR_P; 1557 else 1558 return true; 1559 // Update the MachineOperand. 1560 Cond[0].setImm(BranchCode); 1561 } 1562 1563 return false; 1564} 1565 1566unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1567 MachineBasicBlock::iterator I = MBB.end(); 1568 unsigned Count = 0; 1569 1570 while (I != MBB.begin()) { 1571 --I; 1572 if (I->getOpcode() != X86::JMP && 1573 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1574 break; 1575 // Remove the branch. 1576 I->eraseFromParent(); 1577 I = MBB.end(); 1578 ++Count; 1579 } 1580 1581 return Count; 1582} 1583 1584static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB, 1585 const MachineOperand &MO) { 1586 if (MO.isReg()) 1587 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(), 1588 MO.isKill(), MO.isDead(), MO.getSubReg()); 1589 else if (MO.isImm()) 1590 MIB = MIB.addImm(MO.getImm()); 1591 else if (MO.isFI()) 1592 MIB = MIB.addFrameIndex(MO.getIndex()); 1593 else if (MO.isGlobal()) 1594 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset()); 1595 else if (MO.isCPI()) 1596 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset()); 1597 else if (MO.isJTI()) 1598 MIB = MIB.addJumpTableIndex(MO.getIndex()); 1599 else if (MO.isSymbol()) 1600 MIB = MIB.addExternalSymbol(MO.getSymbolName()); 1601 else 1602 assert(0 && "Unknown operand for X86InstrAddOperand!"); 1603 1604 return MIB; 1605} 1606 1607unsigned 1608X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1609 MachineBasicBlock *FBB, 1610 const SmallVectorImpl<MachineOperand> &Cond) const { 1611 // Shouldn't be a fall through. 1612 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1613 assert((Cond.size() == 1 || Cond.size() == 0) && 1614 "X86 branch conditions have one component!"); 1615 1616 if (Cond.empty()) { 1617 // Unconditional branch? 1618 assert(!FBB && "Unconditional branch with multiple successors!"); 1619 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); 1620 return 1; 1621 } 1622 1623 // Conditional branch. 1624 unsigned Count = 0; 1625 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1626 switch (CC) { 1627 case X86::COND_NP_OR_E: 1628 // Synthesize NP_OR_E with two branches. 1629 BuildMI(&MBB, get(X86::JNP)).addMBB(TBB); 1630 ++Count; 1631 BuildMI(&MBB, get(X86::JE)).addMBB(TBB); 1632 ++Count; 1633 break; 1634 case X86::COND_NE_OR_P: 1635 // Synthesize NE_OR_P with two branches. 1636 BuildMI(&MBB, get(X86::JNE)).addMBB(TBB); 1637 ++Count; 1638 BuildMI(&MBB, get(X86::JP)).addMBB(TBB); 1639 ++Count; 1640 break; 1641 default: { 1642 unsigned Opc = GetCondBranchFromCond(CC); 1643 BuildMI(&MBB, get(Opc)).addMBB(TBB); 1644 ++Count; 1645 } 1646 } 1647 if (FBB) { 1648 // Two-way Conditional branch. Insert the second branch. 1649 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); 1650 ++Count; 1651 } 1652 return Count; 1653} 1654 1655bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, 1656 MachineBasicBlock::iterator MI, 1657 unsigned DestReg, unsigned SrcReg, 1658 const TargetRegisterClass *DestRC, 1659 const TargetRegisterClass *SrcRC) const { 1660 if (DestRC == SrcRC) { 1661 unsigned Opc; 1662 if (DestRC == &X86::GR64RegClass) { 1663 Opc = X86::MOV64rr; 1664 } else if (DestRC == &X86::GR32RegClass) { 1665 Opc = X86::MOV32rr; 1666 } else if (DestRC == &X86::GR16RegClass) { 1667 Opc = X86::MOV16rr; 1668 } else if (DestRC == &X86::GR8RegClass) { 1669 Opc = X86::MOV8rr; 1670 } else if (DestRC == &X86::GR32_RegClass) { 1671 Opc = X86::MOV32_rr; 1672 } else if (DestRC == &X86::GR16_RegClass) { 1673 Opc = X86::MOV16_rr; 1674 } else if (DestRC == &X86::RFP32RegClass) { 1675 Opc = X86::MOV_Fp3232; 1676 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { 1677 Opc = X86::MOV_Fp6464; 1678 } else if (DestRC == &X86::RFP80RegClass) { 1679 Opc = X86::MOV_Fp8080; 1680 } else if (DestRC == &X86::FR32RegClass) { 1681 Opc = X86::FsMOVAPSrr; 1682 } else if (DestRC == &X86::FR64RegClass) { 1683 Opc = X86::FsMOVAPDrr; 1684 } else if (DestRC == &X86::VR128RegClass) { 1685 Opc = X86::MOVAPSrr; 1686 } else if (DestRC == &X86::VR64RegClass) { 1687 Opc = X86::MMX_MOVQ64rr; 1688 } else { 1689 return false; 1690 } 1691 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); 1692 return true; 1693 } 1694 1695 // Moving EFLAGS to / from another register requires a push and a pop. 1696 if (SrcRC == &X86::CCRRegClass) { 1697 if (SrcReg != X86::EFLAGS) 1698 return false; 1699 if (DestRC == &X86::GR64RegClass) { 1700 BuildMI(MBB, MI, get(X86::PUSHFQ)); 1701 BuildMI(MBB, MI, get(X86::POP64r), DestReg); 1702 return true; 1703 } else if (DestRC == &X86::GR32RegClass) { 1704 BuildMI(MBB, MI, get(X86::PUSHFD)); 1705 BuildMI(MBB, MI, get(X86::POP32r), DestReg); 1706 return true; 1707 } 1708 } else if (DestRC == &X86::CCRRegClass) { 1709 if (DestReg != X86::EFLAGS) 1710 return false; 1711 if (SrcRC == &X86::GR64RegClass) { 1712 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); 1713 BuildMI(MBB, MI, get(X86::POPFQ)); 1714 return true; 1715 } else if (SrcRC == &X86::GR32RegClass) { 1716 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); 1717 BuildMI(MBB, MI, get(X86::POPFD)); 1718 return true; 1719 } 1720 } 1721 1722 // Moving from ST(0) turns into FpGET_ST0_32 etc. 1723 if (SrcRC == &X86::RSTRegClass) { 1724 // Copying from ST(0)/ST(1). 1725 if (SrcReg != X86::ST0 && SrcReg != X86::ST1) 1726 // Can only copy from ST(0)/ST(1) right now 1727 return false; 1728 bool isST0 = SrcReg == X86::ST0; 1729 unsigned Opc; 1730 if (DestRC == &X86::RFP32RegClass) 1731 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32; 1732 else if (DestRC == &X86::RFP64RegClass) 1733 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64; 1734 else { 1735 if (DestRC != &X86::RFP80RegClass) 1736 return false; 1737 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; 1738 } 1739 BuildMI(MBB, MI, get(Opc), DestReg); 1740 return true; 1741 } 1742 1743 // Moving to ST(0) turns into FpSET_ST0_32 etc. 1744 if (DestRC == &X86::RSTRegClass) { 1745 // Copying to ST(0). FIXME: handle ST(1) also 1746 if (DestReg != X86::ST0) 1747 // Can only copy to TOS right now 1748 return false; 1749 unsigned Opc; 1750 if (SrcRC == &X86::RFP32RegClass) 1751 Opc = X86::FpSET_ST0_32; 1752 else if (SrcRC == &X86::RFP64RegClass) 1753 Opc = X86::FpSET_ST0_64; 1754 else { 1755 if (SrcRC != &X86::RFP80RegClass) 1756 return false; 1757 Opc = X86::FpSET_ST0_80; 1758 } 1759 BuildMI(MBB, MI, get(Opc)).addReg(SrcReg); 1760 return true; 1761 } 1762 1763 // Not yet supported! 1764 return false; 1765} 1766 1767static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, 1768 bool isStackAligned) { 1769 unsigned Opc = 0; 1770 if (RC == &X86::GR64RegClass) { 1771 Opc = X86::MOV64mr; 1772 } else if (RC == &X86::GR32RegClass) { 1773 Opc = X86::MOV32mr; 1774 } else if (RC == &X86::GR16RegClass) { 1775 Opc = X86::MOV16mr; 1776 } else if (RC == &X86::GR8RegClass) { 1777 Opc = X86::MOV8mr; 1778 } else if (RC == &X86::GR32_RegClass) { 1779 Opc = X86::MOV32_mr; 1780 } else if (RC == &X86::GR16_RegClass) { 1781 Opc = X86::MOV16_mr; 1782 } else if (RC == &X86::RFP80RegClass) { 1783 Opc = X86::ST_FpP80m; // pops 1784 } else if (RC == &X86::RFP64RegClass) { 1785 Opc = X86::ST_Fp64m; 1786 } else if (RC == &X86::RFP32RegClass) { 1787 Opc = X86::ST_Fp32m; 1788 } else if (RC == &X86::FR32RegClass) { 1789 Opc = X86::MOVSSmr; 1790 } else if (RC == &X86::FR64RegClass) { 1791 Opc = X86::MOVSDmr; 1792 } else if (RC == &X86::VR128RegClass) { 1793 // If stack is realigned we can use aligned stores. 1794 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr; 1795 } else if (RC == &X86::VR64RegClass) { 1796 Opc = X86::MMX_MOVQ64mr; 1797 } else { 1798 assert(0 && "Unknown regclass"); 1799 abort(); 1800 } 1801 1802 return Opc; 1803} 1804 1805void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 1806 MachineBasicBlock::iterator MI, 1807 unsigned SrcReg, bool isKill, int FrameIdx, 1808 const TargetRegisterClass *RC) const { 1809 const MachineFunction &MF = *MBB.getParent(); 1810 bool isAligned = (RI.getStackAlignment() >= 16) || 1811 RI.needsStackRealignment(MF); 1812 unsigned Opc = getStoreRegOpcode(RC, isAligned); 1813 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx) 1814 .addReg(SrcReg, false, false, isKill); 1815} 1816 1817void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 1818 bool isKill, 1819 SmallVectorImpl<MachineOperand> &Addr, 1820 const TargetRegisterClass *RC, 1821 SmallVectorImpl<MachineInstr*> &NewMIs) const { 1822 bool isAligned = (RI.getStackAlignment() >= 16) || 1823 RI.needsStackRealignment(MF); 1824 unsigned Opc = getStoreRegOpcode(RC, isAligned); 1825 MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); 1826 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 1827 MIB = X86InstrAddOperand(MIB, Addr[i]); 1828 MIB.addReg(SrcReg, false, false, isKill); 1829 NewMIs.push_back(MIB); 1830} 1831 1832static unsigned getLoadRegOpcode(const TargetRegisterClass *RC, 1833 bool isStackAligned) { 1834 unsigned Opc = 0; 1835 if (RC == &X86::GR64RegClass) { 1836 Opc = X86::MOV64rm; 1837 } else if (RC == &X86::GR32RegClass) { 1838 Opc = X86::MOV32rm; 1839 } else if (RC == &X86::GR16RegClass) { 1840 Opc = X86::MOV16rm; 1841 } else if (RC == &X86::GR8RegClass) { 1842 Opc = X86::MOV8rm; 1843 } else if (RC == &X86::GR32_RegClass) { 1844 Opc = X86::MOV32_rm; 1845 } else if (RC == &X86::GR16_RegClass) { 1846 Opc = X86::MOV16_rm; 1847 } else if (RC == &X86::RFP80RegClass) { 1848 Opc = X86::LD_Fp80m; 1849 } else if (RC == &X86::RFP64RegClass) { 1850 Opc = X86::LD_Fp64m; 1851 } else if (RC == &X86::RFP32RegClass) { 1852 Opc = X86::LD_Fp32m; 1853 } else if (RC == &X86::FR32RegClass) { 1854 Opc = X86::MOVSSrm; 1855 } else if (RC == &X86::FR64RegClass) { 1856 Opc = X86::MOVSDrm; 1857 } else if (RC == &X86::VR128RegClass) { 1858 // If stack is realigned we can use aligned loads. 1859 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm; 1860 } else if (RC == &X86::VR64RegClass) { 1861 Opc = X86::MMX_MOVQ64rm; 1862 } else { 1863 assert(0 && "Unknown regclass"); 1864 abort(); 1865 } 1866 1867 return Opc; 1868} 1869 1870void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 1871 MachineBasicBlock::iterator MI, 1872 unsigned DestReg, int FrameIdx, 1873 const TargetRegisterClass *RC) const{ 1874 const MachineFunction &MF = *MBB.getParent(); 1875 bool isAligned = (RI.getStackAlignment() >= 16) || 1876 RI.needsStackRealignment(MF); 1877 unsigned Opc = getLoadRegOpcode(RC, isAligned); 1878 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx); 1879} 1880 1881void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 1882 SmallVectorImpl<MachineOperand> &Addr, 1883 const TargetRegisterClass *RC, 1884 SmallVectorImpl<MachineInstr*> &NewMIs) const { 1885 bool isAligned = (RI.getStackAlignment() >= 16) || 1886 RI.needsStackRealignment(MF); 1887 unsigned Opc = getLoadRegOpcode(RC, isAligned); 1888 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); 1889 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 1890 MIB = X86InstrAddOperand(MIB, Addr[i]); 1891 NewMIs.push_back(MIB); 1892} 1893 1894bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1895 MachineBasicBlock::iterator MI, 1896 const std::vector<CalleeSavedInfo> &CSI) const { 1897 if (CSI.empty()) 1898 return false; 1899 1900 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1901 unsigned SlotSize = is64Bit ? 8 : 4; 1902 1903 MachineFunction &MF = *MBB.getParent(); 1904 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1905 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); 1906 1907 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 1908 for (unsigned i = CSI.size(); i != 0; --i) { 1909 unsigned Reg = CSI[i-1].getReg(); 1910 // Add the callee-saved register as live-in. It's killed at the spill. 1911 MBB.addLiveIn(Reg); 1912 BuildMI(MBB, MI, get(Opc)) 1913 .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); 1914 } 1915 return true; 1916} 1917 1918bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1919 MachineBasicBlock::iterator MI, 1920 const std::vector<CalleeSavedInfo> &CSI) const { 1921 if (CSI.empty()) 1922 return false; 1923 1924 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1925 1926 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 1927 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1928 unsigned Reg = CSI[i].getReg(); 1929 BuildMI(MBB, MI, get(Opc), Reg); 1930 } 1931 return true; 1932} 1933 1934static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 1935 const SmallVectorImpl<MachineOperand> &MOs, 1936 MachineInstr *MI, const TargetInstrInfo &TII) { 1937 // Create the base instruction with the memory operand as the first part. 1938 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); 1939 MachineInstrBuilder MIB(NewMI); 1940 unsigned NumAddrOps = MOs.size(); 1941 for (unsigned i = 0; i != NumAddrOps; ++i) 1942 MIB = X86InstrAddOperand(MIB, MOs[i]); 1943 if (NumAddrOps < 4) // FrameIndex only 1944 MIB.addImm(1).addReg(0).addImm(0); 1945 1946 // Loop over the rest of the ri operands, converting them over. 1947 unsigned NumOps = MI->getDesc().getNumOperands()-2; 1948 for (unsigned i = 0; i != NumOps; ++i) { 1949 MachineOperand &MO = MI->getOperand(i+2); 1950 MIB = X86InstrAddOperand(MIB, MO); 1951 } 1952 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 1953 MachineOperand &MO = MI->getOperand(i); 1954 MIB = X86InstrAddOperand(MIB, MO); 1955 } 1956 return MIB; 1957} 1958 1959static MachineInstr *FuseInst(MachineFunction &MF, 1960 unsigned Opcode, unsigned OpNo, 1961 const SmallVectorImpl<MachineOperand> &MOs, 1962 MachineInstr *MI, const TargetInstrInfo &TII) { 1963 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); 1964 MachineInstrBuilder MIB(NewMI); 1965 1966 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1967 MachineOperand &MO = MI->getOperand(i); 1968 if (i == OpNo) { 1969 assert(MO.isReg() && "Expected to fold into reg operand!"); 1970 unsigned NumAddrOps = MOs.size(); 1971 for (unsigned i = 0; i != NumAddrOps; ++i) 1972 MIB = X86InstrAddOperand(MIB, MOs[i]); 1973 if (NumAddrOps < 4) // FrameIndex only 1974 MIB.addImm(1).addReg(0).addImm(0); 1975 } else { 1976 MIB = X86InstrAddOperand(MIB, MO); 1977 } 1978 } 1979 return MIB; 1980} 1981 1982static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 1983 const SmallVectorImpl<MachineOperand> &MOs, 1984 MachineInstr *MI) { 1985 MachineFunction &MF = *MI->getParent()->getParent(); 1986 MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode)); 1987 1988 unsigned NumAddrOps = MOs.size(); 1989 for (unsigned i = 0; i != NumAddrOps; ++i) 1990 MIB = X86InstrAddOperand(MIB, MOs[i]); 1991 if (NumAddrOps < 4) // FrameIndex only 1992 MIB.addImm(1).addReg(0).addImm(0); 1993 return MIB.addImm(0); 1994} 1995 1996MachineInstr* 1997X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 1998 MachineInstr *MI, unsigned i, 1999 const SmallVectorImpl<MachineOperand> &MOs) const{ 2000 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; 2001 bool isTwoAddrFold = false; 2002 unsigned NumOps = MI->getDesc().getNumOperands(); 2003 bool isTwoAddr = NumOps > 1 && 2004 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2005 2006 MachineInstr *NewMI = NULL; 2007 // Folding a memory location into the two-address part of a two-address 2008 // instruction is different than folding it other places. It requires 2009 // replacing the *two* registers with the memory location. 2010 if (isTwoAddr && NumOps >= 2 && i < 2 && 2011 MI->getOperand(0).isReg() && 2012 MI->getOperand(1).isReg() && 2013 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2014 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2015 isTwoAddrFold = true; 2016 } else if (i == 0) { // If operand 0 2017 if (MI->getOpcode() == X86::MOV16r0) 2018 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2019 else if (MI->getOpcode() == X86::MOV32r0) 2020 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2021 else if (MI->getOpcode() == X86::MOV64r0) 2022 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2023 else if (MI->getOpcode() == X86::MOV8r0) 2024 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2025 if (NewMI) 2026 return NewMI; 2027 2028 OpcodeTablePtr = &RegOp2MemOpTable0; 2029 } else if (i == 1) { 2030 OpcodeTablePtr = &RegOp2MemOpTable1; 2031 } else if (i == 2) { 2032 OpcodeTablePtr = &RegOp2MemOpTable2; 2033 } 2034 2035 // If table selected... 2036 if (OpcodeTablePtr) { 2037 // Find the Opcode to fuse 2038 DenseMap<unsigned*, unsigned>::iterator I = 2039 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2040 if (I != OpcodeTablePtr->end()) { 2041 if (isTwoAddrFold) 2042 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this); 2043 else 2044 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this); 2045 return NewMI; 2046 } 2047 } 2048 2049 // No fusion 2050 if (PrintFailedFusing) 2051 cerr << "We failed to fuse operand " << i << " in " << *MI; 2052 return NULL; 2053} 2054 2055 2056MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2057 MachineInstr *MI, 2058 const SmallVectorImpl<unsigned> &Ops, 2059 int FrameIndex) const { 2060 // Check switch flag 2061 if (NoFusing) return NULL; 2062 2063 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2064 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2065 // FIXME: Move alignment requirement into tables? 2066 if (Alignment < 16) { 2067 switch (MI->getOpcode()) { 2068 default: break; 2069 // Not always safe to fold movsd into these instructions since their load 2070 // folding variants expects the address to be 16 byte aligned. 2071 case X86::FsANDNPDrr: 2072 case X86::FsANDNPSrr: 2073 case X86::FsANDPDrr: 2074 case X86::FsANDPSrr: 2075 case X86::FsORPDrr: 2076 case X86::FsORPSrr: 2077 case X86::FsXORPDrr: 2078 case X86::FsXORPSrr: 2079 return NULL; 2080 } 2081 } 2082 2083 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2084 unsigned NewOpc = 0; 2085 switch (MI->getOpcode()) { 2086 default: return NULL; 2087 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2088 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2089 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2090 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2091 } 2092 // Change to CMPXXri r, 0 first. 2093 MI->setDesc(get(NewOpc)); 2094 MI->getOperand(1).ChangeToImmediate(0); 2095 } else if (Ops.size() != 1) 2096 return NULL; 2097 2098 SmallVector<MachineOperand,4> MOs; 2099 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2100 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs); 2101} 2102 2103MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2104 MachineInstr *MI, 2105 const SmallVectorImpl<unsigned> &Ops, 2106 MachineInstr *LoadMI) const { 2107 // Check switch flag 2108 if (NoFusing) return NULL; 2109 2110 // Determine the alignment of the load. 2111 unsigned Alignment = 0; 2112 if (LoadMI->hasOneMemOperand()) 2113 Alignment = LoadMI->memoperands_begin()->getAlignment(); 2114 2115 // FIXME: Move alignment requirement into tables? 2116 if (Alignment < 16) { 2117 switch (MI->getOpcode()) { 2118 default: break; 2119 // Not always safe to fold movsd into these instructions since their load 2120 // folding variants expects the address to be 16 byte aligned. 2121 case X86::FsANDNPDrr: 2122 case X86::FsANDNPSrr: 2123 case X86::FsANDPDrr: 2124 case X86::FsANDPSrr: 2125 case X86::FsORPDrr: 2126 case X86::FsORPSrr: 2127 case X86::FsXORPDrr: 2128 case X86::FsXORPSrr: 2129 return NULL; 2130 } 2131 } 2132 2133 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2134 unsigned NewOpc = 0; 2135 switch (MI->getOpcode()) { 2136 default: return NULL; 2137 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2138 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2139 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2140 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2141 } 2142 // Change to CMPXXri r, 0 first. 2143 MI->setDesc(get(NewOpc)); 2144 MI->getOperand(1).ChangeToImmediate(0); 2145 } else if (Ops.size() != 1) 2146 return NULL; 2147 2148 SmallVector<MachineOperand,4> MOs; 2149 if (LoadMI->getOpcode() == X86::V_SET0 || 2150 LoadMI->getOpcode() == X86::V_SETALLONES) { 2151 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 2152 // Create a constant-pool entry and operands to load from it. 2153 2154 // x86-32 PIC requires a PIC base register for constant pools. 2155 unsigned PICBase = 0; 2156 if (TM.getRelocationModel() == Reloc::PIC_ && 2157 !TM.getSubtarget<X86Subtarget>().is64Bit()) 2158 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF); 2159 // This doesn't work for several reasons. 2160 // 1. GlobalBaseReg may have been spilled. 2161 // 2. It may not be live at MI. 2162 return false; 2163 2164 // Create a v4i32 constant-pool entry. 2165 MachineConstantPool &MCP = *MF.getConstantPool(); 2166 const VectorType *Ty = VectorType::get(Type::Int32Ty, 4); 2167 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ? 2168 ConstantVector::getNullValue(Ty) : 2169 ConstantVector::getAllOnesValue(Ty); 2170 unsigned CPI = MCP.getConstantPoolIndex(C, /*AlignmentLog2=*/4); 2171 2172 // Create operands to load from the constant pool entry. 2173 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2174 MOs.push_back(MachineOperand::CreateImm(1)); 2175 MOs.push_back(MachineOperand::CreateReg(0, false)); 2176 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2177 } else { 2178 // Folding a normal load. Just copy the load's address operands. 2179 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2180 for (unsigned i = NumOps - 4; i != NumOps; ++i) 2181 MOs.push_back(LoadMI->getOperand(i)); 2182 } 2183 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs); 2184} 2185 2186 2187bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2188 const SmallVectorImpl<unsigned> &Ops) const { 2189 // Check switch flag 2190 if (NoFusing) return 0; 2191 2192 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2193 switch (MI->getOpcode()) { 2194 default: return false; 2195 case X86::TEST8rr: 2196 case X86::TEST16rr: 2197 case X86::TEST32rr: 2198 case X86::TEST64rr: 2199 return true; 2200 } 2201 } 2202 2203 if (Ops.size() != 1) 2204 return false; 2205 2206 unsigned OpNum = Ops[0]; 2207 unsigned Opc = MI->getOpcode(); 2208 unsigned NumOps = MI->getDesc().getNumOperands(); 2209 bool isTwoAddr = NumOps > 1 && 2210 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2211 2212 // Folding a memory location into the two-address part of a two-address 2213 // instruction is different than folding it other places. It requires 2214 // replacing the *two* registers with the memory location. 2215 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; 2216 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2217 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2218 } else if (OpNum == 0) { // If operand 0 2219 switch (Opc) { 2220 case X86::MOV16r0: 2221 case X86::MOV32r0: 2222 case X86::MOV64r0: 2223 case X86::MOV8r0: 2224 return true; 2225 default: break; 2226 } 2227 OpcodeTablePtr = &RegOp2MemOpTable0; 2228 } else if (OpNum == 1) { 2229 OpcodeTablePtr = &RegOp2MemOpTable1; 2230 } else if (OpNum == 2) { 2231 OpcodeTablePtr = &RegOp2MemOpTable2; 2232 } 2233 2234 if (OpcodeTablePtr) { 2235 // Find the Opcode to fuse 2236 DenseMap<unsigned*, unsigned>::iterator I = 2237 OpcodeTablePtr->find((unsigned*)Opc); 2238 if (I != OpcodeTablePtr->end()) 2239 return true; 2240 } 2241 return false; 2242} 2243 2244bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2245 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2246 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2247 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2248 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2249 if (I == MemOp2RegOpTable.end()) 2250 return false; 2251 unsigned Opc = I->second.first; 2252 unsigned Index = I->second.second & 0xf; 2253 bool FoldedLoad = I->second.second & (1 << 4); 2254 bool FoldedStore = I->second.second & (1 << 5); 2255 if (UnfoldLoad && !FoldedLoad) 2256 return false; 2257 UnfoldLoad &= FoldedLoad; 2258 if (UnfoldStore && !FoldedStore) 2259 return false; 2260 UnfoldStore &= FoldedStore; 2261 2262 const TargetInstrDesc &TID = get(Opc); 2263 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2264 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() 2265 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass); 2266 SmallVector<MachineOperand,4> AddrOps; 2267 SmallVector<MachineOperand,2> BeforeOps; 2268 SmallVector<MachineOperand,2> AfterOps; 2269 SmallVector<MachineOperand,4> ImpOps; 2270 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2271 MachineOperand &Op = MI->getOperand(i); 2272 if (i >= Index && i < Index+4) 2273 AddrOps.push_back(Op); 2274 else if (Op.isReg() && Op.isImplicit()) 2275 ImpOps.push_back(Op); 2276 else if (i < Index) 2277 BeforeOps.push_back(Op); 2278 else if (i > Index) 2279 AfterOps.push_back(Op); 2280 } 2281 2282 // Emit the load instruction. 2283 if (UnfoldLoad) { 2284 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs); 2285 if (UnfoldStore) { 2286 // Address operands cannot be marked isKill. 2287 for (unsigned i = 1; i != 5; ++i) { 2288 MachineOperand &MO = NewMIs[0]->getOperand(i); 2289 if (MO.isReg()) 2290 MO.setIsKill(false); 2291 } 2292 } 2293 } 2294 2295 // Emit the data processing instruction. 2296 MachineInstr *DataMI = MF.CreateMachineInstr(TID, true); 2297 MachineInstrBuilder MIB(DataMI); 2298 2299 if (FoldedStore) 2300 MIB.addReg(Reg, true); 2301 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2302 MIB = X86InstrAddOperand(MIB, BeforeOps[i]); 2303 if (FoldedLoad) 2304 MIB.addReg(Reg); 2305 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2306 MIB = X86InstrAddOperand(MIB, AfterOps[i]); 2307 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2308 MachineOperand &MO = ImpOps[i]; 2309 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead()); 2310 } 2311 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2312 unsigned NewOpc = 0; 2313 switch (DataMI->getOpcode()) { 2314 default: break; 2315 case X86::CMP64ri32: 2316 case X86::CMP32ri: 2317 case X86::CMP16ri: 2318 case X86::CMP8ri: { 2319 MachineOperand &MO0 = DataMI->getOperand(0); 2320 MachineOperand &MO1 = DataMI->getOperand(1); 2321 if (MO1.getImm() == 0) { 2322 switch (DataMI->getOpcode()) { 2323 default: break; 2324 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2325 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2326 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2327 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2328 } 2329 DataMI->setDesc(get(NewOpc)); 2330 MO1.ChangeToRegister(MO0.getReg(), false); 2331 } 2332 } 2333 } 2334 NewMIs.push_back(DataMI); 2335 2336 // Emit the store instruction. 2337 if (UnfoldStore) { 2338 const TargetOperandInfo &DstTOI = TID.OpInfo[0]; 2339 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass() 2340 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); 2341 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs); 2342 } 2343 2344 return true; 2345} 2346 2347bool 2348X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2349 SmallVectorImpl<SDNode*> &NewNodes) const { 2350 if (!N->isMachineOpcode()) 2351 return false; 2352 2353 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2354 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2355 if (I == MemOp2RegOpTable.end()) 2356 return false; 2357 unsigned Opc = I->second.first; 2358 unsigned Index = I->second.second & 0xf; 2359 bool FoldedLoad = I->second.second & (1 << 4); 2360 bool FoldedStore = I->second.second & (1 << 5); 2361 const TargetInstrDesc &TID = get(Opc); 2362 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2363 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() 2364 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass); 2365 std::vector<SDValue> AddrOps; 2366 std::vector<SDValue> BeforeOps; 2367 std::vector<SDValue> AfterOps; 2368 unsigned NumOps = N->getNumOperands(); 2369 for (unsigned i = 0; i != NumOps-1; ++i) { 2370 SDValue Op = N->getOperand(i); 2371 if (i >= Index && i < Index+4) 2372 AddrOps.push_back(Op); 2373 else if (i < Index) 2374 BeforeOps.push_back(Op); 2375 else if (i > Index) 2376 AfterOps.push_back(Op); 2377 } 2378 SDValue Chain = N->getOperand(NumOps-1); 2379 AddrOps.push_back(Chain); 2380 2381 // Emit the load instruction. 2382 SDNode *Load = 0; 2383 const MachineFunction &MF = DAG.getMachineFunction(); 2384 if (FoldedLoad) { 2385 MVT VT = *RC->vt_begin(); 2386 bool isAligned = (RI.getStackAlignment() >= 16) || 2387 RI.needsStackRealignment(MF); 2388 Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), 2389 VT, MVT::Other, 2390 &AddrOps[0], AddrOps.size()); 2391 NewNodes.push_back(Load); 2392 } 2393 2394 // Emit the data processing instruction. 2395 std::vector<MVT> VTs; 2396 const TargetRegisterClass *DstRC = 0; 2397 if (TID.getNumDefs() > 0) { 2398 const TargetOperandInfo &DstTOI = TID.OpInfo[0]; 2399 DstRC = DstTOI.isLookupPtrRegClass() 2400 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); 2401 VTs.push_back(*DstRC->vt_begin()); 2402 } 2403 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2404 MVT VT = N->getValueType(i); 2405 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2406 VTs.push_back(VT); 2407 } 2408 if (Load) 2409 BeforeOps.push_back(SDValue(Load, 0)); 2410 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2411 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size()); 2412 NewNodes.push_back(NewNode); 2413 2414 // Emit the store instruction. 2415 if (FoldedStore) { 2416 AddrOps.pop_back(); 2417 AddrOps.push_back(SDValue(NewNode, 0)); 2418 AddrOps.push_back(Chain); 2419 bool isAligned = (RI.getStackAlignment() >= 16) || 2420 RI.needsStackRealignment(MF); 2421 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), 2422 MVT::Other, &AddrOps[0], AddrOps.size()); 2423 NewNodes.push_back(Store); 2424 } 2425 2426 return true; 2427} 2428 2429unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2430 bool UnfoldLoad, bool UnfoldStore) const { 2431 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2432 MemOp2RegOpTable.find((unsigned*)Opc); 2433 if (I == MemOp2RegOpTable.end()) 2434 return 0; 2435 bool FoldedLoad = I->second.second & (1 << 4); 2436 bool FoldedStore = I->second.second & (1 << 5); 2437 if (UnfoldLoad && !FoldedLoad) 2438 return 0; 2439 if (UnfoldStore && !FoldedStore) 2440 return 0; 2441 return I->second.first; 2442} 2443 2444bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 2445 if (MBB.empty()) return false; 2446 2447 switch (MBB.back().getOpcode()) { 2448 case X86::TCRETURNri: 2449 case X86::TCRETURNdi: 2450 case X86::RET: // Return. 2451 case X86::RETI: 2452 case X86::TAILJMPd: 2453 case X86::TAILJMPr: 2454 case X86::TAILJMPm: 2455 case X86::JMP: // Uncond branch. 2456 case X86::JMP32r: // Indirect branch. 2457 case X86::JMP64r: // Indirect branch (64-bit). 2458 case X86::JMP32m: // Indirect branch through mem. 2459 case X86::JMP64m: // Indirect branch through mem (64-bit). 2460 return true; 2461 default: return false; 2462 } 2463} 2464 2465bool X86InstrInfo:: 2466ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2467 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 2468 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 2469 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 2470 return true; 2471 Cond[0].setImm(GetOppositeBranchCondition(CC)); 2472 return false; 2473} 2474 2475bool X86InstrInfo:: 2476IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const { 2477 // FIXME: Ignore bariers of x87 stack registers for now. We can't 2478 // allow any loads of these registers before FpGet_ST0_80. 2479 return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 2480 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass; 2481} 2482 2483const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { 2484 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 2485 if (Subtarget->is64Bit()) 2486 return &X86::GR64RegClass; 2487 else 2488 return &X86::GR32RegClass; 2489} 2490 2491unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) { 2492 switch (Desc->TSFlags & X86II::ImmMask) { 2493 case X86II::Imm8: return 1; 2494 case X86II::Imm16: return 2; 2495 case X86II::Imm32: return 4; 2496 case X86II::Imm64: return 8; 2497 default: assert(0 && "Immediate size not set!"); 2498 return 0; 2499 } 2500} 2501 2502/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? 2503/// e.g. r8, xmm8, etc. 2504bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) { 2505 if (!MO.isReg()) return false; 2506 switch (MO.getReg()) { 2507 default: break; 2508 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 2509 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 2510 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 2511 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 2512 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 2513 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 2514 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 2515 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 2516 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 2517 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 2518 return true; 2519 } 2520 return false; 2521} 2522 2523 2524/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 2525/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 2526/// size, and 3) use of X86-64 extended registers. 2527unsigned X86InstrInfo::determineREX(const MachineInstr &MI) { 2528 unsigned REX = 0; 2529 const TargetInstrDesc &Desc = MI.getDesc(); 2530 2531 // Pseudo instructions do not need REX prefix byte. 2532 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 2533 return 0; 2534 if (Desc.TSFlags & X86II::REX_W) 2535 REX |= 1 << 3; 2536 2537 unsigned NumOps = Desc.getNumOperands(); 2538 if (NumOps) { 2539 bool isTwoAddr = NumOps > 1 && 2540 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; 2541 2542 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 2543 unsigned i = isTwoAddr ? 1 : 0; 2544 for (unsigned e = NumOps; i != e; ++i) { 2545 const MachineOperand& MO = MI.getOperand(i); 2546 if (MO.isReg()) { 2547 unsigned Reg = MO.getReg(); 2548 if (isX86_64NonExtLowByteReg(Reg)) 2549 REX |= 0x40; 2550 } 2551 } 2552 2553 switch (Desc.TSFlags & X86II::FormMask) { 2554 case X86II::MRMInitReg: 2555 if (isX86_64ExtendedReg(MI.getOperand(0))) 2556 REX |= (1 << 0) | (1 << 2); 2557 break; 2558 case X86II::MRMSrcReg: { 2559 if (isX86_64ExtendedReg(MI.getOperand(0))) 2560 REX |= 1 << 2; 2561 i = isTwoAddr ? 2 : 1; 2562 for (unsigned e = NumOps; i != e; ++i) { 2563 const MachineOperand& MO = MI.getOperand(i); 2564 if (isX86_64ExtendedReg(MO)) 2565 REX |= 1 << 0; 2566 } 2567 break; 2568 } 2569 case X86II::MRMSrcMem: { 2570 if (isX86_64ExtendedReg(MI.getOperand(0))) 2571 REX |= 1 << 2; 2572 unsigned Bit = 0; 2573 i = isTwoAddr ? 2 : 1; 2574 for (; i != NumOps; ++i) { 2575 const MachineOperand& MO = MI.getOperand(i); 2576 if (MO.isReg()) { 2577 if (isX86_64ExtendedReg(MO)) 2578 REX |= 1 << Bit; 2579 Bit++; 2580 } 2581 } 2582 break; 2583 } 2584 case X86II::MRM0m: case X86II::MRM1m: 2585 case X86II::MRM2m: case X86II::MRM3m: 2586 case X86II::MRM4m: case X86II::MRM5m: 2587 case X86II::MRM6m: case X86II::MRM7m: 2588 case X86II::MRMDestMem: { 2589 unsigned e = isTwoAddr ? 5 : 4; 2590 i = isTwoAddr ? 1 : 0; 2591 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) 2592 REX |= 1 << 2; 2593 unsigned Bit = 0; 2594 for (; i != e; ++i) { 2595 const MachineOperand& MO = MI.getOperand(i); 2596 if (MO.isReg()) { 2597 if (isX86_64ExtendedReg(MO)) 2598 REX |= 1 << Bit; 2599 Bit++; 2600 } 2601 } 2602 break; 2603 } 2604 default: { 2605 if (isX86_64ExtendedReg(MI.getOperand(0))) 2606 REX |= 1 << 0; 2607 i = isTwoAddr ? 2 : 1; 2608 for (unsigned e = NumOps; i != e; ++i) { 2609 const MachineOperand& MO = MI.getOperand(i); 2610 if (isX86_64ExtendedReg(MO)) 2611 REX |= 1 << 2; 2612 } 2613 break; 2614 } 2615 } 2616 } 2617 return REX; 2618} 2619 2620/// sizePCRelativeBlockAddress - This method returns the size of a PC 2621/// relative block address instruction 2622/// 2623static unsigned sizePCRelativeBlockAddress() { 2624 return 4; 2625} 2626 2627/// sizeGlobalAddress - Give the size of the emission of this global address 2628/// 2629static unsigned sizeGlobalAddress(bool dword) { 2630 return dword ? 8 : 4; 2631} 2632 2633/// sizeConstPoolAddress - Give the size of the emission of this constant 2634/// pool address 2635/// 2636static unsigned sizeConstPoolAddress(bool dword) { 2637 return dword ? 8 : 4; 2638} 2639 2640/// sizeExternalSymbolAddress - Give the size of the emission of this external 2641/// symbol 2642/// 2643static unsigned sizeExternalSymbolAddress(bool dword) { 2644 return dword ? 8 : 4; 2645} 2646 2647/// sizeJumpTableAddress - Give the size of the emission of this jump 2648/// table address 2649/// 2650static unsigned sizeJumpTableAddress(bool dword) { 2651 return dword ? 8 : 4; 2652} 2653 2654static unsigned sizeConstant(unsigned Size) { 2655 return Size; 2656} 2657 2658static unsigned sizeRegModRMByte(){ 2659 return 1; 2660} 2661 2662static unsigned sizeSIBByte(){ 2663 return 1; 2664} 2665 2666static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { 2667 unsigned FinalSize = 0; 2668 // If this is a simple integer displacement that doesn't require a relocation. 2669 if (!RelocOp) { 2670 FinalSize += sizeConstant(4); 2671 return FinalSize; 2672 } 2673 2674 // Otherwise, this is something that requires a relocation. 2675 if (RelocOp->isGlobal()) { 2676 FinalSize += sizeGlobalAddress(false); 2677 } else if (RelocOp->isCPI()) { 2678 FinalSize += sizeConstPoolAddress(false); 2679 } else if (RelocOp->isJTI()) { 2680 FinalSize += sizeJumpTableAddress(false); 2681 } else { 2682 assert(0 && "Unknown value to relocate!"); 2683 } 2684 return FinalSize; 2685} 2686 2687static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op, 2688 bool IsPIC, bool Is64BitMode) { 2689 const MachineOperand &Op3 = MI.getOperand(Op+3); 2690 int DispVal = 0; 2691 const MachineOperand *DispForReloc = 0; 2692 unsigned FinalSize = 0; 2693 2694 // Figure out what sort of displacement we have to handle here. 2695 if (Op3.isGlobal()) { 2696 DispForReloc = &Op3; 2697 } else if (Op3.isCPI()) { 2698 if (Is64BitMode || IsPIC) { 2699 DispForReloc = &Op3; 2700 } else { 2701 DispVal = 1; 2702 } 2703 } else if (Op3.isJTI()) { 2704 if (Is64BitMode || IsPIC) { 2705 DispForReloc = &Op3; 2706 } else { 2707 DispVal = 1; 2708 } 2709 } else { 2710 DispVal = 1; 2711 } 2712 2713 const MachineOperand &Base = MI.getOperand(Op); 2714 const MachineOperand &IndexReg = MI.getOperand(Op+2); 2715 2716 unsigned BaseReg = Base.getReg(); 2717 2718 // Is a SIB byte needed? 2719 if (IndexReg.getReg() == 0 && 2720 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) { 2721 if (BaseReg == 0) { // Just a displacement? 2722 // Emit special case [disp32] encoding 2723 ++FinalSize; 2724 FinalSize += getDisplacementFieldSize(DispForReloc); 2725 } else { 2726 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); 2727 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 2728 // Emit simple indirect register encoding... [EAX] f.e. 2729 ++FinalSize; 2730 // Be pessimistic and assume it's a disp32, not a disp8 2731 } else { 2732 // Emit the most general non-SIB encoding: [REG+disp32] 2733 ++FinalSize; 2734 FinalSize += getDisplacementFieldSize(DispForReloc); 2735 } 2736 } 2737 2738 } else { // We need a SIB byte, so start by outputting the ModR/M byte first 2739 assert(IndexReg.getReg() != X86::ESP && 2740 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 2741 2742 bool ForceDisp32 = false; 2743 if (BaseReg == 0 || DispForReloc) { 2744 // Emit the normal disp32 encoding. 2745 ++FinalSize; 2746 ForceDisp32 = true; 2747 } else { 2748 ++FinalSize; 2749 } 2750 2751 FinalSize += sizeSIBByte(); 2752 2753 // Do we need to output a displacement? 2754 if (DispVal != 0 || ForceDisp32) { 2755 FinalSize += getDisplacementFieldSize(DispForReloc); 2756 } 2757 } 2758 return FinalSize; 2759} 2760 2761 2762static unsigned GetInstSizeWithDesc(const MachineInstr &MI, 2763 const TargetInstrDesc *Desc, 2764 bool IsPIC, bool Is64BitMode) { 2765 2766 unsigned Opcode = Desc->Opcode; 2767 unsigned FinalSize = 0; 2768 2769 // Emit the lock opcode prefix as needed. 2770 if (Desc->TSFlags & X86II::LOCK) ++FinalSize; 2771 2772 // Emit segment overrid opcode prefix as needed. 2773 switch (Desc->TSFlags & X86II::SegOvrMask) { 2774 case X86II::FS: 2775 case X86II::GS: 2776 ++FinalSize; 2777 break; 2778 default: assert(0 && "Invalid segment!"); 2779 case 0: break; // No segment override! 2780 } 2781 2782 // Emit the repeat opcode prefix as needed. 2783 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize; 2784 2785 // Emit the operand size opcode prefix as needed. 2786 if (Desc->TSFlags & X86II::OpSize) ++FinalSize; 2787 2788 // Emit the address size opcode prefix as needed. 2789 if (Desc->TSFlags & X86II::AdSize) ++FinalSize; 2790 2791 bool Need0FPrefix = false; 2792 switch (Desc->TSFlags & X86II::Op0Mask) { 2793 case X86II::TB: // Two-byte opcode prefix 2794 case X86II::T8: // 0F 38 2795 case X86II::TA: // 0F 3A 2796 Need0FPrefix = true; 2797 break; 2798 case X86II::REP: break; // already handled. 2799 case X86II::XS: // F3 0F 2800 ++FinalSize; 2801 Need0FPrefix = true; 2802 break; 2803 case X86II::XD: // F2 0F 2804 ++FinalSize; 2805 Need0FPrefix = true; 2806 break; 2807 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 2808 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 2809 ++FinalSize; 2810 break; // Two-byte opcode prefix 2811 default: assert(0 && "Invalid prefix!"); 2812 case 0: break; // No prefix! 2813 } 2814 2815 if (Is64BitMode) { 2816 // REX prefix 2817 unsigned REX = X86InstrInfo::determineREX(MI); 2818 if (REX) 2819 ++FinalSize; 2820 } 2821 2822 // 0x0F escape code must be emitted just before the opcode. 2823 if (Need0FPrefix) 2824 ++FinalSize; 2825 2826 switch (Desc->TSFlags & X86II::Op0Mask) { 2827 case X86II::T8: // 0F 38 2828 ++FinalSize; 2829 break; 2830 case X86II::TA: // 0F 3A 2831 ++FinalSize; 2832 break; 2833 } 2834 2835 // If this is a two-address instruction, skip one of the register operands. 2836 unsigned NumOps = Desc->getNumOperands(); 2837 unsigned CurOp = 0; 2838 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) 2839 CurOp++; 2840 2841 switch (Desc->TSFlags & X86II::FormMask) { 2842 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!"); 2843 case X86II::Pseudo: 2844 // Remember the current PC offset, this is the PIC relocation 2845 // base address. 2846 switch (Opcode) { 2847 default: 2848 break; 2849 case TargetInstrInfo::INLINEASM: { 2850 const MachineFunction *MF = MI.getParent()->getParent(); 2851 const char *AsmStr = MI.getOperand(0).getSymbolName(); 2852 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo(); 2853 FinalSize += AI->getInlineAsmLength(AsmStr); 2854 break; 2855 } 2856 case TargetInstrInfo::DBG_LABEL: 2857 case TargetInstrInfo::EH_LABEL: 2858 break; 2859 case TargetInstrInfo::IMPLICIT_DEF: 2860 case TargetInstrInfo::DECLARE: 2861 case X86::DWARF_LOC: 2862 case X86::FP_REG_KILL: 2863 break; 2864 case X86::MOVPC32r: { 2865 // This emits the "call" portion of this pseudo instruction. 2866 ++FinalSize; 2867 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2868 break; 2869 } 2870 case X86::TLS_tp: 2871 case X86::TLS_gs_ri: 2872 FinalSize += 2; 2873 FinalSize += sizeGlobalAddress(false); 2874 break; 2875 } 2876 CurOp = NumOps; 2877 break; 2878 case X86II::RawFrm: 2879 ++FinalSize; 2880 2881 if (CurOp != NumOps) { 2882 const MachineOperand &MO = MI.getOperand(CurOp++); 2883 if (MO.isMBB()) { 2884 FinalSize += sizePCRelativeBlockAddress(); 2885 } else if (MO.isGlobal()) { 2886 FinalSize += sizeGlobalAddress(false); 2887 } else if (MO.isSymbol()) { 2888 FinalSize += sizeExternalSymbolAddress(false); 2889 } else if (MO.isImm()) { 2890 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2891 } else { 2892 assert(0 && "Unknown RawFrm operand!"); 2893 } 2894 } 2895 break; 2896 2897 case X86II::AddRegFrm: 2898 ++FinalSize; 2899 ++CurOp; 2900 2901 if (CurOp != NumOps) { 2902 const MachineOperand &MO1 = MI.getOperand(CurOp++); 2903 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 2904 if (MO1.isImm()) 2905 FinalSize += sizeConstant(Size); 2906 else { 2907 bool dword = false; 2908 if (Opcode == X86::MOV64ri) 2909 dword = true; 2910 if (MO1.isGlobal()) { 2911 FinalSize += sizeGlobalAddress(dword); 2912 } else if (MO1.isSymbol()) 2913 FinalSize += sizeExternalSymbolAddress(dword); 2914 else if (MO1.isCPI()) 2915 FinalSize += sizeConstPoolAddress(dword); 2916 else if (MO1.isJTI()) 2917 FinalSize += sizeJumpTableAddress(dword); 2918 } 2919 } 2920 break; 2921 2922 case X86II::MRMDestReg: { 2923 ++FinalSize; 2924 FinalSize += sizeRegModRMByte(); 2925 CurOp += 2; 2926 if (CurOp != NumOps) { 2927 ++CurOp; 2928 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2929 } 2930 break; 2931 } 2932 case X86II::MRMDestMem: { 2933 ++FinalSize; 2934 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 2935 CurOp += 5; 2936 if (CurOp != NumOps) { 2937 ++CurOp; 2938 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2939 } 2940 break; 2941 } 2942 2943 case X86II::MRMSrcReg: 2944 ++FinalSize; 2945 FinalSize += sizeRegModRMByte(); 2946 CurOp += 2; 2947 if (CurOp != NumOps) { 2948 ++CurOp; 2949 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2950 } 2951 break; 2952 2953 case X86II::MRMSrcMem: { 2954 2955 ++FinalSize; 2956 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode); 2957 CurOp += 5; 2958 if (CurOp != NumOps) { 2959 ++CurOp; 2960 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2961 } 2962 break; 2963 } 2964 2965 case X86II::MRM0r: case X86II::MRM1r: 2966 case X86II::MRM2r: case X86II::MRM3r: 2967 case X86II::MRM4r: case X86II::MRM5r: 2968 case X86II::MRM6r: case X86II::MRM7r: 2969 ++FinalSize; 2970 ++CurOp; 2971 FinalSize += sizeRegModRMByte(); 2972 2973 if (CurOp != NumOps) { 2974 const MachineOperand &MO1 = MI.getOperand(CurOp++); 2975 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 2976 if (MO1.isImm()) 2977 FinalSize += sizeConstant(Size); 2978 else { 2979 bool dword = false; 2980 if (Opcode == X86::MOV64ri32) 2981 dword = true; 2982 if (MO1.isGlobal()) { 2983 FinalSize += sizeGlobalAddress(dword); 2984 } else if (MO1.isSymbol()) 2985 FinalSize += sizeExternalSymbolAddress(dword); 2986 else if (MO1.isCPI()) 2987 FinalSize += sizeConstPoolAddress(dword); 2988 else if (MO1.isJTI()) 2989 FinalSize += sizeJumpTableAddress(dword); 2990 } 2991 } 2992 break; 2993 2994 case X86II::MRM0m: case X86II::MRM1m: 2995 case X86II::MRM2m: case X86II::MRM3m: 2996 case X86II::MRM4m: case X86II::MRM5m: 2997 case X86II::MRM6m: case X86II::MRM7m: { 2998 2999 ++FinalSize; 3000 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3001 CurOp += 4; 3002 3003 if (CurOp != NumOps) { 3004 const MachineOperand &MO = MI.getOperand(CurOp++); 3005 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 3006 if (MO.isImm()) 3007 FinalSize += sizeConstant(Size); 3008 else { 3009 bool dword = false; 3010 if (Opcode == X86::MOV64mi32) 3011 dword = true; 3012 if (MO.isGlobal()) { 3013 FinalSize += sizeGlobalAddress(dword); 3014 } else if (MO.isSymbol()) 3015 FinalSize += sizeExternalSymbolAddress(dword); 3016 else if (MO.isCPI()) 3017 FinalSize += sizeConstPoolAddress(dword); 3018 else if (MO.isJTI()) 3019 FinalSize += sizeJumpTableAddress(dword); 3020 } 3021 } 3022 break; 3023 } 3024 3025 case X86II::MRMInitReg: 3026 ++FinalSize; 3027 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 3028 FinalSize += sizeRegModRMByte(); 3029 ++CurOp; 3030 break; 3031 } 3032 3033 if (!Desc->isVariadic() && CurOp != NumOps) { 3034 cerr << "Cannot determine size: "; 3035 MI.dump(); 3036 cerr << '\n'; 3037 abort(); 3038 } 3039 3040 3041 return FinalSize; 3042} 3043 3044 3045unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 3046 const TargetInstrDesc &Desc = MI->getDesc(); 3047 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_); 3048 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); 3049 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); 3050 if (Desc.getOpcode() == X86::MOVPC32r) { 3051 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); 3052 } 3053 return Size; 3054} 3055 3056/// getGlobalBaseReg - Return a virtual register initialized with the 3057/// the global base register value. Output instructions required to 3058/// initialize the register in the function entry block, if necessary. 3059/// 3060unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3061 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3062 "X86-64 PIC uses RIP relative addressing"); 3063 3064 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3065 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3066 if (GlobalBaseReg != 0) 3067 return GlobalBaseReg; 3068 3069 // Insert the set of GlobalBaseReg into the first MBB of the function 3070 MachineBasicBlock &FirstMBB = MF->front(); 3071 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3072 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3073 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3074 3075 const TargetInstrInfo *TII = TM.getInstrInfo(); 3076 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3077 // only used in JIT code emission as displacement to pc. 3078 BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0); 3079 3080 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3081 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external 3082 if (TM.getRelocationModel() == Reloc::PIC_ && 3083 TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3084 GlobalBaseReg = 3085 RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3086 BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg) 3087 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_"); 3088 } else { 3089 GlobalBaseReg = PC; 3090 } 3091 3092 X86FI->setGlobalBaseReg(GlobalBaseReg); 3093 return GlobalBaseReg; 3094} 3095