History log of /external/llvm/lib/Target/X86/X86InstrInfo.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1070c0a33692cb38ba23efd11ff3116f2fc33834 19-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195094:
------------------------------------------------------------------------
r195094 | atrick | 2013-11-18 19:29:59 -0800 (Mon, 18 Nov 2013) | 3 lines

Use symbolic operands in the patchpoint folding routine and fix a spilling bug.

Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195113 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
354362524a72b3fa43a6c09380b7ae3b2380cbba 19-Nov-2013 Juergen Ributzka <juergen@apple.com> [weak vtables] Remove a bunch of weak vtables

This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 18-Nov-2013 Alexey Samsonov <samsonov@google.com> Revert r194865 and r194874.

This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bb756ca24401e190e3b704e5d92759c7a79cc6b7 17-Nov-2013 Andrew Trick <atrick@apple.com> Added a size field to the stack map record to handle subregister spills.

Implementing this on bigendian platforms could get strange. I added a
target hook, getStackSlotRange, per Jakob's recommendation to make
this as explicit as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8c66df2c7a0e6309eb26d83741f3e121fd3b8550 16-Nov-2013 Lang Hames <lhames@gmail.com> During folding for patchpoint/stackmap instructions, defer creation of new MIs
until we know that folding will be successful.

No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 15-Nov-2013 Juergen Ributzka <juergen@apple.com> [weak vtables] Remove a bunch of weak vtables

This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f58e4144054b85e855c57c86eb058a6bb1907552 14-Nov-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: Handled extractelement from mask vector;
Added VMOSHDUP/VMOVSLDUP shuffle instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7107aded170612748f46380f21ec6b71dfaf4910 12-Nov-2013 Andrew Trick <atrick@apple.com> Cleanup the stackmap operand folding code and fix a corner case.

I still don't know how to refer to the fixed operands symbolically. I
plan to look into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0085d5e5ae45e74254c2aa682e18574cd79f3455 12-Nov-2013 Andrew Trick <atrick@apple.com> Simplify operand folding when rematerializing a load.

We already know how to fold a reload from a frameindex without
analyzing the load instruction. Generalize this to handle any
frameindex load. This streamlines the logic for rematerializing loads
from stack arguments. As a side effect, it allows stackmaps to record
a stack argument location without spilling it.

Verified no effect on codegen for llvm test-suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
01846af6ed371ebe2dba80cc8cd286b2631d4051 11-Nov-2013 Andrew Trick <atrick@apple.com> Fix the recently added anyregcc convention to handle spilled operands.

Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!"

The primary purpose of anyregcc is to prevent a patchpoint's call
arguments and return value from being spilled. They must be available
in a register, although the calling convention does not pin the
register. It's up to the front end to avoid using this convention for
calls with more arguments than allocatable registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
623d2e618f4e672c47edff9ec63ed6d733ac81d3 09-Nov-2013 Juergen Ributzka <juergen@apple.com> [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.

The idea of the AnyReg Calling Convention is to provide the call arguments in
registers, but not to force them to be placed in a paticular order into a
specified set of registers. Instead it is up tp the register allocator to assign
any register as it sees fit. The same applies to the return value (if
applicable).

Differential Revision: http://llvm-reviews.chandlerc.com/D2009

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3d74dea4bddc84d1881efc21eb5eefbddbfa9aed 31-Oct-2013 Andrew Trick <atrick@apple.com> Add support for stack map generation in the X86 backend.

Originally implemented by Lang Hames.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fc678719d935ffb893a3e08905f0d00b649f9d4f 22-Oct-2013 Craig Topper <craig.topper@gmail.com> Replace (V)MOVZDI2PDIrr/rm instructions with patterns that select (V)MOVDI2PDIrr/rm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99 15-Oct-2013 Andrew Trick <atrick@apple.com> Fix the ExecutionDepsFix pass to handle AVX instructions.

This pass is needed to break false dependencies. Without it, unlucky
register assignment can result in wild (5x) swings in
performance. This pass was trying to handle AVX but not getting it
right. AVX doesn't have partial register defs, it has unused register
reads in which the high bits of a source operand are copied into the
unused bits of the dest.

Fixing this requires conservative liveness analysis. This is awkard
because the pass already has its own pseudo-liveness. However, proper
liveness is expensive, and we would like to use a generic utility to
compute it. The fix only invokes liveness on-demand. It is rare to
detect a case that needs undef-read dependence breaking, but when it
happens, it can be needed many times within a very large block.

I think the existing heuristic which uses a register window of 16 is
too conservative for loop-carried false dependencies. If the loop is a
reduction. The out-of-order engine may be able to execute several loop
iterations in parallel. However, I'll leave this tuning exercise for
next time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ff09d7119da02e1834e72884d61d1f1131b43466 15-Oct-2013 Andrew Trick <atrick@apple.com> whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
510fb362a815499dde40cfae807b2ab927527ab0 07-Oct-2013 Craig Topper <craig.topper@gmail.com> Remove FsMOVAPSrr and friends. They have no patterns and are no longer selected anywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d9f7a185e31d70a81775eb88db33c74b92b14697 06-Oct-2013 Benjamin Kramer <benny.kra@googlemail.com> X86: Don't fold spills into SSE operations if the stack is unaligned.

Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
714319a169784577e33fb1ea28ac06be32c9e735 06-Oct-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
984fbe6c65e54fe3815b14619240eafb3024c9bd 05-Oct-2013 Craig Topper <craig.topper@gmail.com> Add TBM instructions to loading folding tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c699417f11dce6d81f630d5b1c82e00dba852b37 02-Oct-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c8f377d5ec99744a43c6c5705d1e41e047a3d80b 17-Sep-2013 Craig Topper <craig.topper@gmail.com> Add AES and SHA instructions to the load folding tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0faffd1aea24995cefade95c495294dbb663ca82 17-Sep-2013 Craig Topper <craig.topper@gmail.com> Fix column alignment. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
da0ce6eb8b11083b5cc1849b625509b87a7d9db9 02-Sep-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: updated the list of high-latency instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cafcc998572057d78d29deb28dd32145f411a7cf 02-Sep-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: gather-scatter tests; added foldable instructions;
Specify GATHER/SCATTER as heavy instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
41f7baf181ef55fb6935ded8ced3797701a681ca 25-Aug-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3491d67d3a50e81e3f65c1bdf01dd7962dc10c46 18-Aug-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fac4a4eb7dfbfc90ae1d5c7d6c39a2d89a33c30e 11-Aug-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.
Added a test for shuffles using VPERM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0f2eec65fb9e9e1dee3f672d38d03d047936a62a 23-Jun-2013 Andrew Trick <atrick@apple.com> Add MI-Sched support for x86 macro fusion.

This is an awful implementation of the target hook. But we don't have
abstractions yet for common machine ops, and I don't see any quick way
to make it table-driven.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 16-Jun-2013 David Blaikie <dblaikie@gmail.com> DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs

Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e5609f37323b105c7720d5d423a9203d1e869c29 10-Jun-2013 Tim Northover <tnorthover@apple.com> X86: Stop LEA64_32r doing unspeakable things to its arguments.

Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a5e5ba611f787f518fd3f7349343f8c4ae863fc2 07-Jun-2013 Bill Wendling <isanbard@gmail.com> Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3ba14fab1b653015428055ddce4205682885ff3f 01-Jun-2013 Tim Northover <tnorthover@apple.com> Revert r183069: "TMP: LEA64_32r fixing"

Very sorry, it was committed from the wrong branch by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4d3ace4da0a000428ad5baea72c82e585fcd531c 01-Jun-2013 Tim Northover <tnorthover@apple.com> TMP: LEA64_32r fixing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
15983b80a0ceb224b74d2ee5ef53d3eed37dc03b 30-May-2013 Tim Northover <tnorthover@apple.com> X86: use sub-register sequences for MOV*r0 operations

Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions,
it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg")
and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is
smaller and partial register updates can sometimes be avoided.

Until recently, this sequence was a barrier to rematerialization though. That
should now be fixed so it's an appropriate time to make the change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
da0416b9356c9ddf3dddeeb1ad5aec4d1de70016 30-May-2013 Tim Northover <tnorthover@apple.com> X86: change zext moves to use sub-register infrastructure.

32-bit writes on amd64 zero out the high bits of the corresponding 64-bit
register. LLVM makes use of this for zero-extension, but until now relied on
custom MCLowering and other code to fixup instructions. Now we have proper
handling of sub-registers, this can be done by creating SUBREG_TO_REG
instructions at selection-time.

Should be no change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ac6d9bec671252dd1e596fa71180ff6b39d06b5d 25-May-2013 Andrew Trick <atrick@apple.com> Track IR ordering of SelectionDAG nodes 2/4.

Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3b4b5367da29a1598dc333acf37652ef286e9225 22-May-2013 David Majnemer <david.majnemer@gmail.com> X86: Remove test instructions proceeding shift by immediate instructions

Allow LLVM to take advantage of shift instructions that set the ZF flag,
making instructions that test the destination superfluous.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8a55c2ecd4d7648a6564091d428e18ec2146ff8e 18-May-2013 David Majnemer <david.majnemer@gmail.com> X86: Bad peephole interaction between adc, MOV32r0

The peephole tries to reorder MOV32r0 instructions such that they are
before the instruction that modifies EFLAGS.

The problem is that the peephole does not consider the case where the
instruction that modifies EFLAGS also depends on the previous state of
EFLAGS.

Instead, walk backwards until we find an instruction that has a def for
EFLAGS but does not have a use.
If we find such an instruction, insert the MOV32r0 before it.
If it cannot find such an instruction, skip the optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
17585dc4d437d0c72f97f9b1aa86218f6b66a677 16-May-2013 David Majnemer <david.majnemer@gmail.com> X86: Remove redundant test instructions

Increase the number of instructions LLVM recognizes as setting the ZF
flag. This allows us to remove test instructions that redundantly
recalculate the flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 20-Apr-2013 Michael Liao <michael.liao@intel.com> ArrayRefize getMachineNode(). No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1fd36e41e408307a4e7362cc9cd83aeb77ee71dd 28-Mar-2013 Preston Gurd <preston.gurd@intel.com> This patch follows is a follow up to r178171, which uses the register
form of call in preference to memory indirect on Atom.

In this case, the patch applies the optimization to the code for reloading
spilled registers.

The patch also includes changes to sibcall.ll and movgs.ll, which were
failing on the Atom buildbot after the first patch was applied.

This patch by Sriram Murali.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0b8c9a80f20772c3793201ab5b251d3520b9cea3 02-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
831737d329a727f53a1fb0572f7b7a8127208881 30-Dec-2012 Bill Wendling <isanbard@gmail.com> Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.

This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
22d8f0d68519240b0936983322cfdb9c84a4ed0c 29-Dec-2012 Craig Topper <craig.topper@gmail.com> Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6d183e400720b703dc9dbe6c8a28b615441601a2 29-Dec-2012 Craig Topper <craig.topper@gmail.com> Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
174a3d3e63734aced494b0f725fd4d0bf1fa3491 26-Dec-2012 Craig Topper <craig.topper@gmail.com> Remove alignment from a bunch more VEX encoded operations in the folding tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d83a73adf0cd8181eb43f2e5116e53a508e126db 26-Dec-2012 Craig Topper <craig.topper@gmail.com> Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1ac0046fa83142724c94c8edd46584d638fc141a 26-Dec-2012 Craig Topper <craig.topper@gmail.com> Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0f77910e6fb2c7fccc9643df8b6859c742d678a2 26-Dec-2012 Craig Topper <craig.topper@gmail.com> Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a4c8a32a9f9ca0db1e7dd95c0a95529403097c1f 25-Dec-2012 Nadav Rotem <nrotem@apple.com> VCVTSS2SD requires a strict alignment. Thanks Elena.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ace0c2fad7c581367cc2519e1d773bca37fc9fec 24-Dec-2012 Nadav Rotem <nrotem@apple.com> Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned.
When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding
tables and removes the alignment restrictions from VEX-encoded instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d0696ef8c33b9b2504e89bc0aab2ea99a6c90756 22-Dec-2012 Nadav Rotem <nrotem@apple.com> In some cases, due to scheduling constraints we copy the EFLAGS.
The only way to read the eflags is using push and pop. If we don't
adjust the stack then we run over the first frame index. This is
not something that we want to do, so we have to make sure that
our machine function does not copy the flags. If it does then
we have to emit the prolog that adjusts the stack.

rdar://12896831



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
739c7a83e16e7daaf22cfa4ae84e8d1cc0260941 21-Dec-2012 Benjamin Kramer <benny.kra@googlemail.com> X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics

This is very mechanical, no functionality change. Preparation for PR14667.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
37a942cd52725b1d390989a8267a764b42fcb5d3 19-Dec-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the explicit MachineInstrBuilder(MI) constructor.

Use the version that also takes an MF reference instead.

It would technically be possible to extract an MF reference from the MI
as MI->getParent()->getParent(), but that would not work for MIs that
are not inserted into any basic block.

Given the reasonably small number of places this constructor was used at
all, I preferred the compile time check to a run time assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
034b94b17006f51722886b0f2283fb6fb19aca1f 19-Dec-2012 Bill Wendling <isanbard@gmail.com> Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b926afcc5b99030fecf496d15cffdd1315fd0ead 17-Dec-2012 Craig Topper <craig.topper@gmail.com> Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add ANDN to isDefConvertible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b72ae7003629771bdb892d9a03cb761b4dbac5be 17-Dec-2012 Craig Topper <craig.topper@gmail.com> Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
16a1acc3b96bb85e53c184f4fd4fd614543cec6b 17-Dec-2012 Craig Topper <craig.topper@gmail.com> Remove store forms of DEC/INC from isDefConvertible. Since they are stores they don't have a register def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170303 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ab69b25f4bc653e11fe81bea0df3c07702e9b6f0 06-Dec-2012 Craig Topper <craig.topper@gmail.com> Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as neverHasSideEffects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 03-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a9fa4fd9736f7d1066223f32fa54efbe86c0fceb 28-Nov-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove all references to TargetInstrInfoImpl.

This class has been merged into its super-class TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f365d3984e2934b182e866d545348988d3b681d5 27-Nov-2012 Manman Ren <mren@apple.com> X86: do not fold load instructions such as [V]MOVS[S|D] to other instructions
when the destination register is wider than the memory load.

These load instructions load from m32 or m64 and set the upper bits to zero,
while the folded instructions may accept m128.

rdar://12721174


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f23b90858c88cc6667d54f88b970fb829b368c76 04-Nov-2012 Craig Topper <craig.topper@gmail.com> Remove alignments from folding tables for scalar FMA4 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b5bc8d00096e794c52dc82fefb31a07ae5a263be 31-Oct-2012 Craig Topper <craig.topper@gmail.com> Add scalar forms of FMA4 VFNMSUB/VFNMADD to folding tables. Patch from Cameron McInally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6765834754cbb3cb0f15b4b15e98c5e73fa50066 09-Oct-2012 Bill Wendling <isanbard@gmail.com> Create enums for the different attributes.

We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ff9d51b994c3672853cd7c7d92d6857d21d4f09d 05-Oct-2012 Craig Topper <craig.topper@gmail.com> Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ExpandPostRAPseudos and mark them as pseudos in the td file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
94c22716d60ff5edf6a98a3c67e0faa001be1142 27-Sep-2012 Sylvestre Ledru <sylvestre@debian.org> Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7e2c793a2b5c746344652b6579e958ee42fafdcc 27-Sep-2012 Sylvestre Ledru <sylvestre@debian.org> Fix a typo 'iff' => 'if'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2c189061184925c6a8ecbb5a19e648b230a41c0e 26-Sep-2012 Bill Wendling <isanbard@gmail.com> Remove the `hasFnAttr' method from Function.

The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4fa2ddbb94bb7b7f67e4f4d0aac292998fbf00ed 26-Sep-2012 Michael Liao <michael.liao@intel.com> Add SARX/SHRX/SHLX code generation support



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6bcdb5b9034a02901175e94e89b4815f28f2f141 26-Sep-2012 Michael Liao <michael.liao@intel.com> Add RORX code generation support



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0832a72a662043efad72f090023a19156974fc0c 26-Sep-2012 Michael Liao <michael.liao@intel.com> Add MULX code generation support



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b118a073d7434727a4ea5a5762f54e54e72bef4f 20-Sep-2012 Michael Liao <michael.liao@intel.com> Re-work X86 code generation of atomic ops with spin-loop

- Rewrite/merge pseudo-atomic instruction emitters to address the
following issue:
* Reduce one unnecessary load in spin-loop

previously the spin-loop looks like

thisMBB:
newMBB:
ld t1 = [bitinstr.addr]
op t2 = t1, [bitinstr.val]
not t3 = t2 (if Invert)
mov EAX = t1
lcs dest = [bitinstr.addr], t3 [EAX is implicit]
bz newMBB
fallthrough -->nextMBB

the 'ld' at the beginning of newMBB should be lift out of the loop
as lcs (or CMPXCHG on x86) will load the current memory value into
EAX. This loop is refined as:

thisMBB:
EAX = LOAD [MI.addr]
mainMBB:
t1 = OP [MI.val], EAX
LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
JNE mainMBB
sinkMBB:

* Remove immopc as, so far, all pseudo-atomic instructions has
all-register form only, there is no immedidate operand.

* Remove unnecessary attributes/modifiers in pseudo-atomic instruction
td

* Fix issues in PR13458

- Add comprehensive tests on atomic ops on various data types.
NOTE: Some of them are turned off due to missing functionality.

- Revise tests due to the new spin-loop generated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b024b7014ad13d076cfc3eb2d63c49681ad1bdd0 18-Sep-2012 Jan Wen Voung <jvoung@google.com> Add some cases to x86 OptimizeCompare to handle DEC and INC, too.

While we are setting the earlier def to true, also make it live.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dfb1e4babd2e825d951d42bcb45438b48c45b155 01-Sep-2012 Craig Topper <craig.topper@gmail.com> Mark FMA4 instructions as commutable and add them to the folding tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bbdbb0550b8397fa00e0376a0c3bb312f51c0dfa 01-Sep-2012 Craig Topper <craig.topper@gmail.com> Add selection of RegOp2MemOpTable3 to canFoldMemoryOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d90219463154cafb5d626b7964bf20e572a186df 28-Aug-2012 Craig Topper <craig.topper@gmail.com> Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
13897fb2638f008b41f6e2bc0dd25d78b72c5351 28-Aug-2012 Craig Topper <craig.topper@gmail.com> Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
91f3a6cfd95f6520a2d297b1ba426f7ebb2df716 24-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Preserve operand flags in convertToThreeAddress() by copying operands.

No test case, this is a generalization of r160260.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8a5bc5ad905bd4e5c0705fdcb0736316af6fdbe1 23-Aug-2012 Craig Topper <craig.topper@gmail.com> Use a switch statement instead of a bunch of if-else checks and pull out the common function call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4dea906e1aa019b8fdb999744bf1cf8333b85890 21-Aug-2012 Craig Topper <craig.topper@gmail.com> Fix up indentation and remove a couple else's after returns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a182367e597516aa5d993a07ee2d0964b3a622e8 21-Aug-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t for tables of opcodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
630e33a8577f8982995b69a06809317b8758e5a2 21-Aug-2012 Craig Topper <craig.topper@gmail.com> Fix up indentation. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
195f1b8a26d7d22fcaac7c6d92fd421857c6a81b 21-Aug-2012 Craig Topper <craig.topper@gmail.com> Add a couple llvm_unreachables. Add a message to several others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cba48d8c0570669c3bef08bd5f071e596902db21 21-Aug-2012 Craig Topper <craig.topper@gmail.com> Replace a break with llvm_unreachable in the default case of a nested switch. Condense code a bit. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
75d8ad461f1ab7542123086d51e61530a5229d9a 20-Aug-2012 Craig Topper <craig.topper@gmail.com> Remove FMA3 intrinsic instructions in favor of patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c586d268124f8801434cc0f68fe10cb3510c7ca6 13-Aug-2012 Manman Ren <mren@apple.com> X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr from
OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed
to a memory operand.

PR13576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
39ad568c62f5120faec29f69d3d614303a1f992d 08-Aug-2012 Manman Ren <mren@apple.com> X86: enable CSE between CMP and SUB

We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.

Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.

rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
130e603115129ec1a6b94550a15f7caea0cbf068 08-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Don't scan physreg use-def chains looking for a PIC base.

We can't rematerialize a PIC base after register allocation anyway, and
scanning physreg use-def chains is very expensive in a function with
many calls.

<rdar://problem/12047515>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2d 02-Aug-2012 Manman Ren <mren@apple.com> X86 Peephole: fold loads to the source register operand if possible.

Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

This patch is a rework of r160919 and was tested on clang self-host on my local
machine.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1503aba4a036f5394c7983417bc1e64613b2fc77 01-Aug-2012 Elena Demikhovsky <elena.demikhovsky@intel.com> Added FMA functionality to X86 target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e8b4a4a9d173d67e35e4b1d32e20140381db6bde 29-Jul-2012 Manman Ren <mren@apple.com> Revert r160920 and r160919 due to dragonegg and clang selfhost failure



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0eb3edea9cb6819334173a7d288da85943201fe5 28-Jul-2012 Manman Ren <mren@apple.com> X86 Peephole: fold loads to the source register operand if possible.

Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
43d9ab1812f7551844112f6f21cf3e487cb77385 28-Jul-2012 Manman Ren <mren@apple.com> X86 Peephole: fix PR13475 in optimizeCompare.

It is possible that an instruction can use and update EFLAGS.
When checking the safety, we should check the usage of EFLAGS first before
declaring it is safe to optimize due to the update.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
62a89f5808bbb620767d95adb784978ed2e7bff0 18-Jul-2012 Manman Ren <mren@apple.com> X86: remove redundant cmp against zero.

Updated OptimizeCompare in peephole to remove redundant cmp against zero.
We only remove Compare if CF and OF are not used.

rdar://11855129


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d93ea88cdef5cd7e5b540f1fe913c798a8d27b24 16-Jul-2012 Nadav Rotem <nadav.rotem@intel.com> Fix a bug in the 3-address conversion of LEA when one of the operands is an
undef virtual register. The problem is that ProcessImplicitDefs removes the
definition of the register and marks all uses as undef. If we lose the undef
marker then we get a register which has no def, is not marked as undef. The
live interval analysis does not collect information for these virtual
registers and we crash in later passes.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
aec9f382dd08799a9676f27fc7766a27897ab8b6 15-Jul-2012 Nadav Rotem <nadav.rotem@intel.com> Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.
Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot.

PR12782.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
23d3622e7647a2836e05bffeb24d3d9235a25f24 13-Jul-2012 Benjamin Kramer <benny.kra@googlemail.com> Make helper functions static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
84ae7e9034ef4dd0b9c88c5cf0e5e91ab50a7ef1 11-Jul-2012 Manman Ren <mren@apple.com> X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.

When Movr0 is between sub and cmp, we move Movr0 before sub if it enables
removal of Cmp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6209364834a4c0ca720d3fcc9ef7fa4c1fb39ecc 09-Jul-2012 Manman Ren <mren@apple.com> X86: implement functions to analyze & synthesize CMOV|SET|Jcc
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond

No functional change intended.
If we want to update the condition code of CMOV|SET|Jcc, we first analyze the
opcode to get the condition code, then update the condition code, finally
synthesize the new opcode form the new condition code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2d4215f75949448d5207ec67b11878741a708fbe 07-Jul-2012 Manman Ren <mren@apple.com> X86: Fix optimizeCompare to correctly check safe condition.

It is safe if EFLAGS is killed or re-defined.
When we are done with the basic block, check whether EFLAGS is live-out.
Do not optimize away cmp if EFLAGS is live-out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2af66dc51a7a0f3490c7e89c636e4015431195cd 06-Jul-2012 Manman Ren <mren@apple.com> X86: peephole optimization to remove cmp instruction

For each Cmp, we check whether there is an earlier Sub which make Cmp
redundant. We handle the case where SUB operates on the same source operands as
Cmp, including the case where the two source operands are swapped.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
59bde4d8a1065d3c48c5ea94a570b2c4d2f294a8 04-Jul-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add early if-conversion support to X86.

Implement the TII hooks needed by EarlyIfConversion to create cmov
instructions and estimate their latency.

Early if-conversion is still not enabled by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
13d89c7976df8e69b3aaaf7858b4433046b658b5 25-Jun-2012 Craig Topper <craig.topper@gmail.com> Remove codegen only instruction in favor of one that has the same definition. Make some pattern operands more explicit about types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e7f702fc2d496aff1e5c1153519931e203b1ca76 24-Jun-2012 Craig Topper <craig.topper@gmail.com> Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2123b182478fd4c27d55596603e007225b669073 24-Jun-2012 Craig Topper <craig.topper@gmail.com> Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
081f931077d413aba46e9c52fd672746f791875d 24-Jun-2012 Craig Topper <craig.topper@gmail.com> Fix build failures from r159106.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7f2ea14c68c8e4477c47d3a0bb96af84e912d933 24-Jun-2012 Craig Topper <craig.topper@gmail.com> Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c82b9a51a2a8516ca3426d8494050301f8f73fcc 24-Jun-2012 Craig Topper <craig.topper@gmail.com> Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3ed920f308d1fb20999bf8bf6247af36261f6b7d 23-Jun-2012 Craig Topper <craig.topper@gmail.com> Compress flags in X86 op folding to reduce space in static tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
eea4a9b1e6aef4b2a03b4faf0efc10c3f7a8d800 23-Jun-2012 Craig Topper <craig.topper@gmail.com> Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with intrinsic patterns. Mem forms omitted because the load size is only 64-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8e58b3e9b875c70e09d97d449373744aacc35ea9 15-Jun-2012 Craig Topper <craig.topper@gmail.com> Move AVX version of convert instructions that write to GPRs to the Op1 table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
312091ece3e7860cea0410318cf1e06cea75954e 15-Jun-2012 Pete Cooper <peter_cooper@apple.com> Move X86::VCVTTSD2SIrr from the 2 operand to 1 operand MemRegOp table.

Can someone with more knowledge of this please look at other entries
to see if others need moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2afde7782dfa56b2e46f79598bdb5f1e09471941 07-Jun-2012 Manman Ren <mren@apple.com> Revert r157755.

The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a7542d5f870c5d98960d1676e23ac1d1d975d7e5 06-Jun-2012 Benjamin Kramer <benny.kra@googlemail.com> Remove unused private fields found by clang's new -Wunused-private-field.

There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
caea5e28b23fa1aca6b038141fc63b50150d9d2e 04-Jun-2012 Craig Topper <craig.topper@gmail.com> Add intrinsic forms for FMA instructions to opcode folding tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fc5ab2449364d4fe56acf320bb6664a18f8e40b6 04-Jun-2012 Craig Topper <craig.topper@gmail.com> Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 forms of scalar FMA instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c73ea9102b711d6c2bfd33a86e1c07565c83ffe7 03-Jun-2012 Manman Ren <mren@apple.com> Revert r157831

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
73c2f7f5ed767a6fc062fd198551be902b7b7d5b 01-Jun-2012 Manman Ren <mren@apple.com> X86: peephole optimization to remove cmp instruction

This patch will optimize the following:
sub r1, r3
cmp r3, r1 or cmp r1, r3
bge L1
TO
sub r1, r3
bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f0234fcbc9be9798c10dedc3e3c134b7afbc6511 01-Jun-2012 Hans Wennborg <hans@hanshq.net> Implement the local-dynamic TLS model for x86 (PR3985)

This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
78fc72d0f1be84ce53d66596ef4c4dc93cd9b0b0 01-Jun-2012 Craig Topper <craig.topper@gmail.com> Add VFNSUB* instructions to folding table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
91c5346d91973a1d3458a20f8c6b0e899b732e38 31-May-2012 Manman Ren <mren@apple.com> X86: replace SUB with CMP if possible

This patch will optimize the following
movq %rdi, %rax
subq %rsi, %rax
cmovsq %rsi, %rdi
movq %rdi, %rax
to
cmpq %rsi, %rdi
cmovsq %rsi, %rdi
movq %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
177cf1e1a3685209ab805f82897902a8d2b61661 31-May-2012 Elena Demikhovsky <elena.demikhovsky@intel.com> Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
53df9259e94a9d6b99348ecf9683cdec7bf94bc8 20-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Make the global base reg GR32_NOSP.

It can sometimes be used in addressing modes that don't support %ESP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 08-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c909950c384e8234a7b3c5a76b7f79e3f7012ceb 20-Apr-2012 Craig Topper <craig.topper@gmail.com> Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
73c504af9d86a426532ee32c5d07a4b872794675 15-Apr-2012 Elena Demikhovsky <elena.demikhovsky@intel.com> Added VPERM optimization for AVX2 shuffles

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
79aa3417eb6f58d668aadfedf075240a41d35a26 17-Mar-2012 Craig Topper <craig.topper@gmail.com> Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
72051bf629087bb7d7e68aa4d553be8137098056 09-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t to store opcodes in static tables in X86 backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
44d23825d61d530b8d562329ec8fc2d4f843bb8d 22-Feb-2012 Craig Topper <craig.topper@gmail.com> Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
527a08b253795cf09de41c289c9dc071f00b1d4a 16-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Use the same CALL instructions for Windows as for everything else.

The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
450b3850ceb913128185c53f7475e86577792444 09-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Handle register masks when searching for EFLAGS clobbers.

Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
969ba287cd2be9b2d6843db6fa5337585f84283b 25-Jan-2012 Craig Topper <craig.topper@gmail.com> Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4bb3f34b2296f0ec70751f332cf7ef96d2d30a48 25-Jan-2012 Craig Topper <craig.topper@gmail.com> Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 20-Jan-2012 David Blaikie <dblaikie@gmail.com> More dead code removal (using -Wunreachable-code)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
40385c81044d5fcb5b81af36acf23cad8f6a5156 19-Jan-2012 Craig Topper <craig.topper@gmail.com> Folding table additions and fixes for AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
446626d236ce0b11a1db0c330fef0405ff4a5ddb 14-Jan-2012 Craig Topper <craig.topper@gmail.com> Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0518970dc88e20ee40aa5eb555209180f052a4d9 13-Jan-2012 Craig Topper <craig.topper@gmail.com> Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148112 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
12216172c04fe76a90e9de34fc4161e92d097278 13-Jan-2012 Craig Topper <craig.topper@gmail.com> Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b9c7f652d779d4c06c02eb664dafbb28dc2d732a 13-Jan-2012 Craig Topper <craig.topper@gmail.com> Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ddfd1377d2e4154d44dc3ad217735adc15af2e3f 14-Dec-2011 Evan Cheng <evan.cheng@apple.com> - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a73fb9adbb2de7cd4837382b0fffd97d82ac675c 09-Dec-2011 Benjamin Kramer <benny.kra@googlemail.com> X86: Split (v)rounds[sd] into a normal and an intrinsic version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146256 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd 07-Dec-2011 Evan Cheng <evan.cheng@apple.com> Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0edd83bfff5b29a6d08718a0abc13aa7197c372d 29-Nov-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.

Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fe2a6c584a62508e7e7ab990a16bf84af51ce52e 29-Nov-2011 Craig Topper <craig.topper@gmail.com> Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
108126cfc6eddf1e0c9c7db39e25323403f04bbc 29-Nov-2011 Craig Topper <craig.topper@gmail.com> Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7f5e43f61d3b28a03537c29156b0bad7dd3476e4 23-Nov-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Fix PR11422.

This was a bug in keeping track of the available domains when merging
domain values.

The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.

Also add an assertion to catch future attempts at emitting AVX2
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
745a86bac9684f9617aeb0e1566194ca797a64d4 19-Nov-2011 Craig Topper <craig.topper@gmail.com> Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d9190c0f148b218ab046deadd0c7ae475414cde5 15-Nov-2011 Jay Foad <jay.foad@gmail.com> Remove some unnecessary includes of PseudoSourceValue.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
44ec9fddc22abeabaf2565691ed02b1f47f532af 15-Nov-2011 Craig Topper <craig.topper@gmail.com> Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4c077a1f04c97210793d62debef250b974d168bc 15-Nov-2011 Craig Topper <craig.topper@gmail.com> Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c2ecf3efbf375fc82bb1cea6afd7448498f9ae75 15-Nov-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Break false dependencies before partial register updates.

Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dcce244dd85ec410c2e0b8ac2b23320df3e3ece9 14-Nov-2011 Craig Topper <craig.topper@gmail.com> Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b80ada98c50df226e210eabc9547101c5dee2181 09-Nov-2011 Craig Topper <craig.topper@gmail.com> Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3e5d5c53a03e4a08cdb67f8a7f44567f925be9a5 07-Nov-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Expand V_SET0 to xorps by default.

The xorps instruction is smaller than pxor, so prefer that encoding.

The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ed744827041a97336461abdc91b43fd0eafb869c 08-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.

In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b66f18486a031ed00adc6a0376ee2239498db70d 07-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Constrain both operands on MOVZX32_NOREXrr8.

This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.

Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.

This fixes a miscompilation in 20040709-2 in the gcc test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
92fb79b7a611ab4c1043f04e8acd08f963d073ad 29-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Expand the x86 V_SET0* pseudos right after register allocation.

This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
98e933f9ad3cc2ede3a0a337144a504265d614cd 28-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.

I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4bd89873be74d7463676fde09ba6ea97a5b9d555 23-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Add support for GR32 <-> FR32 cross class copies.

We already support GR64 <-> VR128 copies. All of these copies break
partial register dependencies by zeroing the high part of the target
register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6b5b79c7e8aec3138727e102e85aaf1c3a01765e 16-Sep-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Add a fixme note!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b4e905d027beb83428b8e4cc40023fce1f647acd 16-Sep-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Add the remaining AVX versions of instructions to X86InstrInfo, this
time for describing high latency ones and for recognizting loads
from the same base pointer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cd2857ee67ba23b427c3671fd1d1e575543fa80a 15-Sep-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Factor out partial register update checks for some SSE instructions.
Also add the AVX versions and add comments!

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
484ddf54c9f9765e65c46ae435e0143d68d259e2 14-Sep-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Teach the foldable tables about 128-bit AVX instructions and make the
alignment check for 256-bit classes more strict. There're no testcases
but we catch more folding cases for AVX while running single and multi
sources in the llvm testsuite.

Since some 128-bit AVX instructions have different number of operands
than their SSE counterparts, they are placed in different tables.

256-bit AVX instructions should also be added in the table soon. And
there a few more 128-bit versions to handled, which should come in
the following commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cbf479df8abe5e208f1438092a9632a145551cbc 08-Sep-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0e59a048495c85bf5cae52a43019fcbbf1119210 03-Sep-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
it!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b8e052e123a1950adc180b89d8aba0df7765964f 03-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Check for EFLAGS live-out before clobbering it.

It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5affa5196f012dc5e4cf69bd8cd2d2f9aeb42e3f 31-Aug-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,
whenever AVX is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b02c0ace207333fb5c66ea6826531ed2f7cee532 11-Aug-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Cleanup: Remove Int_ CVTSS2SI* forms

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2df3f58a0b3937f2cbd76d3417d2905ca86cf8fa 08-Aug-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Hoist hasLoadFromStackSlot and hasStoreToStackSlot.

These the methods are target-independent since they simply scan the
memory operands. They can live in TargetInstrInfoImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
863bd9d5cf86e57752975d1ab6779f3116a23b90 26-Jul-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
This also fixes PR10452

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8c3fee59038d8fd98db2a01b6a309a8941a16a3f 25-Jul-2011 Evan Cheng <evan.cheng@apple.com> Refactor X86 target to separate MC code from Target code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dad38638e172a4c53caf1d9dac9b92228bd4be7a 22-Jul-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Fix PR10422 by adding the necessary AVX UCOMISD memory versions to
load folding logic

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
db125cfaf57cc83e7dd7453de2d509bc8efd0e5e 18-Jul-2011 Chris Lattner <sabre@nondot.org> land David Blaikie's patch to de-constify Type, with a few tweaks.



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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c60f9b752381baa6c4b80c0739034660f1748c84 14-Jul-2011 Evan Cheng <evan.cheng@apple.com> Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
62f67f86fea55562ef28650b87f73924855438fa 14-Jul-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Add 256-bit load/store recognition and matching in several places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4db3cffe94a5285239cc0056f939c6b74a5ca0b6 01-Jul-2011 Evan Cheng <evan.cheng@apple.com> Hide the call to InitMCInstrInfo into tblgen generated ctor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d5b03f252c0db6b49a242abab63d7c5a260fceae 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
22fee2dff4c43b551aefa44a96ca74fcade6bfac 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e837dead3c8dc3445ef6a0e2322179c57e264a13 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
15993f83a419950f06d2879d6701530ae6449317 27-Jun-2011 Evan Cheng <evan.cheng@apple.com> More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2fa82bc3da45d272f12a96a61074b637faa62e0b 23-Jun-2011 Evan Cheng <evan.cheng@apple.com> Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know about stack alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4509ec42b88e9220f61bca5654411e65368ac53a 12-Jun-2011 Rafael Espindola <rafael.espindola@gmail.com> AnalyzeBranch doesn't change which successors a bb has, just the order
we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
be5cbaa62727aa83b4076d39699e8be0c67bdb3a 10-Jun-2011 Eli Friedman <eli.friedman@gmail.com> PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6f19c67d8485ae8efe55e0527b3236b03af2c756 09-Jun-2011 Eli Friedman <eli.friedman@gmail.com> Revert 132789; it breaks tests. My mistake.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
aebc3c1610f7ee563120ba5db7ae064d77af56c4 09-Jun-2011 Eli Friedman <eli.friedman@gmail.com> Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.



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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1f9a09c61489a83360238032b6756395bd69b620 01-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Fix PR10059 and future variations by handling all register subclasses.

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
60045c233a4b88838242abdfb95992d7bf22710d 01-May-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> X86AsmPrinter doesn't know how to handle the X86II::MO_GOT_ABSOLUTE_ADDRESS flag
after folding ADD32ri to ADD32mi, so don't do that.

This only happens when the greedy register allocator gets itself in trouble and
spills %vreg9 here:

16L %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9
48L %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9

That should never happen, the live range should be split instead.

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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7a2bdde0a0eebcd2125055e0eacaca040f0b766c 15-Apr-2011 Chris Lattner <sabre@nondot.org> Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!



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/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f93f7b2446bec3febc30b7136e18704664bd98cc 13-Apr-2011 Bill Wendling <isanbard@gmail.com> Reapply r129401 with patch for clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f9b2dc66c87256b55f9bdfe037d1fa6f705200e8 13-Apr-2011 Bill Wendling <isanbard@gmail.com> Revert r129401 for now. Clang is using the old way of doing things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d5f323d70bd2d9bc8a63a68bfe439a69e0104bbf 13-Apr-2011 Bill Wendling <isanbard@gmail.com> Remove the unaligned load intrinsics in favor of using native unaligned loads.

Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.

First part of <rdar://problem/8460511>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e0ef509aeb47b396cf1bdc170ca4f468f799719f 05-Mar-2011 Andrew Trick <atrick@apple.com> Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.

Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.

Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7558e2e4153233289bc6841f6a85fd54035f293b 24-Feb-2011 Evan Cheng <evan.cheng@apple.com> Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory
operands starts at index 2, not 1.
rdar://9045024
PR9305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7754f85885f8a961cb403ef13ab39583492d2b1e 26-Jan-2011 NAKAMURA Takumi <geek4civic@gmail.com> Target/X86: Tweak win64's tailcall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e5fffe9c3fa402cb5d5167327783f82b86f52b8f 26-Jan-2011 NAKAMURA Takumi <geek4civic@gmail.com> Fix whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3c49706a61f5199fb1a6657834a3a71255466781 09-Dec-2010 Nate Begeman <natebegeman@mac.com> Add support for AVX to materialize +0.0 when doing scalar FP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cd775ceff0b25a0b026f643a7990c2924bd310a3 28-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move callee-saved regs spills / reloads to TFI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2312842de0c641107dd04d7e056d02491cc781ca 19-Oct-2010 Evan Cheng <evan.cheng@apple.com> Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
98694138025fdb0cec0cda5727201ad00ded3d63 19-Oct-2010 Daniel Dunbar <daniel@zuster.org> Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
11e8b74a7ae9ecd59b64180a59143e39bc3b9514 19-Oct-2010 Evan Cheng <evan.cheng@apple.com> - Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d0eeeeb5580622d8700fd1009bbf2465789303a8 12-Oct-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.

The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
15df55d8c238ddd4b595dc0d762fe4c391352f11 08-Oct-2010 Chris Lattner <sabre@nondot.org> reapply: Use the new TB_NOT_REVERSABLE flag instead of special
reapply: reimplement the second half of the or/add optimization. We should now

with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
99ae6659daaebeb32df91653fad09748fda8bcb2 08-Oct-2010 Chris Lattner <sabre@nondot.org> reapply the patch reverted in r116033:
"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b88b00ba2b7d7be2939c55193900cf4e465098c3 08-Oct-2010 Daniel Dunbar <daniel@zuster.org> Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
'add'", which seems to have broken just about everything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b38109fc2dfe3bf983b8b8a08b23d3194517c543 08-Oct-2010 Daniel Dunbar <daniel@zuster.org> Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
32f0cdba302d5f48401aadb9a2eb9e3efd9e6833 08-Oct-2010 Daniel Dunbar <daniel@zuster.org> Revert "reimplement the second half of the or/add optimization. We should now",
which depends on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cd3167b281f08e47a81438718122b6dd75a6316e 08-Oct-2010 Chris Lattner <sabre@nondot.org> reimplement the second half of the or/add optimization. We should now
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
05e27c5786d7ecde5d9c4b28e3632c14832cfb34 08-Oct-2010 Chris Lattner <sabre@nondot.org> Use the new TB_NOT_REVERSABLE flag instead of special
casing FsMOVAPDrr/FsMOVAPSrr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a2283761857d86a3a168705cef8108828d874876 08-Oct-2010 Chris Lattner <sabre@nondot.org> simplify some map operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
122e2ea043918c77ebdd8936875f14282503d60f 08-Oct-2010 Chris Lattner <sabre@nondot.org> Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).

While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.

This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20

the add r/i cases are coming next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
45a1cb26a3b92c3c1bec0db9d67449c17b43c8fd 08-Oct-2010 Chris Lattner <sabre@nondot.org> Reduce casting in various tables by defining the table
with the right types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
afcd543a55c8cc6859443d9a63d52d9e8615770c 08-Oct-2010 Chris Lattner <sabre@nondot.org> simplify code: don't build up vector only to assert it is empty.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
635127a8c615820b88ba181b92f5ce93a3ab9eab 07-Oct-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Constrain the offset register to a *_NOSP register class when inserting LEA
instructions.

This unbreaks the machine code verifier and fixes PR8317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
25cbf504fe803a0b57e877c6f83aed5aa48e7ec7 06-Oct-2010 Chris Lattner <sabre@nondot.org> Use #NAME# to have the CMOV multiclass define things with the same names as before
(e.g. CMOVBE16rr instead of CMOVBErr16).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d350e4757e649dce07f7492115bd9d19c71426bf 06-Oct-2010 Chris Lattner <sabre@nondot.org> switch CMOVBE to the multipattern:
21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b2ef4c1235c846c2503d0796541f4255ef1e13f5 29-Sep-2010 Chris Lattner <sabre@nondot.org> add basic avx support to the disassembler, also teach it about ssmem/sdmem
operands.

With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bf6018ac5a4ce8db0f0719aa666cd81f0904431a 29-Sep-2010 Chris Lattner <sabre@nondot.org> add asmparser support for cvttpd2dq by removing some Int_ prefixes.

Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0c04e4f58f8d1ad4604de17324170fa1f4e43418 29-Sep-2010 Chris Lattner <sabre@nondot.org> implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bc57c6db4a3a1f5df4450d8dbb100e1eb6944c28 22-Sep-2010 Chris Lattner <sabre@nondot.org> fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
Teaching the code generator about CR8-15, how to rex them up, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d8c0a51362cfb7d08bec20e2341f8cc73561526a 17-Sep-2010 Dan Gohman <gohman@apple.com> Avoid emitting a PIC base register if no PIC addresses are needed.
This fixes rdar://8396318.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c52bedba5489aedad7013067ae1fd5b49b5fe525 27-Aug-2010 Anton Korobeynikov <asl@math.spbu.ru> Properly handle passing of FP stuff to varargs function on Win64:
value should be copied to the corresponding shadow reg as well.
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5dad73cec84d24a237c2c0444768cc7c492497d4 17-Aug-2010 Anton Korobeynikov <asl@math.spbu.ru> Revert part of one of the prev. patches - tailjmp will follow later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e9df15e65c28f13287c7fe69f0c5dafe2e8fa48b 17-Aug-2010 Anton Korobeynikov <asl@math.spbu.ru> Enable more win64 calls folding opportunities.
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
642eb02045708d955c8104ad14f46ce5101df2d4 12-Aug-2010 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4d043628133ef7f762b3c18025c2eff144fb8072 12-Aug-2010 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Fix comment order

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d29583bd32eb3e918b797849f55c0ad2667396c4 12-Aug-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.
When a register is defined by a partial load:

%reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
90c579de5a383cee278acc3f7e7b9d0a656e6a35 06-Aug-2010 Owen Anderson <resistor@mac.com> Reapply r110396, with fixes to appease the Linux buildbot gods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1f74590e9d1b9cf0f1f81a156efea73f76546e05 06-Aug-2010 Owen Anderson <resistor@mac.com> Revert r110396 to fix buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9ccaf53ada99c63737547c0235baeb8454b04e80 06-Aug-2010 Owen Anderson <resistor@mac.com> Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b2eeed7464e3492833bb7a495e78a9f031621653 29-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Revert r109652, and remove the offending assert in loadRegFromStackSlot instead.

We do sometimes load from a too small stack slot when dealing with x86 arguments
(varargs and smaller-than-32-bit args). It looks like we know what we are doing
in those cases, so I am going to remove the assert instead of artifically
enlarging stack slot sizes.

The assert in storeRegToStackSlot stays in. We don't want to write beyond the
bounds of a stack slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
81c7b19f0494b3995a564778f666025495033d86 27-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> The isLoadFromStackSlot and isStoreToStackSlot have no way of reporting
subregister operands like this:

%reg1040:sub_32bit<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0, %reg1040<imp-def>; mem:LD4[FixedStack-2](align=8)

Make them return false when subreg operands are present. VirtRegRewriter is
making bad assumptions otherwise.

This fixes PR7713.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
516cd4575ef52bb8e648f04a18556d1906d9f84c 27-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Add assertions that expose the PR7713 miscompilation: Accessing a stack slot
with a too-big register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
134d8eec8789184c7a7290ee101ca3d6f62f384a 22-Jul-2010 Chris Lattner <sabre@nondot.org> remove the JIT "NeedsExactSize" feature and supporting logic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
456fdaf0cea4bd195eacc9796fedb71b62290cfe 22-Jul-2010 Chris Lattner <sabre@nondot.org> instead of migrating it to the MC instruction encoder, just
rip out the implementation of X86InstrInfo::GetInstSizeInBytes.
The code being ripped out just implemented a copy and hacked up
version of the (old) instruction encoder, and is buggy and
terrible in other ways. Since "GetInstSizeInBytes" is really
only there to support the JIT's "NeedsExactSize" hook (which
noone is using), just rip out the code. I will rip out the
NeedsExactSize hook next.

This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fcbd1a749f9db4bf144a3343c4d707e1de087a7e 22-Jul-2010 Rafael Espindola <rafael.espindola@gmail.com> Fixes win64. It was broken by a previous patch where I missed the !isWin64
and then forced every register to be a vr128 on win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c8ea673bc0e19f36738bec998fe27fad01bf9749 21-Jul-2010 Nate Begeman <natebegeman@mac.com> Fix a couple issues with Win64 ABI

1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing

Still to look into:

xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
78e6e009223a38739797629ca2d217acf86dda93 17-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the isMoveInstr() hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 17-Jul-2010 Bill Wendling <isanbard@gmail.com> Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
468a2a44e2a2efb5a2cd441205fc78b80edd3844 16-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill
pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ed42f1e58f1a7a83bdbb4429c716424a1c1583ee 12-Jul-2010 Dan Gohman <gohman@apple.com> Check begin!=end, rather than !begin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5a717a3ae77e66bcd092de04da156030bd18a9ce 12-Jul-2010 Rafael Espindola <rafael.espindola@gmail.com> Convert getLoadStoreRegOpcode to use a switch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0bfd09201efdbba5fb70039ebf1c8aefc673cde1 12-Jul-2010 Rafael Espindola <rafael.espindola@gmail.com> Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to
getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108115 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4ea8771535f16480c40481749397955190787554 11-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2b336bc4fed0812db24ead970f4d1ac0562af563 10-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.

Based on a patch by Rafael Espíndola.

Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.

We support:

FpSET_ST0
INLINEASM

FpSET_ST0
FpSET_ST1
INLINEASM

with and without kills on the arguments. We don't support:

FpSET_ST1
FpSET_ST0
INLINEASM

nor

FpSET_ST1
INLINEASM

Just Don't Do It!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
84023e0fbefc406a4c611d3d64a10df5d3a97dd7 10-Jul-2010 Dan Gohman <gohman@apple.com> Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
61905c8ab3afd7b2806a49d38731dc94f1dc70e5 09-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remember the *_TC opcodes for load/store

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1f32340d95ac480bfc74bcfd00fd5cffbe078652 09-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Automatically fold COPY instructions into stack load/store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9c50e8b89076eacf8eb588449d5425cb9a755e9e 09-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Fix a few tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e86b01c153ba52307ecb6e7513ec33f57caedfdd 09-Jul-2010 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Start the support for AVX instructions with 256-bit %ymm registers. A couple of
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
599b531a960833719f607d66c97871f1f5ad12c0 09-Jul-2010 Chris Lattner <sabre@nondot.org> Change LEA to have 5 operands for its memory operand, just
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ac0ed5dc082dff9ce359af5422f5b82047b4fe6b 09-Jul-2010 Chris Lattner <sabre@nondot.org> add some long-overdue enums to refer to the parts of the 5-operand
X86 memory operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
61c8eccf24eb2368decfc669780c090fa1f25548 09-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remember the VR64 register class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
320bdcbfe2691021702085f718db1617b1d4df49 08-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Implement X86InstrInfo::copyPhysReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0bc25f40402f48ba42fc45403f635b20d90fabb3 08-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Convert EXTRACT_SUBREG to COPY when emitting machine instrs.

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5c00e077952d14899c3fc26709c7b2dfd36d0209 08-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove references to INSERT_SUBREG after de-SSA.

Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5febd075df156408d97cc9737428b66b0aaa5129 08-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> fix copies to/from GR8_ABCD_H even more

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f2e4afd96c9d26ff0dd2fb5eca0a94207d2a8fb4 07-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Allow copies between GR8_ABCD_L and GR8_ABCD_H.

This fixes PR7540.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
98ec91ea80e042907aac8d3cbd9614d29f6cba45 02-Jul-2010 Evan Cheng <evan.cheng@apple.com> - Two-address pass should not assume unfolding is always successful.
- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
19d8597bca73f5983ae6952de1c42d8261857ea2 23-Jun-2010 Bill Wendling <isanbard@gmail.com> Fix the formatting of the switch statement and add a missing break.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c2b3e00cdf0b87bc3f5499a6fd5a2c3935dd952e 21-Jun-2010 Rafael Espindola <rafael.espindola@gmail.com> Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.

I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f0efafa61e2002b1b21df23376687eb14252a355 21-Jun-2010 Rafael Espindola <rafael.espindola@gmail.com> wip

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3bf912593301152b65accb9d9c37a95172f1df5a 18-Jun-2010 Stuart Hastings <stuart@apple.com> Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
21d238fdbacd2be880712202eab03c7e42fe769c 12-Jun-2010 Rafael Espindola <rafael.espindola@gmail.com> Merge getStoreRegOpcode and getLoadRegOpcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9edf7deb37f0f97664f279040fa15d89f32e23d9 03-Jun-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

%reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

%reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
42d075c4fb21995265961501cec9ff6e3fb497ce 02-Jun-2010 Rafael Espindola <rafael.espindola@gmail.com> Remove the TargetRegisterClass member from CalleeSavedInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
22c0e97c567dd15c819906035d15c745100e75bc 25-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Use enums instead of literals for X86 subregisters.

The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3458e9e4dfc8689179a74e954aad78d3a4b564ff 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Rename X86 subregister indices to something shorter.
Use the tablegen-produced enums.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
73ea7bf4509663267317ec3911aac00ca35a2f2c 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Add the SubRegIndex TableGen class.

This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2457f2c66184e978d4ed8fa9e2128effff26cb0b 22-May-2010 Evan Cheng <evan.cheng@apple.com> Implement @llvm.returnaddress. rdar://8015977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e5e4ff974df52aa870085904b6670c4d22ada0ac 20-May-2010 Dan Gohman <gohman@apple.com> Fix assembly parsing and encoding of the pushf and popf family of
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f8c1ef0510801867ffcdd055d4ee361d3ad6ea40 18-May-2010 Dan Gohman <gohman@apple.com> Teach mode load folding and unfolding code about CMP32ri8 and friends.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e5efbafdac9cbaaa9cac8a5c405c3bbcbf3f328d 18-May-2010 Dan Gohman <gohman@apple.com> When converting a test to a cmp to fold a load, use the cmp that has an
8-bit immediate field rather than one with a wider immediate field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0d881042c09b2b57c3ad4128577a99e57d45b5ae 07-May-2010 Dan Gohman <gohman@apple.com> When rematerializing, use the debug location of the original
instruction, rather than a location near where the new instruction
is being inserted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 06-May-2010 Dan Gohman <gohman@apple.com> Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
746ad69e088176819981b4b2c5ac8dcd49f5e60e 06-May-2010 Evan Cheng <evan.cheng@apple.com> Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8601a3d4decff0a380e059b037dabf71075497d3 29-Apr-2010 Evan Cheng <evan.cheng@apple.com> Frame index can be negative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ee9eb411fffddbb8fe70418c05946a131889b487 27-Apr-2010 Chris Lattner <sabre@nondot.org> on darwin empty functions need to codegen into something of non-zero length,
otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fc4d530ad66585e6d66e3d2b9f25f6f70e8c0db8 26-Apr-2010 Evan Cheng <evan.cheng@apple.com> Remove a redundant comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
962021bc7f6721c20c7dfe8ca809e2d98b1c554a 26-Apr-2010 Evan Cheng <evan.cheng@apple.com> - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
46510a73e977273ec67747eb34cbdb43f815e451 15-Apr-2010 Dan Gohman <gohman@apple.com> Add const qualifiers to CodeGen's use of LLVM IR constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fc5a03e46918baf72aef42687d4d31de2399a960 13-Apr-2010 Evan Cheng <evan.cheng@apple.com> Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
97e6992e3ecfd354a53142f0488769b399242295 13-Apr-2010 Eric Christopher <echristo@apple.com> Temporarily revert r101075, it's causing invalid iterator assertions
in a nightly tester.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2aae6ae57249de3de4de5d2f688b6e7cecae13f6 13-Apr-2010 Bill Wendling <isanbard@gmail.com> Micro-optimization:

If we have this situation:

jCC L1
jmp L2
L1:
...
L2:
...

We can get a small performance boost by emitting this instead:

jnCC L2
L1:
...
L2:
...

This testcase shows an example of this:

float func(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
75361b69f3f327842b9dad69fa7f28ae3b688412 08-Apr-2010 Chris Lattner <sabre@nondot.org> rename llvm::llvm_report_error -> llvm::report_fatal_error



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
375be7730a6f3dee7a6dc319ee6c355a11ac99ad 07-Apr-2010 Dale Johannesen <dalej@apple.com> Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fc8e1c36352b9dbd578d54c338b63f1354d184f8 06-Apr-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Properly enable load clustering.

Operand 2 on a load instruction does not have to be a RegisterSDNode for this to
work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c7f3ace20c325521c68335a1689645b43b06ddf0 02-Apr-2010 Chris Lattner <sabre@nondot.org> use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
93d6a7e9c21204c52d6efec6c672163e7de79660 02-Apr-2010 Dale Johannesen <dalej@apple.com> Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d363b4ebc7a98483437a5a88aba01dd9facdcd01 31-Mar-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Replace V_SET0 with variants for each SSE execution domain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
357be7f28940d45822dae8dfb1502348aa8ae425 31-Mar-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Renumber SSE execution domains for better code size.

SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8258d0b4bfd5fe40c29fa19e24c23ba3ac157e23 30-Mar-2010 Eric Christopher <echristo@apple.com> Remove the pmulld intrinsic and autoupdate it as a vector multiply.

Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e4b94b4efb9a4670f25a5a80dd3b97f9583de202 30-Mar-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Basic implementation of SSEDomainFix pass.

Cross-block inference is primitive and wrong, but the pass is working otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
352aa503faee6c58e9cdb5054cc5ec1d90c696b4 25-Mar-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.

On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.

The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.

This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.

The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fe4b92baf11785bf0bfc26b256ca841c9848f77a 24-Mar-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings."

This reverts commit 99345. It was breaking buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c75c5fa12582956fc6b7d7d756b2bdd49fa61f71 24-Mar-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.

This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8d1f0dd983a29d4e8d6c840085538fc9ba7427a1 23-Mar-2010 Evan Cheng <evan.cheng@apple.com> Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f48ef0365545b6160836e3f4b4a210d1e21f1881 14-Mar-2010 Evan Cheng <evan.cheng@apple.com> Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
81d0c36d22142da8413f8b2483582df70968ecb3 09-Mar-2010 Dan Gohman <gohman@apple.com> Don't try to fold V_SET0 and V_SETALLONES to loads in medium and
large code models.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
18ce64e069211c0da39351d7f436c6a431bca2b7 05-Mar-2010 Bill Wendling <isanbard@gmail.com> Revert r97766. It's deleting a tag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
37b52ee6d9141293c9aef0d2a4c753300a687536 05-Mar-2010 Bill Wendling <isanbard@gmail.com> Micro-optimization:

This code:

float floatingPointComparison(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}

produces this:

_floatingPointComparison:
0000000000000000 cvtss2sd %xmm1,%xmm1
0000000000000004 cvtss2sd %xmm0,%xmm0
0000000000000008 mulsd %xmm1,%xmm0
000000000000000c pxor %xmm1,%xmm1
0000000000000010 ucomisd %xmm1,%xmm0
0000000000000014 jne 0x00000004
0000000000000016 jp 0x00000002
0000000000000018 jmp 0x00000008
000000000000001a addsd 0x00000006(%rip),%xmm0
0000000000000022 cvtsd2ss %xmm0,%xmm0
0000000000000026 ret

The "jne/jp/jmp" sequence can be reduced to this instead:

_floatingPointComparison:
0000000000000000 cvtss2sd %xmm1,%xmm1
0000000000000004 cvtss2sd %xmm0,%xmm0
0000000000000008 mulsd %xmm1,%xmm0
000000000000000c pxor %xmm1,%xmm1
0000000000000010 ucomisd %xmm1,%xmm0
0000000000000014 jp 0x00000002
0000000000000016 je 0x00000008
0000000000000018 addsd 0x00000006(%rip),%xmm0
0000000000000020 cvtsd2ss %xmm0,%xmm0
0000000000000024 ret

for a savings of 2 bytes.

This xform can happen when we recognize that jne and jp jump to the same "true"
MBB, the unconditional jump would jump to the "false" MBB, and the "true" branch
is the fall-through MBB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
874cadaf210d4ab05eadc64a41228df0f5078eb7 28-Feb-2010 Dan Gohman <gohman@apple.com> Implement XMM subregs.

Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6fe0df2abb9269d4c8377f2497281abc88baf543 26-Feb-2010 Dan Gohman <gohman@apple.com> movl is a cheaper way to materialize 0 without clobbering EFLAGS than movabsq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b4e8aabba764bcbaf4be1296ba9b7e437f98adb7 22-Feb-2010 Dan Gohman <gohman@apple.com> Fix a typo in a comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0d8db8e0a8492ab2d4bef725ec61b519471b97ec 12-Feb-2010 Chris Lattner <sabre@nondot.org> add a bunch of mod/rm encoding types for fixed mod/rm bytes.
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bd13fb62541136a4891d702feec8b7aba5bf695a 11-Feb-2010 Chris Lattner <sabre@nondot.org> refactor the conditional jump instructions in the .td file to
use a multipattern that generates both the 1-byte and 4-byte
versions from the same defm


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
518bb53485df640d7b7e3f6b0544099020c42aa7 09-Feb-2010 Chris Lattner <sabre@nondot.org> move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
39a612e6f9e63806af410a0ab0d81895391e4c79 05-Feb-2010 Chris Lattner <sabre@nondot.org> port X86InstrInfo::determineREX over to the new encoder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
74a2151392a08e202f497ece7a3129663526d431 05-Feb-2010 Chris Lattner <sabre@nondot.org> move functions for decoding X86II values into the X86II namespace.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a3a0db01217efc6403d90eec2a6ceb919f5031bc 05-Feb-2010 Chris Lattner <sabre@nondot.org> change getSizeOfImm and getBaseOpcodeFor to just take
TSFlags directly instead of a TargetInstrDesc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6ec25f570f8e6d216769c76411267618b5f4c61a 26-Jan-2010 Dale Johannesen <dalej@apple.com> use findDebugLoc in more places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
afc36739cda2bd95ce2856ad90583d0c8bfc20f9 23-Jan-2010 Evan Cheng <evan.cheng@apple.com> Be more conservative with clustering f32 / f64 loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
96dc115ef3ee019cb91d7c112358a77536c38a53 22-Jan-2010 Evan Cheng <evan.cheng@apple.com> Add two target hooks to determine whether two loads are near and should be scheduled together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
94da721d8c0f93cb565e6a7cc48ddd15e69c20a9 21-Jan-2010 Evan Cheng <evan.cheng@apple.com> Fix a minor issue in x86 load / store folding table. movups does an unaligned load so it doesn't require 16-byte alignment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
73e884bb3e971b1e794ba2501df15138f73b8b1a 20-Jan-2010 Dale Johannesen <dalej@apple.com> make findDebugLoc a class method



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
918f0f0beab7401172b0b17aeb04e8d757e97a10 20-Jan-2010 Dale Johannesen <dalej@apple.com> Move findDebugLoc somewhere more central. Fix
more cases where debug declarations affect
debug line info.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3 19-Jan-2010 Jim Grosbach <grosbach@apple.com> For aligned load/store instructions, it's only required to know whether a
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
57d1d936fc41c3482047c9d18dbaa27625df5768 13-Jan-2010 Evan Cheng <evan.cheng@apple.com> For now, avoid issuing extract_subreg to reuse lower 8-bit, it's not safe in 32-bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7da9ecf9677b751d81515f95168ae3cb2df54160 13-Jan-2010 Evan Cheng <evan.cheng@apple.com> Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.

For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f1b4d26e674a067b9f5c8622ad79c95d1e094046 12-Jan-2010 Dan Gohman <gohman@apple.com> Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2 12-Jan-2010 Evan Cheng <evan.cheng@apple.com> Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified
instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
05920b8146558f5e3141a886cd2a00281b10222a 11-Jan-2010 Evan Cheng <evan.cheng@apple.com> Revert 93158. It's breaking quite a few x86_64 tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
71c25b7d7bdf9b49dd70965c7486ce930b846aac 11-Jan-2010 Dan Gohman <gohman@apple.com> Re-instate MOV64r0 and MOV16r0, with adjustments to work with the
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5b90132332b36426fea95c49ba58e735e7fab0b3 05-Jan-2010 David Greene <greened@obbligato.org> Change errs() to dbgs().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c41b638d4a8baab3034f737198e63280fa4f2610 28-Dec-2009 Bill Wendling <isanbard@gmail.com> Remove dead variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9e3238303c2f3d3936828705b23b3efc0e3b1321 23-Dec-2009 Chris Lattner <sabre@nondot.org> completely eliminate the MOV16r0 'instruction'. The only
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b1f49813334278094b1ecd7ad920f5c276f7b3e6 22-Dec-2009 Evan Cheng <evan.cheng@apple.com> Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
400073d5467b79534d8c63b0d996a55e4252ff4b 18-Dec-2009 Evan Cheng <evan.cheng@apple.com> On recent Intel u-arch's, folding loads into some unary SSE instructions can
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
108934c65d4cba18f08ed4fab0cae506c20fd212 18-Dec-2009 Sean Callanan <scallanan@apple.com> Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
Removed tabs and fixed 80-line violations

* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
85de1e5bade2f3755e47ed6fd43c92fcf99ff08b 14-Dec-2009 Bill Wendling <isanbard@gmail.com> Whitespace changes, comment clarification. No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dd99f3a7dc42eb7fb97e22323514027967bc5403 12-Dec-2009 Evan Cheng <evan.cheng@apple.com> Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
04ab19cb1486725de7f201dddf596137b112c17e 12-Dec-2009 Evan Cheng <evan.cheng@apple.com> Add comment about potential partial register stall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
656e51454ac70f5d500565fd33c883f6dea549f2 11-Dec-2009 Evan Cheng <evan.cheng@apple.com> Add support to 3-addressify 16-bit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
864e2efce2cb5d02e376933933d96074723fe77c 05-Dec-2009 Dan Gohman <gohman@apple.com> Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
adbc23cae1d90d5bffd53331fb9c69505c23be97 05-Dec-2009 David Greene <greened@obbligato.org> Remove an unneeded include.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
29dbf50b180bb3342af84ff042a3ff06405c5071 04-Dec-2009 David Greene <greened@obbligato.org> Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7896c9f436a4eda5ec15e882a7505ba482a2fcd0 03-Dec-2009 Chris Lattner <sabre@nondot.org> improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
735afe14eea8049bf69210ce8a3512e391fc643f 24-Nov-2009 Dan Gohman <gohman@apple.com> Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d15ac2fce3961cf40a10ef379efdb7bc915f016b 17-Nov-2009 Evan Cheng <evan.cheng@apple.com> Re-apply 89011. It's not to be blamed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6db07eac953403c8218432300a9f4fb7afe3ba53 17-Nov-2009 Evan Cheng <evan.cheng@apple.com> Revert 89011. Buildbot thinks it might be breaking stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
574186f8adce4064b206dad5e139211e06688308 17-Nov-2009 Evan Cheng <evan.cheng@apple.com> A few more instructions that should be marked re-materializable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
600c04369775b014073ec295545ff9dd2a7f2fed 16-Nov-2009 Evan Cheng <evan.cheng@apple.com> - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots.
- Mark MOVUPSrm re-materializable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d57cdd5683ea926e489067364fb7ffe5fd5d35ee 14-Nov-2009 Evan Cheng <evan.cheng@apple.com> - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dda3978d7877d2d60390833c73ed24857295e89c 13-Nov-2009 David Greene <greened@obbligato.org> Fix a bootstrap failure.

Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE
interfaces to explicitly request checking for post-frame ptr elimination
operands. This uses a heuristic so it isn't reliable for correctness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b87bc95db075dae3033a3c541b55b4cb711c332c 12-Nov-2009 David Greene <greened@obbligato.org> Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a
machine instruction loads or stores from/to a stack slot. Unlike
isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be
something other than a pure load/store (e.g. it may be an arithmetic
operation with a memory operand). This helps AsmPrinter determine when
to print a spill/reload comment.

This is only a hint since we may not be able to figure this out in all
cases. As such, it should not be relied upon for correctness.

Implement for X86. Return false by default for other architectures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
81cf4325698b48b02eddab921ac333c7f25005c3 10-Nov-2009 Jeffrey Yasskin <jyasskin@google.com> Fix DenseMap iterator constness.

This patch forbids implicit conversion of DenseMap::const_iterator to
DenseMap::iterator which was possible because DenseMapIterator inherited
(publicly) from DenseMapConstIterator. Conversion the other way around is now
allowed as one may expect.

The template DenseMapConstIterator is removed and the template parameter
IsConst which specifies whether the iterator is constant is added to
DenseMapIterator.

Actually IsConst parameter is not necessary since the constness can be
determined from KeyT but this is not relevant to the fix and can be addressed
later.

Patch by Victor Zverovich!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0115e164bad632572e2cfbaf72f0f0882d5319de 30-Oct-2009 Dan Gohman <gohman@apple.com> Fix MachineLICM to use the correct virtual register class when
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1b1764b3f7edd26a90991993255536dd7417a5c6 14-Oct-2009 Dan Gohman <gohman@apple.com> Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards
(for uses marked kill and defs marked dead) a few instructions in
addition to forwards. Also, increase the maximum number of instructions
to scan, as it appears to help in a fair number of cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4e6f7a0179d137a63da02e1f6a1db13ec4fa9543 10-Oct-2009 Dan Gohman <gohman@apple.com> Remove a no-longer-necessary #include.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3731bc026cc6c4fb7deb7ac67e2c3be0c22498be 10-Oct-2009 Dan Gohman <gohman@apple.com> Replace X86's CanRematLoadWithDispOperand by calling the target-independent
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
91e69c37153eb7d8cd149d9c2484c3115027b90f 09-Oct-2009 Dan Gohman <gohman@apple.com> Add basic infrastructure and x86 support for preserving MachineMemOperand
information when unfolding memory references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e33f44cfc547359bc28526e4c5e1852b600b4448 07-Oct-2009 Dan Gohman <gohman@apple.com> Replace TargetInstrInfo::isInvariantLoad and its target-specific
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
26207e5bf1123a793bd9b38bcda2f569a6b45ef2 28-Sep-2009 Jakob Stoklund Olesen <stoklund@2pi.dk> Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c76909abfec876c6b751d693ebd3df07df686aa0 25-Sep-2009 Dan Gohman <gohman@apple.com> Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
602b0c8c17f458d2c80f2deb3c8e554d516ee316 25-Sep-2009 Dan Gohman <gohman@apple.com> Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
00133a7d52f32ab9c9ac53e964a5cc68fc626b4d 23-Sep-2009 Dan Gohman <gohman@apple.com> Fix X86's unfoldMemoryOperand to properly handle MachineMemOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4a0b3e170dcf591b0795170f6744d3a17858ee56 21-Sep-2009 Dan Gohman <gohman@apple.com> Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool
loads in order to reduce register pressure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
879caeadf3d5c60a3f5f8cb3262adb8d51c2b4a0 11-Sep-2009 Evan Cheng <evan.cheng@apple.com> Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9cef48eae9a4776ef2f42687072e7c61cb33e10d 11-Sep-2009 Evan Cheng <evan.cheng@apple.com> It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not
safe. This can happen we a subreg_to_reg 0 has been coalesced. One
exception is when the instruction that folds the load is a move, then we
can simply turn it into a 32-bit load from the stack slot.

rdar://7170444


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
31e2c7b4c13c2f31774614b1124533628958d0cd 02-Sep-2009 Daniel Dunbar <daniel@zuster.org> Remove Offset from ExternalSybmol MachineOperands, this is unused (and at least partly unsupported, in X86 encoding at least).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6f9bb6f31b37380fa9c4412b400b53eba65b7410 28-Aug-2009 Anton Korobeynikov <asl@math.spbu.ru> Short-term workaround for frame-related weirdness on win64.
Some other minor win64 fixes as well.

Patch by Michael Beck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
705e07f578e2b3af47ddab610feb4e7f2d3063a5 23-Aug-2009 Chris Lattner <sabre@nondot.org> remove various std::ostream version of printing methods from
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
af76e592c7f9deff0e55c13dbb4a34f07f1c7f64 22-Aug-2009 Chris Lattner <sabre@nondot.org> Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
24f20e083280d979e8fa1bc88959ae9e8339ee99 22-Aug-2009 Devang Patel <dpatel@apple.com> Record variable debug info at ISel time directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1d0be15f89cb5056e20e2d24faa8d6afb1573bca 13-Aug-2009 Owen Anderson <resistor@mac.com> Push LLVMContexts through the IntegerType APIs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
825b72b0571821bf2d378749f69d6c4cfb52d2f9 11-Aug-2009 Owen Anderson <resistor@mac.com> Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3108222c2cb3e61097396274b1c3ae0a86625975 11-Aug-2009 Dan Gohman <gohman@apple.com> Simplify this code. The case where one class is GR64RegClass and the
other is a subclass of it is effectively handled by the prior tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e50ed30282bb5b4a9ed952580523f2dda16215ac 11-Aug-2009 Owen Anderson <resistor@mac.com> Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b4dc13cab7ef894d3bb17657fa993b9f09af476b 08-Aug-2009 Eric Christopher <echristo@apple.com> Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
59e34921a514502ce4e926eeb417d7afd43708dd 06-Aug-2009 Dan Gohman <gohman@apple.com> Use GR32 for copies between GR32_NOSP and GR32_NOREX, as neither
is a subset of the other, but both are subsets of GR32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
be0cf7dbc2d230e10f6eec92fb2219ce69a925cc 05-Aug-2009 Dan Gohman <gohman@apple.com> hasSuperClass tests for a strict superset relation, rather than
a superset relation. This code wants to test the regular superset
relation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d90183d25dcbc0eabde56319fed4e8d6ace2e6eb 02-Aug-2009 Chris Lattner <sabre@nondot.org> Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a7235ea7245028a0723e8ab7fd011386b3900777 31-Jul-2009 Owen Anderson <resistor@mac.com> Move a few more APIs back to 2.5 forms. The only remaining ones left to change back are
metadata related, which I'm waiting on to avoid conflicting with Devang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a4714e025de720d0fcbaa78ab6c12dc789599233 30-Jul-2009 Dan Gohman <gohman@apple.com> Add a new register class to describe operands that can't be SP,
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cb778a8634454c70d88955b3732f330a6cbe5b07 29-Jul-2009 Chris Lattner <sabre@nondot.org> 1. Introduce a new TargetOperandInfo::getRegClass() helper method
and convert code to using it, instead of having lots of things
poke the isLookupPtrRegClass() method directly.

2. Make PointerLikeRegClass contain a 'kind' int, and store it in
the existing regclass field of TargetOperandInfo when the
isLookupPtrRegClass() predicate is set. Make getRegClass pass
this into TargetRegisterInfo::getPointerRegClass(), allowing
targets to have multiple ptr_rc things.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e922c0201916e0b980ab3cfe91e1413e68d55647 22-Jul-2009 Owen Anderson <resistor@mac.com> Get rid of the Pass+Context magic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
93e55deebacb29291fc4314eb3ddb704071b98b2 16-Jul-2009 Jakob Stoklund Olesen <stoklund@2pi.dk> Silence warning in Linux builds:

X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2b48ab947cbc3a448f84062da9e1f1a4e27ad220 16-Jul-2009 Evan Cheng <evan.cheng@apple.com> With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
378445303b10b092a898a75131141a8259cff50b 16-Jul-2009 Evan Cheng <evan.cheng@apple.com> Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f9b36f08efbc66670910a8a85dd89f03d36196d4 15-Jul-2009 Evan Cheng <evan.cheng@apple.com> Move load / store folding alignment require into the table(s).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9ac7542bab447299fc5d67c756e75e44502fc87e 14-Jul-2009 Chris Lattner <sabre@nondot.org> reapply r75408, which eliminates MOV64r0 in favor of using
MOV32r0 + subregs to do the same thing. This should work now
that PR4544 is fixed. Thanks Evan!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c23197a26f34f559ea9797de51e187087c039c42 14-Jul-2009 Torok Edwin <edwintorok@gmail.com> llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
73c6b7127aff4499e4d6a2edb219685aee178ee1 13-Jul-2009 Owen Anderson <resistor@mac.com> Move more functionality over to LLVMContext.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0a5372ed3e8cda10d724feda3c1a1c998db05ca0 13-Jul-2009 Owen Anderson <resistor@mac.com> Begin the painful process of tearing apart the rat'ss nest that is Constants.cpp and ConstantFold.cpp.
This involves temporarily hard wiring some parts to use the global context. This isn't ideal, but it's
the only way I could figure out to make this process vaguely incremental.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
69600cae95b93dd8e3fc869a630b007f1c648d43 12-Jul-2009 Bill Wendling <isanbard@gmail.com> Temporarily revert r75408. It appears to break the Apple-style builds:

x86_64-apple-darwin10-gcc -c -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Wold-style-definition -Wmissing-format-attribute -mdynamic-no-pic -DHAVE_CONFIG_H -I. -I. -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/. -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../include -I./../intl -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libcpp/include -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~obj/src/include -DENABLE_LLVM -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -DLLVM_VERSION_INFO='"9999"' -DBUILD_LLVM_APPLE_STYLE /Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/tree-ssa-alias.c -o tree-ssa-alias.o
/var/tmp//ccJQ2JBT.s:4134:Incorrect register `%rcx' used with `l' suffix
make[2]: *** [tree-ssa-live.o] Error 1
make[2]: *** Waiting for unfinished jobs....



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a6d16ae432f7ca11e888b216bde08d0097bcf441 12-Jul-2009 Chris Lattner <sabre@nondot.org> eliminate MOV64r0 in favor of a Pat<> pattern. This is only nontrivial because
the div lowering code explicitly references it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c25e7581b9b8088910da31702d4ca21c4734c6d7 11-Jul-2009 Torok Edwin <edwintorok@gmail.com> assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
19a2011194399849ecdf1499c7615e8276a8e68c 10-Jul-2009 Evan Cheng <evan.cheng@apple.com> Undo my brain cramp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
84853a17a3f79f37277f6b67ac9f5468ea6d8438 10-Jul-2009 Chris Lattner <sabre@nondot.org> some minor simplifications.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
49ddb61612725f9910146b2b85565242d91c821e 10-Jul-2009 Evan Cheng <evan.cheng@apple.com> CMOVxx doesn't swap operands which it's commuted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3b6b36d6f54e780a2947cb1b9efe4eed7c40dc11 10-Jul-2009 Chris Lattner <sabre@nondot.org> change isGlobalStubReference to take target flags instead of a MachineOperand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
07406346ebbf8a958a956eb05c1e04faedfe1e63 10-Jul-2009 Chris Lattner <sabre@nondot.org> convert some late code (called by regalloc and code emission)
to use isGlobalStubReference instead of GVRequiresExtraLoad
(which should really be part of isel).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ed0dca6a5dfa26e63c5636eb092640159182df89 10-Jul-2009 Chris Lattner <sabre@nondot.org> GVRequiresExtraLoad is now never used for calls, simplify it based on this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
910139f9ca53fc20a680d51ae61bb1e072095141 09-Jul-2009 Evan Cheng <evan.cheng@apple.com> Targets sometimes assign fixed stack object to spill certain callee-saved
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
15a380a03567deba90c074a2cd5a45b81ae0958b 09-Jul-2009 Chris Lattner <sabre@nondot.org> simplify some code based on the fact that picstyles != none are only valid
in pic or dynamic-no-pic mode. Also, x86-64 never used picstylegot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ab7c09b6b6f4516a631fd6788918c237c83939af 08-Jul-2009 Torok Edwin <edwintorok@gmail.com> Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4784f1fc73abf6005b7b7262d395af71b57b1255 30-Jun-2009 Evan Cheng <evan.cheng@apple.com> Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.

The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
74d3f50a803347432b3dc26f67e23297c2a1f232 27-Jun-2009 Chris Lattner <sabre@nondot.org> factor some logic out into a helper function, allow remat of loads from constant
globals. This implements remat-constant.ll even without aggressive-remat.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
18c5987fa33ba9d57ea597e3131f664443765f4e 27-Jun-2009 Chris Lattner <sabre@nondot.org> Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ac5e887a6cf0a6182664d8c11beb0d2270272b02 25-Jun-2009 Chris Lattner <sabre@nondot.org> Use target-specific machine operand flags to eliminate a gross hack
from the asmprinter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b1fb84dee9c3797ec2f2bfd2c9cf8e6ee0436487 25-Jun-2009 Chris Lattner <sabre@nondot.org> just eliminate the code entirely!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bccf4b3050907b61b9d5349601269a0474b4c0fd 04-Jun-2009 Eli Friedman <eli.friedman@gmail.com> PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
the code tried to use "push", which doesn't exist for XMM registers.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2265ba071762b461ed1e65ebd73f596a98208f60 29-May-2009 Bill Wendling <isanbard@gmail.com> The MONITOR and MWAIT instructions have insufficient information for
decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.

Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 13-May-2009 Bill Wendling <isanbard@gmail.com> Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6ed34918ebc2b7bcfcc5e5ee42070303b73811fe 12-May-2009 Evan Cheng <evan.cheng@apple.com> Avoid unneeded SIB byte encoding. Patch by Zoltan Varga.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
45e0010e14d419ebeca9266b9b705867fd251b83 08-May-2009 Evan Cheng <evan.cheng@apple.com> Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g.

/// A:
/// ...
/// <fallthrough to B>
///
/// B: --> loop header
/// ...
/// jcc <cond> C, [exit]
///
/// C:
/// ...
/// jmp B
///
/// ==>
///
/// A:
/// ...
/// jmp B
///
/// C: --> new loop header
/// ...
/// <fallthough to B>
///
/// B:
/// ...
/// jcc <cond> C, [exit]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ef1840173c6e7eadaac3e1bcb443088e49501816 05-May-2009 Evan Cheng <evan.cheng@apple.com> Revert part of 70929 that has to do with determining whether a SIB byte is needed. It causes a lot of x86_64 JIT failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b0030ddca469b3372630b0c01c21245ef0027aa0 05-May-2009 Evan Cheng <evan.cheng@apple.com> - Avoid the longer SIB encoding on x86_64 when it's not needed.
- Synchronize instruction length computation code in X86InstrInfo with code in X86CodeEmitter.cpp
Patch by Zoltan Varga.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4af325d1b4b811277365a20aa6cfc7f719625198 27-Apr-2009 Dan Gohman <gohman@apple.com> Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!

Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6241762c5a8f5e22679ffcd7a592e405e279f0a9 27-Apr-2009 Dan Gohman <gohman@apple.com> Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
70bc17dbf5a991ce8f8f5285f61c352fb55b533d 21-Apr-2009 Dan Gohman <gohman@apple.com> Make X86's copyRegToReg able to handle copies to and from subclasses.
This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0bd07fc5ddd8106cb0a8b5b8680782351cc0b931 18-Apr-2009 Mon P Wang <wangmp@apple.com> Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
18247736894073c2fb1677f7d46762a092cacc36 18-Apr-2009 Bill Wendling <isanbard@gmail.com> Recommit r69335 and r69336. These were not causing problems.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c3a76ef9553a2e89a18eab9d052052305e69fc93 17-Apr-2009 Bill Wendling <isanbard@gmail.com> Revert r69335 and r69336. They were causing build failures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d10a4ce5825d0981107c0106c49089b9e5792e40 17-Apr-2009 Dan Gohman <gohman@apple.com> MOV8rr_NOREX is a "Move" instruction. This doesn't currently
matter, because this instruction isn't generated until after
things that care.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d51def353cb74e18e459cc03dfb501ae631b9334 17-Apr-2009 Dan Gohman <gohman@apple.com> Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything at
present, but it's inconsistent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
df7dfc7715b7d475cfd4d275772836ce5188e605 15-Apr-2009 Dan Gohman <gohman@apple.com> Fix 80-column violations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
25174963f6ddf2abace8e6bd3dde3dd18a5b51bd 15-Apr-2009 Dan Gohman <gohman@apple.com> Add a folding table entry for MOV8rr_NOREX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6d9305c7fd3cd5ecf6e6326da0b8ed1f63a771f3 15-Apr-2009 Dan Gohman <gohman@apple.com> Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when
either the source or destination is a physical h register.

This fixes sqlite3 with the post-RA scheduler enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
21e3dfbc86955cf46a362e8ed36b5b73b42961c9 13-Apr-2009 Dan Gohman <gohman@apple.com> Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8cc632f7052de02ca270284fa672e7ceda261355 13-Apr-2009 Dan Gohman <gohman@apple.com> Fix another hard-coded constant to use X86AddrNumOperands.
This unbreaks the JIT on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a1cd83a25891a09fe6b284a05d28b27eb3531382 09-Apr-2009 Chris Lattner <sabre@nondot.org> Fix code size computation on x86-64, patch by Zoltan Varga!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
094fad37b90946c91a09eb9270a0dbe800f49d87 08-Apr-2009 Rafael Espindola <rafael.espindola@gmail.com> Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
044b5344c4a97b3c709a05b9c5f9296656477652 08-Apr-2009 Bill Wendling <isanbard@gmail.com> Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.

--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 07-Apr-2009 Rafael Espindola <rafael.espindola@gmail.com> Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
da945e3bb2069c1a7194bcd10579a03ff925a031 28-Mar-2009 Rafael Espindola <rafael.espindola@gmail.com> Have only one definition of X86AddrNumOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b449a68146c7188a20bba11db19229a5cb46938a 28-Mar-2009 Rafael Espindola <rafael.espindola@gmail.com> Make code a bit less brittle by no hardcoding the number
of operands in an address in so many places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
705d800879e9eec1120d8a7ec5bf1d05764320cd 27-Mar-2009 Rafael Espindola <rafael.espindola@gmail.com> Avoid hardcoding that X86 addresses have 4 operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1606e8e4cd937e6de6681f686c266cf61722d972 13-Mar-2009 Evan Cheng <evan.cheng@apple.com> Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.

1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.


Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fc53fc657e89c8cad49012be7b77cab7e8133004 04-Mar-2009 Dan Gohman <gohman@apple.com> Correct this comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b37a8206b6ba10c2bd59e19811dfd88091021556 04-Mar-2009 Dan Gohman <gohman@apple.com> When using MachineInstr operand indices on SDNodes, the number
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c94ebef1b1ea6dda54494a0a0eafc96ab685a531 22-Feb-2009 Evan Cheng <evan.cheng@apple.com> Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
97357614b5957cc167c261d3be54713802715d9a 18-Feb-2009 Dan Gohman <gohman@apple.com> Factor out the code to add a MachineOperand to a MachineInstrBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8d13f8f1043d8b47940ecab7bac838ff1e8166f8 13-Feb-2009 Dale Johannesen <dalej@apple.com> Remove non-DebugLoc versions of BuildMI from X86.
There were some that might even matter in X86FastISel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
21b5541814d57d0a31f353948e4e933dbb1af6a4 13-Feb-2009 Dale Johannesen <dalej@apple.com> Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fbef3101a50dac85ac18e09a304b187a4109d7ed 11-Feb-2009 Bill Wendling <isanbard@gmail.com> Propagate DebugLoc info for spiller call-backs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a0eedac226e79d818ce1124fe500a6e354e3444a 10-Feb-2009 Evan Cheng <evan.cheng@apple.com> Implement FpSET_ST1_*.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dc54d317e7a381ef8e4aca80d54ad1466bb85dda 09-Feb-2009 Evan Cheng <evan.cheng@apple.com> Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
770bcc7b15adbc978800db70dbb1c3c22913b52c 06-Feb-2009 Evan Cheng <evan.cheng@apple.com> Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4350eb86a7cdc83fa6a5f4819a7f0534ace5cd58 06-Feb-2009 Evan Cheng <evan.cheng@apple.com> Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ed2eee63a6858312ed17582d8cb85a6856d8eb34 06-Feb-2009 Dale Johannesen <dalej@apple.com> Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9bc96a57206cbebaa9b0ba9979f949eb10c1592c 03-Feb-2009 Bill Wendling <isanbard@gmail.com> Create DebugLoc information in FastISel. Several temporary methods were
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 20-Jan-2009 Evan Cheng <evan.cheng@apple.com> Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
41b762a75e851d80016a15925933490ca2c76567 15-Jan-2009 Dan Gohman <gohman@apple.com> Add load-folding table entries for BT*ri8 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5446274bd242e1f23547ce57aa4d411e46e9acb8 09-Jan-2009 Dan Gohman <gohman@apple.com> Add load-folding table entries for MOVDQA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b33fc7b0630145084d1ebce6942c2161094dd48d 07-Jan-2009 Dan Gohman <gohman@apple.com> Add load-folding table entries for cmovno too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
305fceb56c34e1a46bb3944e9311e9638f90f341 07-Jan-2009 Dan Gohman <gohman@apple.com> Define instructions for cmovo and cmovno.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
653456c351d9bf908ebd982f6ae9df3449c5f34b 07-Jan-2009 Dan Gohman <gohman@apple.com> X86_COND_C and X86_COND_NC are alternate mnemonics for
X86_COND_B and X86_COND_AE, respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cca2983291bb5502085148164ad77e8017dd8cde 07-Jan-2009 Dan Gohman <gohman@apple.com> Revert r42653 and forward-port the code that lets INC64_32r be
converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
movl %esi, %edi
inc %edi
with this:
lea 1(%rsi), %edi
which appears to be beneficial.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d68a07650cdb2e18f18f362ba533459aa10e01b6 05-Jan-2009 Dan Gohman <gohman@apple.com> Tidy up #includes, deleting a bunch of unnecessary #includes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
15a3a49e199c3d7d9f15da0eded5a1edf94dc354 23-Dec-2008 Dan Gohman <gohman@apple.com> Make the fuse-failed debug output human-readable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
af9b952627d8fa10412b8cf7319d3e334446547f 18-Dec-2008 Mon P Wang <wangmp@apple.com> Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
650d7f3ff4d22646def71b842f7f163c539e0aaf 05-Dec-2008 Evan Cheng <evan.cheng@apple.com> Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
84100ba83dd4500019fcbf43b6627a910dff153b 05-Dec-2008 Evan Cheng <evan.cheng@apple.com> Effectively undo 60461 in PIC mode which simply transform V_SET0 / V_SETALLONES into a load from constpool in order to fold into restores. This is not safe to do when PIC base is being used for a number of reasons:
1. GlobalBaseReg may have been spilled.
2. It may not be live at the use.
3. Spiller doesn't know this is happening so it won't prevent GlobalBaseReg from being spilled later (That by itself is a nasty hack. It's needed because we don't insert the reload until later).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c54baa2d43730f1804acfb4f4e738fba72f966bd 03-Dec-2008 Dan Gohman <gohman@apple.com> Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
62c939d7d5572e57963a5f26fb6fe802e13dc0bf 03-Dec-2008 Dan Gohman <gohman@apple.com> Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's
foldMemoryOperand how to "fold" them, by converting them into constant-pool
loads. When they aren't folded, they use xorps/cmpeqd, but for example when
register pressure is high, they may now be folded as memory operands, which
reduces register pressure.

Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will
remat it instead of copying zeros around (V_SETALLONES was already marked).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9f24874f2e38bab927fcc940fc523e22a7d643e2 02-Dec-2008 Bill Wendling <isanbard@gmail.com> Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e3b3c00454f78a62d0f97f96ce66b9e2db3f933d 02-Dec-2008 Bill Wendling <isanbard@gmail.com> Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a047bcacf240291ed5b499ca2c45860320079513 02-Dec-2008 Bill Wendling <isanbard@gmail.com> - Have "ADD" instructions return an implicit EFLAGS.
- Add support for seto, setno, setc, and setnc instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3fafd935607844085a23c012e2a8778fa97206a0 26-Nov-2008 Bill Wendling <isanbard@gmail.com> Generate something sensible for an [SU]ADDO op when the overflow/carry flag is
the conditional for the BRCOND statement. For instance, it will generate:

addl %eax, %ecx
jo LOF

instead of

addl %eax, %ecx
; About 10 instructions to compare the signs of LHS, RHS, and sum.
jl LOF



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
25a1b47cc3a153eb2f4a840b060196c3a19e3e07 26-Nov-2008 Dan Gohman <gohman@apple.com> Fish kill flag annotations in PUSH instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 18-Nov-2008 Dan Gohman <gohman@apple.com> Add more const qualifiers. This fixes build breakage from r59540.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
23066288fdf4867f53f208f9aaf2952b1c049394 27-Oct-2008 Evan Cheng <evan.cheng@apple.com> For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b74f370e437de31b53496e86f024b533ee8ec91b 25-Oct-2008 Nicolas Geoffray <nicolas.geoffray@lip6.fr> Generate code for TLS instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
279c22e6da2612f024b70e5509ffb0cad32f38b2 21-Oct-2008 Dan Gohman <gohman@apple.com> Optimized FCMP_OEQ and FCMP_UNE for x86.

Where previously LLVM might emit code like this:

ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2

it now emits this:

ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2

It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.

To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.

Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3afda6e9d1a74456b9baa87ee6aabbc06e356433 21-Oct-2008 Dan Gohman <gohman@apple.com> When the coalescer is doing rematerializing, have it remove
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.

Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.

These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
74feef261a43392bc85280f66c75fbd4e2ccf73d 17-Oct-2008 Dan Gohman <gohman@apple.com> Define patterns for shld and shrd that match immediate
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8e8b8a223c2b0e69f44c0639f846260c8011668f 16-Oct-2008 Dan Gohman <gohman@apple.com> Const-ify several TargetInstrInfo methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d21a6305ea758a395435c367e1f561c67b5c6ad1 12-Oct-2008 Anton Korobeynikov <asl@math.spbu.ru> Update size of inst correctly with segment override.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57414 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c4e8bec703fe0e7191a1e78557d7ab750e965e20 04-Oct-2008 Anton Korobeynikov <asl@math.spbu.ru> Revert r56675 - it breaks unwinding runtime everywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d735b8019b0f297d7c14b55adcd887af24d8e602 03-Oct-2008 Dan Gohman <gohman@apple.com> Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
57c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37c 30-Sep-2008 Dan Gohman <gohman@apple.com> Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp
and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
83ccd14228ed3b2458a59cc3b2ede763cad6fe50 26-Sep-2008 Dan Gohman <gohman@apple.com> Mark lea fi# as being really rematerializable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a67f32abb5392981dbcb4de4e25bdedb046a8566 26-Sep-2008 Evan Cheng <evan.cheng@apple.com> Avoid spilling EBP / RBP twice in the prologue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8b746969baee26237e4c52de9862d06795eabcda 23-Sep-2008 Dan Gohman <gohman@apple.com> Move the code for initializing the global base reg out of
X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow
it to be reused by FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
014278e6a11fa0767853b831e5bf51b95bf541c5 13-Sep-2008 Dan Gohman <gohman@apple.com> Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
97af60b3ae4085d25ea4812c9e7219dba8293c9b 30-Aug-2008 Evan Cheng <evan.cheng@apple.com> Use static_cast instead of C style cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
94a50da93cb9fdc45f3c3ab06f68380b31dd0c1c 30-Aug-2008 Evan Cheng <evan.cheng@apple.com> Backing out 55521. Not safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4d46d0af583b95a5d4f7d490f542c4fb65b9e824 29-Aug-2008 Evan Cheng <evan.cheng@apple.com> Swap fp comparison operands and change predicate to allow load folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a317767f0e5ecc8106ab9836d0f3702b1c00bedf 26-Aug-2008 Owen Anderson <resistor@mac.com> These assertions should be return false's instead, allowing the client to detect the failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
940f83e772ca2007d62faffc83094bd7e8da6401 26-Aug-2008 Owen Anderson <resistor@mac.com> Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
44eb65cf58e3ab9b5621ce72256d1621a18aeed7 15-Aug-2008 Owen Anderson <resistor@mac.com> Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d9ced092998b5ea3b10ab32b8f2407022b4508db 08-Aug-2008 Dan Gohman <gohman@apple.com> Add an EXTRACTPSmr pattern to match the pattern that
X86ISelLowering creates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54544 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e3d920699c6df959f3e0844aeadd983b2955b23e 07-Aug-2008 Dan Gohman <gohman@apple.com> Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
475871a144eb604ddaf37503397ba0941442e5fb 27-Jul-2008 Dan Gohman <gohman@apple.com> Rename SDOperand to SDValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
41c08405839c49fc6d981c024fc03efb0309acc6 21-Jul-2008 Evan Cheng <evan.cheng@apple.com> Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
88bbf6941f29ee1e7ab5f4cc09098f7aea5808cb 19-Jul-2008 Anton Korobeynikov <asl@math.spbu.ru> Use aligned stack spills, where possible. This fixes PR2549.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53784 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e8be6c63915e0389f1eef6b53c64300d13b2ce99 17-Jul-2008 Dan Gohman <gohman@apple.com> Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cddc11e7570893233af8e84dfb8e7f0f9ab0090d 12-Jul-2008 Dan Gohman <gohman@apple.com> Add a utility function to MachineInstr for testing whether an instruction
has exactly one MachineMemOperand, and change some X86 lowering code to
make use of it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8e5f2c6f65841542e2a7092553fe42a00048e4c7 08-Jul-2008 Dan Gohman <gohman@apple.com> Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6b345ee9b2833cf1b2f79dc16d06d4060bec36ef 07-Jul-2008 Dan Gohman <gohman@apple.com> Make DenseMap's insert return a pair, to more closely resemble std::map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9f1c8317a4676945b4961ddb9827ef2412551620 03-Jul-2008 Evan Cheng <evan.cheng@apple.com> - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
457b88fb95be895d914e52f3b44014a82e645e4a 03-Jul-2008 Evan Cheng <evan.cheng@apple.com> commuteInstruction should preserve dead markers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f660c171c838793b87b7e58e91609cecf256378d 03-Jul-2008 Owen Anderson <resistor@mac.com> Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4406604047423576e36657c7ede266ca42e79642 01-Jul-2008 Dan Gohman <gohman@apple.com> Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9ef4ca2e812fc62e345fa019c2358564bbe46245 24-Jun-2008 Evan Cheng <evan.cheng@apple.com> If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 16-Jun-2008 Evan Cheng <evan.cheng@apple.com> Add option to commuteInstruction() which forces it to create a new (commuted) instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb 06-Jun-2008 Duncan Sands <baldrick@free.fr> Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0b924dcef859daafded64268447aeff3f60f1c08 23-May-2008 Dan Gohman <gohman@apple.com> Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
load-folding table entries for PMULDQ and PMULLD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 14-May-2008 Dan Gohman <gohman@apple.com> Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9f8fea3531f8f8d04d1e183ff570be37d41d13f5 12-May-2008 Bill Wendling <isanbard@gmail.com> Constify the machine instruction passed into the
"is{Trivially,Really}ReMaterializable" methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
082f1161b15f757043ae69b7881898ba323ec86c 02-May-2008 Evan Cheng <evan.cheng@apple.com> Undo r50574. We are already ensuring the folded load address is 16-byte aligned.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ef6a51248903c176b133180292489015e71bce45 02-May-2008 Evan Cheng <evan.cheng@apple.com> Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
546e36a2c17f9eb7b2b1f2f19e522673153948aa 21-Apr-2008 Nicolas Geoffray <nicolas.geoffray@lip6.fr> Don't forget to update the current operand when getting the size of an instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
03eb38848c9f880f8d97508b6a008f81cc4bdcb9 17-Apr-2008 Evan Cheng <evan.cheng@apple.com> Don't forget about sub-register indices when rematting instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
52e724ad7e679ee590f4bd763d55280586a8f1bc 16-Apr-2008 Nicolas Geoffray <nicolas.geoffray@lip6.fr> Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
36b5c1338a03453ba1c110b120269ca972fb65a3 07-Apr-2008 Dan Gohman <gohman@apple.com> Rename MemOperand to MachineMemOperand. This was suggested by
review feedback from Chris quite a while ago. No functionality
change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ffe2eb0120e52db74746b7e5117f8ffd80f1348f 02-Apr-2008 Evan Cheng <evan.cheng@apple.com> ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
247faffb32da8f3c2d805e5450a006408db12d60 01-Apr-2008 Evan Cheng <evan.cheng@apple.com> Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
78b6ce3981a5a1692f7cf0f175852aacf311fd48 01-Apr-2008 Evan Cheng <evan.cheng@apple.com> Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
427f4c106ac14dcf323dc1bbaf1b8040da03c3c7 01-Apr-2008 Evan Cheng <evan.cheng@apple.com> It's not safe to fold a load from GV stub or constantpool into a two-address use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ca1267c02b025cc719190b05f9e1a5d174a9caf7 31-Mar-2008 Evan Cheng <evan.cheng@apple.com> Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9d15abe8385d17aa86c8144c8bbbac958fb91f17 31-Mar-2008 Evan Cheng <evan.cheng@apple.com> Re-apply 48911.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4db4f1ce7e238a49fa387c72ed3ad62c79107754 28-Mar-2008 Evan Cheng <evan.cheng@apple.com> Backing out 48911 for now. It's breaking stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
86f57b098327b33666e50acd2f936c5f2ed95262 28-Mar-2008 Evan Cheng <evan.cheng@apple.com> Load from stub is already re-materializable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e3d8dbf479e52a81b0fd54a28c180e94f15afca0 27-Mar-2008 Evan Cheng <evan.cheng@apple.com> Code clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e771ebd7a32e760a1eb92ec50513c02d14a996df 27-Mar-2008 Evan Cheng <evan.cheng@apple.com> Allow certain lea instructions to be rematerialized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d1e4b3515ccc33e45a74fa8fb300f4ff90e67a85 27-Mar-2008 Evan Cheng <evan.cheng@apple.com> Remove an unused command line option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
27845362d96a90f52ea5c980d4b7b44a2e957b06 25-Mar-2008 Dan Gohman <gohman@apple.com> Add CMP32mr and friends to the load-unfolding table. Among
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
24e0a546b40d67dd3662273eb4aef30c230a15ef 21-Mar-2008 Chris Lattner <sabre@nondot.org> Add support for calls that return two FP values in
ST(0)/ST(1).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c9298235251b014e86a7368d92b589d093acb64a 16-Mar-2008 Christopher Lamb <christopher.lamb@gmail.com> Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6634e26aa11b0e2eabde8b3b463bb943364f8d9d 13-Mar-2008 Christopher Lamb <christopher.lamb@gmail.com> Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1d38677e34f67961bbff40a5fed96f96ebfea836 11-Mar-2008 Chris Lattner <sabre@nondot.org> coalesce away 80-bit floating point copies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
07f7cc3ddb4602c2a0ad5cff6d97c35496ea87ba 11-Mar-2008 Chris Lattner <sabre@nondot.org> convert a massive if statement to a switch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1bc1008b38bfa8f04e85cb702c6bafa4a80f1de1 11-Mar-2008 Christopher Lamb <christopher.lamb@gmail.com> Missed part of recommit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
183275a6279da7de436103d6a03ec2709dc137d1 11-Mar-2008 Chris Lattner <sabre@nondot.org> abort with an assert instead of a cerr to get line#


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4499e495eabe8de7d595416a03c56af4688df507 10-Mar-2008 Evan Cheng <evan.cheng@apple.com> Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3feb0170a8d65984ce5c01a85e7dfd4005f8bb35 10-Mar-2008 Christopher Lamb <christopher.lamb@gmail.com> Allow insert_subreg into implicit, target-specific values.
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f30e1cf9b7f96395768e710b4707ecd5587e1185 09-Mar-2008 Chris Lattner <sabre@nondot.org> teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5c927500c823aecafb46881626a5db7822ad019a 09-Mar-2008 Chris Lattner <sabre@nondot.org> add some code to support cross-register class copying from
RST -> RFP{32/64/80}. We only handle ST(0) for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
90b347dc90a0f002ac5ac1e990991f98371f730b 09-Mar-2008 Chris Lattner <sabre@nondot.org> rearrange some code, no functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c19eca38efee75d76080caedc565f409ae20eb72 23-Feb-2008 Evan Cheng <evan.cheng@apple.com> Turning on remat of pic loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b2a0abce1ed97d6642f91e10114f22e824d933cb 23-Feb-2008 Evan Cheng <evan.cheng@apple.com> No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d8850a512ee4023420abf95f3576827cd28c216a 22-Feb-2008 Evan Cheng <evan.cheng@apple.com> Allow re-materialization of pic load (controlled by -remat-pic-load for now).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a4d16a1f0dcdd1ab2862737105f900e2c577532d 13-Feb-2008 Evan Cheng <evan.cheng@apple.com> commuteInstr() can now commute non-ssa machine instrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5fd79d0560570fed977788a86fa038b898564dfa 08-Feb-2008 Evan Cheng <evan.cheng@apple.com> It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
33663fc104d0cdfc06cac55f677e9bc0bb5f5817 08-Feb-2008 Evan Cheng <evan.cheng@apple.com> Added missing entries in X86 load / store folding tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
15246738f2db3f63a20c1f2b9b19b08e21acffd9 07-Feb-2008 Evan Cheng <evan.cheng@apple.com> In some cases, e.g. ADD32ri, no transformation is made. Guide against it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
144ad580fd7b7a4dfeba11a934de69582855c676 12-Jan-2008 Chris Lattner <sabre@nondot.org> fix a wordo that gordon noticed :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
828bb6c97881fe4f2f27bdc9096ca3f795941253 12-Jan-2008 Chris Lattner <sabre@nondot.org> Any x86 instruction that reads from an invariant location is invariant.
This allows us to sink things like:
cvtsi2sd 32(%esp), %xmm1
when reading from the argument area, for example.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5080f4d9919d39b367891dc51e739c571a66036c 11-Jan-2008 Chris Lattner <sabre@nondot.org> rename MachineInstr::setInstrDescriptor -> setDesc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f9b3f37abc25375be2ada0f88da7eca863095ad3 11-Jan-2008 Chris Lattner <sabre@nondot.org> remove xchg and shift-reg-by-1 instructions, which are dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a22edc82cab86be4cb8876da1e6e78f82bb47a3e 11-Jan-2008 Chris Lattner <sabre@nondot.org> Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad.

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags. Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8794390406608541ab43b8ff196874b2dd055cdb 10-Jan-2008 Chris Lattner <sabre@nondot.org> verify that the frame index is immutable before remat'ing (still disabled)
or being side-effect free.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
269f0595d628eb5d2cf12d11bcda6bd69a73f509 09-Jan-2008 Chris Lattner <sabre@nondot.org> add a testcase


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
323cd29009606d944ff306d6cc40d8167082153a 07-Jan-2008 Bill Wendling <isanbard@gmail.com> Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
749c6f6b5ed301c84aac562e414486549d7b98eb 07-Jan-2008 Chris Lattner <sabre@nondot.org> rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
349c4952009525b27383e2120a6b3c998f39bd09 07-Jan-2008 Chris Lattner <sabre@nondot.org> Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
cc8cd0cbf12c12916d4b38ef0de5be5501c8270e 07-Jan-2008 Chris Lattner <sabre@nondot.org> remove MachineOpCode typedef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8ca5c67c6e95fdcf5ddb2f06586873c843dd0cde 07-Jan-2008 Chris Lattner <sabre@nondot.org> Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly. Change the
various flags from const variables to enums.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
69244300b8a0112efb44b6273ecea4ca6264b8cf 07-Jan-2008 Chris Lattner <sabre@nondot.org> Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
43dbe05279b753aabda571d9c83eaeb36987001a 07-Jan-2008 Owen Anderson <resistor@mac.com> Move even more functionality from MRegisterInfo into TargetInstrInfo.

Some day I'll get it all moved over...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f995830dafb8a20aa14f6b055af79253c9368303 06-Jan-2008 Bill Wendling <isanbard@gmail.com> Fix comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
df303bd7f2c15d6c5fcbee951bd8c21dde3f2718 05-Jan-2008 Bill Wendling <isanbard@gmail.com> Chris and Evan noticed that this check was compleatly fubared. I was
checking that there was a from a global instead of a load from the stub
for a global, which is the one that's safe to hoist.

Consider this program:

volatile char G[100];
int B(char *F, int N) {
for (; N > 0; --N)
F[N] = G[N];
}

In static mode, we shouldn't be hoisting the load from G:

$ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm

LBB1_1: # bb.preheader
leal -1(%eax), %edx
testl %edx, %edx
movl $1, %edx
cmovns %eax, %edx
xorl %esi, %esi
LBB1_2: # bb
movb _G(%eax), %bl
movb %bl, (%ecx,%eax)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f29495a22f3ce2c0cc74eadd5bf074e5fa6ca8bd 05-Jan-2008 Chris Lattner <sabre@nondot.org> enable sinking and licm of loads from the argument area. I'd like to enable this
for remat, but can't due to an RA bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3b5a221f815f66775ee58f0e3bd8205cdf4288b2 05-Jan-2008 Chris Lattner <sabre@nondot.org> simplify some code by using shorter accessors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a83b34bbebe9c251cce72a91f48be9d75a4450b4 05-Jan-2008 Chris Lattner <sabre@nondot.org> revert my previous patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
505d4abd05e1c50c8df132009f9365e390671b84 05-Jan-2008 Chris Lattner <sabre@nondot.org> factor some code better to avoid redundancy between
isReallySideEffectFree and isReallyTriviallyReMaterializable. Why is a load from
a global considered side-effect-free but not rematable?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d94b6a16fec7d5021e3922b0e34f9ddb268d54b1 05-Jan-2008 Owen Anderson <resistor@mac.com> Move some more functionality from MRegisterInfo to TargetInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3100afaf3f2f3b0224fc03038062fc57f1a9a796 02-Jan-2008 Bill Wendling <isanbard@gmail.com> Machine LICM will check that operands are defined outside of the loop. Also
check that register isn't 0 before going further.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f6372aa1cc568df19da7c5023e83c75aa9404a07 01-Jan-2008 Owen Anderson <resistor@mac.com> Move some more instruction creation methods from RegisterInfo into InstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
264e6fec9f3962cb269031d6d84cee9f896e0286 01-Jan-2008 Chris Lattner <sabre@nondot.org> Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
641055225092833197efe8e5bce01d50bcf1daae 01-Jan-2008 Chris Lattner <sabre@nondot.org> Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 31-Dec-2007 Owen Anderson <resistor@mac.com> Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
84bc5427d6883f73cfeae3da640acd011d35c006 31-Dec-2007 Chris Lattner <sabre@nondot.org> Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 31-Dec-2007 Chris Lattner <sabre@nondot.org> Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 30-Dec-2007 Chris Lattner <sabre@nondot.org> Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6259d51c91d7da9bf16114849236b5bdfa85f35e 30-Dec-2007 Bill Wendling <isanbard@gmail.com> If we have a load of a global address that's not modified during the
function, then go ahead and hoist it out of the loop. This is the result:

$ cat a.c
volatile int G;

int A(int N) {
for (; N > 0; --N)
G++;
}
$ llc -o - -relocation-model=pic
_A:
...
LBB1_2: # bb
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %esi
incl (%esi)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
...
$ llc -o - -relocation-model=pic -machine-licm
_A:
...
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %eax
LBB1_2: # bb
incl (%eax)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
...

I'm limiting this to the MOV32rm x86 instruction for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4ee451de366474b9c228b4e5fa573795a715216d 29-Dec-2007 Chris Lattner <sabre@nondot.org> Remove attribution from file headers, per discussion on llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
627c00b663f881600b4af1ae135af6ee2cb19c1a 18-Dec-2007 Bill Wendling <isanbard@gmail.com> Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
041b3f835682588cb63df7e609d726369dd6b7d3 09-Dec-2007 Bill Wendling <isanbard@gmail.com> Reverting 44702. It wasn't correct to rename them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
320c630c1b55e17fa00249d499f974cb1a4238f8 08-Dec-2007 Bill Wendling <isanbard@gmail.com> Renaming:

isTriviallyReMaterializable -> hasNoSideEffects
isReallyTriviallyReMaterializable -> isTriviallyReMaterializable


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c85e1716f0e45e4c18a9ef2fbe431a51ac3a4252 11-Oct-2007 Arnold Schwaighofer <arnold.schwaighofer@gmail.com> Added tail call optimization to the x86 back end. It can be
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b76143cf8f5048e460f8df2ce8995a02ccc40012 09-Oct-2007 Evan Cheng <evan.cheng@apple.com> Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d47c84c1c9ccbd11decf436604d90c60544d7008 08-Oct-2007 Evan Cheng <evan.cheng@apple.com> Allow x86 compare to be commutable by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7ad42d9ec0af47807f069103a350efc1d5aef0a8 06-Oct-2007 Evan Cheng <evan.cheng@apple.com> Commute x86 cmove instructions by swapping the operands and change the condition
to its inverse.
Testing this as llcbeta


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ecf80ac68adf3adca3707dcfc9bf9f02536c27ca 06-Oct-2007 Evan Cheng <evan.cheng@apple.com> Enable convertToThreeAddress for X86 by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b75ed322c4d5fd3ca5ac2fb0cdcedb4413eb8cce 05-Oct-2007 Evan Cheng <evan.cheng@apple.com> INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can
cause performance degradation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
559dc46d4609f8a3743daea19fb29fb4dc0ede46 05-Oct-2007 Evan Cheng <evan.cheng@apple.com> In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.
leal 1(%ecx), %edi, which requires 67H prefix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b952d1f5be9238b7d39ccb72303b677d97bd8ec5 05-Oct-2007 Evan Cheng <evan.cheng@apple.com> Add support to convert more 64-bit instructions to 3-address instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3f411c76276be0aa924e65c2348006baa963fbde 05-Oct-2007 Evan Cheng <evan.cheng@apple.com> Testing convertToThreeeAddress as X86 llcbeta.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e5f6204cd5d2306379bf8954e280ad35619a38b5 29-Sep-2007 Evan Cheng <evan.cheng@apple.com> Enabling new condition code modeling scheme.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0488db9b99fcfca407e859ef5cccf40dea23de16 25-Sep-2007 Evan Cheng <evan.cheng@apple.com> Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a0a7c1de9c174ee8024843e1cfbdaf3f47c9be34 17-Sep-2007 Dan Gohman <gohman@apple.com> Add 64-bit jmp instructions to the list of instructions that
can terminate a block with no fall-through.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e47f1f9633064749ecb915254b1c31697e27aab1 15-Sep-2007 Dan Gohman <gohman@apple.com> Add patterns for SHLD64* and SHRD64*.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
24f2ea3971065eb9e88d50ebeddad0463337cae3 14-Sep-2007 Evan Cheng <evan.cheng@apple.com> Add implicit def of EFLAGS on those instructions that may modify flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
718cb665ca6ce2bc4d8e8479f46a45db91b49f86 07-Sep-2007 Owen Anderson <resistor@mac.com> Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
61d9c861fd6fabfc94421801d3ada9ef648467b7 06-Sep-2007 Evan Cheng <evan.cheng@apple.com> Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:
leal (,%rcx,8), %rcx
It should be
leal (,%rcx,8), %ecx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b81337117cb589376bf60a76355581d9d103ad97 10-Aug-2007 Christopher Lamb <christopher.lamb@gmail.com> Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
85dce6cf781b0c75de0aa178e3ad0df128b3b977 26-Jul-2007 Evan Cheng <evan.cheng@apple.com> Don't pollute the meaning of isUnpredicatedTerminator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
14c46554039ac26c431d72725663409eeab864ae 07-Jul-2007 Evan Cheng <evan.cheng@apple.com> isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e377d4d142d7e2ec9266435087c99ffc43f394aa 04-Jul-2007 Dale Johannesen <dalej@apple.com> Refactor X87 instructions. As a side effect, all
their names are changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
849f214a4e3676e41168b0c5398165c4d4fb99f8 03-Jul-2007 Dale Johannesen <dalej@apple.com> Fix for PR 1505 (and 1489). Rewrite X87 register
model to include f32 variants. Some factoring
improvments forthcoming.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d45eddd214061bf12ad1e6b86497a41725e61d75 26-Jun-2007 Dan Gohman <gohman@apple.com> Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
82a87a01723c095176c6940bcc63d3a7c8007b4b 19-Jun-2007 Dan Gohman <gohman@apple.com> Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
318093b6f8d21ac8eab34573b0526984895fe941 15-Jun-2007 Dale Johannesen <dalej@apple.com> Do not treat FP_REG_KILL as terminator in branch analysis (X86).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c101e95cb6aae1fd6a0727ba4b518a7894ae3089 14-Jun-2007 Dan Gohman <gohman@apple.com> Add a target hook to allow loads from constant pools to be rematerialized, and an
implementation for x86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
13e8b51e3ec014c5d7ae83afdf3b8fd29c3a461d 13-Jun-2007 Dale Johannesen <dalej@apple.com> Handle blocks with 2 unconditional branches in AnalyzeBranch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8 08-Jun-2007 Evan Cheng <evan.cheng@apple.com> Add a utility routine to check for unpredicated terminator instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
126f17a17625876adb63f06d043fc1b1e4f0361c 21-May-2007 Evan Cheng <evan.cheng@apple.com> BlockHasNoFallThrough() now returns true if block ends with a return instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6ae3626a4fda14e6250ac8d8ff487efb8952cdf7 18-May-2007 Evan Cheng <evan.cheng@apple.com> RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1e341729dd003ca33ecea4abf13134f20062c5f8 25-Apr-2007 Evan Cheng <evan.cheng@apple.com> Relex assertions to account for additional implicit def / use operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6dd29e08f7d4e0c0f10086ca8b315d9b51a77a45 24-Apr-2007 Bill Wendling <isanbard@gmail.com> Remove some invalid instructions from this check.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
71bfd11c6775cb7fde580f5b4d21cedc63f0867f 04-Apr-2007 Bill Wendling <isanbard@gmail.com> Adding more MMX instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
823efee6339242559718b92a693d95ba299a61a7 03-Apr-2007 Bill Wendling <isanbard@gmail.com> Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
995f55036fd1b420cf5c5d45096a8e36736303cd 28-Mar-2007 Chris Lattner <sabre@nondot.org> Compile CodeGen/X86/lea-3.ll:test2 to:

_test3:
leaq (,%rdi,4), %rax
orq %rdi, %rax
ret

instead of:
_test2:
movq %rdi, %rax
shlq $2, %rax
orq %rdi, %rax
ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f2177b89a12f9e5977d317aedb598b674b328d08 28-Mar-2007 Chris Lattner <sabre@nondot.org> Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the
system assembler not groking legal instructions like "leal (,%esi,8), %ecx".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a16b7cb1d3a482a28bc8f73433f0034d8d8673d7 20-Mar-2007 Chris Lattner <sabre@nondot.org> Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.

This gives us asm diffs like:

- leal (,%eax,4), %eax
+ shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2f88dcdfb3a9c9592da93dcf3f0e0a9333932187 08-Mar-2007 Bill Wendling <isanbard@gmail.com> Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
moves, loads, etc. are recognized.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1ee29257428960fede862fcfdbe80d5d007927e9 26-Jan-2007 Jim Laskey <jlaskey@mac.com> Make LABEL a builtin opcode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
258ff6726d6c079ec6c5b13e340299cbf7300299 01-Dec-2006 Evan Cheng <evan.cheng@apple.com> convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c0f64ffab93d11fb27a3b8a0707b77400918a20e 28-Nov-2006 Evan Cheng <evan.cheng@apple.com> Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e23fc60854b0e464b9fd22865c06cdc269a26638 17-Nov-2006 Evan Cheng <evan.cheng@apple.com> Fix a potential bug: MOVPDI2DI, etc. are not copy instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6ce7dc2a97260eea5fba414332796464912b9359 15-Nov-2006 Evan Cheng <evan.cheng@apple.com> Properly transfer kill / dead info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 14-Nov-2006 Evan Cheng <evan.cheng@apple.com> Matches MachineInstr changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6ce644392e0dd182f2eda161b5e69206b58a7c5d 30-Oct-2006 Chris Lattner <sabre@nondot.org> fix wonky indentation


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
c24ff8ed12d01a1b1d2fac57876fc7580024ec49 28-Oct-2006 Chris Lattner <sabre@nondot.org> add another target hook for branch folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9cd68759178f9fe25c72253d338e78e414f1d770 21-Oct-2006 Chris Lattner <sabre@nondot.org> Implement support for branch condition reversal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
879d09cf130f3760a08865913c04d9ff328fad5f 21-Oct-2006 Chris Lattner <sabre@nondot.org> Simplify code, no functionality change


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
34a84ac81c1ab3cd017203f69ce74283f42be15a 21-Oct-2006 Chris Lattner <sabre@nondot.org> allow insertion of a conditional branch with fall-through


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2a445add12d6a16d8793de60df92d0733e66af0c 21-Oct-2006 Chris Lattner <sabre@nondot.org> update assert message


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5860715e9da4ae8bc03745e10e695d8b0cd592a6 20-Oct-2006 Chris Lattner <sabre@nondot.org> bugfix


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
7fbe9723e32ff35c4ad765c88209ef9321475a1b 20-Oct-2006 Chris Lattner <sabre@nondot.org> Implement branch analysis/xform hooks required by the branch folding pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ae1dc403274d3a64bcee31f15e2d25e4b7178811 18-Oct-2006 Chris Lattner <sabre@nondot.org> expose DWARF_LABEL opcode# so the branch folder can update debug info properly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d77ddbc0ba4614f4c9ef548e82ba6bc68c586cb5 13-Oct-2006 Chris Lattner <sabre@nondot.org> remove some dead code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6458f1807d32e3625a192526c665a365f5886365 29-Sep-2006 Chris Lattner <sabre@nondot.org> update comments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
25ab690a43cbbb591b76d49e3595b019c32f4b3f 08-Sep-2006 Evan Cheng <evan.cheng@apple.com> Committing X86-64 support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
2926869b4a083fc951484de03a9867eabf81e880 05-Sep-2006 Chris Lattner <sabre@nondot.org> Fix a long-standing wart in the code generator: two-address instruction lowering
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
55371739dec0ade6fcc77de228fb3e4d098845f7 25-Jul-2006 Evan Cheng <evan.cheng@apple.com> Can't commute shufps. The high / low parts elements come from different vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
efeaed8fb4092365b6bd161d424bb33b0ffc3a97 31-May-2006 Evan Cheng <evan.cheng@apple.com> Commute shufps / shufpd.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a0eaf2d0c5a7e3230146ae699b99f324557cf7d3 31-May-2006 Evan Cheng <evan.cheng@apple.com> Somehow I lost a condition when I was shuffling some code around. Anyway,
only transform a shufps to pshufd when the first two operands are the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
aa3c1410b427909da350f2b5e8d4ec3db62a3618 30-May-2006 Evan Cheng <evan.cheng@apple.com> Fix a build breaker.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
51da42c28fba85d8bfe0faf235a42c9a142ff46f 30-May-2006 Evan Cheng <evan.cheng@apple.com> Oops. PSHUFD is only available with SSE2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
ccba76bb254e653646b01cf5b8304b14092d372b 30-May-2006 Evan Cheng <evan.cheng@apple.com> Allow shufps x, x, mask to be converted to pshufd x, mask to save a move.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6de01632016acef6a8c630fa4263efce8f405a53 19-May-2006 Evan Cheng <evan.cheng@apple.com> These can be transformed into lea as well. Not that we use this feature
currently...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f4df680ad407b4d3ef127b31abaf40c0dee1c8c1 11-May-2006 Evan Cheng <evan.cheng@apple.com> Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
403be7eafc8922c20d7e8253bc8d6d0abd0448cb 08-May-2006 Evan Cheng <evan.cheng@apple.com> Fixing truncate. Previously we were emitting truncate from r16 to r8 as
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
993c897390f1fc4ac9032a4d0897f73b2497ded1 18-Apr-2006 Chris Lattner <sabre@nondot.org> Teach the codegen about instructions used for SSE spill code, allowing it
to optimize cases where it has to spill a lot


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
11e15b38e965731e5bfff6c73d8d269196e5048c 03-Apr-2006 Evan Cheng <evan.cheng@apple.com> - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
- Some bug fixes and naming inconsistency fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bc4832bc648f9cfb99a43e01852e0f2c7632f16c 25-Mar-2006 Evan Cheng <evan.cheng@apple.com> Support for scalar to vector with zero extension.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
82521dd83888148824406a0bf8d6affbb6c61b92 21-Mar-2006 Evan Cheng <evan.cheng@apple.com> - Remove scalar to vector pseudo ops. They are just wrong.
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
fe5cb19405794e478b944581c3a7be5c29cbaa0e 16-Feb-2006 Evan Cheng <evan.cheng@apple.com> 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1c07e7286d85bec65238f9649a5510e561599112 02-Feb-2006 Chris Lattner <sabre@nondot.org> fix operand numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
408396014742a05cad1c91949d2226169e3f9d80 02-Feb-2006 Chris Lattner <sabre@nondot.org> Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bda54cdd477b3d9721359331f3dac8a5552abad2 02-Feb-2006 Evan Cheng <evan.cheng@apple.com> Tell codegen MOVAPSrr and MOVAPDrr are copies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
14e2cf62f43130a6ba5c4c72f83051a452633d8b 15-Oct-2005 Nate Begeman <natebegeman@mac.com> Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
11cefd926a1be9e6cd52b4e189a99081a385d57f 16-Jul-2005 Nate Begeman <natebegeman@mac.com> Teach the register allocator that movaps is also a move instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f63be7d3959939b2ffaf0bba5519b71216ec9ee6 06-Jul-2005 Nate Begeman <natebegeman@mac.com> First round of support for doing scalar FP using the SSE2 ISA extension and
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit

SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0e0a7a45d3d0a8c865a078459d2e1c6d8967a100 22-Apr-2005 Misha Brukman <brukman+llvm@gmail.com> * Remove trailing whitespace
* Convert tabs to spaces


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a76f04828ab32c70d2358fec18e4dd941d281c4e 19-Jan-2005 Chris Lattner <sabre@nondot.org> When commuting these instructions, make sure to actually swap the operands too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0df53d22c33c4b34ce1e61dd26eeaee1898c09c0 19-Jan-2005 Chris Lattner <sabre@nondot.org> Improve coverage of the X86 instruction set by adding 16-bit shift doubles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
41e431ba045eb317ebf0ec45b563a5d96c212f5c 19-Jan-2005 Chris Lattner <sabre@nondot.org> Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:

foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret

instead of this:

foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret

Note the magically transmogrifying immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5aee0b97aa46cb25ccfe157a3a5612d155519b28 02-Jan-2005 Chris Lattner <sabre@nondot.org> Disable 2->3 address promotion of add and inc instructions to LEA's. In
addition to being three address, LEA's don't set the flags.

This fixes 186.crafty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bcea4d6f283a5ae6f93dc8e10898311fe53d23a3 02-Jan-2005 Chris Lattner <sabre@nondot.org> Implement the convertToThreeAddress method, add support for inverting JP/JNP
branches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
bcdda01210155d23ce4b29abd830a8767e0289c9 01-Aug-2004 Chris Lattner <sabre@nondot.org> Fix a warning


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
31e155e610d6f506c64185bfa35c0b7ff729e025 31-Jul-2004 Alkis Evlogimenos <alkis@evlogimenos.com> Align breaks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
167cf33e1dba52b22af1e269ef0af2c33ac1dbf4 31-Jul-2004 Chris Lattner <sabre@nondot.org> Add breaks


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6103c1703c99eaec586d442a08868bf7e2555c56 31-Jul-2004 Alkis Evlogimenos <alkis@evlogimenos.com> Simplify code a bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
02a453074dc05910fefdc8eddf87514394145ab8 31-Jul-2004 Alkis Evlogimenos <alkis@evlogimenos.com> Correctly spell 'unconditional'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
36f506eddb25d5198240a1e3fabcb0912111c7ee 31-Jul-2004 Alkis Evlogimenos <alkis@evlogimenos.com> Implement insertGoto and reverseBranchCondition for the X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
8295f202d9cc37a6c325abd38e2feb5b47d7fc63 29-Feb-2004 Alkis Evlogimenos <alkis@evlogimenos.com> A big X86 instruction rename. The instructions are renamed to make
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dce363d5ecf0f6add5541c853eb33214d910812f 29-Feb-2004 Chris Lattner <sabre@nondot.org> Adjust to change in TII ctor arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
1ddf475b6a3d748427546ab8f65a712c8eea3a0f 29-Feb-2004 Chris Lattner <sabre@nondot.org> These two virtual methods are never called.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
890f92328d5478e050d2eba8f4de24737a04a812 22-Feb-2004 Alkis Evlogimenos <alkis@evlogimenos.com> Move MOTy::UseType enum into MachineOperand. This eliminates the
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
be766c72464116a445a02b542a450c4274bab5d0 13-Feb-2004 Alkis Evlogimenos <alkis@evlogimenos.com> Remove getAllocatedRegNum(). Use getReg() instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6d2151871889a4d4c22a0883a8ee667333f1cb0b 10-Feb-2004 Chris Lattner <sabre@nondot.org> Don't use MachineOperator::is(Phys|Virt)Register


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
0bbf3052c23180c9a1ab3ded796a5319f62fa53d 10-Feb-2004 Chris Lattner <sabre@nondot.org> Tighten up checks


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a1b6f95f78dcc093e6b4638badea956f4b67e6b7 01-Feb-2004 Alkis Evlogimenos <alkis@evlogimenos.com> FpMOV is also a move instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
5e30002af70ef09a42cac155d9196f7f0f3b1695 28-Dec-2003 Alkis Evlogimenos <alkis@evlogimenos.com> Add TargetInstrInfo::isMoveInstr() to support coalescing in register
allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
d0fde30ce850b78371fd1386338350591f9ff494 11-Nov-2003 Brian Gaeke <gaeke@uiuc.edu> Put all LLVM code into the llvm namespace, as per bug 109.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b576c94c15af9a440f69d9d03c2afead7971118c 20-Oct-2003 John Criswell <criswell@uiuc.edu> Added LLVM project notice to the top of every C++ source file.
Header files will be on the way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
abf05b2dae7b39df81c2e30c58042dd1a8c32148 03-Aug-2003 Chris Lattner <sabre@nondot.org> * Start using tablegen'd instruction descriptions
* Fix bug in the createNOP method, which was not marking the operands of the
generated XCHG as useanddef. I don't think this method is actually used,
so it wasn't breaking anything, but it should be fixed anyway...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
12745c55e1d5a6e76d41684f1b507ea7c6b888ac 24-May-2003 Misha Brukman <brukman+llvm@gmail.com> Reword to remove reference to how things worked in the past.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
e9d883828ad92f3a1d06e3c9e98c4e3df937197d 24-May-2003 Misha Brukman <brukman+llvm@gmail.com> Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
3501feab811c86c9659248a4875fc31a3165f84d 14-Jan-2003 Chris Lattner <sabre@nondot.org> Rename MachineInstrInfo -> TargetInstrInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b33922351835a3772f8a026baa6109045e26c2ae 18-Dec-2002 Chris Lattner <sabre@nondot.org> Add comments, switch uses/defs to match InstrInfo.def file


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
4ce42a776a98ec0cc8583ce8552eddbf835eb06e 03-Dec-2002 Chris Lattner <sabre@nondot.org> * Move information about Implicit Defs/Uses into X86InstrInfo.def.
* Expose information about implicit defs/uses of register through the
MachineInstrInfo.h file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
a85d6bc2bc282ab301a8c6531427cc3bf97b53ff 22-Nov-2002 Misha Brukman <brukman+llvm@gmail.com> Added -*- C++ -*- mode to the comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
f21dfcddcf199444440004bfa74bb222e2d3ce9e 18-Nov-2002 Chris Lattner <sabre@nondot.org> Expose base opcode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
6aab9cf65cd1e96f9d0fa99f8453da454648bba1 18-Nov-2002 Chris Lattner <sabre@nondot.org> Start to add more information to instr.def


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
dbb61c6445513f5cfd057c74da9e5c8299353c68 17-Nov-2002 Chris Lattner <sabre@nondot.org> Reorganize printing interface a bit


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
b752e9a2aee4165ab07f39a16bbc304e84451e01 30-Oct-2002 Chris Lattner <sabre@nondot.org> Set the destination register field based on the target specific flags


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
055c965bff7c8567e7fae90ffe1e10e109856064 29-Oct-2002 Chris Lattner <sabre@nondot.org> Rename X86InstructionInfo to X86InstrInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
33f53b554acfff0b15f08d551fce5b0701b443c0 29-Oct-2002 Chris Lattner <sabre@nondot.org> Minor renaming


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
9bbf439e388c1d015558815fc47a56919de5ae3b 29-Oct-2002 Chris Lattner <sabre@nondot.org> Implement MachineInstrInfo interface


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.cpp
726140821f96e3472a8eccef0c67c0b5ad65a1d9 26-Oct-2002 Chris Lattner <sabre@nondot.org> Initial checkin of X86 backend.
We can instruction select exactly one instruction 'ret void'. Wow.


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/external/llvm/lib/Target/X86/X86InstrInfo.cpp