X86InstrInfo.cpp revision 62c939d7d5572e57963a5f26fb6fe802e13dc0bf
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/CodeGen/MachineConstantPool.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/LiveVariables.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Target/TargetOptions.h" 29#include "llvm/Target/TargetAsmInfo.h" 30 31using namespace llvm; 32 33namespace { 34 cl::opt<bool> 35 NoFusing("disable-spill-fusing", 36 cl::desc("Disable fusing of spill code into instructions")); 37 cl::opt<bool> 38 PrintFailedFusing("print-failed-fuse-candidates", 39 cl::desc("Print instructions that the allocator wants to" 40 " fuse, but the X86 backend currently can't"), 41 cl::Hidden); 42 cl::opt<bool> 43 ReMatPICStubLoad("remat-pic-stub-load", 44 cl::desc("Re-materialize load from stub in PIC mode"), 45 cl::init(false), cl::Hidden); 46} 47 48X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 49 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 50 TM(tm), RI(tm, *this) { 51 SmallVector<unsigned,16> AmbEntries; 52 static const unsigned OpTbl2Addr[][2] = { 53 { X86::ADC32ri, X86::ADC32mi }, 54 { X86::ADC32ri8, X86::ADC32mi8 }, 55 { X86::ADC32rr, X86::ADC32mr }, 56 { X86::ADC64ri32, X86::ADC64mi32 }, 57 { X86::ADC64ri8, X86::ADC64mi8 }, 58 { X86::ADC64rr, X86::ADC64mr }, 59 { X86::ADD16ri, X86::ADD16mi }, 60 { X86::ADD16ri8, X86::ADD16mi8 }, 61 { X86::ADD16rr, X86::ADD16mr }, 62 { X86::ADD32ri, X86::ADD32mi }, 63 { X86::ADD32ri8, X86::ADD32mi8 }, 64 { X86::ADD32rr, X86::ADD32mr }, 65 { X86::ADD64ri32, X86::ADD64mi32 }, 66 { X86::ADD64ri8, X86::ADD64mi8 }, 67 { X86::ADD64rr, X86::ADD64mr }, 68 { X86::ADD8ri, X86::ADD8mi }, 69 { X86::ADD8rr, X86::ADD8mr }, 70 { X86::AND16ri, X86::AND16mi }, 71 { X86::AND16ri8, X86::AND16mi8 }, 72 { X86::AND16rr, X86::AND16mr }, 73 { X86::AND32ri, X86::AND32mi }, 74 { X86::AND32ri8, X86::AND32mi8 }, 75 { X86::AND32rr, X86::AND32mr }, 76 { X86::AND64ri32, X86::AND64mi32 }, 77 { X86::AND64ri8, X86::AND64mi8 }, 78 { X86::AND64rr, X86::AND64mr }, 79 { X86::AND8ri, X86::AND8mi }, 80 { X86::AND8rr, X86::AND8mr }, 81 { X86::DEC16r, X86::DEC16m }, 82 { X86::DEC32r, X86::DEC32m }, 83 { X86::DEC64_16r, X86::DEC64_16m }, 84 { X86::DEC64_32r, X86::DEC64_32m }, 85 { X86::DEC64r, X86::DEC64m }, 86 { X86::DEC8r, X86::DEC8m }, 87 { X86::INC16r, X86::INC16m }, 88 { X86::INC32r, X86::INC32m }, 89 { X86::INC64_16r, X86::INC64_16m }, 90 { X86::INC64_32r, X86::INC64_32m }, 91 { X86::INC64r, X86::INC64m }, 92 { X86::INC8r, X86::INC8m }, 93 { X86::NEG16r, X86::NEG16m }, 94 { X86::NEG32r, X86::NEG32m }, 95 { X86::NEG64r, X86::NEG64m }, 96 { X86::NEG8r, X86::NEG8m }, 97 { X86::NOT16r, X86::NOT16m }, 98 { X86::NOT32r, X86::NOT32m }, 99 { X86::NOT64r, X86::NOT64m }, 100 { X86::NOT8r, X86::NOT8m }, 101 { X86::OR16ri, X86::OR16mi }, 102 { X86::OR16ri8, X86::OR16mi8 }, 103 { X86::OR16rr, X86::OR16mr }, 104 { X86::OR32ri, X86::OR32mi }, 105 { X86::OR32ri8, X86::OR32mi8 }, 106 { X86::OR32rr, X86::OR32mr }, 107 { X86::OR64ri32, X86::OR64mi32 }, 108 { X86::OR64ri8, X86::OR64mi8 }, 109 { X86::OR64rr, X86::OR64mr }, 110 { X86::OR8ri, X86::OR8mi }, 111 { X86::OR8rr, X86::OR8mr }, 112 { X86::ROL16r1, X86::ROL16m1 }, 113 { X86::ROL16rCL, X86::ROL16mCL }, 114 { X86::ROL16ri, X86::ROL16mi }, 115 { X86::ROL32r1, X86::ROL32m1 }, 116 { X86::ROL32rCL, X86::ROL32mCL }, 117 { X86::ROL32ri, X86::ROL32mi }, 118 { X86::ROL64r1, X86::ROL64m1 }, 119 { X86::ROL64rCL, X86::ROL64mCL }, 120 { X86::ROL64ri, X86::ROL64mi }, 121 { X86::ROL8r1, X86::ROL8m1 }, 122 { X86::ROL8rCL, X86::ROL8mCL }, 123 { X86::ROL8ri, X86::ROL8mi }, 124 { X86::ROR16r1, X86::ROR16m1 }, 125 { X86::ROR16rCL, X86::ROR16mCL }, 126 { X86::ROR16ri, X86::ROR16mi }, 127 { X86::ROR32r1, X86::ROR32m1 }, 128 { X86::ROR32rCL, X86::ROR32mCL }, 129 { X86::ROR32ri, X86::ROR32mi }, 130 { X86::ROR64r1, X86::ROR64m1 }, 131 { X86::ROR64rCL, X86::ROR64mCL }, 132 { X86::ROR64ri, X86::ROR64mi }, 133 { X86::ROR8r1, X86::ROR8m1 }, 134 { X86::ROR8rCL, X86::ROR8mCL }, 135 { X86::ROR8ri, X86::ROR8mi }, 136 { X86::SAR16r1, X86::SAR16m1 }, 137 { X86::SAR16rCL, X86::SAR16mCL }, 138 { X86::SAR16ri, X86::SAR16mi }, 139 { X86::SAR32r1, X86::SAR32m1 }, 140 { X86::SAR32rCL, X86::SAR32mCL }, 141 { X86::SAR32ri, X86::SAR32mi }, 142 { X86::SAR64r1, X86::SAR64m1 }, 143 { X86::SAR64rCL, X86::SAR64mCL }, 144 { X86::SAR64ri, X86::SAR64mi }, 145 { X86::SAR8r1, X86::SAR8m1 }, 146 { X86::SAR8rCL, X86::SAR8mCL }, 147 { X86::SAR8ri, X86::SAR8mi }, 148 { X86::SBB32ri, X86::SBB32mi }, 149 { X86::SBB32ri8, X86::SBB32mi8 }, 150 { X86::SBB32rr, X86::SBB32mr }, 151 { X86::SBB64ri32, X86::SBB64mi32 }, 152 { X86::SBB64ri8, X86::SBB64mi8 }, 153 { X86::SBB64rr, X86::SBB64mr }, 154 { X86::SHL16rCL, X86::SHL16mCL }, 155 { X86::SHL16ri, X86::SHL16mi }, 156 { X86::SHL32rCL, X86::SHL32mCL }, 157 { X86::SHL32ri, X86::SHL32mi }, 158 { X86::SHL64rCL, X86::SHL64mCL }, 159 { X86::SHL64ri, X86::SHL64mi }, 160 { X86::SHL8rCL, X86::SHL8mCL }, 161 { X86::SHL8ri, X86::SHL8mi }, 162 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 163 { X86::SHLD16rri8, X86::SHLD16mri8 }, 164 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 165 { X86::SHLD32rri8, X86::SHLD32mri8 }, 166 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 167 { X86::SHLD64rri8, X86::SHLD64mri8 }, 168 { X86::SHR16r1, X86::SHR16m1 }, 169 { X86::SHR16rCL, X86::SHR16mCL }, 170 { X86::SHR16ri, X86::SHR16mi }, 171 { X86::SHR32r1, X86::SHR32m1 }, 172 { X86::SHR32rCL, X86::SHR32mCL }, 173 { X86::SHR32ri, X86::SHR32mi }, 174 { X86::SHR64r1, X86::SHR64m1 }, 175 { X86::SHR64rCL, X86::SHR64mCL }, 176 { X86::SHR64ri, X86::SHR64mi }, 177 { X86::SHR8r1, X86::SHR8m1 }, 178 { X86::SHR8rCL, X86::SHR8mCL }, 179 { X86::SHR8ri, X86::SHR8mi }, 180 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 181 { X86::SHRD16rri8, X86::SHRD16mri8 }, 182 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 183 { X86::SHRD32rri8, X86::SHRD32mri8 }, 184 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 185 { X86::SHRD64rri8, X86::SHRD64mri8 }, 186 { X86::SUB16ri, X86::SUB16mi }, 187 { X86::SUB16ri8, X86::SUB16mi8 }, 188 { X86::SUB16rr, X86::SUB16mr }, 189 { X86::SUB32ri, X86::SUB32mi }, 190 { X86::SUB32ri8, X86::SUB32mi8 }, 191 { X86::SUB32rr, X86::SUB32mr }, 192 { X86::SUB64ri32, X86::SUB64mi32 }, 193 { X86::SUB64ri8, X86::SUB64mi8 }, 194 { X86::SUB64rr, X86::SUB64mr }, 195 { X86::SUB8ri, X86::SUB8mi }, 196 { X86::SUB8rr, X86::SUB8mr }, 197 { X86::XOR16ri, X86::XOR16mi }, 198 { X86::XOR16ri8, X86::XOR16mi8 }, 199 { X86::XOR16rr, X86::XOR16mr }, 200 { X86::XOR32ri, X86::XOR32mi }, 201 { X86::XOR32ri8, X86::XOR32mi8 }, 202 { X86::XOR32rr, X86::XOR32mr }, 203 { X86::XOR64ri32, X86::XOR64mi32 }, 204 { X86::XOR64ri8, X86::XOR64mi8 }, 205 { X86::XOR64rr, X86::XOR64mr }, 206 { X86::XOR8ri, X86::XOR8mi }, 207 { X86::XOR8rr, X86::XOR8mr } 208 }; 209 210 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 211 unsigned RegOp = OpTbl2Addr[i][0]; 212 unsigned MemOp = OpTbl2Addr[i][1]; 213 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 214 MemOp)).second) 215 assert(false && "Duplicated entries?"); 216 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store 217 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 218 std::make_pair(RegOp, 219 AuxInfo))).second) 220 AmbEntries.push_back(MemOp); 221 } 222 223 // If the third value is 1, then it's folding either a load or a store. 224 static const unsigned OpTbl0[][3] = { 225 { X86::CALL32r, X86::CALL32m, 1 }, 226 { X86::CALL64r, X86::CALL64m, 1 }, 227 { X86::CMP16ri, X86::CMP16mi, 1 }, 228 { X86::CMP16ri8, X86::CMP16mi8, 1 }, 229 { X86::CMP16rr, X86::CMP16mr, 1 }, 230 { X86::CMP32ri, X86::CMP32mi, 1 }, 231 { X86::CMP32ri8, X86::CMP32mi8, 1 }, 232 { X86::CMP32rr, X86::CMP32mr, 1 }, 233 { X86::CMP64ri32, X86::CMP64mi32, 1 }, 234 { X86::CMP64ri8, X86::CMP64mi8, 1 }, 235 { X86::CMP64rr, X86::CMP64mr, 1 }, 236 { X86::CMP8ri, X86::CMP8mi, 1 }, 237 { X86::CMP8rr, X86::CMP8mr, 1 }, 238 { X86::DIV16r, X86::DIV16m, 1 }, 239 { X86::DIV32r, X86::DIV32m, 1 }, 240 { X86::DIV64r, X86::DIV64m, 1 }, 241 { X86::DIV8r, X86::DIV8m, 1 }, 242 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 }, 243 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 }, 244 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 }, 245 { X86::IDIV16r, X86::IDIV16m, 1 }, 246 { X86::IDIV32r, X86::IDIV32m, 1 }, 247 { X86::IDIV64r, X86::IDIV64m, 1 }, 248 { X86::IDIV8r, X86::IDIV8m, 1 }, 249 { X86::IMUL16r, X86::IMUL16m, 1 }, 250 { X86::IMUL32r, X86::IMUL32m, 1 }, 251 { X86::IMUL64r, X86::IMUL64m, 1 }, 252 { X86::IMUL8r, X86::IMUL8m, 1 }, 253 { X86::JMP32r, X86::JMP32m, 1 }, 254 { X86::JMP64r, X86::JMP64m, 1 }, 255 { X86::MOV16ri, X86::MOV16mi, 0 }, 256 { X86::MOV16rr, X86::MOV16mr, 0 }, 257 { X86::MOV16to16_, X86::MOV16_mr, 0 }, 258 { X86::MOV32ri, X86::MOV32mi, 0 }, 259 { X86::MOV32rr, X86::MOV32mr, 0 }, 260 { X86::MOV32to32_, X86::MOV32_mr, 0 }, 261 { X86::MOV64ri32, X86::MOV64mi32, 0 }, 262 { X86::MOV64rr, X86::MOV64mr, 0 }, 263 { X86::MOV8ri, X86::MOV8mi, 0 }, 264 { X86::MOV8rr, X86::MOV8mr, 0 }, 265 { X86::MOVAPDrr, X86::MOVAPDmr, 0 }, 266 { X86::MOVAPSrr, X86::MOVAPSmr, 0 }, 267 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 }, 268 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 }, 269 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 }, 270 { X86::MOVSDrr, X86::MOVSDmr, 0 }, 271 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 }, 272 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 }, 273 { X86::MOVSSrr, X86::MOVSSmr, 0 }, 274 { X86::MOVUPDrr, X86::MOVUPDmr, 0 }, 275 { X86::MOVUPSrr, X86::MOVUPSmr, 0 }, 276 { X86::MUL16r, X86::MUL16m, 1 }, 277 { X86::MUL32r, X86::MUL32m, 1 }, 278 { X86::MUL64r, X86::MUL64m, 1 }, 279 { X86::MUL8r, X86::MUL8m, 1 }, 280 { X86::SETAEr, X86::SETAEm, 0 }, 281 { X86::SETAr, X86::SETAm, 0 }, 282 { X86::SETBEr, X86::SETBEm, 0 }, 283 { X86::SETBr, X86::SETBm, 0 }, 284 { X86::SETCr, X86::SETCm, 0 }, 285 { X86::SETEr, X86::SETEm, 0 }, 286 { X86::SETGEr, X86::SETGEm, 0 }, 287 { X86::SETGr, X86::SETGm, 0 }, 288 { X86::SETLEr, X86::SETLEm, 0 }, 289 { X86::SETLr, X86::SETLm, 0 }, 290 { X86::SETNCr, X86::SETNCm, 0 }, 291 { X86::SETNEr, X86::SETNEm, 0 }, 292 { X86::SETNOr, X86::SETNOm, 0 }, 293 { X86::SETNPr, X86::SETNPm, 0 }, 294 { X86::SETNSr, X86::SETNSm, 0 }, 295 { X86::SETOr, X86::SETOm, 0 }, 296 { X86::SETPr, X86::SETPm, 0 }, 297 { X86::SETSr, X86::SETSm, 0 }, 298 { X86::TAILJMPr, X86::TAILJMPm, 1 }, 299 { X86::TEST16ri, X86::TEST16mi, 1 }, 300 { X86::TEST32ri, X86::TEST32mi, 1 }, 301 { X86::TEST64ri32, X86::TEST64mi32, 1 }, 302 { X86::TEST8ri, X86::TEST8mi, 1 } 303 }; 304 305 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 306 unsigned RegOp = OpTbl0[i][0]; 307 unsigned MemOp = OpTbl0[i][1]; 308 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 309 MemOp)).second) 310 assert(false && "Duplicated entries?"); 311 unsigned FoldedLoad = OpTbl0[i][2]; 312 // Index 0, folded load or store. 313 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 314 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 315 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 316 std::make_pair(RegOp, AuxInfo))).second) 317 AmbEntries.push_back(MemOp); 318 } 319 320 static const unsigned OpTbl1[][2] = { 321 { X86::CMP16rr, X86::CMP16rm }, 322 { X86::CMP32rr, X86::CMP32rm }, 323 { X86::CMP64rr, X86::CMP64rm }, 324 { X86::CMP8rr, X86::CMP8rm }, 325 { X86::CVTSD2SSrr, X86::CVTSD2SSrm }, 326 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm }, 327 { X86::CVTSI2SDrr, X86::CVTSI2SDrm }, 328 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm }, 329 { X86::CVTSI2SSrr, X86::CVTSI2SSrm }, 330 { X86::CVTSS2SDrr, X86::CVTSS2SDrm }, 331 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm }, 332 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm }, 333 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm }, 334 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm }, 335 { X86::FsMOVAPDrr, X86::MOVSDrm }, 336 { X86::FsMOVAPSrr, X86::MOVSSrm }, 337 { X86::IMUL16rri, X86::IMUL16rmi }, 338 { X86::IMUL16rri8, X86::IMUL16rmi8 }, 339 { X86::IMUL32rri, X86::IMUL32rmi }, 340 { X86::IMUL32rri8, X86::IMUL32rmi8 }, 341 { X86::IMUL64rri32, X86::IMUL64rmi32 }, 342 { X86::IMUL64rri8, X86::IMUL64rmi8 }, 343 { X86::Int_CMPSDrr, X86::Int_CMPSDrm }, 344 { X86::Int_CMPSSrr, X86::Int_CMPSSrm }, 345 { X86::Int_COMISDrr, X86::Int_COMISDrm }, 346 { X86::Int_COMISSrr, X86::Int_COMISSrm }, 347 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm }, 348 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm }, 349 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm }, 350 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm }, 351 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm }, 352 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm }, 353 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm }, 354 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm }, 355 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm }, 356 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm }, 357 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm }, 358 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm }, 359 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm }, 360 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm }, 361 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm }, 362 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm }, 363 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm }, 364 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm }, 365 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm }, 366 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm }, 367 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm }, 368 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm }, 369 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm }, 370 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm }, 371 { X86::MOV16rr, X86::MOV16rm }, 372 { X86::MOV16to16_, X86::MOV16_rm }, 373 { X86::MOV32rr, X86::MOV32rm }, 374 { X86::MOV32to32_, X86::MOV32_rm }, 375 { X86::MOV64rr, X86::MOV64rm }, 376 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm }, 377 { X86::MOV64toSDrr, X86::MOV64toSDrm }, 378 { X86::MOV8rr, X86::MOV8rm }, 379 { X86::MOVAPDrr, X86::MOVAPDrm }, 380 { X86::MOVAPSrr, X86::MOVAPSrm }, 381 { X86::MOVDDUPrr, X86::MOVDDUPrm }, 382 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, 383 { X86::MOVDI2SSrr, X86::MOVDI2SSrm }, 384 { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, 385 { X86::MOVSDrr, X86::MOVSDrm }, 386 { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, 387 { X86::MOVSLDUPrr, X86::MOVSLDUPrm }, 388 { X86::MOVSS2PSrr, X86::MOVSS2PSrm }, 389 { X86::MOVSSrr, X86::MOVSSrm }, 390 { X86::MOVSX16rr8, X86::MOVSX16rm8 }, 391 { X86::MOVSX32rr16, X86::MOVSX32rm16 }, 392 { X86::MOVSX32rr8, X86::MOVSX32rm8 }, 393 { X86::MOVSX64rr16, X86::MOVSX64rm16 }, 394 { X86::MOVSX64rr32, X86::MOVSX64rm32 }, 395 { X86::MOVSX64rr8, X86::MOVSX64rm8 }, 396 { X86::MOVUPDrr, X86::MOVUPDrm }, 397 { X86::MOVUPSrr, X86::MOVUPSrm }, 398 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm }, 399 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm }, 400 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm }, 401 { X86::MOVZX16rr8, X86::MOVZX16rm8 }, 402 { X86::MOVZX32rr16, X86::MOVZX32rm16 }, 403 { X86::MOVZX32rr8, X86::MOVZX32rm8 }, 404 { X86::MOVZX64rr16, X86::MOVZX64rm16 }, 405 { X86::MOVZX64rr32, X86::MOVZX64rm32 }, 406 { X86::MOVZX64rr8, X86::MOVZX64rm8 }, 407 { X86::PSHUFDri, X86::PSHUFDmi }, 408 { X86::PSHUFHWri, X86::PSHUFHWmi }, 409 { X86::PSHUFLWri, X86::PSHUFLWmi }, 410 { X86::RCPPSr, X86::RCPPSm }, 411 { X86::RCPPSr_Int, X86::RCPPSm_Int }, 412 { X86::RSQRTPSr, X86::RSQRTPSm }, 413 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int }, 414 { X86::RSQRTSSr, X86::RSQRTSSm }, 415 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int }, 416 { X86::SQRTPDr, X86::SQRTPDm }, 417 { X86::SQRTPDr_Int, X86::SQRTPDm_Int }, 418 { X86::SQRTPSr, X86::SQRTPSm }, 419 { X86::SQRTPSr_Int, X86::SQRTPSm_Int }, 420 { X86::SQRTSDr, X86::SQRTSDm }, 421 { X86::SQRTSDr_Int, X86::SQRTSDm_Int }, 422 { X86::SQRTSSr, X86::SQRTSSm }, 423 { X86::SQRTSSr_Int, X86::SQRTSSm_Int }, 424 { X86::TEST16rr, X86::TEST16rm }, 425 { X86::TEST32rr, X86::TEST32rm }, 426 { X86::TEST64rr, X86::TEST64rm }, 427 { X86::TEST8rr, X86::TEST8rm }, 428 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 429 { X86::UCOMISDrr, X86::UCOMISDrm }, 430 { X86::UCOMISSrr, X86::UCOMISSrm } 431 }; 432 433 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 434 unsigned RegOp = OpTbl1[i][0]; 435 unsigned MemOp = OpTbl1[i][1]; 436 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 437 MemOp)).second) 438 assert(false && "Duplicated entries?"); 439 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load 440 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 441 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 442 std::make_pair(RegOp, AuxInfo))).second) 443 AmbEntries.push_back(MemOp); 444 } 445 446 static const unsigned OpTbl2[][2] = { 447 { X86::ADC32rr, X86::ADC32rm }, 448 { X86::ADC64rr, X86::ADC64rm }, 449 { X86::ADD16rr, X86::ADD16rm }, 450 { X86::ADD32rr, X86::ADD32rm }, 451 { X86::ADD64rr, X86::ADD64rm }, 452 { X86::ADD8rr, X86::ADD8rm }, 453 { X86::ADDPDrr, X86::ADDPDrm }, 454 { X86::ADDPSrr, X86::ADDPSrm }, 455 { X86::ADDSDrr, X86::ADDSDrm }, 456 { X86::ADDSSrr, X86::ADDSSrm }, 457 { X86::ADDSUBPDrr, X86::ADDSUBPDrm }, 458 { X86::ADDSUBPSrr, X86::ADDSUBPSrm }, 459 { X86::AND16rr, X86::AND16rm }, 460 { X86::AND32rr, X86::AND32rm }, 461 { X86::AND64rr, X86::AND64rm }, 462 { X86::AND8rr, X86::AND8rm }, 463 { X86::ANDNPDrr, X86::ANDNPDrm }, 464 { X86::ANDNPSrr, X86::ANDNPSrm }, 465 { X86::ANDPDrr, X86::ANDPDrm }, 466 { X86::ANDPSrr, X86::ANDPSrm }, 467 { X86::CMOVA16rr, X86::CMOVA16rm }, 468 { X86::CMOVA32rr, X86::CMOVA32rm }, 469 { X86::CMOVA64rr, X86::CMOVA64rm }, 470 { X86::CMOVAE16rr, X86::CMOVAE16rm }, 471 { X86::CMOVAE32rr, X86::CMOVAE32rm }, 472 { X86::CMOVAE64rr, X86::CMOVAE64rm }, 473 { X86::CMOVB16rr, X86::CMOVB16rm }, 474 { X86::CMOVB32rr, X86::CMOVB32rm }, 475 { X86::CMOVB64rr, X86::CMOVB64rm }, 476 { X86::CMOVBE16rr, X86::CMOVBE16rm }, 477 { X86::CMOVBE32rr, X86::CMOVBE32rm }, 478 { X86::CMOVBE64rr, X86::CMOVBE64rm }, 479 { X86::CMOVE16rr, X86::CMOVE16rm }, 480 { X86::CMOVE32rr, X86::CMOVE32rm }, 481 { X86::CMOVE64rr, X86::CMOVE64rm }, 482 { X86::CMOVG16rr, X86::CMOVG16rm }, 483 { X86::CMOVG32rr, X86::CMOVG32rm }, 484 { X86::CMOVG64rr, X86::CMOVG64rm }, 485 { X86::CMOVGE16rr, X86::CMOVGE16rm }, 486 { X86::CMOVGE32rr, X86::CMOVGE32rm }, 487 { X86::CMOVGE64rr, X86::CMOVGE64rm }, 488 { X86::CMOVL16rr, X86::CMOVL16rm }, 489 { X86::CMOVL32rr, X86::CMOVL32rm }, 490 { X86::CMOVL64rr, X86::CMOVL64rm }, 491 { X86::CMOVLE16rr, X86::CMOVLE16rm }, 492 { X86::CMOVLE32rr, X86::CMOVLE32rm }, 493 { X86::CMOVLE64rr, X86::CMOVLE64rm }, 494 { X86::CMOVNE16rr, X86::CMOVNE16rm }, 495 { X86::CMOVNE32rr, X86::CMOVNE32rm }, 496 { X86::CMOVNE64rr, X86::CMOVNE64rm }, 497 { X86::CMOVNP16rr, X86::CMOVNP16rm }, 498 { X86::CMOVNP32rr, X86::CMOVNP32rm }, 499 { X86::CMOVNP64rr, X86::CMOVNP64rm }, 500 { X86::CMOVNS16rr, X86::CMOVNS16rm }, 501 { X86::CMOVNS32rr, X86::CMOVNS32rm }, 502 { X86::CMOVNS64rr, X86::CMOVNS64rm }, 503 { X86::CMOVP16rr, X86::CMOVP16rm }, 504 { X86::CMOVP32rr, X86::CMOVP32rm }, 505 { X86::CMOVP64rr, X86::CMOVP64rm }, 506 { X86::CMOVS16rr, X86::CMOVS16rm }, 507 { X86::CMOVS32rr, X86::CMOVS32rm }, 508 { X86::CMOVS64rr, X86::CMOVS64rm }, 509 { X86::CMPPDrri, X86::CMPPDrmi }, 510 { X86::CMPPSrri, X86::CMPPSrmi }, 511 { X86::CMPSDrr, X86::CMPSDrm }, 512 { X86::CMPSSrr, X86::CMPSSrm }, 513 { X86::DIVPDrr, X86::DIVPDrm }, 514 { X86::DIVPSrr, X86::DIVPSrm }, 515 { X86::DIVSDrr, X86::DIVSDrm }, 516 { X86::DIVSSrr, X86::DIVSSrm }, 517 { X86::FsANDNPDrr, X86::FsANDNPDrm }, 518 { X86::FsANDNPSrr, X86::FsANDNPSrm }, 519 { X86::FsANDPDrr, X86::FsANDPDrm }, 520 { X86::FsANDPSrr, X86::FsANDPSrm }, 521 { X86::FsORPDrr, X86::FsORPDrm }, 522 { X86::FsORPSrr, X86::FsORPSrm }, 523 { X86::FsXORPDrr, X86::FsXORPDrm }, 524 { X86::FsXORPSrr, X86::FsXORPSrm }, 525 { X86::HADDPDrr, X86::HADDPDrm }, 526 { X86::HADDPSrr, X86::HADDPSrm }, 527 { X86::HSUBPDrr, X86::HSUBPDrm }, 528 { X86::HSUBPSrr, X86::HSUBPSrm }, 529 { X86::IMUL16rr, X86::IMUL16rm }, 530 { X86::IMUL32rr, X86::IMUL32rm }, 531 { X86::IMUL64rr, X86::IMUL64rm }, 532 { X86::MAXPDrr, X86::MAXPDrm }, 533 { X86::MAXPDrr_Int, X86::MAXPDrm_Int }, 534 { X86::MAXPSrr, X86::MAXPSrm }, 535 { X86::MAXPSrr_Int, X86::MAXPSrm_Int }, 536 { X86::MAXSDrr, X86::MAXSDrm }, 537 { X86::MAXSDrr_Int, X86::MAXSDrm_Int }, 538 { X86::MAXSSrr, X86::MAXSSrm }, 539 { X86::MAXSSrr_Int, X86::MAXSSrm_Int }, 540 { X86::MINPDrr, X86::MINPDrm }, 541 { X86::MINPDrr_Int, X86::MINPDrm_Int }, 542 { X86::MINPSrr, X86::MINPSrm }, 543 { X86::MINPSrr_Int, X86::MINPSrm_Int }, 544 { X86::MINSDrr, X86::MINSDrm }, 545 { X86::MINSDrr_Int, X86::MINSDrm_Int }, 546 { X86::MINSSrr, X86::MINSSrm }, 547 { X86::MINSSrr_Int, X86::MINSSrm_Int }, 548 { X86::MULPDrr, X86::MULPDrm }, 549 { X86::MULPSrr, X86::MULPSrm }, 550 { X86::MULSDrr, X86::MULSDrm }, 551 { X86::MULSSrr, X86::MULSSrm }, 552 { X86::OR16rr, X86::OR16rm }, 553 { X86::OR32rr, X86::OR32rm }, 554 { X86::OR64rr, X86::OR64rm }, 555 { X86::OR8rr, X86::OR8rm }, 556 { X86::ORPDrr, X86::ORPDrm }, 557 { X86::ORPSrr, X86::ORPSrm }, 558 { X86::PACKSSDWrr, X86::PACKSSDWrm }, 559 { X86::PACKSSWBrr, X86::PACKSSWBrm }, 560 { X86::PACKUSWBrr, X86::PACKUSWBrm }, 561 { X86::PADDBrr, X86::PADDBrm }, 562 { X86::PADDDrr, X86::PADDDrm }, 563 { X86::PADDQrr, X86::PADDQrm }, 564 { X86::PADDSBrr, X86::PADDSBrm }, 565 { X86::PADDSWrr, X86::PADDSWrm }, 566 { X86::PADDWrr, X86::PADDWrm }, 567 { X86::PANDNrr, X86::PANDNrm }, 568 { X86::PANDrr, X86::PANDrm }, 569 { X86::PAVGBrr, X86::PAVGBrm }, 570 { X86::PAVGWrr, X86::PAVGWrm }, 571 { X86::PCMPEQBrr, X86::PCMPEQBrm }, 572 { X86::PCMPEQDrr, X86::PCMPEQDrm }, 573 { X86::PCMPEQWrr, X86::PCMPEQWrm }, 574 { X86::PCMPGTBrr, X86::PCMPGTBrm }, 575 { X86::PCMPGTDrr, X86::PCMPGTDrm }, 576 { X86::PCMPGTWrr, X86::PCMPGTWrm }, 577 { X86::PINSRWrri, X86::PINSRWrmi }, 578 { X86::PMADDWDrr, X86::PMADDWDrm }, 579 { X86::PMAXSWrr, X86::PMAXSWrm }, 580 { X86::PMAXUBrr, X86::PMAXUBrm }, 581 { X86::PMINSWrr, X86::PMINSWrm }, 582 { X86::PMINUBrr, X86::PMINUBrm }, 583 { X86::PMULDQrr, X86::PMULDQrm }, 584 { X86::PMULDQrr_int, X86::PMULDQrm_int }, 585 { X86::PMULHUWrr, X86::PMULHUWrm }, 586 { X86::PMULHWrr, X86::PMULHWrm }, 587 { X86::PMULLDrr, X86::PMULLDrm }, 588 { X86::PMULLDrr_int, X86::PMULLDrm_int }, 589 { X86::PMULLWrr, X86::PMULLWrm }, 590 { X86::PMULUDQrr, X86::PMULUDQrm }, 591 { X86::PORrr, X86::PORrm }, 592 { X86::PSADBWrr, X86::PSADBWrm }, 593 { X86::PSLLDrr, X86::PSLLDrm }, 594 { X86::PSLLQrr, X86::PSLLQrm }, 595 { X86::PSLLWrr, X86::PSLLWrm }, 596 { X86::PSRADrr, X86::PSRADrm }, 597 { X86::PSRAWrr, X86::PSRAWrm }, 598 { X86::PSRLDrr, X86::PSRLDrm }, 599 { X86::PSRLQrr, X86::PSRLQrm }, 600 { X86::PSRLWrr, X86::PSRLWrm }, 601 { X86::PSUBBrr, X86::PSUBBrm }, 602 { X86::PSUBDrr, X86::PSUBDrm }, 603 { X86::PSUBSBrr, X86::PSUBSBrm }, 604 { X86::PSUBSWrr, X86::PSUBSWrm }, 605 { X86::PSUBWrr, X86::PSUBWrm }, 606 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm }, 607 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm }, 608 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm }, 609 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm }, 610 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm }, 611 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm }, 612 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm }, 613 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm }, 614 { X86::PXORrr, X86::PXORrm }, 615 { X86::SBB32rr, X86::SBB32rm }, 616 { X86::SBB64rr, X86::SBB64rm }, 617 { X86::SHUFPDrri, X86::SHUFPDrmi }, 618 { X86::SHUFPSrri, X86::SHUFPSrmi }, 619 { X86::SUB16rr, X86::SUB16rm }, 620 { X86::SUB32rr, X86::SUB32rm }, 621 { X86::SUB64rr, X86::SUB64rm }, 622 { X86::SUB8rr, X86::SUB8rm }, 623 { X86::SUBPDrr, X86::SUBPDrm }, 624 { X86::SUBPSrr, X86::SUBPSrm }, 625 { X86::SUBSDrr, X86::SUBSDrm }, 626 { X86::SUBSSrr, X86::SUBSSrm }, 627 // FIXME: TEST*rr -> swapped operand of TEST*mr. 628 { X86::UNPCKHPDrr, X86::UNPCKHPDrm }, 629 { X86::UNPCKHPSrr, X86::UNPCKHPSrm }, 630 { X86::UNPCKLPDrr, X86::UNPCKLPDrm }, 631 { X86::UNPCKLPSrr, X86::UNPCKLPSrm }, 632 { X86::XOR16rr, X86::XOR16rm }, 633 { X86::XOR32rr, X86::XOR32rm }, 634 { X86::XOR64rr, X86::XOR64rm }, 635 { X86::XOR8rr, X86::XOR8rm }, 636 { X86::XORPDrr, X86::XORPDrm }, 637 { X86::XORPSrr, X86::XORPSrm } 638 }; 639 640 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 641 unsigned RegOp = OpTbl2[i][0]; 642 unsigned MemOp = OpTbl2[i][1]; 643 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 644 MemOp)).second) 645 assert(false && "Duplicated entries?"); 646 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load 647 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 648 std::make_pair(RegOp, AuxInfo))).second) 649 AmbEntries.push_back(MemOp); 650 } 651 652 // Remove ambiguous entries. 653 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 654} 655 656bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 657 unsigned& sourceReg, 658 unsigned& destReg) const { 659 switch (MI.getOpcode()) { 660 default: 661 return false; 662 case X86::MOV8rr: 663 case X86::MOV16rr: 664 case X86::MOV32rr: 665 case X86::MOV64rr: 666 case X86::MOV16to16_: 667 case X86::MOV32to32_: 668 case X86::MOVSSrr: 669 case X86::MOVSDrr: 670 671 // FP Stack register class copies 672 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: 673 case X86::MOV_Fp3264: case X86::MOV_Fp3280: 674 case X86::MOV_Fp6432: case X86::MOV_Fp8032: 675 676 case X86::FsMOVAPSrr: 677 case X86::FsMOVAPDrr: 678 case X86::MOVAPSrr: 679 case X86::MOVAPDrr: 680 case X86::MOVSS2PSrr: 681 case X86::MOVSD2PDrr: 682 case X86::MOVPS2SSrr: 683 case X86::MOVPD2SDrr: 684 case X86::MMX_MOVD64rr: 685 case X86::MMX_MOVQ64rr: 686 assert(MI.getNumOperands() >= 2 && 687 MI.getOperand(0).isReg() && 688 MI.getOperand(1).isReg() && 689 "invalid register-register move instruction"); 690 sourceReg = MI.getOperand(1).getReg(); 691 destReg = MI.getOperand(0).getReg(); 692 return true; 693 } 694} 695 696unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 697 int &FrameIndex) const { 698 switch (MI->getOpcode()) { 699 default: break; 700 case X86::MOV8rm: 701 case X86::MOV16rm: 702 case X86::MOV16_rm: 703 case X86::MOV32rm: 704 case X86::MOV32_rm: 705 case X86::MOV64rm: 706 case X86::LD_Fp64m: 707 case X86::MOVSSrm: 708 case X86::MOVSDrm: 709 case X86::MOVAPSrm: 710 case X86::MOVAPDrm: 711 case X86::MMX_MOVD64rm: 712 case X86::MMX_MOVQ64rm: 713 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 714 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() && 715 MI->getOperand(2).getImm() == 1 && 716 MI->getOperand(3).getReg() == 0 && 717 MI->getOperand(4).getImm() == 0) { 718 FrameIndex = MI->getOperand(1).getIndex(); 719 return MI->getOperand(0).getReg(); 720 } 721 break; 722 } 723 return 0; 724} 725 726unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 727 int &FrameIndex) const { 728 switch (MI->getOpcode()) { 729 default: break; 730 case X86::MOV8mr: 731 case X86::MOV16mr: 732 case X86::MOV16_mr: 733 case X86::MOV32mr: 734 case X86::MOV32_mr: 735 case X86::MOV64mr: 736 case X86::ST_FpP64m: 737 case X86::MOVSSmr: 738 case X86::MOVSDmr: 739 case X86::MOVAPSmr: 740 case X86::MOVAPDmr: 741 case X86::MMX_MOVD64mr: 742 case X86::MMX_MOVQ64mr: 743 case X86::MMX_MOVNTQmr: 744 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 745 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() && 746 MI->getOperand(1).getImm() == 1 && 747 MI->getOperand(2).getReg() == 0 && 748 MI->getOperand(3).getImm() == 0) { 749 FrameIndex = MI->getOperand(0).getIndex(); 750 return MI->getOperand(4).getReg(); 751 } 752 break; 753 } 754 return 0; 755} 756 757 758/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 759/// X86::MOVPC32r. 760static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 761 bool isPICBase = false; 762 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 763 E = MRI.def_end(); I != E; ++I) { 764 MachineInstr *DefMI = I.getOperand().getParent(); 765 if (DefMI->getOpcode() != X86::MOVPC32r) 766 return false; 767 assert(!isPICBase && "More than one PIC base?"); 768 isPICBase = true; 769 } 770 return isPICBase; 771} 772 773/// isGVStub - Return true if the GV requires an extra load to get the 774/// real address. 775static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) { 776 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false); 777} 778 779bool 780X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 781 switch (MI->getOpcode()) { 782 default: break; 783 case X86::MOV8rm: 784 case X86::MOV16rm: 785 case X86::MOV16_rm: 786 case X86::MOV32rm: 787 case X86::MOV32_rm: 788 case X86::MOV64rm: 789 case X86::LD_Fp64m: 790 case X86::MOVSSrm: 791 case X86::MOVSDrm: 792 case X86::MOVAPSrm: 793 case X86::MOVAPDrm: 794 case X86::MMX_MOVD64rm: 795 case X86::MMX_MOVQ64rm: { 796 // Loads from constant pools are trivially rematerializable. 797 if (MI->getOperand(1).isReg() && 798 MI->getOperand(2).isImm() && 799 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 800 (MI->getOperand(4).isCPI() || 801 (MI->getOperand(4).isGlobal() && 802 isGVStub(MI->getOperand(4).getGlobal(), TM)))) { 803 unsigned BaseReg = MI->getOperand(1).getReg(); 804 if (BaseReg == 0) 805 return true; 806 // Allow re-materialization of PIC load. 807 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 808 return false; 809 const MachineFunction &MF = *MI->getParent()->getParent(); 810 const MachineRegisterInfo &MRI = MF.getRegInfo(); 811 bool isPICBase = false; 812 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 813 E = MRI.def_end(); I != E; ++I) { 814 MachineInstr *DefMI = I.getOperand().getParent(); 815 if (DefMI->getOpcode() != X86::MOVPC32r) 816 return false; 817 assert(!isPICBase && "More than one PIC base?"); 818 isPICBase = true; 819 } 820 return isPICBase; 821 } 822 return false; 823 } 824 825 case X86::LEA32r: 826 case X86::LEA64r: { 827 if (MI->getOperand(2).isImm() && 828 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 829 !MI->getOperand(4).isReg()) { 830 // lea fi#, lea GV, etc. are all rematerializable. 831 if (!MI->getOperand(1).isReg()) 832 return true; 833 unsigned BaseReg = MI->getOperand(1).getReg(); 834 if (BaseReg == 0) 835 return true; 836 // Allow re-materialization of lea PICBase + x. 837 const MachineFunction &MF = *MI->getParent()->getParent(); 838 const MachineRegisterInfo &MRI = MF.getRegInfo(); 839 return regIsPICBase(BaseReg, MRI); 840 } 841 return false; 842 } 843 } 844 845 // All other instructions marked M_REMATERIALIZABLE are always trivially 846 // rematerializable. 847 return true; 848} 849 850/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 851/// would clobber the EFLAGS condition register. Note the result may be 852/// conservative. If it cannot definitely determine the safety after visiting 853/// two instructions it assumes it's not safe. 854static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 855 MachineBasicBlock::iterator I) { 856 // It's always safe to clobber EFLAGS at the end of a block. 857 if (I == MBB.end()) 858 return true; 859 860 // For compile time consideration, if we are not able to determine the 861 // safety after visiting 2 instructions, we will assume it's not safe. 862 for (unsigned i = 0; i < 2; ++i) { 863 bool SeenDef = false; 864 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) { 865 MachineOperand &MO = I->getOperand(j); 866 if (!MO.isReg()) 867 continue; 868 if (MO.getReg() == X86::EFLAGS) { 869 if (MO.isUse()) 870 return false; 871 SeenDef = true; 872 } 873 } 874 875 if (SeenDef) 876 // This instruction defines EFLAGS, no need to look any further. 877 return true; 878 ++I; 879 880 // If we make it to the end of the block, it's safe to clobber EFLAGS. 881 if (I == MBB.end()) 882 return true; 883 } 884 885 // Conservative answer. 886 return false; 887} 888 889void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 890 MachineBasicBlock::iterator I, 891 unsigned DestReg, 892 const MachineInstr *Orig) const { 893 unsigned SubIdx = Orig->getOperand(0).isReg() 894 ? Orig->getOperand(0).getSubReg() : 0; 895 bool ChangeSubIdx = SubIdx != 0; 896 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) { 897 DestReg = RI.getSubReg(DestReg, SubIdx); 898 SubIdx = 0; 899 } 900 901 // MOV32r0 etc. are implemented with xor which clobbers condition code. 902 // Re-materialize them as movri instructions to avoid side effects. 903 bool Emitted = false; 904 switch (Orig->getOpcode()) { 905 default: break; 906 case X86::MOV8r0: 907 case X86::MOV16r0: 908 case X86::MOV32r0: 909 case X86::MOV64r0: { 910 if (!isSafeToClobberEFLAGS(MBB, I)) { 911 unsigned Opc = 0; 912 switch (Orig->getOpcode()) { 913 default: break; 914 case X86::MOV8r0: Opc = X86::MOV8ri; break; 915 case X86::MOV16r0: Opc = X86::MOV16ri; break; 916 case X86::MOV32r0: Opc = X86::MOV32ri; break; 917 case X86::MOV64r0: Opc = X86::MOV64ri32; break; 918 } 919 BuildMI(MBB, I, get(Opc), DestReg).addImm(0); 920 Emitted = true; 921 } 922 break; 923 } 924 } 925 926 if (!Emitted) { 927 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 928 MI->getOperand(0).setReg(DestReg); 929 MBB.insert(I, MI); 930 } 931 932 if (ChangeSubIdx) { 933 MachineInstr *NewMI = prior(I); 934 NewMI->getOperand(0).setSubReg(SubIdx); 935 } 936} 937 938/// isInvariantLoad - Return true if the specified instruction (which is marked 939/// mayLoad) is loading from a location whose value is invariant across the 940/// function. For example, loading a value from the constant pool or from 941/// from the argument area of a function if it does not change. This should 942/// only return true of *all* loads the instruction does are invariant (if it 943/// does multiple loads). 944bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const { 945 // This code cares about loads from three cases: constant pool entries, 946 // invariant argument slots, and global stubs. In order to handle these cases 947 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV 948 // operand and base our analysis on it. This is safe because the address of 949 // none of these three cases is ever used as anything other than a load base 950 // and X86 doesn't have any instructions that load from multiple places. 951 952 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 953 const MachineOperand &MO = MI->getOperand(i); 954 // Loads from constant pools are trivially invariant. 955 if (MO.isCPI()) 956 return true; 957 958 if (MO.isGlobal()) 959 return isGVStub(MO.getGlobal(), TM); 960 961 // If this is a load from an invariant stack slot, the load is a constant. 962 if (MO.isFI()) { 963 const MachineFrameInfo &MFI = 964 *MI->getParent()->getParent()->getFrameInfo(); 965 int Idx = MO.getIndex(); 966 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx); 967 } 968 } 969 970 // All other instances of these instructions are presumed to have other 971 // issues. 972 return false; 973} 974 975/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 976/// is not marked dead. 977static bool hasLiveCondCodeDef(MachineInstr *MI) { 978 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 979 MachineOperand &MO = MI->getOperand(i); 980 if (MO.isReg() && MO.isDef() && 981 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 982 return true; 983 } 984 } 985 return false; 986} 987 988/// convertToThreeAddress - This method must be implemented by targets that 989/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 990/// may be able to convert a two-address instruction into a true 991/// three-address instruction on demand. This allows the X86 target (for 992/// example) to convert ADD and SHL instructions into LEA instructions if they 993/// would require register copies due to two-addressness. 994/// 995/// This method returns a null pointer if the transformation cannot be 996/// performed, otherwise it returns the new instruction. 997/// 998MachineInstr * 999X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1000 MachineBasicBlock::iterator &MBBI, 1001 LiveVariables *LV) const { 1002 MachineInstr *MI = MBBI; 1003 MachineFunction &MF = *MI->getParent()->getParent(); 1004 // All instructions input are two-addr instructions. Get the known operands. 1005 unsigned Dest = MI->getOperand(0).getReg(); 1006 unsigned Src = MI->getOperand(1).getReg(); 1007 bool isDead = MI->getOperand(0).isDead(); 1008 bool isKill = MI->getOperand(1).isKill(); 1009 1010 MachineInstr *NewMI = NULL; 1011 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1012 // we have better subtarget support, enable the 16-bit LEA generation here. 1013 bool DisableLEA16 = true; 1014 1015 unsigned MIOpc = MI->getOpcode(); 1016 switch (MIOpc) { 1017 case X86::SHUFPSrri: { 1018 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1019 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1020 1021 unsigned B = MI->getOperand(1).getReg(); 1022 unsigned C = MI->getOperand(2).getReg(); 1023 if (B != C) return 0; 1024 unsigned A = MI->getOperand(0).getReg(); 1025 unsigned M = MI->getOperand(3).getImm(); 1026 NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead) 1027 .addReg(B, false, false, isKill).addImm(M); 1028 break; 1029 } 1030 case X86::SHL64ri: { 1031 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1032 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1033 // the flags produced by a shift yet, so this is safe. 1034 unsigned ShAmt = MI->getOperand(2).getImm(); 1035 if (ShAmt == 0 || ShAmt >= 4) return 0; 1036 1037 NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead) 1038 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0); 1039 break; 1040 } 1041 case X86::SHL32ri: { 1042 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1043 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1044 // the flags produced by a shift yet, so this is safe. 1045 unsigned ShAmt = MI->getOperand(2).getImm(); 1046 if (ShAmt == 0 || ShAmt >= 4) return 0; 1047 1048 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? 1049 X86::LEA64_32r : X86::LEA32r; 1050 NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead) 1051 .addReg(0).addImm(1 << ShAmt) 1052 .addReg(Src, false, false, isKill).addImm(0); 1053 break; 1054 } 1055 case X86::SHL16ri: { 1056 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1057 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1058 // the flags produced by a shift yet, so this is safe. 1059 unsigned ShAmt = MI->getOperand(2).getImm(); 1060 if (ShAmt == 0 || ShAmt >= 4) return 0; 1061 1062 if (DisableLEA16) { 1063 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. 1064 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1065 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1066 ? X86::LEA64_32r : X86::LEA32r; 1067 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1068 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1069 1070 // Build and insert into an implicit UNDEF value. This is OK because 1071 // well be shifting and then extracting the lower 16-bits. 1072 BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg); 1073 MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg) 1074 .addReg(leaInReg).addReg(Src, false, false, isKill) 1075 .addImm(X86::SUBREG_16BIT); 1076 1077 NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt) 1078 .addReg(leaInReg, false, false, true).addImm(0); 1079 1080 MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG)) 1081 .addReg(Dest, true, false, false, isDead) 1082 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT); 1083 if (LV) { 1084 // Update live variables 1085 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1086 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1087 if (isKill) 1088 LV->replaceKillInstruction(Src, MI, InsMI); 1089 if (isDead) 1090 LV->replaceKillInstruction(Dest, MI, ExtMI); 1091 } 1092 return ExtMI; 1093 } else { 1094 NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead) 1095 .addReg(0).addImm(1 << ShAmt) 1096 .addReg(Src, false, false, isKill).addImm(0); 1097 } 1098 break; 1099 } 1100 default: { 1101 // The following opcodes also sets the condition code register(s). Only 1102 // convert them to equivalent lea if the condition code register def's 1103 // are dead! 1104 if (hasLiveCondCodeDef(MI)) 1105 return 0; 1106 1107 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1108 switch (MIOpc) { 1109 default: return 0; 1110 case X86::INC64r: 1111 case X86::INC32r: { 1112 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1113 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1114 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1115 NewMI = addRegOffset(BuildMI(MF, get(Opc)) 1116 .addReg(Dest, true, false, false, isDead), 1117 Src, isKill, 1); 1118 break; 1119 } 1120 case X86::INC16r: 1121 case X86::INC64_16r: 1122 if (DisableLEA16) return 0; 1123 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1124 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) 1125 .addReg(Dest, true, false, false, isDead), 1126 Src, isKill, 1); 1127 break; 1128 case X86::DEC64r: 1129 case X86::DEC32r: { 1130 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1131 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1132 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1133 NewMI = addRegOffset(BuildMI(MF, get(Opc)) 1134 .addReg(Dest, true, false, false, isDead), 1135 Src, isKill, -1); 1136 break; 1137 } 1138 case X86::DEC16r: 1139 case X86::DEC64_16r: 1140 if (DisableLEA16) return 0; 1141 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1142 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) 1143 .addReg(Dest, true, false, false, isDead), 1144 Src, isKill, -1); 1145 break; 1146 case X86::ADD64rr: 1147 case X86::ADD32rr: { 1148 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1149 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1150 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1151 unsigned Src2 = MI->getOperand(2).getReg(); 1152 bool isKill2 = MI->getOperand(2).isKill(); 1153 NewMI = addRegReg(BuildMI(MF, get(Opc)) 1154 .addReg(Dest, true, false, false, isDead), 1155 Src, isKill, Src2, isKill2); 1156 if (LV && isKill2) 1157 LV->replaceKillInstruction(Src2, MI, NewMI); 1158 break; 1159 } 1160 case X86::ADD16rr: { 1161 if (DisableLEA16) return 0; 1162 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1163 unsigned Src2 = MI->getOperand(2).getReg(); 1164 bool isKill2 = MI->getOperand(2).isKill(); 1165 NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r)) 1166 .addReg(Dest, true, false, false, isDead), 1167 Src, isKill, Src2, isKill2); 1168 if (LV && isKill2) 1169 LV->replaceKillInstruction(Src2, MI, NewMI); 1170 break; 1171 } 1172 case X86::ADD64ri32: 1173 case X86::ADD64ri8: 1174 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1175 if (MI->getOperand(2).isImm()) 1176 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r)) 1177 .addReg(Dest, true, false, false, isDead), 1178 Src, isKill, MI->getOperand(2).getImm()); 1179 break; 1180 case X86::ADD32ri: 1181 case X86::ADD32ri8: 1182 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1183 if (MI->getOperand(2).isImm()) { 1184 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1185 NewMI = addRegOffset(BuildMI(MF, get(Opc)) 1186 .addReg(Dest, true, false, false, isDead), 1187 Src, isKill, MI->getOperand(2).getImm()); 1188 } 1189 break; 1190 case X86::ADD16ri: 1191 case X86::ADD16ri8: 1192 if (DisableLEA16) return 0; 1193 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1194 if (MI->getOperand(2).isImm()) 1195 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) 1196 .addReg(Dest, true, false, false, isDead), 1197 Src, isKill, MI->getOperand(2).getImm()); 1198 break; 1199 case X86::SHL16ri: 1200 if (DisableLEA16) return 0; 1201 case X86::SHL32ri: 1202 case X86::SHL64ri: { 1203 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() && 1204 "Unknown shl instruction!"); 1205 unsigned ShAmt = MI->getOperand(2).getImm(); 1206 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { 1207 X86AddressMode AM; 1208 AM.Scale = 1 << ShAmt; 1209 AM.IndexReg = Src; 1210 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r 1211 : (MIOpc == X86::SHL32ri 1212 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); 1213 NewMI = addFullAddress(BuildMI(MF, get(Opc)) 1214 .addReg(Dest, true, false, false, isDead), AM); 1215 if (isKill) 1216 NewMI->getOperand(3).setIsKill(true); 1217 } 1218 break; 1219 } 1220 } 1221 } 1222 } 1223 1224 if (!NewMI) return 0; 1225 1226 if (LV) { // Update live variables 1227 if (isKill) 1228 LV->replaceKillInstruction(Src, MI, NewMI); 1229 if (isDead) 1230 LV->replaceKillInstruction(Dest, MI, NewMI); 1231 } 1232 1233 MFI->insert(MBBI, NewMI); // Insert the new inst 1234 return NewMI; 1235} 1236 1237/// commuteInstruction - We have a few instructions that must be hacked on to 1238/// commute them. 1239/// 1240MachineInstr * 1241X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1242 switch (MI->getOpcode()) { 1243 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1244 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1245 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1246 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1247 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1248 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1249 unsigned Opc; 1250 unsigned Size; 1251 switch (MI->getOpcode()) { 1252 default: assert(0 && "Unreachable!"); 1253 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1254 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1255 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1256 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1257 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1258 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1259 } 1260 unsigned Amt = MI->getOperand(3).getImm(); 1261 if (NewMI) { 1262 MachineFunction &MF = *MI->getParent()->getParent(); 1263 MI = MF.CloneMachineInstr(MI); 1264 NewMI = false; 1265 } 1266 MI->setDesc(get(Opc)); 1267 MI->getOperand(3).setImm(Size-Amt); 1268 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1269 } 1270 case X86::CMOVB16rr: 1271 case X86::CMOVB32rr: 1272 case X86::CMOVB64rr: 1273 case X86::CMOVAE16rr: 1274 case X86::CMOVAE32rr: 1275 case X86::CMOVAE64rr: 1276 case X86::CMOVE16rr: 1277 case X86::CMOVE32rr: 1278 case X86::CMOVE64rr: 1279 case X86::CMOVNE16rr: 1280 case X86::CMOVNE32rr: 1281 case X86::CMOVNE64rr: 1282 case X86::CMOVBE16rr: 1283 case X86::CMOVBE32rr: 1284 case X86::CMOVBE64rr: 1285 case X86::CMOVA16rr: 1286 case X86::CMOVA32rr: 1287 case X86::CMOVA64rr: 1288 case X86::CMOVL16rr: 1289 case X86::CMOVL32rr: 1290 case X86::CMOVL64rr: 1291 case X86::CMOVGE16rr: 1292 case X86::CMOVGE32rr: 1293 case X86::CMOVGE64rr: 1294 case X86::CMOVLE16rr: 1295 case X86::CMOVLE32rr: 1296 case X86::CMOVLE64rr: 1297 case X86::CMOVG16rr: 1298 case X86::CMOVG32rr: 1299 case X86::CMOVG64rr: 1300 case X86::CMOVS16rr: 1301 case X86::CMOVS32rr: 1302 case X86::CMOVS64rr: 1303 case X86::CMOVNS16rr: 1304 case X86::CMOVNS32rr: 1305 case X86::CMOVNS64rr: 1306 case X86::CMOVP16rr: 1307 case X86::CMOVP32rr: 1308 case X86::CMOVP64rr: 1309 case X86::CMOVNP16rr: 1310 case X86::CMOVNP32rr: 1311 case X86::CMOVNP64rr: { 1312 unsigned Opc = 0; 1313 switch (MI->getOpcode()) { 1314 default: break; 1315 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1316 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1317 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1318 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1319 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1320 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1321 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1322 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1323 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1324 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1325 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1326 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1327 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1328 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1329 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1330 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1331 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1332 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1333 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1334 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1335 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1336 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1337 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1338 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1339 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1340 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1341 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1342 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1343 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1344 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1345 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1346 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1347 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break; 1348 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1349 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1350 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1351 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1352 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1353 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break; 1354 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1355 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1356 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1357 } 1358 if (NewMI) { 1359 MachineFunction &MF = *MI->getParent()->getParent(); 1360 MI = MF.CloneMachineInstr(MI); 1361 NewMI = false; 1362 } 1363 MI->setDesc(get(Opc)); 1364 // Fallthrough intended. 1365 } 1366 default: 1367 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1368 } 1369} 1370 1371static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1372 switch (BrOpc) { 1373 default: return X86::COND_INVALID; 1374 case X86::JE: return X86::COND_E; 1375 case X86::JNE: return X86::COND_NE; 1376 case X86::JL: return X86::COND_L; 1377 case X86::JLE: return X86::COND_LE; 1378 case X86::JG: return X86::COND_G; 1379 case X86::JGE: return X86::COND_GE; 1380 case X86::JB: return X86::COND_B; 1381 case X86::JBE: return X86::COND_BE; 1382 case X86::JA: return X86::COND_A; 1383 case X86::JAE: return X86::COND_AE; 1384 case X86::JS: return X86::COND_S; 1385 case X86::JNS: return X86::COND_NS; 1386 case X86::JP: return X86::COND_P; 1387 case X86::JNP: return X86::COND_NP; 1388 case X86::JO: return X86::COND_O; 1389 case X86::JNO: return X86::COND_NO; 1390 case X86::JC: return X86::COND_C; 1391 case X86::JNC: return X86::COND_NC; 1392 } 1393} 1394 1395unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1396 switch (CC) { 1397 default: assert(0 && "Illegal condition code!"); 1398 case X86::COND_E: return X86::JE; 1399 case X86::COND_NE: return X86::JNE; 1400 case X86::COND_L: return X86::JL; 1401 case X86::COND_LE: return X86::JLE; 1402 case X86::COND_G: return X86::JG; 1403 case X86::COND_GE: return X86::JGE; 1404 case X86::COND_B: return X86::JB; 1405 case X86::COND_BE: return X86::JBE; 1406 case X86::COND_A: return X86::JA; 1407 case X86::COND_AE: return X86::JAE; 1408 case X86::COND_S: return X86::JS; 1409 case X86::COND_NS: return X86::JNS; 1410 case X86::COND_P: return X86::JP; 1411 case X86::COND_NP: return X86::JNP; 1412 case X86::COND_O: return X86::JO; 1413 case X86::COND_NO: return X86::JNO; 1414 case X86::COND_C: return X86::JC; 1415 case X86::COND_NC: return X86::JNC; 1416 } 1417} 1418 1419/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1420/// e.g. turning COND_E to COND_NE. 1421X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1422 switch (CC) { 1423 default: assert(0 && "Illegal condition code!"); 1424 case X86::COND_E: return X86::COND_NE; 1425 case X86::COND_NE: return X86::COND_E; 1426 case X86::COND_L: return X86::COND_GE; 1427 case X86::COND_LE: return X86::COND_G; 1428 case X86::COND_G: return X86::COND_LE; 1429 case X86::COND_GE: return X86::COND_L; 1430 case X86::COND_B: return X86::COND_AE; 1431 case X86::COND_BE: return X86::COND_A; 1432 case X86::COND_A: return X86::COND_BE; 1433 case X86::COND_AE: return X86::COND_B; 1434 case X86::COND_S: return X86::COND_NS; 1435 case X86::COND_NS: return X86::COND_S; 1436 case X86::COND_P: return X86::COND_NP; 1437 case X86::COND_NP: return X86::COND_P; 1438 case X86::COND_O: return X86::COND_NO; 1439 case X86::COND_NO: return X86::COND_O; 1440 case X86::COND_C: return X86::COND_NC; 1441 case X86::COND_NC: return X86::COND_C; 1442 } 1443} 1444 1445bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1446 const TargetInstrDesc &TID = MI->getDesc(); 1447 if (!TID.isTerminator()) return false; 1448 1449 // Conditional branch is a special case. 1450 if (TID.isBranch() && !TID.isBarrier()) 1451 return true; 1452 if (!TID.isPredicable()) 1453 return true; 1454 return !isPredicated(MI); 1455} 1456 1457// For purposes of branch analysis do not count FP_REG_KILL as a terminator. 1458static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, 1459 const X86InstrInfo &TII) { 1460 if (MI->getOpcode() == X86::FP_REG_KILL) 1461 return false; 1462 return TII.isUnpredicatedTerminator(MI); 1463} 1464 1465bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1466 MachineBasicBlock *&TBB, 1467 MachineBasicBlock *&FBB, 1468 SmallVectorImpl<MachineOperand> &Cond) const { 1469 // Start from the bottom of the block and work up, examining the 1470 // terminator instructions. 1471 MachineBasicBlock::iterator I = MBB.end(); 1472 while (I != MBB.begin()) { 1473 --I; 1474 // Working from the bottom, when we see a non-terminator 1475 // instruction, we're done. 1476 if (!isBrAnalysisUnpredicatedTerminator(I, *this)) 1477 break; 1478 // A terminator that isn't a branch can't easily be handled 1479 // by this analysis. 1480 if (!I->getDesc().isBranch()) 1481 return true; 1482 // Handle unconditional branches. 1483 if (I->getOpcode() == X86::JMP) { 1484 // If the block has any instructions after a JMP, delete them. 1485 while (next(I) != MBB.end()) 1486 next(I)->eraseFromParent(); 1487 Cond.clear(); 1488 FBB = 0; 1489 // Delete the JMP if it's equivalent to a fall-through. 1490 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1491 TBB = 0; 1492 I->eraseFromParent(); 1493 I = MBB.end(); 1494 continue; 1495 } 1496 // TBB is used to indicate the unconditinal destination. 1497 TBB = I->getOperand(0).getMBB(); 1498 continue; 1499 } 1500 // Handle conditional branches. 1501 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1502 if (BranchCode == X86::COND_INVALID) 1503 return true; // Can't handle indirect branch. 1504 // Working from the bottom, handle the first conditional branch. 1505 if (Cond.empty()) { 1506 FBB = TBB; 1507 TBB = I->getOperand(0).getMBB(); 1508 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1509 continue; 1510 } 1511 // Handle subsequent conditional branches. Only handle the case 1512 // where all conditional branches branch to the same destination 1513 // and their condition opcodes fit one of the special 1514 // multi-branch idioms. 1515 assert(Cond.size() == 1); 1516 assert(TBB); 1517 // Only handle the case where all conditional branches branch to 1518 // the same destination. 1519 if (TBB != I->getOperand(0).getMBB()) 1520 return true; 1521 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1522 // If the conditions are the same, we can leave them alone. 1523 if (OldBranchCode == BranchCode) 1524 continue; 1525 // If they differ, see if they fit one of the known patterns. 1526 // Theoretically we could handle more patterns here, but 1527 // we shouldn't expect to see them if instruction selection 1528 // has done a reasonable job. 1529 if ((OldBranchCode == X86::COND_NP && 1530 BranchCode == X86::COND_E) || 1531 (OldBranchCode == X86::COND_E && 1532 BranchCode == X86::COND_NP)) 1533 BranchCode = X86::COND_NP_OR_E; 1534 else if ((OldBranchCode == X86::COND_P && 1535 BranchCode == X86::COND_NE) || 1536 (OldBranchCode == X86::COND_NE && 1537 BranchCode == X86::COND_P)) 1538 BranchCode = X86::COND_NE_OR_P; 1539 else 1540 return true; 1541 // Update the MachineOperand. 1542 Cond[0].setImm(BranchCode); 1543 } 1544 1545 return false; 1546} 1547 1548unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1549 MachineBasicBlock::iterator I = MBB.end(); 1550 unsigned Count = 0; 1551 1552 while (I != MBB.begin()) { 1553 --I; 1554 if (I->getOpcode() != X86::JMP && 1555 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1556 break; 1557 // Remove the branch. 1558 I->eraseFromParent(); 1559 I = MBB.end(); 1560 ++Count; 1561 } 1562 1563 return Count; 1564} 1565 1566static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB, 1567 const MachineOperand &MO) { 1568 if (MO.isReg()) 1569 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(), 1570 MO.isKill(), MO.isDead(), MO.getSubReg()); 1571 else if (MO.isImm()) 1572 MIB = MIB.addImm(MO.getImm()); 1573 else if (MO.isFI()) 1574 MIB = MIB.addFrameIndex(MO.getIndex()); 1575 else if (MO.isGlobal()) 1576 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset()); 1577 else if (MO.isCPI()) 1578 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset()); 1579 else if (MO.isJTI()) 1580 MIB = MIB.addJumpTableIndex(MO.getIndex()); 1581 else if (MO.isSymbol()) 1582 MIB = MIB.addExternalSymbol(MO.getSymbolName()); 1583 else 1584 assert(0 && "Unknown operand for X86InstrAddOperand!"); 1585 1586 return MIB; 1587} 1588 1589unsigned 1590X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1591 MachineBasicBlock *FBB, 1592 const SmallVectorImpl<MachineOperand> &Cond) const { 1593 // Shouldn't be a fall through. 1594 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1595 assert((Cond.size() == 1 || Cond.size() == 0) && 1596 "X86 branch conditions have one component!"); 1597 1598 if (Cond.empty()) { 1599 // Unconditional branch? 1600 assert(!FBB && "Unconditional branch with multiple successors!"); 1601 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); 1602 return 1; 1603 } 1604 1605 // Conditional branch. 1606 unsigned Count = 0; 1607 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1608 switch (CC) { 1609 case X86::COND_NP_OR_E: 1610 // Synthesize NP_OR_E with two branches. 1611 BuildMI(&MBB, get(X86::JNP)).addMBB(TBB); 1612 ++Count; 1613 BuildMI(&MBB, get(X86::JE)).addMBB(TBB); 1614 ++Count; 1615 break; 1616 case X86::COND_NE_OR_P: 1617 // Synthesize NE_OR_P with two branches. 1618 BuildMI(&MBB, get(X86::JNE)).addMBB(TBB); 1619 ++Count; 1620 BuildMI(&MBB, get(X86::JP)).addMBB(TBB); 1621 ++Count; 1622 break; 1623 default: { 1624 unsigned Opc = GetCondBranchFromCond(CC); 1625 BuildMI(&MBB, get(Opc)).addMBB(TBB); 1626 ++Count; 1627 } 1628 } 1629 if (FBB) { 1630 // Two-way Conditional branch. Insert the second branch. 1631 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); 1632 ++Count; 1633 } 1634 return Count; 1635} 1636 1637bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, 1638 MachineBasicBlock::iterator MI, 1639 unsigned DestReg, unsigned SrcReg, 1640 const TargetRegisterClass *DestRC, 1641 const TargetRegisterClass *SrcRC) const { 1642 if (DestRC == SrcRC) { 1643 unsigned Opc; 1644 if (DestRC == &X86::GR64RegClass) { 1645 Opc = X86::MOV64rr; 1646 } else if (DestRC == &X86::GR32RegClass) { 1647 Opc = X86::MOV32rr; 1648 } else if (DestRC == &X86::GR16RegClass) { 1649 Opc = X86::MOV16rr; 1650 } else if (DestRC == &X86::GR8RegClass) { 1651 Opc = X86::MOV8rr; 1652 } else if (DestRC == &X86::GR32_RegClass) { 1653 Opc = X86::MOV32_rr; 1654 } else if (DestRC == &X86::GR16_RegClass) { 1655 Opc = X86::MOV16_rr; 1656 } else if (DestRC == &X86::RFP32RegClass) { 1657 Opc = X86::MOV_Fp3232; 1658 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { 1659 Opc = X86::MOV_Fp6464; 1660 } else if (DestRC == &X86::RFP80RegClass) { 1661 Opc = X86::MOV_Fp8080; 1662 } else if (DestRC == &X86::FR32RegClass) { 1663 Opc = X86::FsMOVAPSrr; 1664 } else if (DestRC == &X86::FR64RegClass) { 1665 Opc = X86::FsMOVAPDrr; 1666 } else if (DestRC == &X86::VR128RegClass) { 1667 Opc = X86::MOVAPSrr; 1668 } else if (DestRC == &X86::VR64RegClass) { 1669 Opc = X86::MMX_MOVQ64rr; 1670 } else { 1671 return false; 1672 } 1673 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); 1674 return true; 1675 } 1676 1677 // Moving EFLAGS to / from another register requires a push and a pop. 1678 if (SrcRC == &X86::CCRRegClass) { 1679 if (SrcReg != X86::EFLAGS) 1680 return false; 1681 if (DestRC == &X86::GR64RegClass) { 1682 BuildMI(MBB, MI, get(X86::PUSHFQ)); 1683 BuildMI(MBB, MI, get(X86::POP64r), DestReg); 1684 return true; 1685 } else if (DestRC == &X86::GR32RegClass) { 1686 BuildMI(MBB, MI, get(X86::PUSHFD)); 1687 BuildMI(MBB, MI, get(X86::POP32r), DestReg); 1688 return true; 1689 } 1690 } else if (DestRC == &X86::CCRRegClass) { 1691 if (DestReg != X86::EFLAGS) 1692 return false; 1693 if (SrcRC == &X86::GR64RegClass) { 1694 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); 1695 BuildMI(MBB, MI, get(X86::POPFQ)); 1696 return true; 1697 } else if (SrcRC == &X86::GR32RegClass) { 1698 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); 1699 BuildMI(MBB, MI, get(X86::POPFD)); 1700 return true; 1701 } 1702 } 1703 1704 // Moving from ST(0) turns into FpGET_ST0_32 etc. 1705 if (SrcRC == &X86::RSTRegClass) { 1706 // Copying from ST(0)/ST(1). 1707 if (SrcReg != X86::ST0 && SrcReg != X86::ST1) 1708 // Can only copy from ST(0)/ST(1) right now 1709 return false; 1710 bool isST0 = SrcReg == X86::ST0; 1711 unsigned Opc; 1712 if (DestRC == &X86::RFP32RegClass) 1713 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32; 1714 else if (DestRC == &X86::RFP64RegClass) 1715 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64; 1716 else { 1717 if (DestRC != &X86::RFP80RegClass) 1718 return false; 1719 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; 1720 } 1721 BuildMI(MBB, MI, get(Opc), DestReg); 1722 return true; 1723 } 1724 1725 // Moving to ST(0) turns into FpSET_ST0_32 etc. 1726 if (DestRC == &X86::RSTRegClass) { 1727 // Copying to ST(0). FIXME: handle ST(1) also 1728 if (DestReg != X86::ST0) 1729 // Can only copy to TOS right now 1730 return false; 1731 unsigned Opc; 1732 if (SrcRC == &X86::RFP32RegClass) 1733 Opc = X86::FpSET_ST0_32; 1734 else if (SrcRC == &X86::RFP64RegClass) 1735 Opc = X86::FpSET_ST0_64; 1736 else { 1737 if (SrcRC != &X86::RFP80RegClass) 1738 return false; 1739 Opc = X86::FpSET_ST0_80; 1740 } 1741 BuildMI(MBB, MI, get(Opc)).addReg(SrcReg); 1742 return true; 1743 } 1744 1745 // Not yet supported! 1746 return false; 1747} 1748 1749static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, 1750 bool isStackAligned) { 1751 unsigned Opc = 0; 1752 if (RC == &X86::GR64RegClass) { 1753 Opc = X86::MOV64mr; 1754 } else if (RC == &X86::GR32RegClass) { 1755 Opc = X86::MOV32mr; 1756 } else if (RC == &X86::GR16RegClass) { 1757 Opc = X86::MOV16mr; 1758 } else if (RC == &X86::GR8RegClass) { 1759 Opc = X86::MOV8mr; 1760 } else if (RC == &X86::GR32_RegClass) { 1761 Opc = X86::MOV32_mr; 1762 } else if (RC == &X86::GR16_RegClass) { 1763 Opc = X86::MOV16_mr; 1764 } else if (RC == &X86::RFP80RegClass) { 1765 Opc = X86::ST_FpP80m; // pops 1766 } else if (RC == &X86::RFP64RegClass) { 1767 Opc = X86::ST_Fp64m; 1768 } else if (RC == &X86::RFP32RegClass) { 1769 Opc = X86::ST_Fp32m; 1770 } else if (RC == &X86::FR32RegClass) { 1771 Opc = X86::MOVSSmr; 1772 } else if (RC == &X86::FR64RegClass) { 1773 Opc = X86::MOVSDmr; 1774 } else if (RC == &X86::VR128RegClass) { 1775 // If stack is realigned we can use aligned stores. 1776 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr; 1777 } else if (RC == &X86::VR64RegClass) { 1778 Opc = X86::MMX_MOVQ64mr; 1779 } else { 1780 assert(0 && "Unknown regclass"); 1781 abort(); 1782 } 1783 1784 return Opc; 1785} 1786 1787void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 1788 MachineBasicBlock::iterator MI, 1789 unsigned SrcReg, bool isKill, int FrameIdx, 1790 const TargetRegisterClass *RC) const { 1791 const MachineFunction &MF = *MBB.getParent(); 1792 bool isAligned = (RI.getStackAlignment() >= 16) || 1793 RI.needsStackRealignment(MF); 1794 unsigned Opc = getStoreRegOpcode(RC, isAligned); 1795 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx) 1796 .addReg(SrcReg, false, false, isKill); 1797} 1798 1799void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 1800 bool isKill, 1801 SmallVectorImpl<MachineOperand> &Addr, 1802 const TargetRegisterClass *RC, 1803 SmallVectorImpl<MachineInstr*> &NewMIs) const { 1804 bool isAligned = (RI.getStackAlignment() >= 16) || 1805 RI.needsStackRealignment(MF); 1806 unsigned Opc = getStoreRegOpcode(RC, isAligned); 1807 MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); 1808 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 1809 MIB = X86InstrAddOperand(MIB, Addr[i]); 1810 MIB.addReg(SrcReg, false, false, isKill); 1811 NewMIs.push_back(MIB); 1812} 1813 1814static unsigned getLoadRegOpcode(const TargetRegisterClass *RC, 1815 bool isStackAligned) { 1816 unsigned Opc = 0; 1817 if (RC == &X86::GR64RegClass) { 1818 Opc = X86::MOV64rm; 1819 } else if (RC == &X86::GR32RegClass) { 1820 Opc = X86::MOV32rm; 1821 } else if (RC == &X86::GR16RegClass) { 1822 Opc = X86::MOV16rm; 1823 } else if (RC == &X86::GR8RegClass) { 1824 Opc = X86::MOV8rm; 1825 } else if (RC == &X86::GR32_RegClass) { 1826 Opc = X86::MOV32_rm; 1827 } else if (RC == &X86::GR16_RegClass) { 1828 Opc = X86::MOV16_rm; 1829 } else if (RC == &X86::RFP80RegClass) { 1830 Opc = X86::LD_Fp80m; 1831 } else if (RC == &X86::RFP64RegClass) { 1832 Opc = X86::LD_Fp64m; 1833 } else if (RC == &X86::RFP32RegClass) { 1834 Opc = X86::LD_Fp32m; 1835 } else if (RC == &X86::FR32RegClass) { 1836 Opc = X86::MOVSSrm; 1837 } else if (RC == &X86::FR64RegClass) { 1838 Opc = X86::MOVSDrm; 1839 } else if (RC == &X86::VR128RegClass) { 1840 // If stack is realigned we can use aligned loads. 1841 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm; 1842 } else if (RC == &X86::VR64RegClass) { 1843 Opc = X86::MMX_MOVQ64rm; 1844 } else { 1845 assert(0 && "Unknown regclass"); 1846 abort(); 1847 } 1848 1849 return Opc; 1850} 1851 1852void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 1853 MachineBasicBlock::iterator MI, 1854 unsigned DestReg, int FrameIdx, 1855 const TargetRegisterClass *RC) const{ 1856 const MachineFunction &MF = *MBB.getParent(); 1857 bool isAligned = (RI.getStackAlignment() >= 16) || 1858 RI.needsStackRealignment(MF); 1859 unsigned Opc = getLoadRegOpcode(RC, isAligned); 1860 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx); 1861} 1862 1863void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 1864 SmallVectorImpl<MachineOperand> &Addr, 1865 const TargetRegisterClass *RC, 1866 SmallVectorImpl<MachineInstr*> &NewMIs) const { 1867 bool isAligned = (RI.getStackAlignment() >= 16) || 1868 RI.needsStackRealignment(MF); 1869 unsigned Opc = getLoadRegOpcode(RC, isAligned); 1870 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); 1871 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 1872 MIB = X86InstrAddOperand(MIB, Addr[i]); 1873 NewMIs.push_back(MIB); 1874} 1875 1876bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1877 MachineBasicBlock::iterator MI, 1878 const std::vector<CalleeSavedInfo> &CSI) const { 1879 if (CSI.empty()) 1880 return false; 1881 1882 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1883 unsigned SlotSize = is64Bit ? 8 : 4; 1884 1885 MachineFunction &MF = *MBB.getParent(); 1886 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1887 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); 1888 1889 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 1890 for (unsigned i = CSI.size(); i != 0; --i) { 1891 unsigned Reg = CSI[i-1].getReg(); 1892 // Add the callee-saved register as live-in. It's killed at the spill. 1893 MBB.addLiveIn(Reg); 1894 BuildMI(MBB, MI, get(Opc)) 1895 .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); 1896 } 1897 return true; 1898} 1899 1900bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1901 MachineBasicBlock::iterator MI, 1902 const std::vector<CalleeSavedInfo> &CSI) const { 1903 if (CSI.empty()) 1904 return false; 1905 1906 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1907 1908 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 1909 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1910 unsigned Reg = CSI[i].getReg(); 1911 BuildMI(MBB, MI, get(Opc), Reg); 1912 } 1913 return true; 1914} 1915 1916static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 1917 const SmallVector<MachineOperand,4> &MOs, 1918 MachineInstr *MI, const TargetInstrInfo &TII) { 1919 // Create the base instruction with the memory operand as the first part. 1920 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); 1921 MachineInstrBuilder MIB(NewMI); 1922 unsigned NumAddrOps = MOs.size(); 1923 for (unsigned i = 0; i != NumAddrOps; ++i) 1924 MIB = X86InstrAddOperand(MIB, MOs[i]); 1925 if (NumAddrOps < 4) // FrameIndex only 1926 MIB.addImm(1).addReg(0).addImm(0); 1927 1928 // Loop over the rest of the ri operands, converting them over. 1929 unsigned NumOps = MI->getDesc().getNumOperands()-2; 1930 for (unsigned i = 0; i != NumOps; ++i) { 1931 MachineOperand &MO = MI->getOperand(i+2); 1932 MIB = X86InstrAddOperand(MIB, MO); 1933 } 1934 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 1935 MachineOperand &MO = MI->getOperand(i); 1936 MIB = X86InstrAddOperand(MIB, MO); 1937 } 1938 return MIB; 1939} 1940 1941static MachineInstr *FuseInst(MachineFunction &MF, 1942 unsigned Opcode, unsigned OpNo, 1943 const SmallVector<MachineOperand,4> &MOs, 1944 MachineInstr *MI, const TargetInstrInfo &TII) { 1945 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); 1946 MachineInstrBuilder MIB(NewMI); 1947 1948 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1949 MachineOperand &MO = MI->getOperand(i); 1950 if (i == OpNo) { 1951 assert(MO.isReg() && "Expected to fold into reg operand!"); 1952 unsigned NumAddrOps = MOs.size(); 1953 for (unsigned i = 0; i != NumAddrOps; ++i) 1954 MIB = X86InstrAddOperand(MIB, MOs[i]); 1955 if (NumAddrOps < 4) // FrameIndex only 1956 MIB.addImm(1).addReg(0).addImm(0); 1957 } else { 1958 MIB = X86InstrAddOperand(MIB, MO); 1959 } 1960 } 1961 return MIB; 1962} 1963 1964static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 1965 const SmallVector<MachineOperand,4> &MOs, 1966 MachineInstr *MI) { 1967 MachineFunction &MF = *MI->getParent()->getParent(); 1968 MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode)); 1969 1970 unsigned NumAddrOps = MOs.size(); 1971 for (unsigned i = 0; i != NumAddrOps; ++i) 1972 MIB = X86InstrAddOperand(MIB, MOs[i]); 1973 if (NumAddrOps < 4) // FrameIndex only 1974 MIB.addImm(1).addReg(0).addImm(0); 1975 return MIB.addImm(0); 1976} 1977 1978MachineInstr* 1979X86InstrInfo::foldMemoryOperand(MachineFunction &MF, 1980 MachineInstr *MI, unsigned i, 1981 const SmallVector<MachineOperand,4> &MOs) const{ 1982 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; 1983 bool isTwoAddrFold = false; 1984 unsigned NumOps = MI->getDesc().getNumOperands(); 1985 bool isTwoAddr = NumOps > 1 && 1986 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 1987 1988 MachineInstr *NewMI = NULL; 1989 // Folding a memory location into the two-address part of a two-address 1990 // instruction is different than folding it other places. It requires 1991 // replacing the *two* registers with the memory location. 1992 if (isTwoAddr && NumOps >= 2 && i < 2 && 1993 MI->getOperand(0).isReg() && 1994 MI->getOperand(1).isReg() && 1995 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 1996 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 1997 isTwoAddrFold = true; 1998 } else if (i == 0) { // If operand 0 1999 if (MI->getOpcode() == X86::MOV16r0) 2000 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2001 else if (MI->getOpcode() == X86::MOV32r0) 2002 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2003 else if (MI->getOpcode() == X86::MOV64r0) 2004 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2005 else if (MI->getOpcode() == X86::MOV8r0) 2006 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2007 if (NewMI) 2008 return NewMI; 2009 2010 OpcodeTablePtr = &RegOp2MemOpTable0; 2011 } else if (i == 1) { 2012 OpcodeTablePtr = &RegOp2MemOpTable1; 2013 } else if (i == 2) { 2014 OpcodeTablePtr = &RegOp2MemOpTable2; 2015 } 2016 2017 // If table selected... 2018 if (OpcodeTablePtr) { 2019 // Find the Opcode to fuse 2020 DenseMap<unsigned*, unsigned>::iterator I = 2021 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2022 if (I != OpcodeTablePtr->end()) { 2023 if (isTwoAddrFold) 2024 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this); 2025 else 2026 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this); 2027 return NewMI; 2028 } 2029 } 2030 2031 // No fusion 2032 if (PrintFailedFusing) 2033 cerr << "We failed to fuse operand " << i << *MI; 2034 return NULL; 2035} 2036 2037 2038MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, 2039 MachineInstr *MI, 2040 const SmallVectorImpl<unsigned> &Ops, 2041 int FrameIndex) const { 2042 // Check switch flag 2043 if (NoFusing) return NULL; 2044 2045 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2046 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2047 // FIXME: Move alignment requirement into tables? 2048 if (Alignment < 16) { 2049 switch (MI->getOpcode()) { 2050 default: break; 2051 // Not always safe to fold movsd into these instructions since their load 2052 // folding variants expects the address to be 16 byte aligned. 2053 case X86::FsANDNPDrr: 2054 case X86::FsANDNPSrr: 2055 case X86::FsANDPDrr: 2056 case X86::FsANDPSrr: 2057 case X86::FsORPDrr: 2058 case X86::FsORPSrr: 2059 case X86::FsXORPDrr: 2060 case X86::FsXORPSrr: 2061 return NULL; 2062 } 2063 } 2064 2065 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2066 unsigned NewOpc = 0; 2067 switch (MI->getOpcode()) { 2068 default: return NULL; 2069 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2070 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2071 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2072 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2073 } 2074 // Change to CMPXXri r, 0 first. 2075 MI->setDesc(get(NewOpc)); 2076 MI->getOperand(1).ChangeToImmediate(0); 2077 } else if (Ops.size() != 1) 2078 return NULL; 2079 2080 SmallVector<MachineOperand,4> MOs; 2081 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2082 return foldMemoryOperand(MF, MI, Ops[0], MOs); 2083} 2084 2085MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, 2086 MachineInstr *MI, 2087 const SmallVectorImpl<unsigned> &Ops, 2088 MachineInstr *LoadMI) const { 2089 // Check switch flag 2090 if (NoFusing) return NULL; 2091 2092 // Determine the alignment of the load. 2093 unsigned Alignment = 0; 2094 if (LoadMI->hasOneMemOperand()) 2095 Alignment = LoadMI->memoperands_begin()->getAlignment(); 2096 2097 // FIXME: Move alignment requirement into tables? 2098 if (Alignment < 16) { 2099 switch (MI->getOpcode()) { 2100 default: break; 2101 // Not always safe to fold movsd into these instructions since their load 2102 // folding variants expects the address to be 16 byte aligned. 2103 case X86::FsANDNPDrr: 2104 case X86::FsANDNPSrr: 2105 case X86::FsANDPDrr: 2106 case X86::FsANDPSrr: 2107 case X86::FsORPDrr: 2108 case X86::FsORPSrr: 2109 case X86::FsXORPDrr: 2110 case X86::FsXORPSrr: 2111 return NULL; 2112 } 2113 } 2114 2115 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2116 unsigned NewOpc = 0; 2117 switch (MI->getOpcode()) { 2118 default: return NULL; 2119 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2120 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2121 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2122 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2123 } 2124 // Change to CMPXXri r, 0 first. 2125 MI->setDesc(get(NewOpc)); 2126 MI->getOperand(1).ChangeToImmediate(0); 2127 } else if (Ops.size() != 1) 2128 return NULL; 2129 2130 SmallVector<MachineOperand,4> MOs; 2131 if (LoadMI->getOpcode() == X86::V_SET0 || 2132 LoadMI->getOpcode() == X86::V_SETALLONES) { 2133 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 2134 // Create a constant-pool entry and operands to load from it. 2135 2136 // x86-32 PIC requires a PIC base register for constant pools. 2137 unsigned PICBase = 0; 2138 if (TM.getRelocationModel() == Reloc::PIC_ && 2139 !TM.getSubtarget<X86Subtarget>().is64Bit()) 2140 PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF); 2141 2142 // Create a v4i32 constant-pool entry. 2143 MachineConstantPool &MCP = *MF.getConstantPool(); 2144 const VectorType *Ty = VectorType::get(Type::Int32Ty, 4); 2145 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ? 2146 ConstantVector::getNullValue(Ty) : 2147 ConstantVector::getAllOnesValue(Ty); 2148 unsigned CPI = MCP.getConstantPoolIndex(C, /*AlignmentLog2=*/4); 2149 2150 // Create operands to load from the constant pool entry. 2151 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2152 MOs.push_back(MachineOperand::CreateImm(1)); 2153 MOs.push_back(MachineOperand::CreateReg(0, false)); 2154 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2155 } else { 2156 // Folding a normal load. Just copy the load's address operands. 2157 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2158 for (unsigned i = NumOps - 4; i != NumOps; ++i) 2159 MOs.push_back(LoadMI->getOperand(i)); 2160 } 2161 return foldMemoryOperand(MF, MI, Ops[0], MOs); 2162} 2163 2164 2165bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2166 const SmallVectorImpl<unsigned> &Ops) const { 2167 // Check switch flag 2168 if (NoFusing) return 0; 2169 2170 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2171 switch (MI->getOpcode()) { 2172 default: return false; 2173 case X86::TEST8rr: 2174 case X86::TEST16rr: 2175 case X86::TEST32rr: 2176 case X86::TEST64rr: 2177 return true; 2178 } 2179 } 2180 2181 if (Ops.size() != 1) 2182 return false; 2183 2184 unsigned OpNum = Ops[0]; 2185 unsigned Opc = MI->getOpcode(); 2186 unsigned NumOps = MI->getDesc().getNumOperands(); 2187 bool isTwoAddr = NumOps > 1 && 2188 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2189 2190 // Folding a memory location into the two-address part of a two-address 2191 // instruction is different than folding it other places. It requires 2192 // replacing the *two* registers with the memory location. 2193 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; 2194 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2195 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2196 } else if (OpNum == 0) { // If operand 0 2197 switch (Opc) { 2198 case X86::MOV16r0: 2199 case X86::MOV32r0: 2200 case X86::MOV64r0: 2201 case X86::MOV8r0: 2202 return true; 2203 default: break; 2204 } 2205 OpcodeTablePtr = &RegOp2MemOpTable0; 2206 } else if (OpNum == 1) { 2207 OpcodeTablePtr = &RegOp2MemOpTable1; 2208 } else if (OpNum == 2) { 2209 OpcodeTablePtr = &RegOp2MemOpTable2; 2210 } 2211 2212 if (OpcodeTablePtr) { 2213 // Find the Opcode to fuse 2214 DenseMap<unsigned*, unsigned>::iterator I = 2215 OpcodeTablePtr->find((unsigned*)Opc); 2216 if (I != OpcodeTablePtr->end()) 2217 return true; 2218 } 2219 return false; 2220} 2221 2222bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2223 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2224 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2225 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2226 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2227 if (I == MemOp2RegOpTable.end()) 2228 return false; 2229 unsigned Opc = I->second.first; 2230 unsigned Index = I->second.second & 0xf; 2231 bool FoldedLoad = I->second.second & (1 << 4); 2232 bool FoldedStore = I->second.second & (1 << 5); 2233 if (UnfoldLoad && !FoldedLoad) 2234 return false; 2235 UnfoldLoad &= FoldedLoad; 2236 if (UnfoldStore && !FoldedStore) 2237 return false; 2238 UnfoldStore &= FoldedStore; 2239 2240 const TargetInstrDesc &TID = get(Opc); 2241 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2242 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() 2243 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass); 2244 SmallVector<MachineOperand,4> AddrOps; 2245 SmallVector<MachineOperand,2> BeforeOps; 2246 SmallVector<MachineOperand,2> AfterOps; 2247 SmallVector<MachineOperand,4> ImpOps; 2248 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2249 MachineOperand &Op = MI->getOperand(i); 2250 if (i >= Index && i < Index+4) 2251 AddrOps.push_back(Op); 2252 else if (Op.isReg() && Op.isImplicit()) 2253 ImpOps.push_back(Op); 2254 else if (i < Index) 2255 BeforeOps.push_back(Op); 2256 else if (i > Index) 2257 AfterOps.push_back(Op); 2258 } 2259 2260 // Emit the load instruction. 2261 if (UnfoldLoad) { 2262 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs); 2263 if (UnfoldStore) { 2264 // Address operands cannot be marked isKill. 2265 for (unsigned i = 1; i != 5; ++i) { 2266 MachineOperand &MO = NewMIs[0]->getOperand(i); 2267 if (MO.isReg()) 2268 MO.setIsKill(false); 2269 } 2270 } 2271 } 2272 2273 // Emit the data processing instruction. 2274 MachineInstr *DataMI = MF.CreateMachineInstr(TID, true); 2275 MachineInstrBuilder MIB(DataMI); 2276 2277 if (FoldedStore) 2278 MIB.addReg(Reg, true); 2279 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2280 MIB = X86InstrAddOperand(MIB, BeforeOps[i]); 2281 if (FoldedLoad) 2282 MIB.addReg(Reg); 2283 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2284 MIB = X86InstrAddOperand(MIB, AfterOps[i]); 2285 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2286 MachineOperand &MO = ImpOps[i]; 2287 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead()); 2288 } 2289 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2290 unsigned NewOpc = 0; 2291 switch (DataMI->getOpcode()) { 2292 default: break; 2293 case X86::CMP64ri32: 2294 case X86::CMP32ri: 2295 case X86::CMP16ri: 2296 case X86::CMP8ri: { 2297 MachineOperand &MO0 = DataMI->getOperand(0); 2298 MachineOperand &MO1 = DataMI->getOperand(1); 2299 if (MO1.getImm() == 0) { 2300 switch (DataMI->getOpcode()) { 2301 default: break; 2302 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2303 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2304 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2305 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2306 } 2307 DataMI->setDesc(get(NewOpc)); 2308 MO1.ChangeToRegister(MO0.getReg(), false); 2309 } 2310 } 2311 } 2312 NewMIs.push_back(DataMI); 2313 2314 // Emit the store instruction. 2315 if (UnfoldStore) { 2316 const TargetOperandInfo &DstTOI = TID.OpInfo[0]; 2317 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass() 2318 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); 2319 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs); 2320 } 2321 2322 return true; 2323} 2324 2325bool 2326X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2327 SmallVectorImpl<SDNode*> &NewNodes) const { 2328 if (!N->isMachineOpcode()) 2329 return false; 2330 2331 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2332 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2333 if (I == MemOp2RegOpTable.end()) 2334 return false; 2335 unsigned Opc = I->second.first; 2336 unsigned Index = I->second.second & 0xf; 2337 bool FoldedLoad = I->second.second & (1 << 4); 2338 bool FoldedStore = I->second.second & (1 << 5); 2339 const TargetInstrDesc &TID = get(Opc); 2340 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2341 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() 2342 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass); 2343 std::vector<SDValue> AddrOps; 2344 std::vector<SDValue> BeforeOps; 2345 std::vector<SDValue> AfterOps; 2346 unsigned NumOps = N->getNumOperands(); 2347 for (unsigned i = 0; i != NumOps-1; ++i) { 2348 SDValue Op = N->getOperand(i); 2349 if (i >= Index && i < Index+4) 2350 AddrOps.push_back(Op); 2351 else if (i < Index) 2352 BeforeOps.push_back(Op); 2353 else if (i > Index) 2354 AfterOps.push_back(Op); 2355 } 2356 SDValue Chain = N->getOperand(NumOps-1); 2357 AddrOps.push_back(Chain); 2358 2359 // Emit the load instruction. 2360 SDNode *Load = 0; 2361 const MachineFunction &MF = DAG.getMachineFunction(); 2362 if (FoldedLoad) { 2363 MVT VT = *RC->vt_begin(); 2364 bool isAligned = (RI.getStackAlignment() >= 16) || 2365 RI.needsStackRealignment(MF); 2366 Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), 2367 VT, MVT::Other, 2368 &AddrOps[0], AddrOps.size()); 2369 NewNodes.push_back(Load); 2370 } 2371 2372 // Emit the data processing instruction. 2373 std::vector<MVT> VTs; 2374 const TargetRegisterClass *DstRC = 0; 2375 if (TID.getNumDefs() > 0) { 2376 const TargetOperandInfo &DstTOI = TID.OpInfo[0]; 2377 DstRC = DstTOI.isLookupPtrRegClass() 2378 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); 2379 VTs.push_back(*DstRC->vt_begin()); 2380 } 2381 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2382 MVT VT = N->getValueType(i); 2383 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2384 VTs.push_back(VT); 2385 } 2386 if (Load) 2387 BeforeOps.push_back(SDValue(Load, 0)); 2388 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2389 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size()); 2390 NewNodes.push_back(NewNode); 2391 2392 // Emit the store instruction. 2393 if (FoldedStore) { 2394 AddrOps.pop_back(); 2395 AddrOps.push_back(SDValue(NewNode, 0)); 2396 AddrOps.push_back(Chain); 2397 bool isAligned = (RI.getStackAlignment() >= 16) || 2398 RI.needsStackRealignment(MF); 2399 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), 2400 MVT::Other, &AddrOps[0], AddrOps.size()); 2401 NewNodes.push_back(Store); 2402 } 2403 2404 return true; 2405} 2406 2407unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2408 bool UnfoldLoad, bool UnfoldStore) const { 2409 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2410 MemOp2RegOpTable.find((unsigned*)Opc); 2411 if (I == MemOp2RegOpTable.end()) 2412 return 0; 2413 bool FoldedLoad = I->second.second & (1 << 4); 2414 bool FoldedStore = I->second.second & (1 << 5); 2415 if (UnfoldLoad && !FoldedLoad) 2416 return 0; 2417 if (UnfoldStore && !FoldedStore) 2418 return 0; 2419 return I->second.first; 2420} 2421 2422bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 2423 if (MBB.empty()) return false; 2424 2425 switch (MBB.back().getOpcode()) { 2426 case X86::TCRETURNri: 2427 case X86::TCRETURNdi: 2428 case X86::RET: // Return. 2429 case X86::RETI: 2430 case X86::TAILJMPd: 2431 case X86::TAILJMPr: 2432 case X86::TAILJMPm: 2433 case X86::JMP: // Uncond branch. 2434 case X86::JMP32r: // Indirect branch. 2435 case X86::JMP64r: // Indirect branch (64-bit). 2436 case X86::JMP32m: // Indirect branch through mem. 2437 case X86::JMP64m: // Indirect branch through mem (64-bit). 2438 return true; 2439 default: return false; 2440 } 2441} 2442 2443bool X86InstrInfo:: 2444ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2445 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 2446 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 2447 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 2448 return true; 2449 Cond[0].setImm(GetOppositeBranchCondition(CC)); 2450 return false; 2451} 2452 2453bool X86InstrInfo:: 2454IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const { 2455 // FIXME: Ignore bariers of x87 stack registers for now. We can't 2456 // allow any loads of these registers before FpGet_ST0_80. 2457 return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 2458 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass; 2459} 2460 2461const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { 2462 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 2463 if (Subtarget->is64Bit()) 2464 return &X86::GR64RegClass; 2465 else 2466 return &X86::GR32RegClass; 2467} 2468 2469unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) { 2470 switch (Desc->TSFlags & X86II::ImmMask) { 2471 case X86II::Imm8: return 1; 2472 case X86II::Imm16: return 2; 2473 case X86II::Imm32: return 4; 2474 case X86II::Imm64: return 8; 2475 default: assert(0 && "Immediate size not set!"); 2476 return 0; 2477 } 2478} 2479 2480/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? 2481/// e.g. r8, xmm8, etc. 2482bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) { 2483 if (!MO.isReg()) return false; 2484 switch (MO.getReg()) { 2485 default: break; 2486 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 2487 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 2488 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 2489 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 2490 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 2491 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 2492 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 2493 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 2494 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 2495 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 2496 return true; 2497 } 2498 return false; 2499} 2500 2501 2502/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 2503/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 2504/// size, and 3) use of X86-64 extended registers. 2505unsigned X86InstrInfo::determineREX(const MachineInstr &MI) { 2506 unsigned REX = 0; 2507 const TargetInstrDesc &Desc = MI.getDesc(); 2508 2509 // Pseudo instructions do not need REX prefix byte. 2510 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 2511 return 0; 2512 if (Desc.TSFlags & X86II::REX_W) 2513 REX |= 1 << 3; 2514 2515 unsigned NumOps = Desc.getNumOperands(); 2516 if (NumOps) { 2517 bool isTwoAddr = NumOps > 1 && 2518 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; 2519 2520 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 2521 unsigned i = isTwoAddr ? 1 : 0; 2522 for (unsigned e = NumOps; i != e; ++i) { 2523 const MachineOperand& MO = MI.getOperand(i); 2524 if (MO.isReg()) { 2525 unsigned Reg = MO.getReg(); 2526 if (isX86_64NonExtLowByteReg(Reg)) 2527 REX |= 0x40; 2528 } 2529 } 2530 2531 switch (Desc.TSFlags & X86II::FormMask) { 2532 case X86II::MRMInitReg: 2533 if (isX86_64ExtendedReg(MI.getOperand(0))) 2534 REX |= (1 << 0) | (1 << 2); 2535 break; 2536 case X86II::MRMSrcReg: { 2537 if (isX86_64ExtendedReg(MI.getOperand(0))) 2538 REX |= 1 << 2; 2539 i = isTwoAddr ? 2 : 1; 2540 for (unsigned e = NumOps; i != e; ++i) { 2541 const MachineOperand& MO = MI.getOperand(i); 2542 if (isX86_64ExtendedReg(MO)) 2543 REX |= 1 << 0; 2544 } 2545 break; 2546 } 2547 case X86II::MRMSrcMem: { 2548 if (isX86_64ExtendedReg(MI.getOperand(0))) 2549 REX |= 1 << 2; 2550 unsigned Bit = 0; 2551 i = isTwoAddr ? 2 : 1; 2552 for (; i != NumOps; ++i) { 2553 const MachineOperand& MO = MI.getOperand(i); 2554 if (MO.isReg()) { 2555 if (isX86_64ExtendedReg(MO)) 2556 REX |= 1 << Bit; 2557 Bit++; 2558 } 2559 } 2560 break; 2561 } 2562 case X86II::MRM0m: case X86II::MRM1m: 2563 case X86II::MRM2m: case X86II::MRM3m: 2564 case X86II::MRM4m: case X86II::MRM5m: 2565 case X86II::MRM6m: case X86II::MRM7m: 2566 case X86II::MRMDestMem: { 2567 unsigned e = isTwoAddr ? 5 : 4; 2568 i = isTwoAddr ? 1 : 0; 2569 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) 2570 REX |= 1 << 2; 2571 unsigned Bit = 0; 2572 for (; i != e; ++i) { 2573 const MachineOperand& MO = MI.getOperand(i); 2574 if (MO.isReg()) { 2575 if (isX86_64ExtendedReg(MO)) 2576 REX |= 1 << Bit; 2577 Bit++; 2578 } 2579 } 2580 break; 2581 } 2582 default: { 2583 if (isX86_64ExtendedReg(MI.getOperand(0))) 2584 REX |= 1 << 0; 2585 i = isTwoAddr ? 2 : 1; 2586 for (unsigned e = NumOps; i != e; ++i) { 2587 const MachineOperand& MO = MI.getOperand(i); 2588 if (isX86_64ExtendedReg(MO)) 2589 REX |= 1 << 2; 2590 } 2591 break; 2592 } 2593 } 2594 } 2595 return REX; 2596} 2597 2598/// sizePCRelativeBlockAddress - This method returns the size of a PC 2599/// relative block address instruction 2600/// 2601static unsigned sizePCRelativeBlockAddress() { 2602 return 4; 2603} 2604 2605/// sizeGlobalAddress - Give the size of the emission of this global address 2606/// 2607static unsigned sizeGlobalAddress(bool dword) { 2608 return dword ? 8 : 4; 2609} 2610 2611/// sizeConstPoolAddress - Give the size of the emission of this constant 2612/// pool address 2613/// 2614static unsigned sizeConstPoolAddress(bool dword) { 2615 return dword ? 8 : 4; 2616} 2617 2618/// sizeExternalSymbolAddress - Give the size of the emission of this external 2619/// symbol 2620/// 2621static unsigned sizeExternalSymbolAddress(bool dword) { 2622 return dword ? 8 : 4; 2623} 2624 2625/// sizeJumpTableAddress - Give the size of the emission of this jump 2626/// table address 2627/// 2628static unsigned sizeJumpTableAddress(bool dword) { 2629 return dword ? 8 : 4; 2630} 2631 2632static unsigned sizeConstant(unsigned Size) { 2633 return Size; 2634} 2635 2636static unsigned sizeRegModRMByte(){ 2637 return 1; 2638} 2639 2640static unsigned sizeSIBByte(){ 2641 return 1; 2642} 2643 2644static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { 2645 unsigned FinalSize = 0; 2646 // If this is a simple integer displacement that doesn't require a relocation. 2647 if (!RelocOp) { 2648 FinalSize += sizeConstant(4); 2649 return FinalSize; 2650 } 2651 2652 // Otherwise, this is something that requires a relocation. 2653 if (RelocOp->isGlobal()) { 2654 FinalSize += sizeGlobalAddress(false); 2655 } else if (RelocOp->isCPI()) { 2656 FinalSize += sizeConstPoolAddress(false); 2657 } else if (RelocOp->isJTI()) { 2658 FinalSize += sizeJumpTableAddress(false); 2659 } else { 2660 assert(0 && "Unknown value to relocate!"); 2661 } 2662 return FinalSize; 2663} 2664 2665static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op, 2666 bool IsPIC, bool Is64BitMode) { 2667 const MachineOperand &Op3 = MI.getOperand(Op+3); 2668 int DispVal = 0; 2669 const MachineOperand *DispForReloc = 0; 2670 unsigned FinalSize = 0; 2671 2672 // Figure out what sort of displacement we have to handle here. 2673 if (Op3.isGlobal()) { 2674 DispForReloc = &Op3; 2675 } else if (Op3.isCPI()) { 2676 if (Is64BitMode || IsPIC) { 2677 DispForReloc = &Op3; 2678 } else { 2679 DispVal = 1; 2680 } 2681 } else if (Op3.isJTI()) { 2682 if (Is64BitMode || IsPIC) { 2683 DispForReloc = &Op3; 2684 } else { 2685 DispVal = 1; 2686 } 2687 } else { 2688 DispVal = 1; 2689 } 2690 2691 const MachineOperand &Base = MI.getOperand(Op); 2692 const MachineOperand &IndexReg = MI.getOperand(Op+2); 2693 2694 unsigned BaseReg = Base.getReg(); 2695 2696 // Is a SIB byte needed? 2697 if (IndexReg.getReg() == 0 && 2698 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) { 2699 if (BaseReg == 0) { // Just a displacement? 2700 // Emit special case [disp32] encoding 2701 ++FinalSize; 2702 FinalSize += getDisplacementFieldSize(DispForReloc); 2703 } else { 2704 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); 2705 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 2706 // Emit simple indirect register encoding... [EAX] f.e. 2707 ++FinalSize; 2708 // Be pessimistic and assume it's a disp32, not a disp8 2709 } else { 2710 // Emit the most general non-SIB encoding: [REG+disp32] 2711 ++FinalSize; 2712 FinalSize += getDisplacementFieldSize(DispForReloc); 2713 } 2714 } 2715 2716 } else { // We need a SIB byte, so start by outputting the ModR/M byte first 2717 assert(IndexReg.getReg() != X86::ESP && 2718 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 2719 2720 bool ForceDisp32 = false; 2721 if (BaseReg == 0 || DispForReloc) { 2722 // Emit the normal disp32 encoding. 2723 ++FinalSize; 2724 ForceDisp32 = true; 2725 } else { 2726 ++FinalSize; 2727 } 2728 2729 FinalSize += sizeSIBByte(); 2730 2731 // Do we need to output a displacement? 2732 if (DispVal != 0 || ForceDisp32) { 2733 FinalSize += getDisplacementFieldSize(DispForReloc); 2734 } 2735 } 2736 return FinalSize; 2737} 2738 2739 2740static unsigned GetInstSizeWithDesc(const MachineInstr &MI, 2741 const TargetInstrDesc *Desc, 2742 bool IsPIC, bool Is64BitMode) { 2743 2744 unsigned Opcode = Desc->Opcode; 2745 unsigned FinalSize = 0; 2746 2747 // Emit the lock opcode prefix as needed. 2748 if (Desc->TSFlags & X86II::LOCK) ++FinalSize; 2749 2750 // Emit segment overrid opcode prefix as needed. 2751 switch (Desc->TSFlags & X86II::SegOvrMask) { 2752 case X86II::FS: 2753 case X86II::GS: 2754 ++FinalSize; 2755 break; 2756 default: assert(0 && "Invalid segment!"); 2757 case 0: break; // No segment override! 2758 } 2759 2760 // Emit the repeat opcode prefix as needed. 2761 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize; 2762 2763 // Emit the operand size opcode prefix as needed. 2764 if (Desc->TSFlags & X86II::OpSize) ++FinalSize; 2765 2766 // Emit the address size opcode prefix as needed. 2767 if (Desc->TSFlags & X86II::AdSize) ++FinalSize; 2768 2769 bool Need0FPrefix = false; 2770 switch (Desc->TSFlags & X86II::Op0Mask) { 2771 case X86II::TB: // Two-byte opcode prefix 2772 case X86II::T8: // 0F 38 2773 case X86II::TA: // 0F 3A 2774 Need0FPrefix = true; 2775 break; 2776 case X86II::REP: break; // already handled. 2777 case X86II::XS: // F3 0F 2778 ++FinalSize; 2779 Need0FPrefix = true; 2780 break; 2781 case X86II::XD: // F2 0F 2782 ++FinalSize; 2783 Need0FPrefix = true; 2784 break; 2785 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 2786 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 2787 ++FinalSize; 2788 break; // Two-byte opcode prefix 2789 default: assert(0 && "Invalid prefix!"); 2790 case 0: break; // No prefix! 2791 } 2792 2793 if (Is64BitMode) { 2794 // REX prefix 2795 unsigned REX = X86InstrInfo::determineREX(MI); 2796 if (REX) 2797 ++FinalSize; 2798 } 2799 2800 // 0x0F escape code must be emitted just before the opcode. 2801 if (Need0FPrefix) 2802 ++FinalSize; 2803 2804 switch (Desc->TSFlags & X86II::Op0Mask) { 2805 case X86II::T8: // 0F 38 2806 ++FinalSize; 2807 break; 2808 case X86II::TA: // 0F 3A 2809 ++FinalSize; 2810 break; 2811 } 2812 2813 // If this is a two-address instruction, skip one of the register operands. 2814 unsigned NumOps = Desc->getNumOperands(); 2815 unsigned CurOp = 0; 2816 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) 2817 CurOp++; 2818 2819 switch (Desc->TSFlags & X86II::FormMask) { 2820 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!"); 2821 case X86II::Pseudo: 2822 // Remember the current PC offset, this is the PIC relocation 2823 // base address. 2824 switch (Opcode) { 2825 default: 2826 break; 2827 case TargetInstrInfo::INLINEASM: { 2828 const MachineFunction *MF = MI.getParent()->getParent(); 2829 const char *AsmStr = MI.getOperand(0).getSymbolName(); 2830 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo(); 2831 FinalSize += AI->getInlineAsmLength(AsmStr); 2832 break; 2833 } 2834 case TargetInstrInfo::DBG_LABEL: 2835 case TargetInstrInfo::EH_LABEL: 2836 break; 2837 case TargetInstrInfo::IMPLICIT_DEF: 2838 case TargetInstrInfo::DECLARE: 2839 case X86::DWARF_LOC: 2840 case X86::FP_REG_KILL: 2841 break; 2842 case X86::MOVPC32r: { 2843 // This emits the "call" portion of this pseudo instruction. 2844 ++FinalSize; 2845 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2846 break; 2847 } 2848 case X86::TLS_tp: 2849 case X86::TLS_gs_ri: 2850 FinalSize += 2; 2851 FinalSize += sizeGlobalAddress(false); 2852 break; 2853 } 2854 CurOp = NumOps; 2855 break; 2856 case X86II::RawFrm: 2857 ++FinalSize; 2858 2859 if (CurOp != NumOps) { 2860 const MachineOperand &MO = MI.getOperand(CurOp++); 2861 if (MO.isMBB()) { 2862 FinalSize += sizePCRelativeBlockAddress(); 2863 } else if (MO.isGlobal()) { 2864 FinalSize += sizeGlobalAddress(false); 2865 } else if (MO.isSymbol()) { 2866 FinalSize += sizeExternalSymbolAddress(false); 2867 } else if (MO.isImm()) { 2868 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2869 } else { 2870 assert(0 && "Unknown RawFrm operand!"); 2871 } 2872 } 2873 break; 2874 2875 case X86II::AddRegFrm: 2876 ++FinalSize; 2877 ++CurOp; 2878 2879 if (CurOp != NumOps) { 2880 const MachineOperand &MO1 = MI.getOperand(CurOp++); 2881 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 2882 if (MO1.isImm()) 2883 FinalSize += sizeConstant(Size); 2884 else { 2885 bool dword = false; 2886 if (Opcode == X86::MOV64ri) 2887 dword = true; 2888 if (MO1.isGlobal()) { 2889 FinalSize += sizeGlobalAddress(dword); 2890 } else if (MO1.isSymbol()) 2891 FinalSize += sizeExternalSymbolAddress(dword); 2892 else if (MO1.isCPI()) 2893 FinalSize += sizeConstPoolAddress(dword); 2894 else if (MO1.isJTI()) 2895 FinalSize += sizeJumpTableAddress(dword); 2896 } 2897 } 2898 break; 2899 2900 case X86II::MRMDestReg: { 2901 ++FinalSize; 2902 FinalSize += sizeRegModRMByte(); 2903 CurOp += 2; 2904 if (CurOp != NumOps) { 2905 ++CurOp; 2906 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2907 } 2908 break; 2909 } 2910 case X86II::MRMDestMem: { 2911 ++FinalSize; 2912 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 2913 CurOp += 5; 2914 if (CurOp != NumOps) { 2915 ++CurOp; 2916 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2917 } 2918 break; 2919 } 2920 2921 case X86II::MRMSrcReg: 2922 ++FinalSize; 2923 FinalSize += sizeRegModRMByte(); 2924 CurOp += 2; 2925 if (CurOp != NumOps) { 2926 ++CurOp; 2927 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2928 } 2929 break; 2930 2931 case X86II::MRMSrcMem: { 2932 2933 ++FinalSize; 2934 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode); 2935 CurOp += 5; 2936 if (CurOp != NumOps) { 2937 ++CurOp; 2938 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2939 } 2940 break; 2941 } 2942 2943 case X86II::MRM0r: case X86II::MRM1r: 2944 case X86II::MRM2r: case X86II::MRM3r: 2945 case X86II::MRM4r: case X86II::MRM5r: 2946 case X86II::MRM6r: case X86II::MRM7r: 2947 ++FinalSize; 2948 ++CurOp; 2949 FinalSize += sizeRegModRMByte(); 2950 2951 if (CurOp != NumOps) { 2952 const MachineOperand &MO1 = MI.getOperand(CurOp++); 2953 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 2954 if (MO1.isImm()) 2955 FinalSize += sizeConstant(Size); 2956 else { 2957 bool dword = false; 2958 if (Opcode == X86::MOV64ri32) 2959 dword = true; 2960 if (MO1.isGlobal()) { 2961 FinalSize += sizeGlobalAddress(dword); 2962 } else if (MO1.isSymbol()) 2963 FinalSize += sizeExternalSymbolAddress(dword); 2964 else if (MO1.isCPI()) 2965 FinalSize += sizeConstPoolAddress(dword); 2966 else if (MO1.isJTI()) 2967 FinalSize += sizeJumpTableAddress(dword); 2968 } 2969 } 2970 break; 2971 2972 case X86II::MRM0m: case X86II::MRM1m: 2973 case X86II::MRM2m: case X86II::MRM3m: 2974 case X86II::MRM4m: case X86II::MRM5m: 2975 case X86II::MRM6m: case X86II::MRM7m: { 2976 2977 ++FinalSize; 2978 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 2979 CurOp += 4; 2980 2981 if (CurOp != NumOps) { 2982 const MachineOperand &MO = MI.getOperand(CurOp++); 2983 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 2984 if (MO.isImm()) 2985 FinalSize += sizeConstant(Size); 2986 else { 2987 bool dword = false; 2988 if (Opcode == X86::MOV64mi32) 2989 dword = true; 2990 if (MO.isGlobal()) { 2991 FinalSize += sizeGlobalAddress(dword); 2992 } else if (MO.isSymbol()) 2993 FinalSize += sizeExternalSymbolAddress(dword); 2994 else if (MO.isCPI()) 2995 FinalSize += sizeConstPoolAddress(dword); 2996 else if (MO.isJTI()) 2997 FinalSize += sizeJumpTableAddress(dword); 2998 } 2999 } 3000 break; 3001 } 3002 3003 case X86II::MRMInitReg: 3004 ++FinalSize; 3005 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 3006 FinalSize += sizeRegModRMByte(); 3007 ++CurOp; 3008 break; 3009 } 3010 3011 if (!Desc->isVariadic() && CurOp != NumOps) { 3012 cerr << "Cannot determine size: "; 3013 MI.dump(); 3014 cerr << '\n'; 3015 abort(); 3016 } 3017 3018 3019 return FinalSize; 3020} 3021 3022 3023unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 3024 const TargetInstrDesc &Desc = MI->getDesc(); 3025 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_); 3026 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); 3027 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); 3028 if (Desc.getOpcode() == X86::MOVPC32r) { 3029 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); 3030 } 3031 return Size; 3032} 3033 3034/// getGlobalBaseReg - Return a virtual register initialized with the 3035/// the global base register value. Output instructions required to 3036/// initialize the register in the function entry block, if necessary. 3037/// 3038unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3039 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3040 "X86-64 PIC uses RIP relative addressing"); 3041 3042 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3043 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3044 if (GlobalBaseReg != 0) 3045 return GlobalBaseReg; 3046 3047 // Insert the set of GlobalBaseReg into the first MBB of the function 3048 MachineBasicBlock &FirstMBB = MF->front(); 3049 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3050 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3051 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3052 3053 const TargetInstrInfo *TII = TM.getInstrInfo(); 3054 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3055 // only used in JIT code emission as displacement to pc. 3056 BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0); 3057 3058 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3059 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external 3060 if (TM.getRelocationModel() == Reloc::PIC_ && 3061 TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3062 GlobalBaseReg = 3063 RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3064 BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg) 3065 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_"); 3066 } else { 3067 GlobalBaseReg = PC; 3068 } 3069 3070 X86FI->setGlobalBaseReg(GlobalBaseReg); 3071 return GlobalBaseReg; 3072} 3073