X86InstrInfo.cpp revision ae1dc403274d3a64bcee31f15e2d25e4b7178811 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86GenInstrInfo.inc"
17#include "X86InstrBuilder.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21using namespace llvm;
22
23X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
24  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
25    TM(tm), RI(tm, *this) {
26}
27
28/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
29/// instruction if it has one.  This is used by codegen passes that update
30/// DWARF line number info as they modify the code.
31unsigned X86InstrInfo::getDWARF_LABELOpcode() const {
32  return X86::DWARF_LABEL;
33}
34
35
36bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
37                               unsigned& sourceReg,
38                               unsigned& destReg) const {
39  MachineOpCode oc = MI.getOpcode();
40  if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
41      oc == X86::MOV32rr || oc == X86::MOV64rr ||
42      oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
43      oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
44      oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
45      oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
46      oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
47      oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
48      oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
49      oc == X86::MOVPDI2DIrr) {
50      assert(MI.getNumOperands() == 2 &&
51             MI.getOperand(0).isRegister() &&
52             MI.getOperand(1).isRegister() &&
53             "invalid register-register move instruction");
54      sourceReg = MI.getOperand(1).getReg();
55      destReg = MI.getOperand(0).getReg();
56      return true;
57  }
58  return false;
59}
60
61unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
62                                           int &FrameIndex) const {
63  switch (MI->getOpcode()) {
64  default: break;
65  case X86::MOV8rm:
66  case X86::MOV16rm:
67  case X86::MOV16_rm:
68  case X86::MOV32rm:
69  case X86::MOV32_rm:
70  case X86::MOV64rm:
71  case X86::FpLD64m:
72  case X86::MOVSSrm:
73  case X86::MOVSDrm:
74  case X86::MOVAPSrm:
75  case X86::MOVAPDrm:
76    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
77        MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
78        MI->getOperand(2).getImmedValue() == 1 &&
79        MI->getOperand(3).getReg() == 0 &&
80        MI->getOperand(4).getImmedValue() == 0) {
81      FrameIndex = MI->getOperand(1).getFrameIndex();
82      return MI->getOperand(0).getReg();
83    }
84    break;
85  }
86  return 0;
87}
88
89unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
90                                          int &FrameIndex) const {
91  switch (MI->getOpcode()) {
92  default: break;
93  case X86::MOV8mr:
94  case X86::MOV16mr:
95  case X86::MOV16_mr:
96  case X86::MOV32mr:
97  case X86::MOV32_mr:
98  case X86::MOV64mr:
99  case X86::FpSTP64m:
100  case X86::MOVSSmr:
101  case X86::MOVSDmr:
102  case X86::MOVAPSmr:
103  case X86::MOVAPDmr:
104    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
105        MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
106        MI->getOperand(1).getImmedValue() == 1 &&
107        MI->getOperand(2).getReg() == 0 &&
108        MI->getOperand(3).getImmedValue() == 0) {
109      FrameIndex = MI->getOperand(0).getFrameIndex();
110      return MI->getOperand(4).getReg();
111    }
112    break;
113  }
114  return 0;
115}
116
117
118/// convertToThreeAddress - This method must be implemented by targets that
119/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
120/// may be able to convert a two-address instruction into a true
121/// three-address instruction on demand.  This allows the X86 target (for
122/// example) to convert ADD and SHL instructions into LEA instructions if they
123/// would require register copies due to two-addressness.
124///
125/// This method returns a null pointer if the transformation cannot be
126/// performed, otherwise it returns the new instruction.
127///
128MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
129  // All instructions input are two-addr instructions.  Get the known operands.
130  unsigned Dest = MI->getOperand(0).getReg();
131  unsigned Src = MI->getOperand(1).getReg();
132
133  switch (MI->getOpcode()) {
134  default: break;
135  case X86::SHUFPSrri: {
136    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
137    const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
138    unsigned A = MI->getOperand(0).getReg();
139    unsigned B = MI->getOperand(1).getReg();
140    unsigned C = MI->getOperand(2).getReg();
141    unsigned M = MI->getOperand(3).getImmedValue();
142    if (!Subtarget->hasSSE2() || B != C) return 0;
143    return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
144  }
145  }
146
147  // FIXME: None of these instructions are promotable to LEAs without
148  // additional information.  In particular, LEA doesn't set the flags that
149  // add and inc do.  :(
150  return 0;
151
152  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
153  // we have subtarget support, enable the 16-bit LEA generation here.
154  bool DisableLEA16 = true;
155
156  switch (MI->getOpcode()) {
157  case X86::INC32r:
158  case X86::INC64_32r:
159    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
160    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
161  case X86::INC16r:
162  case X86::INC64_16r:
163    if (DisableLEA16) return 0;
164    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
165    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
166  case X86::DEC32r:
167  case X86::DEC64_32r:
168    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
169    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
170  case X86::DEC16r:
171  case X86::DEC64_16r:
172    if (DisableLEA16) return 0;
173    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
174    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
175  case X86::ADD32rr:
176    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
177    return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
178                     MI->getOperand(2).getReg());
179  case X86::ADD16rr:
180    if (DisableLEA16) return 0;
181    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
182    return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
183                     MI->getOperand(2).getReg());
184  case X86::ADD32ri:
185  case X86::ADD32ri8:
186    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
187    if (MI->getOperand(2).isImmediate())
188      return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
189                          MI->getOperand(2).getImmedValue());
190    return 0;
191  case X86::ADD16ri:
192  case X86::ADD16ri8:
193    if (DisableLEA16) return 0;
194    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
195    if (MI->getOperand(2).isImmediate())
196      return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
197                          MI->getOperand(2).getImmedValue());
198    break;
199
200  case X86::SHL16ri:
201    if (DisableLEA16) return 0;
202  case X86::SHL32ri:
203    assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
204           "Unknown shl instruction!");
205    unsigned ShAmt = MI->getOperand(2).getImmedValue();
206    if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
207      X86AddressMode AM;
208      AM.Scale = 1 << ShAmt;
209      AM.IndexReg = Src;
210      unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
211      return addFullAddress(BuildMI(Opc, 5, Dest), AM);
212    }
213    break;
214  }
215
216  return 0;
217}
218
219/// commuteInstruction - We have a few instructions that must be hacked on to
220/// commute them.
221///
222MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
223  // FIXME: Can commute cmoves by changing the condition!
224  switch (MI->getOpcode()) {
225  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
226  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
227  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
228  case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
229    unsigned Opc;
230    unsigned Size;
231    switch (MI->getOpcode()) {
232    default: assert(0 && "Unreachable!");
233    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
234    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
235    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
236    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
237    }
238    unsigned Amt = MI->getOperand(3).getImmedValue();
239    unsigned A = MI->getOperand(0).getReg();
240    unsigned B = MI->getOperand(1).getReg();
241    unsigned C = MI->getOperand(2).getReg();
242    return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
243  }
244  default:
245    return TargetInstrInfo::commuteInstruction(MI);
246  }
247}
248
249const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
250  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
251  if (Subtarget->is64Bit())
252    return &X86::GR64RegClass;
253  else
254    return &X86::GR32RegClass;
255}
256