X86InstrInfo.cpp revision fe5cb19405794e478b944581c3a7be5c29cbaa0e 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "X86GenInstrInfo.inc"
19using namespace llvm;
20
21X86InstrInfo::X86InstrInfo()
22  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
23}
24
25
26bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
27                               unsigned& sourceReg,
28                               unsigned& destReg) const {
29  MachineOpCode oc = MI.getOpcode();
30  if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
31      oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
32      oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
33      oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
34      assert(MI.getNumOperands() == 2 &&
35             MI.getOperand(0).isRegister() &&
36             MI.getOperand(1).isRegister() &&
37             "invalid register-register move instruction");
38      sourceReg = MI.getOperand(1).getReg();
39      destReg = MI.getOperand(0).getReg();
40      return true;
41  }
42  return false;
43}
44
45unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
46                                           int &FrameIndex) const {
47  switch (MI->getOpcode()) {
48  default: break;
49  case X86::MOV8rm:
50  case X86::MOV16rm:
51  case X86::MOV32rm:
52  case X86::FpLD64m:
53  case X86::MOVSSrm:
54  case X86::MOVSDrm:
55    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
56        MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
57        MI->getOperand(2).getImmedValue() == 1 &&
58        MI->getOperand(3).getReg() == 0 &&
59        MI->getOperand(4).getImmedValue() == 0) {
60      FrameIndex = MI->getOperand(1).getFrameIndex();
61      return MI->getOperand(0).getReg();
62    }
63    break;
64  }
65  return 0;
66}
67
68unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
69                                          int &FrameIndex) const {
70  switch (MI->getOpcode()) {
71  default: break;
72  case X86::MOV8mr:
73  case X86::MOV16mr:
74  case X86::MOV32mr:
75  case X86::FpSTP64m:
76  case X86::MOVSSmr:
77  case X86::MOVSDmr:
78    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
79        MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
80        MI->getOperand(1).getImmedValue() == 1 &&
81        MI->getOperand(2).getReg() == 0 &&
82        MI->getOperand(3).getImmedValue() == 0) {
83      FrameIndex = MI->getOperand(0).getFrameIndex();
84      return MI->getOperand(4).getReg();
85    }
86    break;
87  }
88  return 0;
89}
90
91
92
93/// convertToThreeAddress - This method must be implemented by targets that
94/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
95/// may be able to convert a two-address instruction into a true
96/// three-address instruction on demand.  This allows the X86 target (for
97/// example) to convert ADD and SHL instructions into LEA instructions if they
98/// would require register copies due to two-addressness.
99///
100/// This method returns a null pointer if the transformation cannot be
101/// performed, otherwise it returns the new instruction.
102///
103MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
104  // All instructions input are two-addr instructions.  Get the known operands.
105  unsigned Dest = MI->getOperand(0).getReg();
106  unsigned Src = MI->getOperand(1).getReg();
107
108  // FIXME: None of these instructions are promotable to LEAs without
109  // additional information.  In particular, LEA doesn't set the flags that
110  // add and inc do.  :(
111  return 0;
112
113  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
114  // we have subtarget support, enable the 16-bit LEA generation here.
115  bool DisableLEA16 = true;
116
117  switch (MI->getOpcode()) {
118  case X86::INC32r:
119    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
120    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
121  case X86::INC16r:
122    if (DisableLEA16) return 0;
123    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
124    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
125  case X86::DEC32r:
126    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
127    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
128  case X86::DEC16r:
129    if (DisableLEA16) return 0;
130    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
131    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
132  case X86::ADD32rr:
133    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
134    return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
135                     MI->getOperand(2).getReg());
136  case X86::ADD16rr:
137    if (DisableLEA16) return 0;
138    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
139    return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
140                     MI->getOperand(2).getReg());
141  case X86::ADD32ri:
142    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
143    if (MI->getOperand(2).isImmediate())
144      return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
145                          MI->getOperand(2).getImmedValue());
146    return 0;
147  case X86::ADD16ri:
148    if (DisableLEA16) return 0;
149    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
150    if (MI->getOperand(2).isImmediate())
151      return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
152                          MI->getOperand(2).getImmedValue());
153    break;
154
155  case X86::SHL16ri:
156    if (DisableLEA16) return 0;
157  case X86::SHL32ri:
158    assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
159           "Unknown shl instruction!");
160    unsigned ShAmt = MI->getOperand(2).getImmedValue();
161    if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
162      X86AddressMode AM;
163      AM.Scale = 1 << ShAmt;
164      AM.IndexReg = Src;
165      unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
166      return addFullAddress(BuildMI(Opc, 5, Dest), AM);
167    }
168    break;
169  }
170
171  return 0;
172}
173
174/// commuteInstruction - We have a few instructions that must be hacked on to
175/// commute them.
176///
177MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
178  switch (MI->getOpcode()) {
179  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
180  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
181  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
182  case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
183    unsigned Opc;
184    unsigned Size;
185    switch (MI->getOpcode()) {
186    default: assert(0 && "Unreachable!");
187    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
188    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
189    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
190    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
191    }
192    unsigned Amt = MI->getOperand(3).getImmedValue();
193    unsigned A = MI->getOperand(0).getReg();
194    unsigned B = MI->getOperand(1).getReg();
195    unsigned C = MI->getOperand(2).getReg();
196    return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
197  }
198  default:
199    return TargetInstrInfo::commuteInstruction(MI);
200  }
201}
202
203
204void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
205                              MachineBasicBlock& TMBB) const {
206  BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
207}
208
209MachineBasicBlock::iterator
210X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
211  unsigned Opcode = MI->getOpcode();
212  assert(isBranch(Opcode) && "MachineInstr must be a branch");
213  unsigned ROpcode;
214  switch (Opcode) {
215  default: assert(0 && "Cannot reverse unconditional branches!");
216  case X86::JB:  ROpcode = X86::JAE; break;
217  case X86::JAE: ROpcode = X86::JB;  break;
218  case X86::JE:  ROpcode = X86::JNE; break;
219  case X86::JNE: ROpcode = X86::JE;  break;
220  case X86::JBE: ROpcode = X86::JA;  break;
221  case X86::JA:  ROpcode = X86::JBE; break;
222  case X86::JS:  ROpcode = X86::JNS; break;
223  case X86::JNS: ROpcode = X86::JS;  break;
224  case X86::JP:  ROpcode = X86::JNP; break;
225  case X86::JNP: ROpcode = X86::JP;  break;
226  case X86::JL:  ROpcode = X86::JGE; break;
227  case X86::JGE: ROpcode = X86::JL;  break;
228  case X86::JLE: ROpcode = X86::JG;  break;
229  case X86::JG:  ROpcode = X86::JLE; break;
230  }
231  MachineBasicBlock* MBB = MI->getParent();
232  MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
233  return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
234}
235
236