X86InstrInfo.cpp revision 81cf4325698b48b02eddab921ac333c7f25005c3 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86GenInstrInfo.inc"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/LLVMContext.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/LiveVariables.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/raw_ostream.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/MC/MCAsmInfo.h"
34using namespace llvm;
35
36static cl::opt<bool>
37NoFusing("disable-spill-fusing",
38         cl::desc("Disable fusing of spill code into instructions"));
39static cl::opt<bool>
40PrintFailedFusing("print-failed-fuse-candidates",
41                  cl::desc("Print instructions that the allocator wants to"
42                           " fuse, but the X86 backend currently can't"),
43                  cl::Hidden);
44static cl::opt<bool>
45ReMatPICStubLoad("remat-pic-stub-load",
46                 cl::desc("Re-materialize load from stub in PIC mode"),
47                 cl::init(false), cl::Hidden);
48
49X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
50  : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
51    TM(tm), RI(tm, *this) {
52  SmallVector<unsigned,16> AmbEntries;
53  static const unsigned OpTbl2Addr[][2] = {
54    { X86::ADC32ri,     X86::ADC32mi },
55    { X86::ADC32ri8,    X86::ADC32mi8 },
56    { X86::ADC32rr,     X86::ADC32mr },
57    { X86::ADC64ri32,   X86::ADC64mi32 },
58    { X86::ADC64ri8,    X86::ADC64mi8 },
59    { X86::ADC64rr,     X86::ADC64mr },
60    { X86::ADD16ri,     X86::ADD16mi },
61    { X86::ADD16ri8,    X86::ADD16mi8 },
62    { X86::ADD16rr,     X86::ADD16mr },
63    { X86::ADD32ri,     X86::ADD32mi },
64    { X86::ADD32ri8,    X86::ADD32mi8 },
65    { X86::ADD32rr,     X86::ADD32mr },
66    { X86::ADD64ri32,   X86::ADD64mi32 },
67    { X86::ADD64ri8,    X86::ADD64mi8 },
68    { X86::ADD64rr,     X86::ADD64mr },
69    { X86::ADD8ri,      X86::ADD8mi },
70    { X86::ADD8rr,      X86::ADD8mr },
71    { X86::AND16ri,     X86::AND16mi },
72    { X86::AND16ri8,    X86::AND16mi8 },
73    { X86::AND16rr,     X86::AND16mr },
74    { X86::AND32ri,     X86::AND32mi },
75    { X86::AND32ri8,    X86::AND32mi8 },
76    { X86::AND32rr,     X86::AND32mr },
77    { X86::AND64ri32,   X86::AND64mi32 },
78    { X86::AND64ri8,    X86::AND64mi8 },
79    { X86::AND64rr,     X86::AND64mr },
80    { X86::AND8ri,      X86::AND8mi },
81    { X86::AND8rr,      X86::AND8mr },
82    { X86::DEC16r,      X86::DEC16m },
83    { X86::DEC32r,      X86::DEC32m },
84    { X86::DEC64_16r,   X86::DEC64_16m },
85    { X86::DEC64_32r,   X86::DEC64_32m },
86    { X86::DEC64r,      X86::DEC64m },
87    { X86::DEC8r,       X86::DEC8m },
88    { X86::INC16r,      X86::INC16m },
89    { X86::INC32r,      X86::INC32m },
90    { X86::INC64_16r,   X86::INC64_16m },
91    { X86::INC64_32r,   X86::INC64_32m },
92    { X86::INC64r,      X86::INC64m },
93    { X86::INC8r,       X86::INC8m },
94    { X86::NEG16r,      X86::NEG16m },
95    { X86::NEG32r,      X86::NEG32m },
96    { X86::NEG64r,      X86::NEG64m },
97    { X86::NEG8r,       X86::NEG8m },
98    { X86::NOT16r,      X86::NOT16m },
99    { X86::NOT32r,      X86::NOT32m },
100    { X86::NOT64r,      X86::NOT64m },
101    { X86::NOT8r,       X86::NOT8m },
102    { X86::OR16ri,      X86::OR16mi },
103    { X86::OR16ri8,     X86::OR16mi8 },
104    { X86::OR16rr,      X86::OR16mr },
105    { X86::OR32ri,      X86::OR32mi },
106    { X86::OR32ri8,     X86::OR32mi8 },
107    { X86::OR32rr,      X86::OR32mr },
108    { X86::OR64ri32,    X86::OR64mi32 },
109    { X86::OR64ri8,     X86::OR64mi8 },
110    { X86::OR64rr,      X86::OR64mr },
111    { X86::OR8ri,       X86::OR8mi },
112    { X86::OR8rr,       X86::OR8mr },
113    { X86::ROL16r1,     X86::ROL16m1 },
114    { X86::ROL16rCL,    X86::ROL16mCL },
115    { X86::ROL16ri,     X86::ROL16mi },
116    { X86::ROL32r1,     X86::ROL32m1 },
117    { X86::ROL32rCL,    X86::ROL32mCL },
118    { X86::ROL32ri,     X86::ROL32mi },
119    { X86::ROL64r1,     X86::ROL64m1 },
120    { X86::ROL64rCL,    X86::ROL64mCL },
121    { X86::ROL64ri,     X86::ROL64mi },
122    { X86::ROL8r1,      X86::ROL8m1 },
123    { X86::ROL8rCL,     X86::ROL8mCL },
124    { X86::ROL8ri,      X86::ROL8mi },
125    { X86::ROR16r1,     X86::ROR16m1 },
126    { X86::ROR16rCL,    X86::ROR16mCL },
127    { X86::ROR16ri,     X86::ROR16mi },
128    { X86::ROR32r1,     X86::ROR32m1 },
129    { X86::ROR32rCL,    X86::ROR32mCL },
130    { X86::ROR32ri,     X86::ROR32mi },
131    { X86::ROR64r1,     X86::ROR64m1 },
132    { X86::ROR64rCL,    X86::ROR64mCL },
133    { X86::ROR64ri,     X86::ROR64mi },
134    { X86::ROR8r1,      X86::ROR8m1 },
135    { X86::ROR8rCL,     X86::ROR8mCL },
136    { X86::ROR8ri,      X86::ROR8mi },
137    { X86::SAR16r1,     X86::SAR16m1 },
138    { X86::SAR16rCL,    X86::SAR16mCL },
139    { X86::SAR16ri,     X86::SAR16mi },
140    { X86::SAR32r1,     X86::SAR32m1 },
141    { X86::SAR32rCL,    X86::SAR32mCL },
142    { X86::SAR32ri,     X86::SAR32mi },
143    { X86::SAR64r1,     X86::SAR64m1 },
144    { X86::SAR64rCL,    X86::SAR64mCL },
145    { X86::SAR64ri,     X86::SAR64mi },
146    { X86::SAR8r1,      X86::SAR8m1 },
147    { X86::SAR8rCL,     X86::SAR8mCL },
148    { X86::SAR8ri,      X86::SAR8mi },
149    { X86::SBB32ri,     X86::SBB32mi },
150    { X86::SBB32ri8,    X86::SBB32mi8 },
151    { X86::SBB32rr,     X86::SBB32mr },
152    { X86::SBB64ri32,   X86::SBB64mi32 },
153    { X86::SBB64ri8,    X86::SBB64mi8 },
154    { X86::SBB64rr,     X86::SBB64mr },
155    { X86::SHL16rCL,    X86::SHL16mCL },
156    { X86::SHL16ri,     X86::SHL16mi },
157    { X86::SHL32rCL,    X86::SHL32mCL },
158    { X86::SHL32ri,     X86::SHL32mi },
159    { X86::SHL64rCL,    X86::SHL64mCL },
160    { X86::SHL64ri,     X86::SHL64mi },
161    { X86::SHL8rCL,     X86::SHL8mCL },
162    { X86::SHL8ri,      X86::SHL8mi },
163    { X86::SHLD16rrCL,  X86::SHLD16mrCL },
164    { X86::SHLD16rri8,  X86::SHLD16mri8 },
165    { X86::SHLD32rrCL,  X86::SHLD32mrCL },
166    { X86::SHLD32rri8,  X86::SHLD32mri8 },
167    { X86::SHLD64rrCL,  X86::SHLD64mrCL },
168    { X86::SHLD64rri8,  X86::SHLD64mri8 },
169    { X86::SHR16r1,     X86::SHR16m1 },
170    { X86::SHR16rCL,    X86::SHR16mCL },
171    { X86::SHR16ri,     X86::SHR16mi },
172    { X86::SHR32r1,     X86::SHR32m1 },
173    { X86::SHR32rCL,    X86::SHR32mCL },
174    { X86::SHR32ri,     X86::SHR32mi },
175    { X86::SHR64r1,     X86::SHR64m1 },
176    { X86::SHR64rCL,    X86::SHR64mCL },
177    { X86::SHR64ri,     X86::SHR64mi },
178    { X86::SHR8r1,      X86::SHR8m1 },
179    { X86::SHR8rCL,     X86::SHR8mCL },
180    { X86::SHR8ri,      X86::SHR8mi },
181    { X86::SHRD16rrCL,  X86::SHRD16mrCL },
182    { X86::SHRD16rri8,  X86::SHRD16mri8 },
183    { X86::SHRD32rrCL,  X86::SHRD32mrCL },
184    { X86::SHRD32rri8,  X86::SHRD32mri8 },
185    { X86::SHRD64rrCL,  X86::SHRD64mrCL },
186    { X86::SHRD64rri8,  X86::SHRD64mri8 },
187    { X86::SUB16ri,     X86::SUB16mi },
188    { X86::SUB16ri8,    X86::SUB16mi8 },
189    { X86::SUB16rr,     X86::SUB16mr },
190    { X86::SUB32ri,     X86::SUB32mi },
191    { X86::SUB32ri8,    X86::SUB32mi8 },
192    { X86::SUB32rr,     X86::SUB32mr },
193    { X86::SUB64ri32,   X86::SUB64mi32 },
194    { X86::SUB64ri8,    X86::SUB64mi8 },
195    { X86::SUB64rr,     X86::SUB64mr },
196    { X86::SUB8ri,      X86::SUB8mi },
197    { X86::SUB8rr,      X86::SUB8mr },
198    { X86::XOR16ri,     X86::XOR16mi },
199    { X86::XOR16ri8,    X86::XOR16mi8 },
200    { X86::XOR16rr,     X86::XOR16mr },
201    { X86::XOR32ri,     X86::XOR32mi },
202    { X86::XOR32ri8,    X86::XOR32mi8 },
203    { X86::XOR32rr,     X86::XOR32mr },
204    { X86::XOR64ri32,   X86::XOR64mi32 },
205    { X86::XOR64ri8,    X86::XOR64mi8 },
206    { X86::XOR64rr,     X86::XOR64mr },
207    { X86::XOR8ri,      X86::XOR8mi },
208    { X86::XOR8rr,      X86::XOR8mr }
209  };
210
211  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
212    unsigned RegOp = OpTbl2Addr[i][0];
213    unsigned MemOp = OpTbl2Addr[i][1];
214    if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
215                                               std::make_pair(MemOp,0))).second)
216      assert(false && "Duplicated entries?");
217    // Index 0, folded load and store, no alignment requirement.
218    unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
219    if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
220                                                std::make_pair(RegOp,
221                                                              AuxInfo))).second)
222      AmbEntries.push_back(MemOp);
223  }
224
225  // If the third value is 1, then it's folding either a load or a store.
226  static const unsigned OpTbl0[][4] = {
227    { X86::BT16ri8,     X86::BT16mi8, 1, 0 },
228    { X86::BT32ri8,     X86::BT32mi8, 1, 0 },
229    { X86::BT64ri8,     X86::BT64mi8, 1, 0 },
230    { X86::CALL32r,     X86::CALL32m, 1, 0 },
231    { X86::CALL64r,     X86::CALL64m, 1, 0 },
232    { X86::CMP16ri,     X86::CMP16mi, 1, 0 },
233    { X86::CMP16ri8,    X86::CMP16mi8, 1, 0 },
234    { X86::CMP16rr,     X86::CMP16mr, 1, 0 },
235    { X86::CMP32ri,     X86::CMP32mi, 1, 0 },
236    { X86::CMP32ri8,    X86::CMP32mi8, 1, 0 },
237    { X86::CMP32rr,     X86::CMP32mr, 1, 0 },
238    { X86::CMP64ri32,   X86::CMP64mi32, 1, 0 },
239    { X86::CMP64ri8,    X86::CMP64mi8, 1, 0 },
240    { X86::CMP64rr,     X86::CMP64mr, 1, 0 },
241    { X86::CMP8ri,      X86::CMP8mi, 1, 0 },
242    { X86::CMP8rr,      X86::CMP8mr, 1, 0 },
243    { X86::DIV16r,      X86::DIV16m, 1, 0 },
244    { X86::DIV32r,      X86::DIV32m, 1, 0 },
245    { X86::DIV64r,      X86::DIV64m, 1, 0 },
246    { X86::DIV8r,       X86::DIV8m, 1, 0 },
247    { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
248    { X86::FsMOVAPDrr,  X86::MOVSDmr, 0, 0 },
249    { X86::FsMOVAPSrr,  X86::MOVSSmr, 0, 0 },
250    { X86::IDIV16r,     X86::IDIV16m, 1, 0 },
251    { X86::IDIV32r,     X86::IDIV32m, 1, 0 },
252    { X86::IDIV64r,     X86::IDIV64m, 1, 0 },
253    { X86::IDIV8r,      X86::IDIV8m, 1, 0 },
254    { X86::IMUL16r,     X86::IMUL16m, 1, 0 },
255    { X86::IMUL32r,     X86::IMUL32m, 1, 0 },
256    { X86::IMUL64r,     X86::IMUL64m, 1, 0 },
257    { X86::IMUL8r,      X86::IMUL8m, 1, 0 },
258    { X86::JMP32r,      X86::JMP32m, 1, 0 },
259    { X86::JMP64r,      X86::JMP64m, 1, 0 },
260    { X86::MOV16ri,     X86::MOV16mi, 0, 0 },
261    { X86::MOV16rr,     X86::MOV16mr, 0, 0 },
262    { X86::MOV32ri,     X86::MOV32mi, 0, 0 },
263    { X86::MOV32rr,     X86::MOV32mr, 0, 0 },
264    { X86::MOV64ri32,   X86::MOV64mi32, 0, 0 },
265    { X86::MOV64rr,     X86::MOV64mr, 0, 0 },
266    { X86::MOV8ri,      X86::MOV8mi, 0, 0 },
267    { X86::MOV8rr,      X86::MOV8mr, 0, 0 },
268    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
269    { X86::MOVAPDrr,    X86::MOVAPDmr, 0, 16 },
270    { X86::MOVAPSrr,    X86::MOVAPSmr, 0, 16 },
271    { X86::MOVDQArr,    X86::MOVDQAmr, 0, 16 },
272    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
273    { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
274    { X86::MOVPS2SSrr,  X86::MOVPS2SSmr, 0, 0 },
275    { X86::MOVSDrr,     X86::MOVSDmr, 0, 0 },
276    { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
277    { X86::MOVSS2DIrr,  X86::MOVSS2DImr, 0, 0 },
278    { X86::MOVSSrr,     X86::MOVSSmr, 0, 0 },
279    { X86::MOVUPDrr,    X86::MOVUPDmr, 0, 0 },
280    { X86::MOVUPSrr,    X86::MOVUPSmr, 0, 0 },
281    { X86::MUL16r,      X86::MUL16m, 1, 0 },
282    { X86::MUL32r,      X86::MUL32m, 1, 0 },
283    { X86::MUL64r,      X86::MUL64m, 1, 0 },
284    { X86::MUL8r,       X86::MUL8m, 1, 0 },
285    { X86::SETAEr,      X86::SETAEm, 0, 0 },
286    { X86::SETAr,       X86::SETAm, 0, 0 },
287    { X86::SETBEr,      X86::SETBEm, 0, 0 },
288    { X86::SETBr,       X86::SETBm, 0, 0 },
289    { X86::SETEr,       X86::SETEm, 0, 0 },
290    { X86::SETGEr,      X86::SETGEm, 0, 0 },
291    { X86::SETGr,       X86::SETGm, 0, 0 },
292    { X86::SETLEr,      X86::SETLEm, 0, 0 },
293    { X86::SETLr,       X86::SETLm, 0, 0 },
294    { X86::SETNEr,      X86::SETNEm, 0, 0 },
295    { X86::SETNOr,      X86::SETNOm, 0, 0 },
296    { X86::SETNPr,      X86::SETNPm, 0, 0 },
297    { X86::SETNSr,      X86::SETNSm, 0, 0 },
298    { X86::SETOr,       X86::SETOm, 0, 0 },
299    { X86::SETPr,       X86::SETPm, 0, 0 },
300    { X86::SETSr,       X86::SETSm, 0, 0 },
301    { X86::TAILJMPr,    X86::TAILJMPm, 1, 0 },
302    { X86::TEST16ri,    X86::TEST16mi, 1, 0 },
303    { X86::TEST32ri,    X86::TEST32mi, 1, 0 },
304    { X86::TEST64ri32,  X86::TEST64mi32, 1, 0 },
305    { X86::TEST8ri,     X86::TEST8mi, 1, 0 }
306  };
307
308  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
309    unsigned RegOp = OpTbl0[i][0];
310    unsigned MemOp = OpTbl0[i][1];
311    unsigned Align = OpTbl0[i][3];
312    if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
313                                           std::make_pair(MemOp,Align))).second)
314      assert(false && "Duplicated entries?");
315    unsigned FoldedLoad = OpTbl0[i][2];
316    // Index 0, folded load or store.
317    unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
318    if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
319      if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
320                                     std::make_pair(RegOp, AuxInfo))).second)
321        AmbEntries.push_back(MemOp);
322  }
323
324  static const unsigned OpTbl1[][3] = {
325    { X86::CMP16rr,         X86::CMP16rm, 0 },
326    { X86::CMP32rr,         X86::CMP32rm, 0 },
327    { X86::CMP64rr,         X86::CMP64rm, 0 },
328    { X86::CMP8rr,          X86::CMP8rm, 0 },
329    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm, 0 },
330    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm, 0 },
331    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm, 0 },
332    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm, 0 },
333    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm, 0 },
334    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm, 0 },
335    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm, 0 },
336    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm, 0 },
337    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm, 0 },
338    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm, 0 },
339    { X86::FsMOVAPDrr,      X86::MOVSDrm, 0 },
340    { X86::FsMOVAPSrr,      X86::MOVSSrm, 0 },
341    { X86::IMUL16rri,       X86::IMUL16rmi, 0 },
342    { X86::IMUL16rri8,      X86::IMUL16rmi8, 0 },
343    { X86::IMUL32rri,       X86::IMUL32rmi, 0 },
344    { X86::IMUL32rri8,      X86::IMUL32rmi8, 0 },
345    { X86::IMUL64rri32,     X86::IMUL64rmi32, 0 },
346    { X86::IMUL64rri8,      X86::IMUL64rmi8, 0 },
347    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm, 0 },
348    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm, 0 },
349    { X86::Int_COMISDrr,    X86::Int_COMISDrm, 0 },
350    { X86::Int_COMISSrr,    X86::Int_COMISSrm, 0 },
351    { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm, 16 },
352    { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm, 16 },
353    { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm, 16 },
354    { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm, 16 },
355    { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm, 16 },
356    { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm, 0 },
357    { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
358    { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm, 0 },
359    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm, 0 },
360    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
361    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm, 0 },
362    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
363    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm, 0 },
364    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm, 0 },
365    { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
366    { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm, 0 },
367    { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
368    { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
369    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
370    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
371    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
372    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
373    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm, 0 },
374    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm, 0 },
375    { X86::MOV16rr,         X86::MOV16rm, 0 },
376    { X86::MOV32rr,         X86::MOV32rm, 0 },
377    { X86::MOV64rr,         X86::MOV64rm, 0 },
378    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm, 0 },
379    { X86::MOV64toSDrr,     X86::MOV64toSDrm, 0 },
380    { X86::MOV8rr,          X86::MOV8rm, 0 },
381    { X86::MOVAPDrr,        X86::MOVAPDrm, 16 },
382    { X86::MOVAPSrr,        X86::MOVAPSrm, 16 },
383    { X86::MOVDDUPrr,       X86::MOVDDUPrm, 0 },
384    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm, 0 },
385    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm, 0 },
386    { X86::MOVDQArr,        X86::MOVDQArm, 16 },
387    { X86::MOVSD2PDrr,      X86::MOVSD2PDrm, 0 },
388    { X86::MOVSDrr,         X86::MOVSDrm, 0 },
389    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm, 16 },
390    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm, 16 },
391    { X86::MOVSS2PSrr,      X86::MOVSS2PSrm, 0 },
392    { X86::MOVSSrr,         X86::MOVSSrm, 0 },
393    { X86::MOVSX16rr8,      X86::MOVSX16rm8, 0 },
394    { X86::MOVSX32rr16,     X86::MOVSX32rm16, 0 },
395    { X86::MOVSX32rr8,      X86::MOVSX32rm8, 0 },
396    { X86::MOVSX64rr16,     X86::MOVSX64rm16, 0 },
397    { X86::MOVSX64rr32,     X86::MOVSX64rm32, 0 },
398    { X86::MOVSX64rr8,      X86::MOVSX64rm8, 0 },
399    { X86::MOVUPDrr,        X86::MOVUPDrm, 16 },
400    { X86::MOVUPSrr,        X86::MOVUPSrm, 16 },
401    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm, 0 },
402    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm, 0 },
403    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
404    { X86::MOVZX16rr8,      X86::MOVZX16rm8, 0 },
405    { X86::MOVZX32rr16,     X86::MOVZX32rm16, 0 },
406    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
407    { X86::MOVZX32rr8,      X86::MOVZX32rm8, 0 },
408    { X86::MOVZX64rr16,     X86::MOVZX64rm16, 0 },
409    { X86::MOVZX64rr32,     X86::MOVZX64rm32, 0 },
410    { X86::MOVZX64rr8,      X86::MOVZX64rm8, 0 },
411    { X86::PSHUFDri,        X86::PSHUFDmi, 16 },
412    { X86::PSHUFHWri,       X86::PSHUFHWmi, 16 },
413    { X86::PSHUFLWri,       X86::PSHUFLWmi, 16 },
414    { X86::RCPPSr,          X86::RCPPSm, 16 },
415    { X86::RCPPSr_Int,      X86::RCPPSm_Int, 16 },
416    { X86::RSQRTPSr,        X86::RSQRTPSm, 16 },
417    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int, 16 },
418    { X86::RSQRTSSr,        X86::RSQRTSSm, 0 },
419    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int, 0 },
420    { X86::SQRTPDr,         X86::SQRTPDm, 16 },
421    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int, 16 },
422    { X86::SQRTPSr,         X86::SQRTPSm, 16 },
423    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int, 16 },
424    { X86::SQRTSDr,         X86::SQRTSDm, 0 },
425    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int, 0 },
426    { X86::SQRTSSr,         X86::SQRTSSm, 0 },
427    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int, 0 },
428    { X86::TEST16rr,        X86::TEST16rm, 0 },
429    { X86::TEST32rr,        X86::TEST32rm, 0 },
430    { X86::TEST64rr,        X86::TEST64rm, 0 },
431    { X86::TEST8rr,         X86::TEST8rm, 0 },
432    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
433    { X86::UCOMISDrr,       X86::UCOMISDrm, 0 },
434    { X86::UCOMISSrr,       X86::UCOMISSrm, 0 }
435  };
436
437  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
438    unsigned RegOp = OpTbl1[i][0];
439    unsigned MemOp = OpTbl1[i][1];
440    unsigned Align = OpTbl1[i][2];
441    if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
442                                           std::make_pair(MemOp,Align))).second)
443      assert(false && "Duplicated entries?");
444    // Index 1, folded load
445    unsigned AuxInfo = 1 | (1 << 4);
446    if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
447      if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
448                                     std::make_pair(RegOp, AuxInfo))).second)
449        AmbEntries.push_back(MemOp);
450  }
451
452  static const unsigned OpTbl2[][3] = {
453    { X86::ADC32rr,         X86::ADC32rm, 0 },
454    { X86::ADC64rr,         X86::ADC64rm, 0 },
455    { X86::ADD16rr,         X86::ADD16rm, 0 },
456    { X86::ADD32rr,         X86::ADD32rm, 0 },
457    { X86::ADD64rr,         X86::ADD64rm, 0 },
458    { X86::ADD8rr,          X86::ADD8rm, 0 },
459    { X86::ADDPDrr,         X86::ADDPDrm, 16 },
460    { X86::ADDPSrr,         X86::ADDPSrm, 16 },
461    { X86::ADDSDrr,         X86::ADDSDrm, 0 },
462    { X86::ADDSSrr,         X86::ADDSSrm, 0 },
463    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm, 16 },
464    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm, 16 },
465    { X86::AND16rr,         X86::AND16rm, 0 },
466    { X86::AND32rr,         X86::AND32rm, 0 },
467    { X86::AND64rr,         X86::AND64rm, 0 },
468    { X86::AND8rr,          X86::AND8rm, 0 },
469    { X86::ANDNPDrr,        X86::ANDNPDrm, 16 },
470    { X86::ANDNPSrr,        X86::ANDNPSrm, 16 },
471    { X86::ANDPDrr,         X86::ANDPDrm, 16 },
472    { X86::ANDPSrr,         X86::ANDPSrm, 16 },
473    { X86::CMOVA16rr,       X86::CMOVA16rm, 0 },
474    { X86::CMOVA32rr,       X86::CMOVA32rm, 0 },
475    { X86::CMOVA64rr,       X86::CMOVA64rm, 0 },
476    { X86::CMOVAE16rr,      X86::CMOVAE16rm, 0 },
477    { X86::CMOVAE32rr,      X86::CMOVAE32rm, 0 },
478    { X86::CMOVAE64rr,      X86::CMOVAE64rm, 0 },
479    { X86::CMOVB16rr,       X86::CMOVB16rm, 0 },
480    { X86::CMOVB32rr,       X86::CMOVB32rm, 0 },
481    { X86::CMOVB64rr,       X86::CMOVB64rm, 0 },
482    { X86::CMOVBE16rr,      X86::CMOVBE16rm, 0 },
483    { X86::CMOVBE32rr,      X86::CMOVBE32rm, 0 },
484    { X86::CMOVBE64rr,      X86::CMOVBE64rm, 0 },
485    { X86::CMOVE16rr,       X86::CMOVE16rm, 0 },
486    { X86::CMOVE32rr,       X86::CMOVE32rm, 0 },
487    { X86::CMOVE64rr,       X86::CMOVE64rm, 0 },
488    { X86::CMOVG16rr,       X86::CMOVG16rm, 0 },
489    { X86::CMOVG32rr,       X86::CMOVG32rm, 0 },
490    { X86::CMOVG64rr,       X86::CMOVG64rm, 0 },
491    { X86::CMOVGE16rr,      X86::CMOVGE16rm, 0 },
492    { X86::CMOVGE32rr,      X86::CMOVGE32rm, 0 },
493    { X86::CMOVGE64rr,      X86::CMOVGE64rm, 0 },
494    { X86::CMOVL16rr,       X86::CMOVL16rm, 0 },
495    { X86::CMOVL32rr,       X86::CMOVL32rm, 0 },
496    { X86::CMOVL64rr,       X86::CMOVL64rm, 0 },
497    { X86::CMOVLE16rr,      X86::CMOVLE16rm, 0 },
498    { X86::CMOVLE32rr,      X86::CMOVLE32rm, 0 },
499    { X86::CMOVLE64rr,      X86::CMOVLE64rm, 0 },
500    { X86::CMOVNE16rr,      X86::CMOVNE16rm, 0 },
501    { X86::CMOVNE32rr,      X86::CMOVNE32rm, 0 },
502    { X86::CMOVNE64rr,      X86::CMOVNE64rm, 0 },
503    { X86::CMOVNO16rr,      X86::CMOVNO16rm, 0 },
504    { X86::CMOVNO32rr,      X86::CMOVNO32rm, 0 },
505    { X86::CMOVNO64rr,      X86::CMOVNO64rm, 0 },
506    { X86::CMOVNP16rr,      X86::CMOVNP16rm, 0 },
507    { X86::CMOVNP32rr,      X86::CMOVNP32rm, 0 },
508    { X86::CMOVNP64rr,      X86::CMOVNP64rm, 0 },
509    { X86::CMOVNS16rr,      X86::CMOVNS16rm, 0 },
510    { X86::CMOVNS32rr,      X86::CMOVNS32rm, 0 },
511    { X86::CMOVNS64rr,      X86::CMOVNS64rm, 0 },
512    { X86::CMOVO16rr,       X86::CMOVO16rm, 0 },
513    { X86::CMOVO32rr,       X86::CMOVO32rm, 0 },
514    { X86::CMOVO64rr,       X86::CMOVO64rm, 0 },
515    { X86::CMOVP16rr,       X86::CMOVP16rm, 0 },
516    { X86::CMOVP32rr,       X86::CMOVP32rm, 0 },
517    { X86::CMOVP64rr,       X86::CMOVP64rm, 0 },
518    { X86::CMOVS16rr,       X86::CMOVS16rm, 0 },
519    { X86::CMOVS32rr,       X86::CMOVS32rm, 0 },
520    { X86::CMOVS64rr,       X86::CMOVS64rm, 0 },
521    { X86::CMPPDrri,        X86::CMPPDrmi, 16 },
522    { X86::CMPPSrri,        X86::CMPPSrmi, 16 },
523    { X86::CMPSDrr,         X86::CMPSDrm, 0 },
524    { X86::CMPSSrr,         X86::CMPSSrm, 0 },
525    { X86::DIVPDrr,         X86::DIVPDrm, 16 },
526    { X86::DIVPSrr,         X86::DIVPSrm, 16 },
527    { X86::DIVSDrr,         X86::DIVSDrm, 0 },
528    { X86::DIVSSrr,         X86::DIVSSrm, 0 },
529    { X86::FsANDNPDrr,      X86::FsANDNPDrm, 16 },
530    { X86::FsANDNPSrr,      X86::FsANDNPSrm, 16 },
531    { X86::FsANDPDrr,       X86::FsANDPDrm, 16 },
532    { X86::FsANDPSrr,       X86::FsANDPSrm, 16 },
533    { X86::FsORPDrr,        X86::FsORPDrm, 16 },
534    { X86::FsORPSrr,        X86::FsORPSrm, 16 },
535    { X86::FsXORPDrr,       X86::FsXORPDrm, 16 },
536    { X86::FsXORPSrr,       X86::FsXORPSrm, 16 },
537    { X86::HADDPDrr,        X86::HADDPDrm, 16 },
538    { X86::HADDPSrr,        X86::HADDPSrm, 16 },
539    { X86::HSUBPDrr,        X86::HSUBPDrm, 16 },
540    { X86::HSUBPSrr,        X86::HSUBPSrm, 16 },
541    { X86::IMUL16rr,        X86::IMUL16rm, 0 },
542    { X86::IMUL32rr,        X86::IMUL32rm, 0 },
543    { X86::IMUL64rr,        X86::IMUL64rm, 0 },
544    { X86::MAXPDrr,         X86::MAXPDrm, 16 },
545    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int, 16 },
546    { X86::MAXPSrr,         X86::MAXPSrm, 16 },
547    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int, 16 },
548    { X86::MAXSDrr,         X86::MAXSDrm, 0 },
549    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int, 0 },
550    { X86::MAXSSrr,         X86::MAXSSrm, 0 },
551    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int, 0 },
552    { X86::MINPDrr,         X86::MINPDrm, 16 },
553    { X86::MINPDrr_Int,     X86::MINPDrm_Int, 16 },
554    { X86::MINPSrr,         X86::MINPSrm, 16 },
555    { X86::MINPSrr_Int,     X86::MINPSrm_Int, 16 },
556    { X86::MINSDrr,         X86::MINSDrm, 0 },
557    { X86::MINSDrr_Int,     X86::MINSDrm_Int, 0 },
558    { X86::MINSSrr,         X86::MINSSrm, 0 },
559    { X86::MINSSrr_Int,     X86::MINSSrm_Int, 0 },
560    { X86::MULPDrr,         X86::MULPDrm, 16 },
561    { X86::MULPSrr,         X86::MULPSrm, 16 },
562    { X86::MULSDrr,         X86::MULSDrm, 0 },
563    { X86::MULSSrr,         X86::MULSSrm, 0 },
564    { X86::OR16rr,          X86::OR16rm, 0 },
565    { X86::OR32rr,          X86::OR32rm, 0 },
566    { X86::OR64rr,          X86::OR64rm, 0 },
567    { X86::OR8rr,           X86::OR8rm, 0 },
568    { X86::ORPDrr,          X86::ORPDrm, 16 },
569    { X86::ORPSrr,          X86::ORPSrm, 16 },
570    { X86::PACKSSDWrr,      X86::PACKSSDWrm, 16 },
571    { X86::PACKSSWBrr,      X86::PACKSSWBrm, 16 },
572    { X86::PACKUSWBrr,      X86::PACKUSWBrm, 16 },
573    { X86::PADDBrr,         X86::PADDBrm, 16 },
574    { X86::PADDDrr,         X86::PADDDrm, 16 },
575    { X86::PADDQrr,         X86::PADDQrm, 16 },
576    { X86::PADDSBrr,        X86::PADDSBrm, 16 },
577    { X86::PADDSWrr,        X86::PADDSWrm, 16 },
578    { X86::PADDWrr,         X86::PADDWrm, 16 },
579    { X86::PANDNrr,         X86::PANDNrm, 16 },
580    { X86::PANDrr,          X86::PANDrm, 16 },
581    { X86::PAVGBrr,         X86::PAVGBrm, 16 },
582    { X86::PAVGWrr,         X86::PAVGWrm, 16 },
583    { X86::PCMPEQBrr,       X86::PCMPEQBrm, 16 },
584    { X86::PCMPEQDrr,       X86::PCMPEQDrm, 16 },
585    { X86::PCMPEQWrr,       X86::PCMPEQWrm, 16 },
586    { X86::PCMPGTBrr,       X86::PCMPGTBrm, 16 },
587    { X86::PCMPGTDrr,       X86::PCMPGTDrm, 16 },
588    { X86::PCMPGTWrr,       X86::PCMPGTWrm, 16 },
589    { X86::PINSRWrri,       X86::PINSRWrmi, 16 },
590    { X86::PMADDWDrr,       X86::PMADDWDrm, 16 },
591    { X86::PMAXSWrr,        X86::PMAXSWrm, 16 },
592    { X86::PMAXUBrr,        X86::PMAXUBrm, 16 },
593    { X86::PMINSWrr,        X86::PMINSWrm, 16 },
594    { X86::PMINUBrr,        X86::PMINUBrm, 16 },
595    { X86::PMULDQrr,        X86::PMULDQrm, 16 },
596    { X86::PMULHUWrr,       X86::PMULHUWrm, 16 },
597    { X86::PMULHWrr,        X86::PMULHWrm, 16 },
598    { X86::PMULLDrr,        X86::PMULLDrm, 16 },
599    { X86::PMULLDrr_int,    X86::PMULLDrm_int, 16 },
600    { X86::PMULLWrr,        X86::PMULLWrm, 16 },
601    { X86::PMULUDQrr,       X86::PMULUDQrm, 16 },
602    { X86::PORrr,           X86::PORrm, 16 },
603    { X86::PSADBWrr,        X86::PSADBWrm, 16 },
604    { X86::PSLLDrr,         X86::PSLLDrm, 16 },
605    { X86::PSLLQrr,         X86::PSLLQrm, 16 },
606    { X86::PSLLWrr,         X86::PSLLWrm, 16 },
607    { X86::PSRADrr,         X86::PSRADrm, 16 },
608    { X86::PSRAWrr,         X86::PSRAWrm, 16 },
609    { X86::PSRLDrr,         X86::PSRLDrm, 16 },
610    { X86::PSRLQrr,         X86::PSRLQrm, 16 },
611    { X86::PSRLWrr,         X86::PSRLWrm, 16 },
612    { X86::PSUBBrr,         X86::PSUBBrm, 16 },
613    { X86::PSUBDrr,         X86::PSUBDrm, 16 },
614    { X86::PSUBSBrr,        X86::PSUBSBrm, 16 },
615    { X86::PSUBSWrr,        X86::PSUBSWrm, 16 },
616    { X86::PSUBWrr,         X86::PSUBWrm, 16 },
617    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm, 16 },
618    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm, 16 },
619    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm, 16 },
620    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm, 16 },
621    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm, 16 },
622    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm, 16 },
623    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm, 16 },
624    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm, 16 },
625    { X86::PXORrr,          X86::PXORrm, 16 },
626    { X86::SBB32rr,         X86::SBB32rm, 0 },
627    { X86::SBB64rr,         X86::SBB64rm, 0 },
628    { X86::SHUFPDrri,       X86::SHUFPDrmi, 16 },
629    { X86::SHUFPSrri,       X86::SHUFPSrmi, 16 },
630    { X86::SUB16rr,         X86::SUB16rm, 0 },
631    { X86::SUB32rr,         X86::SUB32rm, 0 },
632    { X86::SUB64rr,         X86::SUB64rm, 0 },
633    { X86::SUB8rr,          X86::SUB8rm, 0 },
634    { X86::SUBPDrr,         X86::SUBPDrm, 16 },
635    { X86::SUBPSrr,         X86::SUBPSrm, 16 },
636    { X86::SUBSDrr,         X86::SUBSDrm, 0 },
637    { X86::SUBSSrr,         X86::SUBSSrm, 0 },
638    // FIXME: TEST*rr -> swapped operand of TEST*mr.
639    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm, 16 },
640    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm, 16 },
641    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm, 16 },
642    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm, 16 },
643    { X86::XOR16rr,         X86::XOR16rm, 0 },
644    { X86::XOR32rr,         X86::XOR32rm, 0 },
645    { X86::XOR64rr,         X86::XOR64rm, 0 },
646    { X86::XOR8rr,          X86::XOR8rm, 0 },
647    { X86::XORPDrr,         X86::XORPDrm, 16 },
648    { X86::XORPSrr,         X86::XORPSrm, 16 }
649  };
650
651  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
652    unsigned RegOp = OpTbl2[i][0];
653    unsigned MemOp = OpTbl2[i][1];
654    unsigned Align = OpTbl2[i][2];
655    if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
656                                           std::make_pair(MemOp,Align))).second)
657      assert(false && "Duplicated entries?");
658    // Index 2, folded load
659    unsigned AuxInfo = 2 | (1 << 4);
660    if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
661                                   std::make_pair(RegOp, AuxInfo))).second)
662      AmbEntries.push_back(MemOp);
663  }
664
665  // Remove ambiguous entries.
666  assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
667}
668
669bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
670                               unsigned &SrcReg, unsigned &DstReg,
671                               unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
672  switch (MI.getOpcode()) {
673  default:
674    return false;
675  case X86::MOV8rr:
676  case X86::MOV8rr_NOREX:
677  case X86::MOV16rr:
678  case X86::MOV32rr:
679  case X86::MOV64rr:
680  case X86::MOVSSrr:
681  case X86::MOVSDrr:
682
683  // FP Stack register class copies
684  case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
685  case X86::MOV_Fp3264: case X86::MOV_Fp3280:
686  case X86::MOV_Fp6432: case X86::MOV_Fp8032:
687
688  case X86::FsMOVAPSrr:
689  case X86::FsMOVAPDrr:
690  case X86::MOVAPSrr:
691  case X86::MOVAPDrr:
692  case X86::MOVDQArr:
693  case X86::MOVSS2PSrr:
694  case X86::MOVSD2PDrr:
695  case X86::MOVPS2SSrr:
696  case X86::MOVPD2SDrr:
697  case X86::MMX_MOVQ64rr:
698    assert(MI.getNumOperands() >= 2 &&
699           MI.getOperand(0).isReg() &&
700           MI.getOperand(1).isReg() &&
701           "invalid register-register move instruction");
702    SrcReg = MI.getOperand(1).getReg();
703    DstReg = MI.getOperand(0).getReg();
704    SrcSubIdx = MI.getOperand(1).getSubReg();
705    DstSubIdx = MI.getOperand(0).getSubReg();
706    return true;
707  }
708}
709
710unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
711                                           int &FrameIndex) const {
712  switch (MI->getOpcode()) {
713  default: break;
714  case X86::MOV8rm:
715  case X86::MOV16rm:
716  case X86::MOV32rm:
717  case X86::MOV64rm:
718  case X86::LD_Fp64m:
719  case X86::MOVSSrm:
720  case X86::MOVSDrm:
721  case X86::MOVAPSrm:
722  case X86::MOVAPDrm:
723  case X86::MOVDQArm:
724  case X86::MMX_MOVD64rm:
725  case X86::MMX_MOVQ64rm:
726    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
727        MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
728        MI->getOperand(2).getImm() == 1 &&
729        MI->getOperand(3).getReg() == 0 &&
730        MI->getOperand(4).getImm() == 0) {
731      FrameIndex = MI->getOperand(1).getIndex();
732      return MI->getOperand(0).getReg();
733    }
734    break;
735  }
736  return 0;
737}
738
739unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
740                                          int &FrameIndex) const {
741  switch (MI->getOpcode()) {
742  default: break;
743  case X86::MOV8mr:
744  case X86::MOV16mr:
745  case X86::MOV32mr:
746  case X86::MOV64mr:
747  case X86::ST_FpP64m:
748  case X86::MOVSSmr:
749  case X86::MOVSDmr:
750  case X86::MOVAPSmr:
751  case X86::MOVAPDmr:
752  case X86::MOVDQAmr:
753  case X86::MMX_MOVD64mr:
754  case X86::MMX_MOVQ64mr:
755  case X86::MMX_MOVNTQmr:
756    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
757        MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
758        MI->getOperand(1).getImm() == 1 &&
759        MI->getOperand(2).getReg() == 0 &&
760        MI->getOperand(3).getImm() == 0) {
761      FrameIndex = MI->getOperand(0).getIndex();
762      return MI->getOperand(X86AddrNumOperands).getReg();
763    }
764    break;
765  }
766  return 0;
767}
768
769/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
770/// X86::MOVPC32r.
771static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
772  bool isPICBase = false;
773  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
774         E = MRI.def_end(); I != E; ++I) {
775    MachineInstr *DefMI = I.getOperand().getParent();
776    if (DefMI->getOpcode() != X86::MOVPC32r)
777      return false;
778    assert(!isPICBase && "More than one PIC base?");
779    isPICBase = true;
780  }
781  return isPICBase;
782}
783
784bool
785X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
786                                                AliasAnalysis *AA) const {
787  switch (MI->getOpcode()) {
788  default: break;
789    case X86::MOV8rm:
790    case X86::MOV16rm:
791    case X86::MOV32rm:
792    case X86::MOV64rm:
793    case X86::LD_Fp64m:
794    case X86::MOVSSrm:
795    case X86::MOVSDrm:
796    case X86::MOVAPSrm:
797    case X86::MOVAPDrm:
798    case X86::MOVDQArm:
799    case X86::MMX_MOVD64rm:
800    case X86::MMX_MOVQ64rm: {
801      // Loads from constant pools are trivially rematerializable.
802      if (MI->getOperand(1).isReg() &&
803          MI->getOperand(2).isImm() &&
804          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
805          MI->isInvariantLoad(AA)) {
806        unsigned BaseReg = MI->getOperand(1).getReg();
807        if (BaseReg == 0 || BaseReg == X86::RIP)
808          return true;
809        // Allow re-materialization of PIC load.
810        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
811          return false;
812        const MachineFunction &MF = *MI->getParent()->getParent();
813        const MachineRegisterInfo &MRI = MF.getRegInfo();
814        bool isPICBase = false;
815        for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
816               E = MRI.def_end(); I != E; ++I) {
817          MachineInstr *DefMI = I.getOperand().getParent();
818          if (DefMI->getOpcode() != X86::MOVPC32r)
819            return false;
820          assert(!isPICBase && "More than one PIC base?");
821          isPICBase = true;
822        }
823        return isPICBase;
824      }
825      return false;
826    }
827
828     case X86::LEA32r:
829     case X86::LEA64r: {
830       if (MI->getOperand(2).isImm() &&
831           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
832           !MI->getOperand(4).isReg()) {
833         // lea fi#, lea GV, etc. are all rematerializable.
834         if (!MI->getOperand(1).isReg())
835           return true;
836         unsigned BaseReg = MI->getOperand(1).getReg();
837         if (BaseReg == 0)
838           return true;
839         // Allow re-materialization of lea PICBase + x.
840         const MachineFunction &MF = *MI->getParent()->getParent();
841         const MachineRegisterInfo &MRI = MF.getRegInfo();
842         return regIsPICBase(BaseReg, MRI);
843       }
844       return false;
845     }
846  }
847
848  // All other instructions marked M_REMATERIALIZABLE are always trivially
849  // rematerializable.
850  return true;
851}
852
853/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
854/// would clobber the EFLAGS condition register. Note the result may be
855/// conservative. If it cannot definitely determine the safety after visiting
856/// a few instructions in each direction it assumes it's not safe.
857static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
858                                  MachineBasicBlock::iterator I) {
859  // It's always safe to clobber EFLAGS at the end of a block.
860  if (I == MBB.end())
861    return true;
862
863  // For compile time consideration, if we are not able to determine the
864  // safety after visiting 4 instructions in each direction, we will assume
865  // it's not safe.
866  MachineBasicBlock::iterator Iter = I;
867  for (unsigned i = 0; i < 4; ++i) {
868    bool SeenDef = false;
869    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
870      MachineOperand &MO = Iter->getOperand(j);
871      if (!MO.isReg())
872        continue;
873      if (MO.getReg() == X86::EFLAGS) {
874        if (MO.isUse())
875          return false;
876        SeenDef = true;
877      }
878    }
879
880    if (SeenDef)
881      // This instruction defines EFLAGS, no need to look any further.
882      return true;
883    ++Iter;
884
885    // If we make it to the end of the block, it's safe to clobber EFLAGS.
886    if (Iter == MBB.end())
887      return true;
888  }
889
890  Iter = I;
891  for (unsigned i = 0; i < 4; ++i) {
892    // If we make it to the beginning of the block, it's safe to clobber
893    // EFLAGS iff EFLAGS is not live-in.
894    if (Iter == MBB.begin())
895      return !MBB.isLiveIn(X86::EFLAGS);
896
897    --Iter;
898    bool SawKill = false;
899    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
900      MachineOperand &MO = Iter->getOperand(j);
901      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
902        if (MO.isDef()) return MO.isDead();
903        if (MO.isKill()) SawKill = true;
904      }
905    }
906
907    if (SawKill)
908      // This instruction kills EFLAGS and doesn't redefine it, so
909      // there's no need to look further.
910      return true;
911  }
912
913  // Conservative answer.
914  return false;
915}
916
917void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
918                                 MachineBasicBlock::iterator I,
919                                 unsigned DestReg, unsigned SubIdx,
920                                 const MachineInstr *Orig) const {
921  DebugLoc DL = DebugLoc::getUnknownLoc();
922  if (I != MBB.end()) DL = I->getDebugLoc();
923
924  if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
925    DestReg = RI.getSubReg(DestReg, SubIdx);
926    SubIdx = 0;
927  }
928
929  // MOV32r0 etc. are implemented with xor which clobbers condition code.
930  // Re-materialize them as movri instructions to avoid side effects.
931  bool Clone = true;
932  unsigned Opc = Orig->getOpcode();
933  switch (Opc) {
934  default: break;
935  case X86::MOV8r0:
936  case X86::MOV16r0:
937  case X86::MOV32r0: {
938    if (!isSafeToClobberEFLAGS(MBB, I)) {
939      switch (Opc) {
940      default: break;
941      case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
942      case X86::MOV16r0: Opc = X86::MOV16ri; break;
943      case X86::MOV32r0: Opc = X86::MOV32ri; break;
944      }
945      Clone = false;
946    }
947    break;
948  }
949  }
950
951  if (Clone) {
952    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
953    MI->getOperand(0).setReg(DestReg);
954    MBB.insert(I, MI);
955  } else {
956    BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
957  }
958
959  MachineInstr *NewMI = prior(I);
960  NewMI->getOperand(0).setSubReg(SubIdx);
961}
962
963/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
964/// is not marked dead.
965static bool hasLiveCondCodeDef(MachineInstr *MI) {
966  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
967    MachineOperand &MO = MI->getOperand(i);
968    if (MO.isReg() && MO.isDef() &&
969        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
970      return true;
971    }
972  }
973  return false;
974}
975
976/// convertToThreeAddress - This method must be implemented by targets that
977/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
978/// may be able to convert a two-address instruction into a true
979/// three-address instruction on demand.  This allows the X86 target (for
980/// example) to convert ADD and SHL instructions into LEA instructions if they
981/// would require register copies due to two-addressness.
982///
983/// This method returns a null pointer if the transformation cannot be
984/// performed, otherwise it returns the new instruction.
985///
986MachineInstr *
987X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
988                                    MachineBasicBlock::iterator &MBBI,
989                                    LiveVariables *LV) const {
990  MachineInstr *MI = MBBI;
991  MachineFunction &MF = *MI->getParent()->getParent();
992  // All instructions input are two-addr instructions.  Get the known operands.
993  unsigned Dest = MI->getOperand(0).getReg();
994  unsigned Src = MI->getOperand(1).getReg();
995  bool isDead = MI->getOperand(0).isDead();
996  bool isKill = MI->getOperand(1).isKill();
997
998  MachineInstr *NewMI = NULL;
999  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1000  // we have better subtarget support, enable the 16-bit LEA generation here.
1001  bool DisableLEA16 = true;
1002
1003  unsigned MIOpc = MI->getOpcode();
1004  switch (MIOpc) {
1005  case X86::SHUFPSrri: {
1006    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1007    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1008
1009    unsigned B = MI->getOperand(1).getReg();
1010    unsigned C = MI->getOperand(2).getReg();
1011    if (B != C) return 0;
1012    unsigned A = MI->getOperand(0).getReg();
1013    unsigned M = MI->getOperand(3).getImm();
1014    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1015      .addReg(A, RegState::Define | getDeadRegState(isDead))
1016      .addReg(B, getKillRegState(isKill)).addImm(M);
1017    break;
1018  }
1019  case X86::SHL64ri: {
1020    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1021    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1022    // the flags produced by a shift yet, so this is safe.
1023    unsigned ShAmt = MI->getOperand(2).getImm();
1024    if (ShAmt == 0 || ShAmt >= 4) return 0;
1025
1026    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1027      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1028      .addReg(0).addImm(1 << ShAmt)
1029      .addReg(Src, getKillRegState(isKill))
1030      .addImm(0);
1031    break;
1032  }
1033  case X86::SHL32ri: {
1034    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1035    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1036    // the flags produced by a shift yet, so this is safe.
1037    unsigned ShAmt = MI->getOperand(2).getImm();
1038    if (ShAmt == 0 || ShAmt >= 4) return 0;
1039
1040    unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1041      X86::LEA64_32r : X86::LEA32r;
1042    NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1043      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1044      .addReg(0).addImm(1 << ShAmt)
1045      .addReg(Src, getKillRegState(isKill)).addImm(0);
1046    break;
1047  }
1048  case X86::SHL16ri: {
1049    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1050    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1051    // the flags produced by a shift yet, so this is safe.
1052    unsigned ShAmt = MI->getOperand(2).getImm();
1053    if (ShAmt == 0 || ShAmt >= 4) return 0;
1054
1055    if (DisableLEA16) {
1056      // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1057      MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1058      unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1059        ? X86::LEA64_32r : X86::LEA32r;
1060      unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1061      unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1062
1063      // Build and insert into an implicit UNDEF value. This is OK because
1064      // well be shifting and then extracting the lower 16-bits.
1065      BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1066      MachineInstr *InsMI =
1067        BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1068        .addReg(leaInReg)
1069        .addReg(Src, getKillRegState(isKill))
1070        .addImm(X86::SUBREG_16BIT);
1071
1072      NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1073        .addReg(0).addImm(1 << ShAmt)
1074        .addReg(leaInReg, RegState::Kill)
1075        .addImm(0);
1076
1077      MachineInstr *ExtMI =
1078        BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1079        .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1080        .addReg(leaOutReg, RegState::Kill)
1081        .addImm(X86::SUBREG_16BIT);
1082
1083      if (LV) {
1084        // Update live variables
1085        LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1086        LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1087        if (isKill)
1088          LV->replaceKillInstruction(Src, MI, InsMI);
1089        if (isDead)
1090          LV->replaceKillInstruction(Dest, MI, ExtMI);
1091      }
1092      return ExtMI;
1093    } else {
1094      NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1095        .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1096        .addReg(0).addImm(1 << ShAmt)
1097        .addReg(Src, getKillRegState(isKill))
1098        .addImm(0);
1099    }
1100    break;
1101  }
1102  default: {
1103    // The following opcodes also sets the condition code register(s). Only
1104    // convert them to equivalent lea if the condition code register def's
1105    // are dead!
1106    if (hasLiveCondCodeDef(MI))
1107      return 0;
1108
1109    bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1110    switch (MIOpc) {
1111    default: return 0;
1112    case X86::INC64r:
1113    case X86::INC32r:
1114    case X86::INC64_32r: {
1115      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1116      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1117        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1118      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1119                              .addReg(Dest, RegState::Define |
1120                                      getDeadRegState(isDead)),
1121                              Src, isKill, 1);
1122      break;
1123    }
1124    case X86::INC16r:
1125    case X86::INC64_16r:
1126      if (DisableLEA16) return 0;
1127      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1128      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1129                           .addReg(Dest, RegState::Define |
1130                                   getDeadRegState(isDead)),
1131                           Src, isKill, 1);
1132      break;
1133    case X86::DEC64r:
1134    case X86::DEC32r:
1135    case X86::DEC64_32r: {
1136      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1137      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1138        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1139      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1140                              .addReg(Dest, RegState::Define |
1141                                      getDeadRegState(isDead)),
1142                              Src, isKill, -1);
1143      break;
1144    }
1145    case X86::DEC16r:
1146    case X86::DEC64_16r:
1147      if (DisableLEA16) return 0;
1148      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1149      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1150                           .addReg(Dest, RegState::Define |
1151                                   getDeadRegState(isDead)),
1152                           Src, isKill, -1);
1153      break;
1154    case X86::ADD64rr:
1155    case X86::ADD32rr: {
1156      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1157      unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1158        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1159      unsigned Src2 = MI->getOperand(2).getReg();
1160      bool isKill2 = MI->getOperand(2).isKill();
1161      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1162                        .addReg(Dest, RegState::Define |
1163                                getDeadRegState(isDead)),
1164                        Src, isKill, Src2, isKill2);
1165      if (LV && isKill2)
1166        LV->replaceKillInstruction(Src2, MI, NewMI);
1167      break;
1168    }
1169    case X86::ADD16rr: {
1170      if (DisableLEA16) return 0;
1171      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1172      unsigned Src2 = MI->getOperand(2).getReg();
1173      bool isKill2 = MI->getOperand(2).isKill();
1174      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1175                        .addReg(Dest, RegState::Define |
1176                                getDeadRegState(isDead)),
1177                        Src, isKill, Src2, isKill2);
1178      if (LV && isKill2)
1179        LV->replaceKillInstruction(Src2, MI, NewMI);
1180      break;
1181    }
1182    case X86::ADD64ri32:
1183    case X86::ADD64ri8:
1184      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1185      if (MI->getOperand(2).isImm())
1186        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1187                                .addReg(Dest, RegState::Define |
1188                                        getDeadRegState(isDead)),
1189                                Src, isKill, MI->getOperand(2).getImm());
1190      break;
1191    case X86::ADD32ri:
1192    case X86::ADD32ri8:
1193      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1194      if (MI->getOperand(2).isImm()) {
1195        unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1196        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1197                                .addReg(Dest, RegState::Define |
1198                                        getDeadRegState(isDead)),
1199                                Src, isKill, MI->getOperand(2).getImm());
1200      }
1201      break;
1202    case X86::ADD16ri:
1203    case X86::ADD16ri8:
1204      if (DisableLEA16) return 0;
1205      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1206      if (MI->getOperand(2).isImm())
1207        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1208                             .addReg(Dest, RegState::Define |
1209                                     getDeadRegState(isDead)),
1210                             Src, isKill, MI->getOperand(2).getImm());
1211      break;
1212    case X86::SHL16ri:
1213      if (DisableLEA16) return 0;
1214    case X86::SHL32ri:
1215    case X86::SHL64ri: {
1216      assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1217             "Unknown shl instruction!");
1218      unsigned ShAmt = MI->getOperand(2).getImm();
1219      if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1220        X86AddressMode AM;
1221        AM.Scale = 1 << ShAmt;
1222        AM.IndexReg = Src;
1223        unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1224          : (MIOpc == X86::SHL32ri
1225             ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1226        NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1227                               .addReg(Dest, RegState::Define |
1228                                       getDeadRegState(isDead)), AM);
1229        if (isKill)
1230          NewMI->getOperand(3).setIsKill(true);
1231      }
1232      break;
1233    }
1234    }
1235  }
1236  }
1237
1238  if (!NewMI) return 0;
1239
1240  if (LV) {  // Update live variables
1241    if (isKill)
1242      LV->replaceKillInstruction(Src, MI, NewMI);
1243    if (isDead)
1244      LV->replaceKillInstruction(Dest, MI, NewMI);
1245  }
1246
1247  MFI->insert(MBBI, NewMI);          // Insert the new inst
1248  return NewMI;
1249}
1250
1251/// commuteInstruction - We have a few instructions that must be hacked on to
1252/// commute them.
1253///
1254MachineInstr *
1255X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1256  switch (MI->getOpcode()) {
1257  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1258  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1259  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1260  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1261  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1262  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1263    unsigned Opc;
1264    unsigned Size;
1265    switch (MI->getOpcode()) {
1266    default: llvm_unreachable("Unreachable!");
1267    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1268    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1269    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1270    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1271    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1272    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1273    }
1274    unsigned Amt = MI->getOperand(3).getImm();
1275    if (NewMI) {
1276      MachineFunction &MF = *MI->getParent()->getParent();
1277      MI = MF.CloneMachineInstr(MI);
1278      NewMI = false;
1279    }
1280    MI->setDesc(get(Opc));
1281    MI->getOperand(3).setImm(Size-Amt);
1282    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1283  }
1284  case X86::CMOVB16rr:
1285  case X86::CMOVB32rr:
1286  case X86::CMOVB64rr:
1287  case X86::CMOVAE16rr:
1288  case X86::CMOVAE32rr:
1289  case X86::CMOVAE64rr:
1290  case X86::CMOVE16rr:
1291  case X86::CMOVE32rr:
1292  case X86::CMOVE64rr:
1293  case X86::CMOVNE16rr:
1294  case X86::CMOVNE32rr:
1295  case X86::CMOVNE64rr:
1296  case X86::CMOVBE16rr:
1297  case X86::CMOVBE32rr:
1298  case X86::CMOVBE64rr:
1299  case X86::CMOVA16rr:
1300  case X86::CMOVA32rr:
1301  case X86::CMOVA64rr:
1302  case X86::CMOVL16rr:
1303  case X86::CMOVL32rr:
1304  case X86::CMOVL64rr:
1305  case X86::CMOVGE16rr:
1306  case X86::CMOVGE32rr:
1307  case X86::CMOVGE64rr:
1308  case X86::CMOVLE16rr:
1309  case X86::CMOVLE32rr:
1310  case X86::CMOVLE64rr:
1311  case X86::CMOVG16rr:
1312  case X86::CMOVG32rr:
1313  case X86::CMOVG64rr:
1314  case X86::CMOVS16rr:
1315  case X86::CMOVS32rr:
1316  case X86::CMOVS64rr:
1317  case X86::CMOVNS16rr:
1318  case X86::CMOVNS32rr:
1319  case X86::CMOVNS64rr:
1320  case X86::CMOVP16rr:
1321  case X86::CMOVP32rr:
1322  case X86::CMOVP64rr:
1323  case X86::CMOVNP16rr:
1324  case X86::CMOVNP32rr:
1325  case X86::CMOVNP64rr:
1326  case X86::CMOVO16rr:
1327  case X86::CMOVO32rr:
1328  case X86::CMOVO64rr:
1329  case X86::CMOVNO16rr:
1330  case X86::CMOVNO32rr:
1331  case X86::CMOVNO64rr: {
1332    unsigned Opc = 0;
1333    switch (MI->getOpcode()) {
1334    default: break;
1335    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
1336    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
1337    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
1338    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1339    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1340    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1341    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
1342    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
1343    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
1344    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1345    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1346    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1347    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1348    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1349    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1350    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
1351    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
1352    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
1353    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
1354    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
1355    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
1356    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1357    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1358    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1359    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1360    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1361    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1362    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
1363    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
1364    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
1365    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
1366    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
1367    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
1368    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1369    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1370    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1371    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
1372    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
1373    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
1374    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1375    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1376    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1377    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
1378    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
1379    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
1380    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1381    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1382    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1383    }
1384    if (NewMI) {
1385      MachineFunction &MF = *MI->getParent()->getParent();
1386      MI = MF.CloneMachineInstr(MI);
1387      NewMI = false;
1388    }
1389    MI->setDesc(get(Opc));
1390    // Fallthrough intended.
1391  }
1392  default:
1393    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1394  }
1395}
1396
1397static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1398  switch (BrOpc) {
1399  default: return X86::COND_INVALID;
1400  case X86::JE:  return X86::COND_E;
1401  case X86::JNE: return X86::COND_NE;
1402  case X86::JL:  return X86::COND_L;
1403  case X86::JLE: return X86::COND_LE;
1404  case X86::JG:  return X86::COND_G;
1405  case X86::JGE: return X86::COND_GE;
1406  case X86::JB:  return X86::COND_B;
1407  case X86::JBE: return X86::COND_BE;
1408  case X86::JA:  return X86::COND_A;
1409  case X86::JAE: return X86::COND_AE;
1410  case X86::JS:  return X86::COND_S;
1411  case X86::JNS: return X86::COND_NS;
1412  case X86::JP:  return X86::COND_P;
1413  case X86::JNP: return X86::COND_NP;
1414  case X86::JO:  return X86::COND_O;
1415  case X86::JNO: return X86::COND_NO;
1416  }
1417}
1418
1419unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1420  switch (CC) {
1421  default: llvm_unreachable("Illegal condition code!");
1422  case X86::COND_E:  return X86::JE;
1423  case X86::COND_NE: return X86::JNE;
1424  case X86::COND_L:  return X86::JL;
1425  case X86::COND_LE: return X86::JLE;
1426  case X86::COND_G:  return X86::JG;
1427  case X86::COND_GE: return X86::JGE;
1428  case X86::COND_B:  return X86::JB;
1429  case X86::COND_BE: return X86::JBE;
1430  case X86::COND_A:  return X86::JA;
1431  case X86::COND_AE: return X86::JAE;
1432  case X86::COND_S:  return X86::JS;
1433  case X86::COND_NS: return X86::JNS;
1434  case X86::COND_P:  return X86::JP;
1435  case X86::COND_NP: return X86::JNP;
1436  case X86::COND_O:  return X86::JO;
1437  case X86::COND_NO: return X86::JNO;
1438  }
1439}
1440
1441/// GetOppositeBranchCondition - Return the inverse of the specified condition,
1442/// e.g. turning COND_E to COND_NE.
1443X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1444  switch (CC) {
1445  default: llvm_unreachable("Illegal condition code!");
1446  case X86::COND_E:  return X86::COND_NE;
1447  case X86::COND_NE: return X86::COND_E;
1448  case X86::COND_L:  return X86::COND_GE;
1449  case X86::COND_LE: return X86::COND_G;
1450  case X86::COND_G:  return X86::COND_LE;
1451  case X86::COND_GE: return X86::COND_L;
1452  case X86::COND_B:  return X86::COND_AE;
1453  case X86::COND_BE: return X86::COND_A;
1454  case X86::COND_A:  return X86::COND_BE;
1455  case X86::COND_AE: return X86::COND_B;
1456  case X86::COND_S:  return X86::COND_NS;
1457  case X86::COND_NS: return X86::COND_S;
1458  case X86::COND_P:  return X86::COND_NP;
1459  case X86::COND_NP: return X86::COND_P;
1460  case X86::COND_O:  return X86::COND_NO;
1461  case X86::COND_NO: return X86::COND_O;
1462  }
1463}
1464
1465bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1466  const TargetInstrDesc &TID = MI->getDesc();
1467  if (!TID.isTerminator()) return false;
1468
1469  // Conditional branch is a special case.
1470  if (TID.isBranch() && !TID.isBarrier())
1471    return true;
1472  if (!TID.isPredicable())
1473    return true;
1474  return !isPredicated(MI);
1475}
1476
1477// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1478static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1479                                               const X86InstrInfo &TII) {
1480  if (MI->getOpcode() == X86::FP_REG_KILL)
1481    return false;
1482  return TII.isUnpredicatedTerminator(MI);
1483}
1484
1485bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1486                                 MachineBasicBlock *&TBB,
1487                                 MachineBasicBlock *&FBB,
1488                                 SmallVectorImpl<MachineOperand> &Cond,
1489                                 bool AllowModify) const {
1490  // Start from the bottom of the block and work up, examining the
1491  // terminator instructions.
1492  MachineBasicBlock::iterator I = MBB.end();
1493  while (I != MBB.begin()) {
1494    --I;
1495    // Working from the bottom, when we see a non-terminator
1496    // instruction, we're done.
1497    if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1498      break;
1499    // A terminator that isn't a branch can't easily be handled
1500    // by this analysis.
1501    if (!I->getDesc().isBranch())
1502      return true;
1503    // Handle unconditional branches.
1504    if (I->getOpcode() == X86::JMP) {
1505      if (!AllowModify) {
1506        TBB = I->getOperand(0).getMBB();
1507        continue;
1508      }
1509
1510      // If the block has any instructions after a JMP, delete them.
1511      while (next(I) != MBB.end())
1512        next(I)->eraseFromParent();
1513      Cond.clear();
1514      FBB = 0;
1515      // Delete the JMP if it's equivalent to a fall-through.
1516      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1517        TBB = 0;
1518        I->eraseFromParent();
1519        I = MBB.end();
1520        continue;
1521      }
1522      // TBB is used to indicate the unconditinal destination.
1523      TBB = I->getOperand(0).getMBB();
1524      continue;
1525    }
1526    // Handle conditional branches.
1527    X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1528    if (BranchCode == X86::COND_INVALID)
1529      return true;  // Can't handle indirect branch.
1530    // Working from the bottom, handle the first conditional branch.
1531    if (Cond.empty()) {
1532      FBB = TBB;
1533      TBB = I->getOperand(0).getMBB();
1534      Cond.push_back(MachineOperand::CreateImm(BranchCode));
1535      continue;
1536    }
1537    // Handle subsequent conditional branches. Only handle the case
1538    // where all conditional branches branch to the same destination
1539    // and their condition opcodes fit one of the special
1540    // multi-branch idioms.
1541    assert(Cond.size() == 1);
1542    assert(TBB);
1543    // Only handle the case where all conditional branches branch to
1544    // the same destination.
1545    if (TBB != I->getOperand(0).getMBB())
1546      return true;
1547    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1548    // If the conditions are the same, we can leave them alone.
1549    if (OldBranchCode == BranchCode)
1550      continue;
1551    // If they differ, see if they fit one of the known patterns.
1552    // Theoretically we could handle more patterns here, but
1553    // we shouldn't expect to see them if instruction selection
1554    // has done a reasonable job.
1555    if ((OldBranchCode == X86::COND_NP &&
1556         BranchCode == X86::COND_E) ||
1557        (OldBranchCode == X86::COND_E &&
1558         BranchCode == X86::COND_NP))
1559      BranchCode = X86::COND_NP_OR_E;
1560    else if ((OldBranchCode == X86::COND_P &&
1561              BranchCode == X86::COND_NE) ||
1562             (OldBranchCode == X86::COND_NE &&
1563              BranchCode == X86::COND_P))
1564      BranchCode = X86::COND_NE_OR_P;
1565    else
1566      return true;
1567    // Update the MachineOperand.
1568    Cond[0].setImm(BranchCode);
1569  }
1570
1571  return false;
1572}
1573
1574unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1575  MachineBasicBlock::iterator I = MBB.end();
1576  unsigned Count = 0;
1577
1578  while (I != MBB.begin()) {
1579    --I;
1580    if (I->getOpcode() != X86::JMP &&
1581        GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1582      break;
1583    // Remove the branch.
1584    I->eraseFromParent();
1585    I = MBB.end();
1586    ++Count;
1587  }
1588
1589  return Count;
1590}
1591
1592unsigned
1593X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1594                           MachineBasicBlock *FBB,
1595                           const SmallVectorImpl<MachineOperand> &Cond) const {
1596  // FIXME this should probably have a DebugLoc operand
1597  DebugLoc dl = DebugLoc::getUnknownLoc();
1598  // Shouldn't be a fall through.
1599  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1600  assert((Cond.size() == 1 || Cond.size() == 0) &&
1601         "X86 branch conditions have one component!");
1602
1603  if (Cond.empty()) {
1604    // Unconditional branch?
1605    assert(!FBB && "Unconditional branch with multiple successors!");
1606    BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1607    return 1;
1608  }
1609
1610  // Conditional branch.
1611  unsigned Count = 0;
1612  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1613  switch (CC) {
1614  case X86::COND_NP_OR_E:
1615    // Synthesize NP_OR_E with two branches.
1616    BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1617    ++Count;
1618    BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1619    ++Count;
1620    break;
1621  case X86::COND_NE_OR_P:
1622    // Synthesize NE_OR_P with two branches.
1623    BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1624    ++Count;
1625    BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1626    ++Count;
1627    break;
1628  default: {
1629    unsigned Opc = GetCondBranchFromCond(CC);
1630    BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1631    ++Count;
1632  }
1633  }
1634  if (FBB) {
1635    // Two-way Conditional branch. Insert the second branch.
1636    BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1637    ++Count;
1638  }
1639  return Count;
1640}
1641
1642/// isHReg - Test if the given register is a physical h register.
1643static bool isHReg(unsigned Reg) {
1644  return X86::GR8_ABCD_HRegClass.contains(Reg);
1645}
1646
1647bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1648                                MachineBasicBlock::iterator MI,
1649                                unsigned DestReg, unsigned SrcReg,
1650                                const TargetRegisterClass *DestRC,
1651                                const TargetRegisterClass *SrcRC) const {
1652  DebugLoc DL = DebugLoc::getUnknownLoc();
1653  if (MI != MBB.end()) DL = MI->getDebugLoc();
1654
1655  // Determine if DstRC and SrcRC have a common superclass in common.
1656  const TargetRegisterClass *CommonRC = DestRC;
1657  if (DestRC == SrcRC)
1658    /* Source and destination have the same register class. */;
1659  else if (CommonRC->hasSuperClass(SrcRC))
1660    CommonRC = SrcRC;
1661  else if (!DestRC->hasSubClass(SrcRC)) {
1662    // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1663    // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1664    // GR32_NOSP, copy as GR32.
1665    if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1666        DestRC->hasSuperClass(&X86::GR64RegClass))
1667      CommonRC = &X86::GR64RegClass;
1668    else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1669             DestRC->hasSuperClass(&X86::GR32RegClass))
1670      CommonRC = &X86::GR32RegClass;
1671    else
1672      CommonRC = 0;
1673  }
1674
1675  if (CommonRC) {
1676    unsigned Opc;
1677    if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1678      Opc = X86::MOV64rr;
1679    } else if (CommonRC == &X86::GR32RegClass ||
1680               CommonRC == &X86::GR32_NOSPRegClass) {
1681      Opc = X86::MOV32rr;
1682    } else if (CommonRC == &X86::GR16RegClass) {
1683      Opc = X86::MOV16rr;
1684    } else if (CommonRC == &X86::GR8RegClass) {
1685      // Copying to or from a physical H register on x86-64 requires a NOREX
1686      // move.  Otherwise use a normal move.
1687      if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1688          TM.getSubtarget<X86Subtarget>().is64Bit())
1689        Opc = X86::MOV8rr_NOREX;
1690      else
1691        Opc = X86::MOV8rr;
1692    } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1693      Opc = X86::MOV64rr;
1694    } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1695      Opc = X86::MOV32rr;
1696    } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1697      Opc = X86::MOV16rr;
1698    } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1699      Opc = X86::MOV8rr;
1700    } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1701      if (TM.getSubtarget<X86Subtarget>().is64Bit())
1702        Opc = X86::MOV8rr_NOREX;
1703      else
1704        Opc = X86::MOV8rr;
1705    } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1706               CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1707      Opc = X86::MOV64rr;
1708    } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1709      Opc = X86::MOV32rr;
1710    } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1711      Opc = X86::MOV16rr;
1712    } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1713      Opc = X86::MOV8rr;
1714    } else if (CommonRC == &X86::RFP32RegClass) {
1715      Opc = X86::MOV_Fp3232;
1716    } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1717      Opc = X86::MOV_Fp6464;
1718    } else if (CommonRC == &X86::RFP80RegClass) {
1719      Opc = X86::MOV_Fp8080;
1720    } else if (CommonRC == &X86::FR32RegClass) {
1721      Opc = X86::FsMOVAPSrr;
1722    } else if (CommonRC == &X86::FR64RegClass) {
1723      Opc = X86::FsMOVAPDrr;
1724    } else if (CommonRC == &X86::VR128RegClass) {
1725      Opc = X86::MOVAPSrr;
1726    } else if (CommonRC == &X86::VR64RegClass) {
1727      Opc = X86::MMX_MOVQ64rr;
1728    } else {
1729      return false;
1730    }
1731    BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1732    return true;
1733  }
1734
1735  // Moving EFLAGS to / from another register requires a push and a pop.
1736  if (SrcRC == &X86::CCRRegClass) {
1737    if (SrcReg != X86::EFLAGS)
1738      return false;
1739    if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1740      BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1741      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1742      return true;
1743    } else if (DestRC == &X86::GR32RegClass ||
1744               DestRC == &X86::GR32_NOSPRegClass) {
1745      BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1746      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1747      return true;
1748    }
1749  } else if (DestRC == &X86::CCRRegClass) {
1750    if (DestReg != X86::EFLAGS)
1751      return false;
1752    if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1753      BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1754      BuildMI(MBB, MI, DL, get(X86::POPFQ));
1755      return true;
1756    } else if (SrcRC == &X86::GR32RegClass ||
1757               DestRC == &X86::GR32_NOSPRegClass) {
1758      BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1759      BuildMI(MBB, MI, DL, get(X86::POPFD));
1760      return true;
1761    }
1762  }
1763
1764  // Moving from ST(0) turns into FpGET_ST0_32 etc.
1765  if (SrcRC == &X86::RSTRegClass) {
1766    // Copying from ST(0)/ST(1).
1767    if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1768      // Can only copy from ST(0)/ST(1) right now
1769      return false;
1770    bool isST0 = SrcReg == X86::ST0;
1771    unsigned Opc;
1772    if (DestRC == &X86::RFP32RegClass)
1773      Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1774    else if (DestRC == &X86::RFP64RegClass)
1775      Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1776    else {
1777      if (DestRC != &X86::RFP80RegClass)
1778        return false;
1779      Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1780    }
1781    BuildMI(MBB, MI, DL, get(Opc), DestReg);
1782    return true;
1783  }
1784
1785  // Moving to ST(0) turns into FpSET_ST0_32 etc.
1786  if (DestRC == &X86::RSTRegClass) {
1787    // Copying to ST(0) / ST(1).
1788    if (DestReg != X86::ST0 && DestReg != X86::ST1)
1789      // Can only copy to TOS right now
1790      return false;
1791    bool isST0 = DestReg == X86::ST0;
1792    unsigned Opc;
1793    if (SrcRC == &X86::RFP32RegClass)
1794      Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1795    else if (SrcRC == &X86::RFP64RegClass)
1796      Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1797    else {
1798      if (SrcRC != &X86::RFP80RegClass)
1799        return false;
1800      Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1801    }
1802    BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1803    return true;
1804  }
1805
1806  // Not yet supported!
1807  return false;
1808}
1809
1810static unsigned getStoreRegOpcode(unsigned SrcReg,
1811                                  const TargetRegisterClass *RC,
1812                                  bool isStackAligned,
1813                                  TargetMachine &TM) {
1814  unsigned Opc = 0;
1815  if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1816    Opc = X86::MOV64mr;
1817  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1818    Opc = X86::MOV32mr;
1819  } else if (RC == &X86::GR16RegClass) {
1820    Opc = X86::MOV16mr;
1821  } else if (RC == &X86::GR8RegClass) {
1822    // Copying to or from a physical H register on x86-64 requires a NOREX
1823    // move.  Otherwise use a normal move.
1824    if (isHReg(SrcReg) &&
1825        TM.getSubtarget<X86Subtarget>().is64Bit())
1826      Opc = X86::MOV8mr_NOREX;
1827    else
1828      Opc = X86::MOV8mr;
1829  } else if (RC == &X86::GR64_ABCDRegClass) {
1830    Opc = X86::MOV64mr;
1831  } else if (RC == &X86::GR32_ABCDRegClass) {
1832    Opc = X86::MOV32mr;
1833  } else if (RC == &X86::GR16_ABCDRegClass) {
1834    Opc = X86::MOV16mr;
1835  } else if (RC == &X86::GR8_ABCD_LRegClass) {
1836    Opc = X86::MOV8mr;
1837  } else if (RC == &X86::GR8_ABCD_HRegClass) {
1838    if (TM.getSubtarget<X86Subtarget>().is64Bit())
1839      Opc = X86::MOV8mr_NOREX;
1840    else
1841      Opc = X86::MOV8mr;
1842  } else if (RC == &X86::GR64_NOREXRegClass ||
1843             RC == &X86::GR64_NOREX_NOSPRegClass) {
1844    Opc = X86::MOV64mr;
1845  } else if (RC == &X86::GR32_NOREXRegClass) {
1846    Opc = X86::MOV32mr;
1847  } else if (RC == &X86::GR16_NOREXRegClass) {
1848    Opc = X86::MOV16mr;
1849  } else if (RC == &X86::GR8_NOREXRegClass) {
1850    Opc = X86::MOV8mr;
1851  } else if (RC == &X86::RFP80RegClass) {
1852    Opc = X86::ST_FpP80m;   // pops
1853  } else if (RC == &X86::RFP64RegClass) {
1854    Opc = X86::ST_Fp64m;
1855  } else if (RC == &X86::RFP32RegClass) {
1856    Opc = X86::ST_Fp32m;
1857  } else if (RC == &X86::FR32RegClass) {
1858    Opc = X86::MOVSSmr;
1859  } else if (RC == &X86::FR64RegClass) {
1860    Opc = X86::MOVSDmr;
1861  } else if (RC == &X86::VR128RegClass) {
1862    // If stack is realigned we can use aligned stores.
1863    Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1864  } else if (RC == &X86::VR64RegClass) {
1865    Opc = X86::MMX_MOVQ64mr;
1866  } else {
1867    llvm_unreachable("Unknown regclass");
1868  }
1869
1870  return Opc;
1871}
1872
1873void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1874                                       MachineBasicBlock::iterator MI,
1875                                       unsigned SrcReg, bool isKill, int FrameIdx,
1876                                       const TargetRegisterClass *RC) const {
1877  const MachineFunction &MF = *MBB.getParent();
1878  bool isAligned = (RI.getStackAlignment() >= 16) ||
1879    RI.needsStackRealignment(MF);
1880  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1881  DebugLoc DL = DebugLoc::getUnknownLoc();
1882  if (MI != MBB.end()) DL = MI->getDebugLoc();
1883  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1884    .addReg(SrcReg, getKillRegState(isKill));
1885}
1886
1887void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1888                                  bool isKill,
1889                                  SmallVectorImpl<MachineOperand> &Addr,
1890                                  const TargetRegisterClass *RC,
1891                                  MachineInstr::mmo_iterator MMOBegin,
1892                                  MachineInstr::mmo_iterator MMOEnd,
1893                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
1894  bool isAligned = (RI.getStackAlignment() >= 16) ||
1895    RI.needsStackRealignment(MF);
1896  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1897  DebugLoc DL = DebugLoc::getUnknownLoc();
1898  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1899  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1900    MIB.addOperand(Addr[i]);
1901  MIB.addReg(SrcReg, getKillRegState(isKill));
1902  (*MIB).setMemRefs(MMOBegin, MMOEnd);
1903  NewMIs.push_back(MIB);
1904}
1905
1906static unsigned getLoadRegOpcode(unsigned DestReg,
1907                                 const TargetRegisterClass *RC,
1908                                 bool isStackAligned,
1909                                 const TargetMachine &TM) {
1910  unsigned Opc = 0;
1911  if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1912    Opc = X86::MOV64rm;
1913  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1914    Opc = X86::MOV32rm;
1915  } else if (RC == &X86::GR16RegClass) {
1916    Opc = X86::MOV16rm;
1917  } else if (RC == &X86::GR8RegClass) {
1918    // Copying to or from a physical H register on x86-64 requires a NOREX
1919    // move.  Otherwise use a normal move.
1920    if (isHReg(DestReg) &&
1921        TM.getSubtarget<X86Subtarget>().is64Bit())
1922      Opc = X86::MOV8rm_NOREX;
1923    else
1924      Opc = X86::MOV8rm;
1925  } else if (RC == &X86::GR64_ABCDRegClass) {
1926    Opc = X86::MOV64rm;
1927  } else if (RC == &X86::GR32_ABCDRegClass) {
1928    Opc = X86::MOV32rm;
1929  } else if (RC == &X86::GR16_ABCDRegClass) {
1930    Opc = X86::MOV16rm;
1931  } else if (RC == &X86::GR8_ABCD_LRegClass) {
1932    Opc = X86::MOV8rm;
1933  } else if (RC == &X86::GR8_ABCD_HRegClass) {
1934    if (TM.getSubtarget<X86Subtarget>().is64Bit())
1935      Opc = X86::MOV8rm_NOREX;
1936    else
1937      Opc = X86::MOV8rm;
1938  } else if (RC == &X86::GR64_NOREXRegClass ||
1939             RC == &X86::GR64_NOREX_NOSPRegClass) {
1940    Opc = X86::MOV64rm;
1941  } else if (RC == &X86::GR32_NOREXRegClass) {
1942    Opc = X86::MOV32rm;
1943  } else if (RC == &X86::GR16_NOREXRegClass) {
1944    Opc = X86::MOV16rm;
1945  } else if (RC == &X86::GR8_NOREXRegClass) {
1946    Opc = X86::MOV8rm;
1947  } else if (RC == &X86::RFP80RegClass) {
1948    Opc = X86::LD_Fp80m;
1949  } else if (RC == &X86::RFP64RegClass) {
1950    Opc = X86::LD_Fp64m;
1951  } else if (RC == &X86::RFP32RegClass) {
1952    Opc = X86::LD_Fp32m;
1953  } else if (RC == &X86::FR32RegClass) {
1954    Opc = X86::MOVSSrm;
1955  } else if (RC == &X86::FR64RegClass) {
1956    Opc = X86::MOVSDrm;
1957  } else if (RC == &X86::VR128RegClass) {
1958    // If stack is realigned we can use aligned loads.
1959    Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1960  } else if (RC == &X86::VR64RegClass) {
1961    Opc = X86::MMX_MOVQ64rm;
1962  } else {
1963    llvm_unreachable("Unknown regclass");
1964  }
1965
1966  return Opc;
1967}
1968
1969void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1970                                        MachineBasicBlock::iterator MI,
1971                                        unsigned DestReg, int FrameIdx,
1972                                        const TargetRegisterClass *RC) const{
1973  const MachineFunction &MF = *MBB.getParent();
1974  bool isAligned = (RI.getStackAlignment() >= 16) ||
1975    RI.needsStackRealignment(MF);
1976  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
1977  DebugLoc DL = DebugLoc::getUnknownLoc();
1978  if (MI != MBB.end()) DL = MI->getDebugLoc();
1979  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
1980}
1981
1982void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1983                                 SmallVectorImpl<MachineOperand> &Addr,
1984                                 const TargetRegisterClass *RC,
1985                                 MachineInstr::mmo_iterator MMOBegin,
1986                                 MachineInstr::mmo_iterator MMOEnd,
1987                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1988  bool isAligned = (RI.getStackAlignment() >= 16) ||
1989    RI.needsStackRealignment(MF);
1990  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
1991  DebugLoc DL = DebugLoc::getUnknownLoc();
1992  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
1993  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1994    MIB.addOperand(Addr[i]);
1995  (*MIB).setMemRefs(MMOBegin, MMOEnd);
1996  NewMIs.push_back(MIB);
1997}
1998
1999bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2000                                             MachineBasicBlock::iterator MI,
2001                                const std::vector<CalleeSavedInfo> &CSI) const {
2002  if (CSI.empty())
2003    return false;
2004
2005  DebugLoc DL = DebugLoc::getUnknownLoc();
2006  if (MI != MBB.end()) DL = MI->getDebugLoc();
2007
2008  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2009  bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2010  unsigned SlotSize = is64Bit ? 8 : 4;
2011
2012  MachineFunction &MF = *MBB.getParent();
2013  unsigned FPReg = RI.getFrameRegister(MF);
2014  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2015  unsigned CalleeFrameSize = 0;
2016
2017  unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2018  for (unsigned i = CSI.size(); i != 0; --i) {
2019    unsigned Reg = CSI[i-1].getReg();
2020    const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2021    // Add the callee-saved register as live-in. It's killed at the spill.
2022    MBB.addLiveIn(Reg);
2023    if (Reg == FPReg)
2024      // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2025      continue;
2026    if (RegClass != &X86::VR128RegClass && !isWin64) {
2027      CalleeFrameSize += SlotSize;
2028      BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2029    } else {
2030      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2031    }
2032  }
2033
2034  X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2035  return true;
2036}
2037
2038bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2039                                               MachineBasicBlock::iterator MI,
2040                                const std::vector<CalleeSavedInfo> &CSI) const {
2041  if (CSI.empty())
2042    return false;
2043
2044  DebugLoc DL = DebugLoc::getUnknownLoc();
2045  if (MI != MBB.end()) DL = MI->getDebugLoc();
2046
2047  MachineFunction &MF = *MBB.getParent();
2048  unsigned FPReg = RI.getFrameRegister(MF);
2049  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2050  bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2051  unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2052  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2053    unsigned Reg = CSI[i].getReg();
2054    if (Reg == FPReg)
2055      // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2056      continue;
2057    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2058    if (RegClass != &X86::VR128RegClass && !isWin64) {
2059      BuildMI(MBB, MI, DL, get(Opc), Reg);
2060    } else {
2061      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2062    }
2063  }
2064  return true;
2065}
2066
2067static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2068                                     const SmallVectorImpl<MachineOperand> &MOs,
2069                                     MachineInstr *MI,
2070                                     const TargetInstrInfo &TII) {
2071  // Create the base instruction with the memory operand as the first part.
2072  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2073                                              MI->getDebugLoc(), true);
2074  MachineInstrBuilder MIB(NewMI);
2075  unsigned NumAddrOps = MOs.size();
2076  for (unsigned i = 0; i != NumAddrOps; ++i)
2077    MIB.addOperand(MOs[i]);
2078  if (NumAddrOps < 4)  // FrameIndex only
2079    addOffset(MIB, 0);
2080
2081  // Loop over the rest of the ri operands, converting them over.
2082  unsigned NumOps = MI->getDesc().getNumOperands()-2;
2083  for (unsigned i = 0; i != NumOps; ++i) {
2084    MachineOperand &MO = MI->getOperand(i+2);
2085    MIB.addOperand(MO);
2086  }
2087  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2088    MachineOperand &MO = MI->getOperand(i);
2089    MIB.addOperand(MO);
2090  }
2091  return MIB;
2092}
2093
2094static MachineInstr *FuseInst(MachineFunction &MF,
2095                              unsigned Opcode, unsigned OpNo,
2096                              const SmallVectorImpl<MachineOperand> &MOs,
2097                              MachineInstr *MI, const TargetInstrInfo &TII) {
2098  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2099                                              MI->getDebugLoc(), true);
2100  MachineInstrBuilder MIB(NewMI);
2101
2102  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2103    MachineOperand &MO = MI->getOperand(i);
2104    if (i == OpNo) {
2105      assert(MO.isReg() && "Expected to fold into reg operand!");
2106      unsigned NumAddrOps = MOs.size();
2107      for (unsigned i = 0; i != NumAddrOps; ++i)
2108        MIB.addOperand(MOs[i]);
2109      if (NumAddrOps < 4)  // FrameIndex only
2110        addOffset(MIB, 0);
2111    } else {
2112      MIB.addOperand(MO);
2113    }
2114  }
2115  return MIB;
2116}
2117
2118static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2119                                const SmallVectorImpl<MachineOperand> &MOs,
2120                                MachineInstr *MI) {
2121  MachineFunction &MF = *MI->getParent()->getParent();
2122  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2123
2124  unsigned NumAddrOps = MOs.size();
2125  for (unsigned i = 0; i != NumAddrOps; ++i)
2126    MIB.addOperand(MOs[i]);
2127  if (NumAddrOps < 4)  // FrameIndex only
2128    addOffset(MIB, 0);
2129  return MIB.addImm(0);
2130}
2131
2132MachineInstr*
2133X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2134                                    MachineInstr *MI, unsigned i,
2135                                    const SmallVectorImpl<MachineOperand> &MOs,
2136                                    unsigned Size, unsigned Align) const {
2137  const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2138  bool isTwoAddrFold = false;
2139  unsigned NumOps = MI->getDesc().getNumOperands();
2140  bool isTwoAddr = NumOps > 1 &&
2141    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2142
2143  MachineInstr *NewMI = NULL;
2144  // Folding a memory location into the two-address part of a two-address
2145  // instruction is different than folding it other places.  It requires
2146  // replacing the *two* registers with the memory location.
2147  if (isTwoAddr && NumOps >= 2 && i < 2 &&
2148      MI->getOperand(0).isReg() &&
2149      MI->getOperand(1).isReg() &&
2150      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2151    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2152    isTwoAddrFold = true;
2153  } else if (i == 0) { // If operand 0
2154    if (MI->getOpcode() == X86::MOV16r0)
2155      NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2156    else if (MI->getOpcode() == X86::MOV32r0)
2157      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2158    else if (MI->getOpcode() == X86::MOV8r0)
2159      NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2160    if (NewMI)
2161      return NewMI;
2162
2163    OpcodeTablePtr = &RegOp2MemOpTable0;
2164  } else if (i == 1) {
2165    OpcodeTablePtr = &RegOp2MemOpTable1;
2166  } else if (i == 2) {
2167    OpcodeTablePtr = &RegOp2MemOpTable2;
2168  }
2169
2170  // If table selected...
2171  if (OpcodeTablePtr) {
2172    // Find the Opcode to fuse
2173    DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2174      OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2175    if (I != OpcodeTablePtr->end()) {
2176      unsigned Opcode = I->second.first;
2177      unsigned MinAlign = I->second.second;
2178      if (Align < MinAlign)
2179        return NULL;
2180      bool NarrowToMOV32rm = false;
2181      if (Size) {
2182        unsigned RCSize =  MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2183        if (Size < RCSize) {
2184          // Check if it's safe to fold the load. If the size of the object is
2185          // narrower than the load width, then it's not.
2186          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2187            return NULL;
2188          // If this is a 64-bit load, but the spill slot is 32, then we can do
2189          // a 32-bit load which is implicitly zero-extended. This likely is due
2190          // to liveintervalanalysis remat'ing a load from stack slot.
2191          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2192            return NULL;
2193          Opcode = X86::MOV32rm;
2194          NarrowToMOV32rm = true;
2195        }
2196      }
2197
2198      if (isTwoAddrFold)
2199        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2200      else
2201        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2202
2203      if (NarrowToMOV32rm) {
2204        // If this is the special case where we use a MOV32rm to load a 32-bit
2205        // value and zero-extend the top bits. Change the destination register
2206        // to a 32-bit one.
2207        unsigned DstReg = NewMI->getOperand(0).getReg();
2208        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2209          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2210                                                   4/*x86_subreg_32bit*/));
2211        else
2212          NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2213      }
2214      return NewMI;
2215    }
2216  }
2217
2218  // No fusion
2219  if (PrintFailedFusing)
2220    errs() << "We failed to fuse operand " << i << " in " << *MI;
2221  return NULL;
2222}
2223
2224
2225MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2226                                                  MachineInstr *MI,
2227                                           const SmallVectorImpl<unsigned> &Ops,
2228                                                  int FrameIndex) const {
2229  // Check switch flag
2230  if (NoFusing) return NULL;
2231
2232  const MachineFrameInfo *MFI = MF.getFrameInfo();
2233  unsigned Size = MFI->getObjectSize(FrameIndex);
2234  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2235  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2236    unsigned NewOpc = 0;
2237    unsigned RCSize = 0;
2238    switch (MI->getOpcode()) {
2239    default: return NULL;
2240    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
2241    case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2242    case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2243    case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2244    }
2245    // Check if it's safe to fold the load. If the size of the object is
2246    // narrower than the load width, then it's not.
2247    if (Size < RCSize)
2248      return NULL;
2249    // Change to CMPXXri r, 0 first.
2250    MI->setDesc(get(NewOpc));
2251    MI->getOperand(1).ChangeToImmediate(0);
2252  } else if (Ops.size() != 1)
2253    return NULL;
2254
2255  SmallVector<MachineOperand,4> MOs;
2256  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2257  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2258}
2259
2260MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2261                                                  MachineInstr *MI,
2262                                           const SmallVectorImpl<unsigned> &Ops,
2263                                                  MachineInstr *LoadMI) const {
2264  // Check switch flag
2265  if (NoFusing) return NULL;
2266
2267  // Determine the alignment of the load.
2268  unsigned Alignment = 0;
2269  if (LoadMI->hasOneMemOperand())
2270    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2271  else
2272    switch (LoadMI->getOpcode()) {
2273    case X86::V_SET0:
2274    case X86::V_SETALLONES:
2275      Alignment = 16;
2276      break;
2277    case X86::FsFLD0SD:
2278      Alignment = 8;
2279      break;
2280    case X86::FsFLD0SS:
2281      Alignment = 4;
2282      break;
2283    default:
2284      llvm_unreachable("Don't know how to fold this instruction!");
2285    }
2286  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2287    unsigned NewOpc = 0;
2288    switch (MI->getOpcode()) {
2289    default: return NULL;
2290    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2291    case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2292    case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2293    case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2294    }
2295    // Change to CMPXXri r, 0 first.
2296    MI->setDesc(get(NewOpc));
2297    MI->getOperand(1).ChangeToImmediate(0);
2298  } else if (Ops.size() != 1)
2299    return NULL;
2300
2301  SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2302  switch (LoadMI->getOpcode()) {
2303  case X86::V_SET0:
2304  case X86::V_SETALLONES:
2305  case X86::FsFLD0SD:
2306  case X86::FsFLD0SS: {
2307    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2308    // Create a constant-pool entry and operands to load from it.
2309
2310    // x86-32 PIC requires a PIC base register for constant pools.
2311    unsigned PICBase = 0;
2312    if (TM.getRelocationModel() == Reloc::PIC_) {
2313      if (TM.getSubtarget<X86Subtarget>().is64Bit())
2314        PICBase = X86::RIP;
2315      else
2316        // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2317        // This doesn't work for several reasons.
2318        // 1. GlobalBaseReg may have been spilled.
2319        // 2. It may not be live at MI.
2320        return NULL;
2321    }
2322
2323    // Create a constant-pool entry.
2324    MachineConstantPool &MCP = *MF.getConstantPool();
2325    const Type *Ty;
2326    if (LoadMI->getOpcode() == X86::FsFLD0SS)
2327      Ty = Type::getFloatTy(MF.getFunction()->getContext());
2328    else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2329      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2330    else
2331      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2332    Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2333                    Constant::getAllOnesValue(Ty) :
2334                    Constant::getNullValue(Ty);
2335    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2336
2337    // Create operands to load from the constant pool entry.
2338    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2339    MOs.push_back(MachineOperand::CreateImm(1));
2340    MOs.push_back(MachineOperand::CreateReg(0, false));
2341    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2342    MOs.push_back(MachineOperand::CreateReg(0, false));
2343    break;
2344  }
2345  default: {
2346    // Folding a normal load. Just copy the load's address operands.
2347    unsigned NumOps = LoadMI->getDesc().getNumOperands();
2348    for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2349      MOs.push_back(LoadMI->getOperand(i));
2350    break;
2351  }
2352  }
2353  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2354}
2355
2356
2357bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2358                                  const SmallVectorImpl<unsigned> &Ops) const {
2359  // Check switch flag
2360  if (NoFusing) return 0;
2361
2362  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2363    switch (MI->getOpcode()) {
2364    default: return false;
2365    case X86::TEST8rr:
2366    case X86::TEST16rr:
2367    case X86::TEST32rr:
2368    case X86::TEST64rr:
2369      return true;
2370    }
2371  }
2372
2373  if (Ops.size() != 1)
2374    return false;
2375
2376  unsigned OpNum = Ops[0];
2377  unsigned Opc = MI->getOpcode();
2378  unsigned NumOps = MI->getDesc().getNumOperands();
2379  bool isTwoAddr = NumOps > 1 &&
2380    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2381
2382  // Folding a memory location into the two-address part of a two-address
2383  // instruction is different than folding it other places.  It requires
2384  // replacing the *two* registers with the memory location.
2385  const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2386  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2387    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2388  } else if (OpNum == 0) { // If operand 0
2389    switch (Opc) {
2390    case X86::MOV8r0:
2391    case X86::MOV16r0:
2392    case X86::MOV32r0:
2393      return true;
2394    default: break;
2395    }
2396    OpcodeTablePtr = &RegOp2MemOpTable0;
2397  } else if (OpNum == 1) {
2398    OpcodeTablePtr = &RegOp2MemOpTable1;
2399  } else if (OpNum == 2) {
2400    OpcodeTablePtr = &RegOp2MemOpTable2;
2401  }
2402
2403  if (OpcodeTablePtr) {
2404    // Find the Opcode to fuse
2405    DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2406      OpcodeTablePtr->find((unsigned*)Opc);
2407    if (I != OpcodeTablePtr->end())
2408      return true;
2409  }
2410  return false;
2411}
2412
2413bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2414                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2415                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
2416  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2417    MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2418  if (I == MemOp2RegOpTable.end())
2419    return false;
2420  DebugLoc dl = MI->getDebugLoc();
2421  unsigned Opc = I->second.first;
2422  unsigned Index = I->second.second & 0xf;
2423  bool FoldedLoad = I->second.second & (1 << 4);
2424  bool FoldedStore = I->second.second & (1 << 5);
2425  if (UnfoldLoad && !FoldedLoad)
2426    return false;
2427  UnfoldLoad &= FoldedLoad;
2428  if (UnfoldStore && !FoldedStore)
2429    return false;
2430  UnfoldStore &= FoldedStore;
2431
2432  const TargetInstrDesc &TID = get(Opc);
2433  const TargetOperandInfo &TOI = TID.OpInfo[Index];
2434  const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2435  SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2436  SmallVector<MachineOperand,2> BeforeOps;
2437  SmallVector<MachineOperand,2> AfterOps;
2438  SmallVector<MachineOperand,4> ImpOps;
2439  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2440    MachineOperand &Op = MI->getOperand(i);
2441    if (i >= Index && i < Index + X86AddrNumOperands)
2442      AddrOps.push_back(Op);
2443    else if (Op.isReg() && Op.isImplicit())
2444      ImpOps.push_back(Op);
2445    else if (i < Index)
2446      BeforeOps.push_back(Op);
2447    else if (i > Index)
2448      AfterOps.push_back(Op);
2449  }
2450
2451  // Emit the load instruction.
2452  if (UnfoldLoad) {
2453    std::pair<MachineInstr::mmo_iterator,
2454              MachineInstr::mmo_iterator> MMOs =
2455      MF.extractLoadMemRefs(MI->memoperands_begin(),
2456                            MI->memoperands_end());
2457    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2458    if (UnfoldStore) {
2459      // Address operands cannot be marked isKill.
2460      for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2461        MachineOperand &MO = NewMIs[0]->getOperand(i);
2462        if (MO.isReg())
2463          MO.setIsKill(false);
2464      }
2465    }
2466  }
2467
2468  // Emit the data processing instruction.
2469  MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2470  MachineInstrBuilder MIB(DataMI);
2471
2472  if (FoldedStore)
2473    MIB.addReg(Reg, RegState::Define);
2474  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2475    MIB.addOperand(BeforeOps[i]);
2476  if (FoldedLoad)
2477    MIB.addReg(Reg);
2478  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2479    MIB.addOperand(AfterOps[i]);
2480  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2481    MachineOperand &MO = ImpOps[i];
2482    MIB.addReg(MO.getReg(),
2483               getDefRegState(MO.isDef()) |
2484               RegState::Implicit |
2485               getKillRegState(MO.isKill()) |
2486               getDeadRegState(MO.isDead()) |
2487               getUndefRegState(MO.isUndef()));
2488  }
2489  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2490  unsigned NewOpc = 0;
2491  switch (DataMI->getOpcode()) {
2492  default: break;
2493  case X86::CMP64ri32:
2494  case X86::CMP32ri:
2495  case X86::CMP16ri:
2496  case X86::CMP8ri: {
2497    MachineOperand &MO0 = DataMI->getOperand(0);
2498    MachineOperand &MO1 = DataMI->getOperand(1);
2499    if (MO1.getImm() == 0) {
2500      switch (DataMI->getOpcode()) {
2501      default: break;
2502      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2503      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
2504      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
2505      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
2506      }
2507      DataMI->setDesc(get(NewOpc));
2508      MO1.ChangeToRegister(MO0.getReg(), false);
2509    }
2510  }
2511  }
2512  NewMIs.push_back(DataMI);
2513
2514  // Emit the store instruction.
2515  if (UnfoldStore) {
2516    const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2517    std::pair<MachineInstr::mmo_iterator,
2518              MachineInstr::mmo_iterator> MMOs =
2519      MF.extractStoreMemRefs(MI->memoperands_begin(),
2520                             MI->memoperands_end());
2521    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2522  }
2523
2524  return true;
2525}
2526
2527bool
2528X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2529                                  SmallVectorImpl<SDNode*> &NewNodes) const {
2530  if (!N->isMachineOpcode())
2531    return false;
2532
2533  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2534    MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2535  if (I == MemOp2RegOpTable.end())
2536    return false;
2537  unsigned Opc = I->second.first;
2538  unsigned Index = I->second.second & 0xf;
2539  bool FoldedLoad = I->second.second & (1 << 4);
2540  bool FoldedStore = I->second.second & (1 << 5);
2541  const TargetInstrDesc &TID = get(Opc);
2542  const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2543  unsigned NumDefs = TID.NumDefs;
2544  std::vector<SDValue> AddrOps;
2545  std::vector<SDValue> BeforeOps;
2546  std::vector<SDValue> AfterOps;
2547  DebugLoc dl = N->getDebugLoc();
2548  unsigned NumOps = N->getNumOperands();
2549  for (unsigned i = 0; i != NumOps-1; ++i) {
2550    SDValue Op = N->getOperand(i);
2551    if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2552      AddrOps.push_back(Op);
2553    else if (i < Index-NumDefs)
2554      BeforeOps.push_back(Op);
2555    else if (i > Index-NumDefs)
2556      AfterOps.push_back(Op);
2557  }
2558  SDValue Chain = N->getOperand(NumOps-1);
2559  AddrOps.push_back(Chain);
2560
2561  // Emit the load instruction.
2562  SDNode *Load = 0;
2563  MachineFunction &MF = DAG.getMachineFunction();
2564  if (FoldedLoad) {
2565    EVT VT = *RC->vt_begin();
2566    bool isAligned = (RI.getStackAlignment() >= 16) ||
2567      RI.needsStackRealignment(MF);
2568    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2569                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
2570    NewNodes.push_back(Load);
2571
2572    // Preserve memory reference information.
2573    std::pair<MachineInstr::mmo_iterator,
2574              MachineInstr::mmo_iterator> MMOs =
2575      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2576                            cast<MachineSDNode>(N)->memoperands_end());
2577    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2578  }
2579
2580  // Emit the data processing instruction.
2581  std::vector<EVT> VTs;
2582  const TargetRegisterClass *DstRC = 0;
2583  if (TID.getNumDefs() > 0) {
2584    DstRC = TID.OpInfo[0].getRegClass(&RI);
2585    VTs.push_back(*DstRC->vt_begin());
2586  }
2587  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2588    EVT VT = N->getValueType(i);
2589    if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2590      VTs.push_back(VT);
2591  }
2592  if (Load)
2593    BeforeOps.push_back(SDValue(Load, 0));
2594  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2595  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2596                                      BeforeOps.size());
2597  NewNodes.push_back(NewNode);
2598
2599  // Emit the store instruction.
2600  if (FoldedStore) {
2601    AddrOps.pop_back();
2602    AddrOps.push_back(SDValue(NewNode, 0));
2603    AddrOps.push_back(Chain);
2604    bool isAligned = (RI.getStackAlignment() >= 16) ||
2605      RI.needsStackRealignment(MF);
2606    SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2607                                                         isAligned, TM),
2608                                       dl, MVT::Other,
2609                                       &AddrOps[0], AddrOps.size());
2610    NewNodes.push_back(Store);
2611
2612    // Preserve memory reference information.
2613    std::pair<MachineInstr::mmo_iterator,
2614              MachineInstr::mmo_iterator> MMOs =
2615      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2616                             cast<MachineSDNode>(N)->memoperands_end());
2617    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2618  }
2619
2620  return true;
2621}
2622
2623unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2624                                      bool UnfoldLoad, bool UnfoldStore,
2625                                      unsigned *LoadRegIndex) const {
2626  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2627    MemOp2RegOpTable.find((unsigned*)Opc);
2628  if (I == MemOp2RegOpTable.end())
2629    return 0;
2630  bool FoldedLoad = I->second.second & (1 << 4);
2631  bool FoldedStore = I->second.second & (1 << 5);
2632  if (UnfoldLoad && !FoldedLoad)
2633    return 0;
2634  if (UnfoldStore && !FoldedStore)
2635    return 0;
2636  if (LoadRegIndex)
2637    *LoadRegIndex = I->second.second & 0xf;
2638  return I->second.first;
2639}
2640
2641bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2642  if (MBB.empty()) return false;
2643
2644  switch (MBB.back().getOpcode()) {
2645  case X86::TCRETURNri:
2646  case X86::TCRETURNdi:
2647  case X86::RET:     // Return.
2648  case X86::RETI:
2649  case X86::TAILJMPd:
2650  case X86::TAILJMPr:
2651  case X86::TAILJMPm:
2652  case X86::JMP:     // Uncond branch.
2653  case X86::JMP32r:  // Indirect branch.
2654  case X86::JMP64r:  // Indirect branch (64-bit).
2655  case X86::JMP32m:  // Indirect branch through mem.
2656  case X86::JMP64m:  // Indirect branch through mem (64-bit).
2657    return true;
2658  default: return false;
2659  }
2660}
2661
2662bool X86InstrInfo::
2663ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2664  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2665  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2666  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2667    return true;
2668  Cond[0].setImm(GetOppositeBranchCondition(CC));
2669  return false;
2670}
2671
2672bool X86InstrInfo::
2673isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2674  // FIXME: Return false for x87 stack register classes for now. We can't
2675  // allow any loads of these registers before FpGet_ST0_80.
2676  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2677           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2678}
2679
2680unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2681  switch (Desc->TSFlags & X86II::ImmMask) {
2682  case X86II::Imm8:   return 1;
2683  case X86II::Imm16:  return 2;
2684  case X86II::Imm32:  return 4;
2685  case X86II::Imm64:  return 8;
2686  default: llvm_unreachable("Immediate size not set!");
2687    return 0;
2688  }
2689}
2690
2691/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2692/// e.g. r8, xmm8, etc.
2693bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2694  if (!MO.isReg()) return false;
2695  switch (MO.getReg()) {
2696  default: break;
2697  case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
2698  case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
2699  case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
2700  case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
2701  case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
2702  case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
2703  case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
2704  case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
2705  case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
2706  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2707    return true;
2708  }
2709  return false;
2710}
2711
2712
2713/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2714/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2715/// size, and 3) use of X86-64 extended registers.
2716unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2717  unsigned REX = 0;
2718  const TargetInstrDesc &Desc = MI.getDesc();
2719
2720  // Pseudo instructions do not need REX prefix byte.
2721  if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2722    return 0;
2723  if (Desc.TSFlags & X86II::REX_W)
2724    REX |= 1 << 3;
2725
2726  unsigned NumOps = Desc.getNumOperands();
2727  if (NumOps) {
2728    bool isTwoAddr = NumOps > 1 &&
2729      Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2730
2731    // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2732    unsigned i = isTwoAddr ? 1 : 0;
2733    for (unsigned e = NumOps; i != e; ++i) {
2734      const MachineOperand& MO = MI.getOperand(i);
2735      if (MO.isReg()) {
2736        unsigned Reg = MO.getReg();
2737        if (isX86_64NonExtLowByteReg(Reg))
2738          REX |= 0x40;
2739      }
2740    }
2741
2742    switch (Desc.TSFlags & X86II::FormMask) {
2743    case X86II::MRMInitReg:
2744      if (isX86_64ExtendedReg(MI.getOperand(0)))
2745        REX |= (1 << 0) | (1 << 2);
2746      break;
2747    case X86II::MRMSrcReg: {
2748      if (isX86_64ExtendedReg(MI.getOperand(0)))
2749        REX |= 1 << 2;
2750      i = isTwoAddr ? 2 : 1;
2751      for (unsigned e = NumOps; i != e; ++i) {
2752        const MachineOperand& MO = MI.getOperand(i);
2753        if (isX86_64ExtendedReg(MO))
2754          REX |= 1 << 0;
2755      }
2756      break;
2757    }
2758    case X86II::MRMSrcMem: {
2759      if (isX86_64ExtendedReg(MI.getOperand(0)))
2760        REX |= 1 << 2;
2761      unsigned Bit = 0;
2762      i = isTwoAddr ? 2 : 1;
2763      for (; i != NumOps; ++i) {
2764        const MachineOperand& MO = MI.getOperand(i);
2765        if (MO.isReg()) {
2766          if (isX86_64ExtendedReg(MO))
2767            REX |= 1 << Bit;
2768          Bit++;
2769        }
2770      }
2771      break;
2772    }
2773    case X86II::MRM0m: case X86II::MRM1m:
2774    case X86II::MRM2m: case X86II::MRM3m:
2775    case X86II::MRM4m: case X86II::MRM5m:
2776    case X86II::MRM6m: case X86II::MRM7m:
2777    case X86II::MRMDestMem: {
2778      unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2779      i = isTwoAddr ? 1 : 0;
2780      if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2781        REX |= 1 << 2;
2782      unsigned Bit = 0;
2783      for (; i != e; ++i) {
2784        const MachineOperand& MO = MI.getOperand(i);
2785        if (MO.isReg()) {
2786          if (isX86_64ExtendedReg(MO))
2787            REX |= 1 << Bit;
2788          Bit++;
2789        }
2790      }
2791      break;
2792    }
2793    default: {
2794      if (isX86_64ExtendedReg(MI.getOperand(0)))
2795        REX |= 1 << 0;
2796      i = isTwoAddr ? 2 : 1;
2797      for (unsigned e = NumOps; i != e; ++i) {
2798        const MachineOperand& MO = MI.getOperand(i);
2799        if (isX86_64ExtendedReg(MO))
2800          REX |= 1 << 2;
2801      }
2802      break;
2803    }
2804    }
2805  }
2806  return REX;
2807}
2808
2809/// sizePCRelativeBlockAddress - This method returns the size of a PC
2810/// relative block address instruction
2811///
2812static unsigned sizePCRelativeBlockAddress() {
2813  return 4;
2814}
2815
2816/// sizeGlobalAddress - Give the size of the emission of this global address
2817///
2818static unsigned sizeGlobalAddress(bool dword) {
2819  return dword ? 8 : 4;
2820}
2821
2822/// sizeConstPoolAddress - Give the size of the emission of this constant
2823/// pool address
2824///
2825static unsigned sizeConstPoolAddress(bool dword) {
2826  return dword ? 8 : 4;
2827}
2828
2829/// sizeExternalSymbolAddress - Give the size of the emission of this external
2830/// symbol
2831///
2832static unsigned sizeExternalSymbolAddress(bool dword) {
2833  return dword ? 8 : 4;
2834}
2835
2836/// sizeJumpTableAddress - Give the size of the emission of this jump
2837/// table address
2838///
2839static unsigned sizeJumpTableAddress(bool dword) {
2840  return dword ? 8 : 4;
2841}
2842
2843static unsigned sizeConstant(unsigned Size) {
2844  return Size;
2845}
2846
2847static unsigned sizeRegModRMByte(){
2848  return 1;
2849}
2850
2851static unsigned sizeSIBByte(){
2852  return 1;
2853}
2854
2855static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2856  unsigned FinalSize = 0;
2857  // If this is a simple integer displacement that doesn't require a relocation.
2858  if (!RelocOp) {
2859    FinalSize += sizeConstant(4);
2860    return FinalSize;
2861  }
2862
2863  // Otherwise, this is something that requires a relocation.
2864  if (RelocOp->isGlobal()) {
2865    FinalSize += sizeGlobalAddress(false);
2866  } else if (RelocOp->isCPI()) {
2867    FinalSize += sizeConstPoolAddress(false);
2868  } else if (RelocOp->isJTI()) {
2869    FinalSize += sizeJumpTableAddress(false);
2870  } else {
2871    llvm_unreachable("Unknown value to relocate!");
2872  }
2873  return FinalSize;
2874}
2875
2876static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2877                                    bool IsPIC, bool Is64BitMode) {
2878  const MachineOperand &Op3 = MI.getOperand(Op+3);
2879  int DispVal = 0;
2880  const MachineOperand *DispForReloc = 0;
2881  unsigned FinalSize = 0;
2882
2883  // Figure out what sort of displacement we have to handle here.
2884  if (Op3.isGlobal()) {
2885    DispForReloc = &Op3;
2886  } else if (Op3.isCPI()) {
2887    if (Is64BitMode || IsPIC) {
2888      DispForReloc = &Op3;
2889    } else {
2890      DispVal = 1;
2891    }
2892  } else if (Op3.isJTI()) {
2893    if (Is64BitMode || IsPIC) {
2894      DispForReloc = &Op3;
2895    } else {
2896      DispVal = 1;
2897    }
2898  } else {
2899    DispVal = 1;
2900  }
2901
2902  const MachineOperand &Base     = MI.getOperand(Op);
2903  const MachineOperand &IndexReg = MI.getOperand(Op+2);
2904
2905  unsigned BaseReg = Base.getReg();
2906
2907  // Is a SIB byte needed?
2908  if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2909      IndexReg.getReg() == 0 &&
2910      (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2911    if (BaseReg == 0) {  // Just a displacement?
2912      // Emit special case [disp32] encoding
2913      ++FinalSize;
2914      FinalSize += getDisplacementFieldSize(DispForReloc);
2915    } else {
2916      unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2917      if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2918        // Emit simple indirect register encoding... [EAX] f.e.
2919        ++FinalSize;
2920      // Be pessimistic and assume it's a disp32, not a disp8
2921      } else {
2922        // Emit the most general non-SIB encoding: [REG+disp32]
2923        ++FinalSize;
2924        FinalSize += getDisplacementFieldSize(DispForReloc);
2925      }
2926    }
2927
2928  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
2929    assert(IndexReg.getReg() != X86::ESP &&
2930           IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2931
2932    bool ForceDisp32 = false;
2933    if (BaseReg == 0 || DispForReloc) {
2934      // Emit the normal disp32 encoding.
2935      ++FinalSize;
2936      ForceDisp32 = true;
2937    } else {
2938      ++FinalSize;
2939    }
2940
2941    FinalSize += sizeSIBByte();
2942
2943    // Do we need to output a displacement?
2944    if (DispVal != 0 || ForceDisp32) {
2945      FinalSize += getDisplacementFieldSize(DispForReloc);
2946    }
2947  }
2948  return FinalSize;
2949}
2950
2951
2952static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2953                                    const TargetInstrDesc *Desc,
2954                                    bool IsPIC, bool Is64BitMode) {
2955
2956  unsigned Opcode = Desc->Opcode;
2957  unsigned FinalSize = 0;
2958
2959  // Emit the lock opcode prefix as needed.
2960  if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2961
2962  // Emit segment override opcode prefix as needed.
2963  switch (Desc->TSFlags & X86II::SegOvrMask) {
2964  case X86II::FS:
2965  case X86II::GS:
2966   ++FinalSize;
2967   break;
2968  default: llvm_unreachable("Invalid segment!");
2969  case 0: break;  // No segment override!
2970  }
2971
2972  // Emit the repeat opcode prefix as needed.
2973  if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2974
2975  // Emit the operand size opcode prefix as needed.
2976  if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2977
2978  // Emit the address size opcode prefix as needed.
2979  if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2980
2981  bool Need0FPrefix = false;
2982  switch (Desc->TSFlags & X86II::Op0Mask) {
2983  case X86II::TB:  // Two-byte opcode prefix
2984  case X86II::T8:  // 0F 38
2985  case X86II::TA:  // 0F 3A
2986    Need0FPrefix = true;
2987    break;
2988  case X86II::TF: // F2 0F 38
2989    ++FinalSize;
2990    Need0FPrefix = true;
2991    break;
2992  case X86II::REP: break; // already handled.
2993  case X86II::XS:   // F3 0F
2994    ++FinalSize;
2995    Need0FPrefix = true;
2996    break;
2997  case X86II::XD:   // F2 0F
2998    ++FinalSize;
2999    Need0FPrefix = true;
3000    break;
3001  case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3002  case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3003    ++FinalSize;
3004    break; // Two-byte opcode prefix
3005  default: llvm_unreachable("Invalid prefix!");
3006  case 0: break;  // No prefix!
3007  }
3008
3009  if (Is64BitMode) {
3010    // REX prefix
3011    unsigned REX = X86InstrInfo::determineREX(MI);
3012    if (REX)
3013      ++FinalSize;
3014  }
3015
3016  // 0x0F escape code must be emitted just before the opcode.
3017  if (Need0FPrefix)
3018    ++FinalSize;
3019
3020  switch (Desc->TSFlags & X86II::Op0Mask) {
3021  case X86II::T8:  // 0F 38
3022    ++FinalSize;
3023    break;
3024  case X86II::TA:  // 0F 3A
3025    ++FinalSize;
3026    break;
3027  case X86II::TF: // F2 0F 38
3028    ++FinalSize;
3029    break;
3030  }
3031
3032  // If this is a two-address instruction, skip one of the register operands.
3033  unsigned NumOps = Desc->getNumOperands();
3034  unsigned CurOp = 0;
3035  if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3036    CurOp++;
3037  else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3038    // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3039    --NumOps;
3040
3041  switch (Desc->TSFlags & X86II::FormMask) {
3042  default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3043  case X86II::Pseudo:
3044    // Remember the current PC offset, this is the PIC relocation
3045    // base address.
3046    switch (Opcode) {
3047    default:
3048      break;
3049    case TargetInstrInfo::INLINEASM: {
3050      const MachineFunction *MF = MI.getParent()->getParent();
3051      const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3052      FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3053                                          *MF->getTarget().getMCAsmInfo());
3054      break;
3055    }
3056    case TargetInstrInfo::DBG_LABEL:
3057    case TargetInstrInfo::EH_LABEL:
3058      break;
3059    case TargetInstrInfo::IMPLICIT_DEF:
3060    case TargetInstrInfo::KILL:
3061    case X86::DWARF_LOC:
3062    case X86::FP_REG_KILL:
3063      break;
3064    case X86::MOVPC32r: {
3065      // This emits the "call" portion of this pseudo instruction.
3066      ++FinalSize;
3067      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3068      break;
3069    }
3070    }
3071    CurOp = NumOps;
3072    break;
3073  case X86II::RawFrm:
3074    ++FinalSize;
3075
3076    if (CurOp != NumOps) {
3077      const MachineOperand &MO = MI.getOperand(CurOp++);
3078      if (MO.isMBB()) {
3079        FinalSize += sizePCRelativeBlockAddress();
3080      } else if (MO.isGlobal()) {
3081        FinalSize += sizeGlobalAddress(false);
3082      } else if (MO.isSymbol()) {
3083        FinalSize += sizeExternalSymbolAddress(false);
3084      } else if (MO.isImm()) {
3085        FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3086      } else {
3087        llvm_unreachable("Unknown RawFrm operand!");
3088      }
3089    }
3090    break;
3091
3092  case X86II::AddRegFrm:
3093    ++FinalSize;
3094    ++CurOp;
3095
3096    if (CurOp != NumOps) {
3097      const MachineOperand &MO1 = MI.getOperand(CurOp++);
3098      unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3099      if (MO1.isImm())
3100        FinalSize += sizeConstant(Size);
3101      else {
3102        bool dword = false;
3103        if (Opcode == X86::MOV64ri)
3104          dword = true;
3105        if (MO1.isGlobal()) {
3106          FinalSize += sizeGlobalAddress(dword);
3107        } else if (MO1.isSymbol())
3108          FinalSize += sizeExternalSymbolAddress(dword);
3109        else if (MO1.isCPI())
3110          FinalSize += sizeConstPoolAddress(dword);
3111        else if (MO1.isJTI())
3112          FinalSize += sizeJumpTableAddress(dword);
3113      }
3114    }
3115    break;
3116
3117  case X86II::MRMDestReg: {
3118    ++FinalSize;
3119    FinalSize += sizeRegModRMByte();
3120    CurOp += 2;
3121    if (CurOp != NumOps) {
3122      ++CurOp;
3123      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3124    }
3125    break;
3126  }
3127  case X86II::MRMDestMem: {
3128    ++FinalSize;
3129    FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3130    CurOp +=  X86AddrNumOperands + 1;
3131    if (CurOp != NumOps) {
3132      ++CurOp;
3133      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3134    }
3135    break;
3136  }
3137
3138  case X86II::MRMSrcReg:
3139    ++FinalSize;
3140    FinalSize += sizeRegModRMByte();
3141    CurOp += 2;
3142    if (CurOp != NumOps) {
3143      ++CurOp;
3144      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3145    }
3146    break;
3147
3148  case X86II::MRMSrcMem: {
3149    int AddrOperands;
3150    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3151        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3152      AddrOperands = X86AddrNumOperands - 1; // No segment register
3153    else
3154      AddrOperands = X86AddrNumOperands;
3155
3156    ++FinalSize;
3157    FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3158    CurOp += AddrOperands + 1;
3159    if (CurOp != NumOps) {
3160      ++CurOp;
3161      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3162    }
3163    break;
3164  }
3165
3166  case X86II::MRM0r: case X86II::MRM1r:
3167  case X86II::MRM2r: case X86II::MRM3r:
3168  case X86II::MRM4r: case X86II::MRM5r:
3169  case X86II::MRM6r: case X86II::MRM7r:
3170    ++FinalSize;
3171    if (Desc->getOpcode() == X86::LFENCE ||
3172        Desc->getOpcode() == X86::MFENCE) {
3173      // Special handling of lfence and mfence;
3174      FinalSize += sizeRegModRMByte();
3175    } else if (Desc->getOpcode() == X86::MONITOR ||
3176               Desc->getOpcode() == X86::MWAIT) {
3177      // Special handling of monitor and mwait.
3178      FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3179    } else {
3180      ++CurOp;
3181      FinalSize += sizeRegModRMByte();
3182    }
3183
3184    if (CurOp != NumOps) {
3185      const MachineOperand &MO1 = MI.getOperand(CurOp++);
3186      unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3187      if (MO1.isImm())
3188        FinalSize += sizeConstant(Size);
3189      else {
3190        bool dword = false;
3191        if (Opcode == X86::MOV64ri32)
3192          dword = true;
3193        if (MO1.isGlobal()) {
3194          FinalSize += sizeGlobalAddress(dword);
3195        } else if (MO1.isSymbol())
3196          FinalSize += sizeExternalSymbolAddress(dword);
3197        else if (MO1.isCPI())
3198          FinalSize += sizeConstPoolAddress(dword);
3199        else if (MO1.isJTI())
3200          FinalSize += sizeJumpTableAddress(dword);
3201      }
3202    }
3203    break;
3204
3205  case X86II::MRM0m: case X86II::MRM1m:
3206  case X86II::MRM2m: case X86II::MRM3m:
3207  case X86II::MRM4m: case X86II::MRM5m:
3208  case X86II::MRM6m: case X86II::MRM7m: {
3209
3210    ++FinalSize;
3211    FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3212    CurOp += X86AddrNumOperands;
3213
3214    if (CurOp != NumOps) {
3215      const MachineOperand &MO = MI.getOperand(CurOp++);
3216      unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3217      if (MO.isImm())
3218        FinalSize += sizeConstant(Size);
3219      else {
3220        bool dword = false;
3221        if (Opcode == X86::MOV64mi32)
3222          dword = true;
3223        if (MO.isGlobal()) {
3224          FinalSize += sizeGlobalAddress(dword);
3225        } else if (MO.isSymbol())
3226          FinalSize += sizeExternalSymbolAddress(dword);
3227        else if (MO.isCPI())
3228          FinalSize += sizeConstPoolAddress(dword);
3229        else if (MO.isJTI())
3230          FinalSize += sizeJumpTableAddress(dword);
3231      }
3232    }
3233    break;
3234  }
3235
3236  case X86II::MRMInitReg:
3237    ++FinalSize;
3238    // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3239    FinalSize += sizeRegModRMByte();
3240    ++CurOp;
3241    break;
3242  }
3243
3244  if (!Desc->isVariadic() && CurOp != NumOps) {
3245    std::string msg;
3246    raw_string_ostream Msg(msg);
3247    Msg << "Cannot determine size: " << MI;
3248    llvm_report_error(Msg.str());
3249  }
3250
3251
3252  return FinalSize;
3253}
3254
3255
3256unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3257  const TargetInstrDesc &Desc = MI->getDesc();
3258  bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3259  bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3260  unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3261  if (Desc.getOpcode() == X86::MOVPC32r)
3262    Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3263  return Size;
3264}
3265
3266/// getGlobalBaseReg - Return a virtual register initialized with the
3267/// the global base register value. Output instructions required to
3268/// initialize the register in the function entry block, if necessary.
3269///
3270unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3271  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3272         "X86-64 PIC uses RIP relative addressing");
3273
3274  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3275  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3276  if (GlobalBaseReg != 0)
3277    return GlobalBaseReg;
3278
3279  // Insert the set of GlobalBaseReg into the first MBB of the function
3280  MachineBasicBlock &FirstMBB = MF->front();
3281  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3282  DebugLoc DL = DebugLoc::getUnknownLoc();
3283  if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3284  MachineRegisterInfo &RegInfo = MF->getRegInfo();
3285  unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3286
3287  const TargetInstrInfo *TII = TM.getInstrInfo();
3288  // Operand of MovePCtoStack is completely ignored by asm printer. It's
3289  // only used in JIT code emission as displacement to pc.
3290  BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3291
3292  // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3293  // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3294  if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3295    GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3296    // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3297    BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3298      .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3299                                    X86II::MO_GOT_ABSOLUTE_ADDRESS);
3300  } else {
3301    GlobalBaseReg = PC;
3302  }
3303
3304  X86FI->setGlobalBaseReg(GlobalBaseReg);
3305  return GlobalBaseReg;
3306}
3307