X86InstrInfo.cpp revision 90c579de5a383cee278acc3f7e7b9d0a656e6a35
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/LiveVariables.h" 29#include "llvm/CodeGen/PseudoSourceValue.h" 30#include "llvm/MC/MCInst.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetOptions.h" 36#include "llvm/MC/MCAsmInfo.h" 37 38#include <limits> 39 40using namespace llvm; 41 42static cl::opt<bool> 43NoFusing("disable-spill-fusing", 44 cl::desc("Disable fusing of spill code into instructions")); 45static cl::opt<bool> 46PrintFailedFusing("print-failed-fuse-candidates", 47 cl::desc("Print instructions that the allocator wants to" 48 " fuse, but the X86 backend currently can't"), 49 cl::Hidden); 50static cl::opt<bool> 51ReMatPICStubLoad("remat-pic-stub-load", 52 cl::desc("Re-materialize load from stub in PIC mode"), 53 cl::init(false), cl::Hidden); 54 55X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 56 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 57 TM(tm), RI(tm, *this) { 58 SmallVector<unsigned,16> AmbEntries; 59 static const unsigned OpTbl2Addr[][2] = { 60 { X86::ADC32ri, X86::ADC32mi }, 61 { X86::ADC32ri8, X86::ADC32mi8 }, 62 { X86::ADC32rr, X86::ADC32mr }, 63 { X86::ADC64ri32, X86::ADC64mi32 }, 64 { X86::ADC64ri8, X86::ADC64mi8 }, 65 { X86::ADC64rr, X86::ADC64mr }, 66 { X86::ADD16ri, X86::ADD16mi }, 67 { X86::ADD16ri8, X86::ADD16mi8 }, 68 { X86::ADD16rr, X86::ADD16mr }, 69 { X86::ADD32ri, X86::ADD32mi }, 70 { X86::ADD32ri8, X86::ADD32mi8 }, 71 { X86::ADD32rr, X86::ADD32mr }, 72 { X86::ADD64ri32, X86::ADD64mi32 }, 73 { X86::ADD64ri8, X86::ADD64mi8 }, 74 { X86::ADD64rr, X86::ADD64mr }, 75 { X86::ADD8ri, X86::ADD8mi }, 76 { X86::ADD8rr, X86::ADD8mr }, 77 { X86::AND16ri, X86::AND16mi }, 78 { X86::AND16ri8, X86::AND16mi8 }, 79 { X86::AND16rr, X86::AND16mr }, 80 { X86::AND32ri, X86::AND32mi }, 81 { X86::AND32ri8, X86::AND32mi8 }, 82 { X86::AND32rr, X86::AND32mr }, 83 { X86::AND64ri32, X86::AND64mi32 }, 84 { X86::AND64ri8, X86::AND64mi8 }, 85 { X86::AND64rr, X86::AND64mr }, 86 { X86::AND8ri, X86::AND8mi }, 87 { X86::AND8rr, X86::AND8mr }, 88 { X86::DEC16r, X86::DEC16m }, 89 { X86::DEC32r, X86::DEC32m }, 90 { X86::DEC64_16r, X86::DEC64_16m }, 91 { X86::DEC64_32r, X86::DEC64_32m }, 92 { X86::DEC64r, X86::DEC64m }, 93 { X86::DEC8r, X86::DEC8m }, 94 { X86::INC16r, X86::INC16m }, 95 { X86::INC32r, X86::INC32m }, 96 { X86::INC64_16r, X86::INC64_16m }, 97 { X86::INC64_32r, X86::INC64_32m }, 98 { X86::INC64r, X86::INC64m }, 99 { X86::INC8r, X86::INC8m }, 100 { X86::NEG16r, X86::NEG16m }, 101 { X86::NEG32r, X86::NEG32m }, 102 { X86::NEG64r, X86::NEG64m }, 103 { X86::NEG8r, X86::NEG8m }, 104 { X86::NOT16r, X86::NOT16m }, 105 { X86::NOT32r, X86::NOT32m }, 106 { X86::NOT64r, X86::NOT64m }, 107 { X86::NOT8r, X86::NOT8m }, 108 { X86::OR16ri, X86::OR16mi }, 109 { X86::OR16ri8, X86::OR16mi8 }, 110 { X86::OR16rr, X86::OR16mr }, 111 { X86::OR32ri, X86::OR32mi }, 112 { X86::OR32ri8, X86::OR32mi8 }, 113 { X86::OR32rr, X86::OR32mr }, 114 { X86::OR64ri32, X86::OR64mi32 }, 115 { X86::OR64ri8, X86::OR64mi8 }, 116 { X86::OR64rr, X86::OR64mr }, 117 { X86::OR8ri, X86::OR8mi }, 118 { X86::OR8rr, X86::OR8mr }, 119 { X86::ROL16r1, X86::ROL16m1 }, 120 { X86::ROL16rCL, X86::ROL16mCL }, 121 { X86::ROL16ri, X86::ROL16mi }, 122 { X86::ROL32r1, X86::ROL32m1 }, 123 { X86::ROL32rCL, X86::ROL32mCL }, 124 { X86::ROL32ri, X86::ROL32mi }, 125 { X86::ROL64r1, X86::ROL64m1 }, 126 { X86::ROL64rCL, X86::ROL64mCL }, 127 { X86::ROL64ri, X86::ROL64mi }, 128 { X86::ROL8r1, X86::ROL8m1 }, 129 { X86::ROL8rCL, X86::ROL8mCL }, 130 { X86::ROL8ri, X86::ROL8mi }, 131 { X86::ROR16r1, X86::ROR16m1 }, 132 { X86::ROR16rCL, X86::ROR16mCL }, 133 { X86::ROR16ri, X86::ROR16mi }, 134 { X86::ROR32r1, X86::ROR32m1 }, 135 { X86::ROR32rCL, X86::ROR32mCL }, 136 { X86::ROR32ri, X86::ROR32mi }, 137 { X86::ROR64r1, X86::ROR64m1 }, 138 { X86::ROR64rCL, X86::ROR64mCL }, 139 { X86::ROR64ri, X86::ROR64mi }, 140 { X86::ROR8r1, X86::ROR8m1 }, 141 { X86::ROR8rCL, X86::ROR8mCL }, 142 { X86::ROR8ri, X86::ROR8mi }, 143 { X86::SAR16r1, X86::SAR16m1 }, 144 { X86::SAR16rCL, X86::SAR16mCL }, 145 { X86::SAR16ri, X86::SAR16mi }, 146 { X86::SAR32r1, X86::SAR32m1 }, 147 { X86::SAR32rCL, X86::SAR32mCL }, 148 { X86::SAR32ri, X86::SAR32mi }, 149 { X86::SAR64r1, X86::SAR64m1 }, 150 { X86::SAR64rCL, X86::SAR64mCL }, 151 { X86::SAR64ri, X86::SAR64mi }, 152 { X86::SAR8r1, X86::SAR8m1 }, 153 { X86::SAR8rCL, X86::SAR8mCL }, 154 { X86::SAR8ri, X86::SAR8mi }, 155 { X86::SBB32ri, X86::SBB32mi }, 156 { X86::SBB32ri8, X86::SBB32mi8 }, 157 { X86::SBB32rr, X86::SBB32mr }, 158 { X86::SBB64ri32, X86::SBB64mi32 }, 159 { X86::SBB64ri8, X86::SBB64mi8 }, 160 { X86::SBB64rr, X86::SBB64mr }, 161 { X86::SHL16rCL, X86::SHL16mCL }, 162 { X86::SHL16ri, X86::SHL16mi }, 163 { X86::SHL32rCL, X86::SHL32mCL }, 164 { X86::SHL32ri, X86::SHL32mi }, 165 { X86::SHL64rCL, X86::SHL64mCL }, 166 { X86::SHL64ri, X86::SHL64mi }, 167 { X86::SHL8rCL, X86::SHL8mCL }, 168 { X86::SHL8ri, X86::SHL8mi }, 169 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 170 { X86::SHLD16rri8, X86::SHLD16mri8 }, 171 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 172 { X86::SHLD32rri8, X86::SHLD32mri8 }, 173 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 174 { X86::SHLD64rri8, X86::SHLD64mri8 }, 175 { X86::SHR16r1, X86::SHR16m1 }, 176 { X86::SHR16rCL, X86::SHR16mCL }, 177 { X86::SHR16ri, X86::SHR16mi }, 178 { X86::SHR32r1, X86::SHR32m1 }, 179 { X86::SHR32rCL, X86::SHR32mCL }, 180 { X86::SHR32ri, X86::SHR32mi }, 181 { X86::SHR64r1, X86::SHR64m1 }, 182 { X86::SHR64rCL, X86::SHR64mCL }, 183 { X86::SHR64ri, X86::SHR64mi }, 184 { X86::SHR8r1, X86::SHR8m1 }, 185 { X86::SHR8rCL, X86::SHR8mCL }, 186 { X86::SHR8ri, X86::SHR8mi }, 187 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 188 { X86::SHRD16rri8, X86::SHRD16mri8 }, 189 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 190 { X86::SHRD32rri8, X86::SHRD32mri8 }, 191 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 192 { X86::SHRD64rri8, X86::SHRD64mri8 }, 193 { X86::SUB16ri, X86::SUB16mi }, 194 { X86::SUB16ri8, X86::SUB16mi8 }, 195 { X86::SUB16rr, X86::SUB16mr }, 196 { X86::SUB32ri, X86::SUB32mi }, 197 { X86::SUB32ri8, X86::SUB32mi8 }, 198 { X86::SUB32rr, X86::SUB32mr }, 199 { X86::SUB64ri32, X86::SUB64mi32 }, 200 { X86::SUB64ri8, X86::SUB64mi8 }, 201 { X86::SUB64rr, X86::SUB64mr }, 202 { X86::SUB8ri, X86::SUB8mi }, 203 { X86::SUB8rr, X86::SUB8mr }, 204 { X86::XOR16ri, X86::XOR16mi }, 205 { X86::XOR16ri8, X86::XOR16mi8 }, 206 { X86::XOR16rr, X86::XOR16mr }, 207 { X86::XOR32ri, X86::XOR32mi }, 208 { X86::XOR32ri8, X86::XOR32mi8 }, 209 { X86::XOR32rr, X86::XOR32mr }, 210 { X86::XOR64ri32, X86::XOR64mi32 }, 211 { X86::XOR64ri8, X86::XOR64mi8 }, 212 { X86::XOR64rr, X86::XOR64mr }, 213 { X86::XOR8ri, X86::XOR8mi }, 214 { X86::XOR8rr, X86::XOR8mr } 215 }; 216 217 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 218 unsigned RegOp = OpTbl2Addr[i][0]; 219 unsigned MemOp = OpTbl2Addr[i][1]; 220 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 221 std::make_pair(MemOp,0))).second) 222 assert(false && "Duplicated entries?"); 223 // Index 0, folded load and store, no alignment requirement. 224 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); 225 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 226 std::make_pair(RegOp, 227 AuxInfo))).second) 228 AmbEntries.push_back(MemOp); 229 } 230 231 // If the third value is 1, then it's folding either a load or a store. 232 static const unsigned OpTbl0[][4] = { 233 { X86::BT16ri8, X86::BT16mi8, 1, 0 }, 234 { X86::BT32ri8, X86::BT32mi8, 1, 0 }, 235 { X86::BT64ri8, X86::BT64mi8, 1, 0 }, 236 { X86::CALL32r, X86::CALL32m, 1, 0 }, 237 { X86::CALL64r, X86::CALL64m, 1, 0 }, 238 { X86::CMP16ri, X86::CMP16mi, 1, 0 }, 239 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 }, 240 { X86::CMP16rr, X86::CMP16mr, 1, 0 }, 241 { X86::CMP32ri, X86::CMP32mi, 1, 0 }, 242 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 }, 243 { X86::CMP32rr, X86::CMP32mr, 1, 0 }, 244 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 }, 245 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 }, 246 { X86::CMP64rr, X86::CMP64mr, 1, 0 }, 247 { X86::CMP8ri, X86::CMP8mi, 1, 0 }, 248 { X86::CMP8rr, X86::CMP8mr, 1, 0 }, 249 { X86::DIV16r, X86::DIV16m, 1, 0 }, 250 { X86::DIV32r, X86::DIV32m, 1, 0 }, 251 { X86::DIV64r, X86::DIV64m, 1, 0 }, 252 { X86::DIV8r, X86::DIV8m, 1, 0 }, 253 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 }, 254 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 }, 255 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 }, 256 { X86::IDIV16r, X86::IDIV16m, 1, 0 }, 257 { X86::IDIV32r, X86::IDIV32m, 1, 0 }, 258 { X86::IDIV64r, X86::IDIV64m, 1, 0 }, 259 { X86::IDIV8r, X86::IDIV8m, 1, 0 }, 260 { X86::IMUL16r, X86::IMUL16m, 1, 0 }, 261 { X86::IMUL32r, X86::IMUL32m, 1, 0 }, 262 { X86::IMUL64r, X86::IMUL64m, 1, 0 }, 263 { X86::IMUL8r, X86::IMUL8m, 1, 0 }, 264 { X86::JMP32r, X86::JMP32m, 1, 0 }, 265 { X86::JMP64r, X86::JMP64m, 1, 0 }, 266 { X86::MOV16ri, X86::MOV16mi, 0, 0 }, 267 { X86::MOV16rr, X86::MOV16mr, 0, 0 }, 268 { X86::MOV32ri, X86::MOV32mi, 0, 0 }, 269 { X86::MOV32rr, X86::MOV32mr, 0, 0 }, 270 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 }, 271 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 }, 272 { X86::MOV64rr, X86::MOV64mr, 0, 0 }, 273 { X86::MOV8ri, X86::MOV8mi, 0, 0 }, 274 { X86::MOV8rr, X86::MOV8mr, 0, 0 }, 275 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 }, 276 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 }, 277 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 }, 278 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 }, 279 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 }, 280 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 }, 281 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 }, 282 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 }, 283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 }, 284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 }, 285 { X86::MUL16r, X86::MUL16m, 1, 0 }, 286 { X86::MUL32r, X86::MUL32m, 1, 0 }, 287 { X86::MUL64r, X86::MUL64m, 1, 0 }, 288 { X86::MUL8r, X86::MUL8m, 1, 0 }, 289 { X86::SETAEr, X86::SETAEm, 0, 0 }, 290 { X86::SETAr, X86::SETAm, 0, 0 }, 291 { X86::SETBEr, X86::SETBEm, 0, 0 }, 292 { X86::SETBr, X86::SETBm, 0, 0 }, 293 { X86::SETEr, X86::SETEm, 0, 0 }, 294 { X86::SETGEr, X86::SETGEm, 0, 0 }, 295 { X86::SETGr, X86::SETGm, 0, 0 }, 296 { X86::SETLEr, X86::SETLEm, 0, 0 }, 297 { X86::SETLr, X86::SETLm, 0, 0 }, 298 { X86::SETNEr, X86::SETNEm, 0, 0 }, 299 { X86::SETNOr, X86::SETNOm, 0, 0 }, 300 { X86::SETNPr, X86::SETNPm, 0, 0 }, 301 { X86::SETNSr, X86::SETNSm, 0, 0 }, 302 { X86::SETOr, X86::SETOm, 0, 0 }, 303 { X86::SETPr, X86::SETPm, 0, 0 }, 304 { X86::SETSr, X86::SETSm, 0, 0 }, 305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, 306 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 }, 307 { X86::TEST16ri, X86::TEST16mi, 1, 0 }, 308 { X86::TEST32ri, X86::TEST32mi, 1, 0 }, 309 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, 310 { X86::TEST8ri, X86::TEST8mi, 1, 0 } 311 }; 312 313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 314 unsigned RegOp = OpTbl0[i][0]; 315 unsigned MemOp = OpTbl0[i][1]; 316 unsigned Align = OpTbl0[i][3]; 317 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 318 std::make_pair(MemOp,Align))).second) 319 assert(false && "Duplicated entries?"); 320 unsigned FoldedLoad = OpTbl0[i][2]; 321 // Index 0, folded load or store. 322 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 323 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 324 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 325 std::make_pair(RegOp, AuxInfo))).second) 326 AmbEntries.push_back(MemOp); 327 } 328 329 static const unsigned OpTbl1[][3] = { 330 { X86::CMP16rr, X86::CMP16rm, 0 }, 331 { X86::CMP32rr, X86::CMP32rm, 0 }, 332 { X86::CMP64rr, X86::CMP64rm, 0 }, 333 { X86::CMP8rr, X86::CMP8rm, 0 }, 334 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 335 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 336 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 337 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 338 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 339 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 340 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 341 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 342 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 343 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 344 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 }, 345 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 }, 346 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 347 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 348 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 349 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 350 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 351 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 352 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 353 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 354 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 355 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 356 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 }, 357 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 }, 358 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 }, 359 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 }, 360 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 }, 361 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 }, 362 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 }, 363 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 }, 364 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 365 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 366 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 367 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 368 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 369 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 370 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 }, 371 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 }, 372 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 }, 373 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 }, 374 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 375 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 376 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 377 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 378 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 379 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 380 { X86::MOV16rr, X86::MOV16rm, 0 }, 381 { X86::MOV32rr, X86::MOV32rm, 0 }, 382 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 }, 383 { X86::MOV64rr, X86::MOV64rm, 0 }, 384 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 385 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 386 { X86::MOV8rr, X86::MOV8rm, 0 }, 387 { X86::MOVAPDrr, X86::MOVAPDrm, 16 }, 388 { X86::MOVAPSrr, X86::MOVAPSrm, 16 }, 389 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 390 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 391 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 392 { X86::MOVDQArr, X86::MOVDQArm, 16 }, 393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 }, 394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 }, 395 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 396 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 397 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 398 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 399 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 400 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 401 { X86::MOVUPDrr, X86::MOVUPDrm, 16 }, 402 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 403 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 404 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 405 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 }, 406 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 407 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 408 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 409 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 410 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 411 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 412 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 413 { X86::PSHUFDri, X86::PSHUFDmi, 16 }, 414 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 }, 415 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 }, 416 { X86::RCPPSr, X86::RCPPSm, 16 }, 417 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 }, 418 { X86::RSQRTPSr, X86::RSQRTPSm, 16 }, 419 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 }, 420 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 421 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 422 { X86::SQRTPDr, X86::SQRTPDm, 16 }, 423 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 }, 424 { X86::SQRTPSr, X86::SQRTPSm, 16 }, 425 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 }, 426 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 427 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 428 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 429 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 430 { X86::TEST16rr, X86::TEST16rm, 0 }, 431 { X86::TEST32rr, X86::TEST32rm, 0 }, 432 { X86::TEST64rr, X86::TEST64rm, 0 }, 433 { X86::TEST8rr, X86::TEST8rm, 0 }, 434 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 435 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 436 { X86::UCOMISSrr, X86::UCOMISSrm, 0 } 437 }; 438 439 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 440 unsigned RegOp = OpTbl1[i][0]; 441 unsigned MemOp = OpTbl1[i][1]; 442 unsigned Align = OpTbl1[i][2]; 443 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 444 std::make_pair(MemOp,Align))).second) 445 assert(false && "Duplicated entries?"); 446 // Index 1, folded load 447 unsigned AuxInfo = 1 | (1 << 4); 448 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 449 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 450 std::make_pair(RegOp, AuxInfo))).second) 451 AmbEntries.push_back(MemOp); 452 } 453 454 static const unsigned OpTbl2[][3] = { 455 { X86::ADC32rr, X86::ADC32rm, 0 }, 456 { X86::ADC64rr, X86::ADC64rm, 0 }, 457 { X86::ADD16rr, X86::ADD16rm, 0 }, 458 { X86::ADD32rr, X86::ADD32rm, 0 }, 459 { X86::ADD64rr, X86::ADD64rm, 0 }, 460 { X86::ADD8rr, X86::ADD8rm, 0 }, 461 { X86::ADDPDrr, X86::ADDPDrm, 16 }, 462 { X86::ADDPSrr, X86::ADDPSrm, 16 }, 463 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 464 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 465 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 }, 466 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 }, 467 { X86::AND16rr, X86::AND16rm, 0 }, 468 { X86::AND32rr, X86::AND32rm, 0 }, 469 { X86::AND64rr, X86::AND64rm, 0 }, 470 { X86::AND8rr, X86::AND8rm, 0 }, 471 { X86::ANDNPDrr, X86::ANDNPDrm, 16 }, 472 { X86::ANDNPSrr, X86::ANDNPSrm, 16 }, 473 { X86::ANDPDrr, X86::ANDPDrm, 16 }, 474 { X86::ANDPSrr, X86::ANDPSrm, 16 }, 475 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 476 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 477 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 478 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 479 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 480 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 481 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 482 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 483 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 484 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 485 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 486 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 487 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 488 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 489 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 490 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 491 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 492 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 493 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 494 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 495 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 496 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 497 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 498 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 499 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 500 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 501 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 502 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 503 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 504 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 505 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 506 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 507 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 508 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 509 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 510 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 511 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 512 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 513 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 514 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 515 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 516 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 517 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 518 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 519 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 520 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 521 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 522 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 523 { X86::CMPPDrri, X86::CMPPDrmi, 16 }, 524 { X86::CMPPSrri, X86::CMPPSrmi, 16 }, 525 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 526 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 527 { X86::DIVPDrr, X86::DIVPDrm, 16 }, 528 { X86::DIVPSrr, X86::DIVPSrm, 16 }, 529 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 530 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 531 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 }, 532 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 }, 533 { X86::FsANDPDrr, X86::FsANDPDrm, 16 }, 534 { X86::FsANDPSrr, X86::FsANDPSrm, 16 }, 535 { X86::FsORPDrr, X86::FsORPDrm, 16 }, 536 { X86::FsORPSrr, X86::FsORPSrm, 16 }, 537 { X86::FsXORPDrr, X86::FsXORPDrm, 16 }, 538 { X86::FsXORPSrr, X86::FsXORPSrm, 16 }, 539 { X86::HADDPDrr, X86::HADDPDrm, 16 }, 540 { X86::HADDPSrr, X86::HADDPSrm, 16 }, 541 { X86::HSUBPDrr, X86::HSUBPDrm, 16 }, 542 { X86::HSUBPSrr, X86::HSUBPSrm, 16 }, 543 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 544 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 545 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 546 { X86::MAXPDrr, X86::MAXPDrm, 16 }, 547 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 }, 548 { X86::MAXPSrr, X86::MAXPSrm, 16 }, 549 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 }, 550 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 551 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 552 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 553 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 554 { X86::MINPDrr, X86::MINPDrm, 16 }, 555 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 }, 556 { X86::MINPSrr, X86::MINPSrm, 16 }, 557 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 }, 558 { X86::MINSDrr, X86::MINSDrm, 0 }, 559 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 560 { X86::MINSSrr, X86::MINSSrm, 0 }, 561 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 562 { X86::MULPDrr, X86::MULPDrm, 16 }, 563 { X86::MULPSrr, X86::MULPSrm, 16 }, 564 { X86::MULSDrr, X86::MULSDrm, 0 }, 565 { X86::MULSSrr, X86::MULSSrm, 0 }, 566 { X86::OR16rr, X86::OR16rm, 0 }, 567 { X86::OR32rr, X86::OR32rm, 0 }, 568 { X86::OR64rr, X86::OR64rm, 0 }, 569 { X86::OR8rr, X86::OR8rm, 0 }, 570 { X86::ORPDrr, X86::ORPDrm, 16 }, 571 { X86::ORPSrr, X86::ORPSrm, 16 }, 572 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 }, 573 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 }, 574 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 }, 575 { X86::PADDBrr, X86::PADDBrm, 16 }, 576 { X86::PADDDrr, X86::PADDDrm, 16 }, 577 { X86::PADDQrr, X86::PADDQrm, 16 }, 578 { X86::PADDSBrr, X86::PADDSBrm, 16 }, 579 { X86::PADDSWrr, X86::PADDSWrm, 16 }, 580 { X86::PADDWrr, X86::PADDWrm, 16 }, 581 { X86::PANDNrr, X86::PANDNrm, 16 }, 582 { X86::PANDrr, X86::PANDrm, 16 }, 583 { X86::PAVGBrr, X86::PAVGBrm, 16 }, 584 { X86::PAVGWrr, X86::PAVGWrm, 16 }, 585 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 }, 586 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 }, 587 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 }, 588 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 }, 589 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 }, 590 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 }, 591 { X86::PINSRWrri, X86::PINSRWrmi, 16 }, 592 { X86::PMADDWDrr, X86::PMADDWDrm, 16 }, 593 { X86::PMAXSWrr, X86::PMAXSWrm, 16 }, 594 { X86::PMAXUBrr, X86::PMAXUBrm, 16 }, 595 { X86::PMINSWrr, X86::PMINSWrm, 16 }, 596 { X86::PMINUBrr, X86::PMINUBrm, 16 }, 597 { X86::PMULDQrr, X86::PMULDQrm, 16 }, 598 { X86::PMULHUWrr, X86::PMULHUWrm, 16 }, 599 { X86::PMULHWrr, X86::PMULHWrm, 16 }, 600 { X86::PMULLDrr, X86::PMULLDrm, 16 }, 601 { X86::PMULLWrr, X86::PMULLWrm, 16 }, 602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 }, 603 { X86::PORrr, X86::PORrm, 16 }, 604 { X86::PSADBWrr, X86::PSADBWrm, 16 }, 605 { X86::PSLLDrr, X86::PSLLDrm, 16 }, 606 { X86::PSLLQrr, X86::PSLLQrm, 16 }, 607 { X86::PSLLWrr, X86::PSLLWrm, 16 }, 608 { X86::PSRADrr, X86::PSRADrm, 16 }, 609 { X86::PSRAWrr, X86::PSRAWrm, 16 }, 610 { X86::PSRLDrr, X86::PSRLDrm, 16 }, 611 { X86::PSRLQrr, X86::PSRLQrm, 16 }, 612 { X86::PSRLWrr, X86::PSRLWrm, 16 }, 613 { X86::PSUBBrr, X86::PSUBBrm, 16 }, 614 { X86::PSUBDrr, X86::PSUBDrm, 16 }, 615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 }, 616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 }, 617 { X86::PSUBWrr, X86::PSUBWrm, 16 }, 618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 }, 619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 }, 620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 }, 621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 }, 622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 }, 623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 }, 624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 }, 625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 }, 626 { X86::PXORrr, X86::PXORrm, 16 }, 627 { X86::SBB32rr, X86::SBB32rm, 0 }, 628 { X86::SBB64rr, X86::SBB64rm, 0 }, 629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 }, 630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 }, 631 { X86::SUB16rr, X86::SUB16rm, 0 }, 632 { X86::SUB32rr, X86::SUB32rm, 0 }, 633 { X86::SUB64rr, X86::SUB64rm, 0 }, 634 { X86::SUB8rr, X86::SUB8rm, 0 }, 635 { X86::SUBPDrr, X86::SUBPDrm, 16 }, 636 { X86::SUBPSrr, X86::SUBPSrm, 16 }, 637 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 638 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 639 // FIXME: TEST*rr -> swapped operand of TEST*mr. 640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 }, 641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 }, 642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 }, 643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 }, 644 { X86::XOR16rr, X86::XOR16rm, 0 }, 645 { X86::XOR32rr, X86::XOR32rm, 0 }, 646 { X86::XOR64rr, X86::XOR64rm, 0 }, 647 { X86::XOR8rr, X86::XOR8rm, 0 }, 648 { X86::XORPDrr, X86::XORPDrm, 16 }, 649 { X86::XORPSrr, X86::XORPSrm, 16 } 650 }; 651 652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 653 unsigned RegOp = OpTbl2[i][0]; 654 unsigned MemOp = OpTbl2[i][1]; 655 unsigned Align = OpTbl2[i][2]; 656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 657 std::make_pair(MemOp,Align))).second) 658 assert(false && "Duplicated entries?"); 659 // Index 2, folded load 660 unsigned AuxInfo = 2 | (1 << 4); 661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 662 std::make_pair(RegOp, AuxInfo))).second) 663 AmbEntries.push_back(MemOp); 664 } 665 666 // Remove ambiguous entries. 667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 668} 669 670bool 671X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 672 unsigned &SrcReg, unsigned &DstReg, 673 unsigned &SubIdx) const { 674 switch (MI.getOpcode()) { 675 default: break; 676 case X86::MOVSX16rr8: 677 case X86::MOVZX16rr8: 678 case X86::MOVSX32rr8: 679 case X86::MOVZX32rr8: 680 case X86::MOVSX64rr8: 681 case X86::MOVZX64rr8: 682 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 683 // It's not always legal to reference the low 8-bit of the larger 684 // register in 32-bit mode. 685 return false; 686 case X86::MOVSX32rr16: 687 case X86::MOVZX32rr16: 688 case X86::MOVSX64rr16: 689 case X86::MOVZX64rr16: 690 case X86::MOVSX64rr32: 691 case X86::MOVZX64rr32: { 692 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 693 // Be conservative. 694 return false; 695 SrcReg = MI.getOperand(1).getReg(); 696 DstReg = MI.getOperand(0).getReg(); 697 switch (MI.getOpcode()) { 698 default: 699 llvm_unreachable(0); 700 break; 701 case X86::MOVSX16rr8: 702 case X86::MOVZX16rr8: 703 case X86::MOVSX32rr8: 704 case X86::MOVZX32rr8: 705 case X86::MOVSX64rr8: 706 case X86::MOVZX64rr8: 707 SubIdx = X86::sub_8bit; 708 break; 709 case X86::MOVSX32rr16: 710 case X86::MOVZX32rr16: 711 case X86::MOVSX64rr16: 712 case X86::MOVZX64rr16: 713 SubIdx = X86::sub_16bit; 714 break; 715 case X86::MOVSX64rr32: 716 case X86::MOVZX64rr32: 717 SubIdx = X86::sub_32bit; 718 break; 719 } 720 return true; 721 } 722 } 723 return false; 724} 725 726/// isFrameOperand - Return true and the FrameIndex if the specified 727/// operand and follow operands form a reference to the stack frame. 728bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 729 int &FrameIndex) const { 730 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 731 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 732 MI->getOperand(Op+1).getImm() == 1 && 733 MI->getOperand(Op+2).getReg() == 0 && 734 MI->getOperand(Op+3).getImm() == 0) { 735 FrameIndex = MI->getOperand(Op).getIndex(); 736 return true; 737 } 738 return false; 739} 740 741static bool isFrameLoadOpcode(int Opcode) { 742 switch (Opcode) { 743 default: break; 744 case X86::MOV8rm: 745 case X86::MOV16rm: 746 case X86::MOV32rm: 747 case X86::MOV32rm_TC: 748 case X86::MOV64rm: 749 case X86::MOV64rm_TC: 750 case X86::LD_Fp64m: 751 case X86::MOVSSrm: 752 case X86::MOVSDrm: 753 case X86::MOVAPSrm: 754 case X86::MOVAPDrm: 755 case X86::MOVDQArm: 756 case X86::MMX_MOVD64rm: 757 case X86::MMX_MOVQ64rm: 758 return true; 759 break; 760 } 761 return false; 762} 763 764static bool isFrameStoreOpcode(int Opcode) { 765 switch (Opcode) { 766 default: break; 767 case X86::MOV8mr: 768 case X86::MOV16mr: 769 case X86::MOV32mr: 770 case X86::MOV32mr_TC: 771 case X86::MOV64mr: 772 case X86::MOV64mr_TC: 773 case X86::ST_FpP64m: 774 case X86::MOVSSmr: 775 case X86::MOVSDmr: 776 case X86::MOVAPSmr: 777 case X86::MOVAPDmr: 778 case X86::MOVDQAmr: 779 case X86::MMX_MOVD64mr: 780 case X86::MMX_MOVQ64mr: 781 case X86::MMX_MOVNTQmr: 782 return true; 783 } 784 return false; 785} 786 787unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 788 int &FrameIndex) const { 789 if (isFrameLoadOpcode(MI->getOpcode())) 790 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 791 return MI->getOperand(0).getReg(); 792 return 0; 793} 794 795unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 796 int &FrameIndex) const { 797 if (isFrameLoadOpcode(MI->getOpcode())) { 798 unsigned Reg; 799 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 800 return Reg; 801 // Check for post-frame index elimination operations 802 const MachineMemOperand *Dummy; 803 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 804 } 805 return 0; 806} 807 808bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 809 const MachineMemOperand *&MMO, 810 int &FrameIndex) const { 811 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 812 oe = MI->memoperands_end(); 813 o != oe; 814 ++o) { 815 if ((*o)->isLoad() && (*o)->getValue()) 816 if (const FixedStackPseudoSourceValue *Value = 817 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 818 FrameIndex = Value->getFrameIndex(); 819 MMO = *o; 820 return true; 821 } 822 } 823 return false; 824} 825 826unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 827 int &FrameIndex) const { 828 if (isFrameStoreOpcode(MI->getOpcode())) 829 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 830 isFrameOperand(MI, 0, FrameIndex)) 831 return MI->getOperand(X86::AddrNumOperands).getReg(); 832 return 0; 833} 834 835unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 836 int &FrameIndex) const { 837 if (isFrameStoreOpcode(MI->getOpcode())) { 838 unsigned Reg; 839 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 840 return Reg; 841 // Check for post-frame index elimination operations 842 const MachineMemOperand *Dummy; 843 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 844 } 845 return 0; 846} 847 848bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI, 849 const MachineMemOperand *&MMO, 850 int &FrameIndex) const { 851 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 852 oe = MI->memoperands_end(); 853 o != oe; 854 ++o) { 855 if ((*o)->isStore() && (*o)->getValue()) 856 if (const FixedStackPseudoSourceValue *Value = 857 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 858 FrameIndex = Value->getFrameIndex(); 859 MMO = *o; 860 return true; 861 } 862 } 863 return false; 864} 865 866/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 867/// X86::MOVPC32r. 868static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 869 bool isPICBase = false; 870 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 871 E = MRI.def_end(); I != E; ++I) { 872 MachineInstr *DefMI = I.getOperand().getParent(); 873 if (DefMI->getOpcode() != X86::MOVPC32r) 874 return false; 875 assert(!isPICBase && "More than one PIC base?"); 876 isPICBase = true; 877 } 878 return isPICBase; 879} 880 881bool 882X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 883 AliasAnalysis *AA) const { 884 switch (MI->getOpcode()) { 885 default: break; 886 case X86::MOV8rm: 887 case X86::MOV16rm: 888 case X86::MOV32rm: 889 case X86::MOV64rm: 890 case X86::LD_Fp64m: 891 case X86::MOVSSrm: 892 case X86::MOVSDrm: 893 case X86::MOVAPSrm: 894 case X86::MOVUPSrm: 895 case X86::MOVUPSrm_Int: 896 case X86::MOVAPDrm: 897 case X86::MOVDQArm: 898 case X86::MMX_MOVD64rm: 899 case X86::MMX_MOVQ64rm: 900 case X86::FsMOVAPSrm: 901 case X86::FsMOVAPDrm: { 902 // Loads from constant pools are trivially rematerializable. 903 if (MI->getOperand(1).isReg() && 904 MI->getOperand(2).isImm() && 905 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 906 MI->isInvariantLoad(AA)) { 907 unsigned BaseReg = MI->getOperand(1).getReg(); 908 if (BaseReg == 0 || BaseReg == X86::RIP) 909 return true; 910 // Allow re-materialization of PIC load. 911 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 912 return false; 913 const MachineFunction &MF = *MI->getParent()->getParent(); 914 const MachineRegisterInfo &MRI = MF.getRegInfo(); 915 bool isPICBase = false; 916 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 917 E = MRI.def_end(); I != E; ++I) { 918 MachineInstr *DefMI = I.getOperand().getParent(); 919 if (DefMI->getOpcode() != X86::MOVPC32r) 920 return false; 921 assert(!isPICBase && "More than one PIC base?"); 922 isPICBase = true; 923 } 924 return isPICBase; 925 } 926 return false; 927 } 928 929 case X86::LEA32r: 930 case X86::LEA64r: { 931 if (MI->getOperand(2).isImm() && 932 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 933 !MI->getOperand(4).isReg()) { 934 // lea fi#, lea GV, etc. are all rematerializable. 935 if (!MI->getOperand(1).isReg()) 936 return true; 937 unsigned BaseReg = MI->getOperand(1).getReg(); 938 if (BaseReg == 0) 939 return true; 940 // Allow re-materialization of lea PICBase + x. 941 const MachineFunction &MF = *MI->getParent()->getParent(); 942 const MachineRegisterInfo &MRI = MF.getRegInfo(); 943 return regIsPICBase(BaseReg, MRI); 944 } 945 return false; 946 } 947 } 948 949 // All other instructions marked M_REMATERIALIZABLE are always trivially 950 // rematerializable. 951 return true; 952} 953 954/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 955/// would clobber the EFLAGS condition register. Note the result may be 956/// conservative. If it cannot definitely determine the safety after visiting 957/// a few instructions in each direction it assumes it's not safe. 958static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 959 MachineBasicBlock::iterator I) { 960 MachineBasicBlock::iterator E = MBB.end(); 961 962 // It's always safe to clobber EFLAGS at the end of a block. 963 if (I == E) 964 return true; 965 966 // For compile time consideration, if we are not able to determine the 967 // safety after visiting 4 instructions in each direction, we will assume 968 // it's not safe. 969 MachineBasicBlock::iterator Iter = I; 970 for (unsigned i = 0; i < 4; ++i) { 971 bool SeenDef = false; 972 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 973 MachineOperand &MO = Iter->getOperand(j); 974 if (!MO.isReg()) 975 continue; 976 if (MO.getReg() == X86::EFLAGS) { 977 if (MO.isUse()) 978 return false; 979 SeenDef = true; 980 } 981 } 982 983 if (SeenDef) 984 // This instruction defines EFLAGS, no need to look any further. 985 return true; 986 ++Iter; 987 // Skip over DBG_VALUE. 988 while (Iter != E && Iter->isDebugValue()) 989 ++Iter; 990 991 // If we make it to the end of the block, it's safe to clobber EFLAGS. 992 if (Iter == E) 993 return true; 994 } 995 996 MachineBasicBlock::iterator B = MBB.begin(); 997 Iter = I; 998 for (unsigned i = 0; i < 4; ++i) { 999 // If we make it to the beginning of the block, it's safe to clobber 1000 // EFLAGS iff EFLAGS is not live-in. 1001 if (Iter == B) 1002 return !MBB.isLiveIn(X86::EFLAGS); 1003 1004 --Iter; 1005 // Skip over DBG_VALUE. 1006 while (Iter != B && Iter->isDebugValue()) 1007 --Iter; 1008 1009 bool SawKill = false; 1010 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1011 MachineOperand &MO = Iter->getOperand(j); 1012 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1013 if (MO.isDef()) return MO.isDead(); 1014 if (MO.isKill()) SawKill = true; 1015 } 1016 } 1017 1018 if (SawKill) 1019 // This instruction kills EFLAGS and doesn't redefine it, so 1020 // there's no need to look further. 1021 return true; 1022 } 1023 1024 // Conservative answer. 1025 return false; 1026} 1027 1028void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1029 MachineBasicBlock::iterator I, 1030 unsigned DestReg, unsigned SubIdx, 1031 const MachineInstr *Orig, 1032 const TargetRegisterInfo &TRI) const { 1033 DebugLoc DL = Orig->getDebugLoc(); 1034 1035 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1036 // Re-materialize them as movri instructions to avoid side effects. 1037 bool Clone = true; 1038 unsigned Opc = Orig->getOpcode(); 1039 switch (Opc) { 1040 default: break; 1041 case X86::MOV8r0: 1042 case X86::MOV16r0: 1043 case X86::MOV32r0: 1044 case X86::MOV64r0: { 1045 if (!isSafeToClobberEFLAGS(MBB, I)) { 1046 switch (Opc) { 1047 default: break; 1048 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1049 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1050 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1051 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1052 } 1053 Clone = false; 1054 } 1055 break; 1056 } 1057 } 1058 1059 if (Clone) { 1060 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1061 MBB.insert(I, MI); 1062 } else { 1063 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1064 } 1065 1066 MachineInstr *NewMI = prior(I); 1067 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1068} 1069 1070/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1071/// is not marked dead. 1072static bool hasLiveCondCodeDef(MachineInstr *MI) { 1073 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1074 MachineOperand &MO = MI->getOperand(i); 1075 if (MO.isReg() && MO.isDef() && 1076 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1077 return true; 1078 } 1079 } 1080 return false; 1081} 1082 1083/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1084/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1085/// to a 32-bit superregister and then truncating back down to a 16-bit 1086/// subregister. 1087MachineInstr * 1088X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1089 MachineFunction::iterator &MFI, 1090 MachineBasicBlock::iterator &MBBI, 1091 LiveVariables *LV) const { 1092 MachineInstr *MI = MBBI; 1093 unsigned Dest = MI->getOperand(0).getReg(); 1094 unsigned Src = MI->getOperand(1).getReg(); 1095 bool isDead = MI->getOperand(0).isDead(); 1096 bool isKill = MI->getOperand(1).isKill(); 1097 1098 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1099 ? X86::LEA64_32r : X86::LEA32r; 1100 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1101 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1102 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1103 1104 // Build and insert into an implicit UNDEF value. This is OK because 1105 // well be shifting and then extracting the lower 16-bits. 1106 // This has the potential to cause partial register stall. e.g. 1107 // movw (%rbp,%rcx,2), %dx 1108 // leal -65(%rdx), %esi 1109 // But testing has shown this *does* help performance in 64-bit mode (at 1110 // least on modern x86 machines). 1111 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1112 MachineInstr *InsMI = 1113 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1114 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1115 .addReg(Src, getKillRegState(isKill)); 1116 1117 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1118 get(Opc), leaOutReg); 1119 switch (MIOpc) { 1120 default: 1121 llvm_unreachable(0); 1122 break; 1123 case X86::SHL16ri: { 1124 unsigned ShAmt = MI->getOperand(2).getImm(); 1125 MIB.addReg(0).addImm(1 << ShAmt) 1126 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1127 break; 1128 } 1129 case X86::INC16r: 1130 case X86::INC64_16r: 1131 addRegOffset(MIB, leaInReg, true, 1); 1132 break; 1133 case X86::DEC16r: 1134 case X86::DEC64_16r: 1135 addRegOffset(MIB, leaInReg, true, -1); 1136 break; 1137 case X86::ADD16ri: 1138 case X86::ADD16ri8: 1139 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1140 break; 1141 case X86::ADD16rr: { 1142 unsigned Src2 = MI->getOperand(2).getReg(); 1143 bool isKill2 = MI->getOperand(2).isKill(); 1144 unsigned leaInReg2 = 0; 1145 MachineInstr *InsMI2 = 0; 1146 if (Src == Src2) { 1147 // ADD16rr %reg1028<kill>, %reg1028 1148 // just a single insert_subreg. 1149 addRegReg(MIB, leaInReg, true, leaInReg, false); 1150 } else { 1151 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1152 // Build and insert into an implicit UNDEF value. This is OK because 1153 // well be shifting and then extracting the lower 16-bits. 1154 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); 1155 InsMI2 = 1156 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1157 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1158 .addReg(Src2, getKillRegState(isKill2)); 1159 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1160 } 1161 if (LV && isKill2 && InsMI2) 1162 LV->replaceKillInstruction(Src2, MI, InsMI2); 1163 break; 1164 } 1165 } 1166 1167 MachineInstr *NewMI = MIB; 1168 MachineInstr *ExtMI = 1169 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1170 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1171 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1172 1173 if (LV) { 1174 // Update live variables 1175 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1176 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1177 if (isKill) 1178 LV->replaceKillInstruction(Src, MI, InsMI); 1179 if (isDead) 1180 LV->replaceKillInstruction(Dest, MI, ExtMI); 1181 } 1182 1183 return ExtMI; 1184} 1185 1186/// convertToThreeAddress - This method must be implemented by targets that 1187/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1188/// may be able to convert a two-address instruction into a true 1189/// three-address instruction on demand. This allows the X86 target (for 1190/// example) to convert ADD and SHL instructions into LEA instructions if they 1191/// would require register copies due to two-addressness. 1192/// 1193/// This method returns a null pointer if the transformation cannot be 1194/// performed, otherwise it returns the new instruction. 1195/// 1196MachineInstr * 1197X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1198 MachineBasicBlock::iterator &MBBI, 1199 LiveVariables *LV) const { 1200 MachineInstr *MI = MBBI; 1201 MachineFunction &MF = *MI->getParent()->getParent(); 1202 // All instructions input are two-addr instructions. Get the known operands. 1203 unsigned Dest = MI->getOperand(0).getReg(); 1204 unsigned Src = MI->getOperand(1).getReg(); 1205 bool isDead = MI->getOperand(0).isDead(); 1206 bool isKill = MI->getOperand(1).isKill(); 1207 1208 MachineInstr *NewMI = NULL; 1209 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1210 // we have better subtarget support, enable the 16-bit LEA generation here. 1211 // 16-bit LEA is also slow on Core2. 1212 bool DisableLEA16 = true; 1213 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1214 1215 unsigned MIOpc = MI->getOpcode(); 1216 switch (MIOpc) { 1217 case X86::SHUFPSrri: { 1218 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1219 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1220 1221 unsigned B = MI->getOperand(1).getReg(); 1222 unsigned C = MI->getOperand(2).getReg(); 1223 if (B != C) return 0; 1224 unsigned A = MI->getOperand(0).getReg(); 1225 unsigned M = MI->getOperand(3).getImm(); 1226 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1227 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1228 .addReg(B, getKillRegState(isKill)).addImm(M); 1229 break; 1230 } 1231 case X86::SHL64ri: { 1232 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1233 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1234 // the flags produced by a shift yet, so this is safe. 1235 unsigned ShAmt = MI->getOperand(2).getImm(); 1236 if (ShAmt == 0 || ShAmt >= 4) return 0; 1237 1238 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1239 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1240 .addReg(0).addImm(1 << ShAmt) 1241 .addReg(Src, getKillRegState(isKill)) 1242 .addImm(0).addReg(0); 1243 break; 1244 } 1245 case X86::SHL32ri: { 1246 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1247 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1248 // the flags produced by a shift yet, so this is safe. 1249 unsigned ShAmt = MI->getOperand(2).getImm(); 1250 if (ShAmt == 0 || ShAmt >= 4) return 0; 1251 1252 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1253 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1254 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1255 .addReg(0).addImm(1 << ShAmt) 1256 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0); 1257 break; 1258 } 1259 case X86::SHL16ri: { 1260 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1261 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1262 // the flags produced by a shift yet, so this is safe. 1263 unsigned ShAmt = MI->getOperand(2).getImm(); 1264 if (ShAmt == 0 || ShAmt >= 4) return 0; 1265 1266 if (DisableLEA16) 1267 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1268 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1269 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1270 .addReg(0).addImm(1 << ShAmt) 1271 .addReg(Src, getKillRegState(isKill)) 1272 .addImm(0).addReg(0); 1273 break; 1274 } 1275 default: { 1276 // The following opcodes also sets the condition code register(s). Only 1277 // convert them to equivalent lea if the condition code register def's 1278 // are dead! 1279 if (hasLiveCondCodeDef(MI)) 1280 return 0; 1281 1282 switch (MIOpc) { 1283 default: return 0; 1284 case X86::INC64r: 1285 case X86::INC32r: 1286 case X86::INC64_32r: { 1287 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1288 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1289 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1290 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1291 .addReg(Dest, RegState::Define | 1292 getDeadRegState(isDead)), 1293 Src, isKill, 1); 1294 break; 1295 } 1296 case X86::INC16r: 1297 case X86::INC64_16r: 1298 if (DisableLEA16) 1299 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1300 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1301 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1302 .addReg(Dest, RegState::Define | 1303 getDeadRegState(isDead)), 1304 Src, isKill, 1); 1305 break; 1306 case X86::DEC64r: 1307 case X86::DEC32r: 1308 case X86::DEC64_32r: { 1309 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1310 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1311 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1312 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1313 .addReg(Dest, RegState::Define | 1314 getDeadRegState(isDead)), 1315 Src, isKill, -1); 1316 break; 1317 } 1318 case X86::DEC16r: 1319 case X86::DEC64_16r: 1320 if (DisableLEA16) 1321 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1322 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1323 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1324 .addReg(Dest, RegState::Define | 1325 getDeadRegState(isDead)), 1326 Src, isKill, -1); 1327 break; 1328 case X86::ADD64rr: 1329 case X86::ADD32rr: { 1330 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1331 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1332 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1333 unsigned Src2 = MI->getOperand(2).getReg(); 1334 bool isKill2 = MI->getOperand(2).isKill(); 1335 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1336 .addReg(Dest, RegState::Define | 1337 getDeadRegState(isDead)), 1338 Src, isKill, Src2, isKill2); 1339 if (LV && isKill2) 1340 LV->replaceKillInstruction(Src2, MI, NewMI); 1341 break; 1342 } 1343 case X86::ADD16rr: { 1344 if (DisableLEA16) 1345 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1346 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1347 unsigned Src2 = MI->getOperand(2).getReg(); 1348 bool isKill2 = MI->getOperand(2).isKill(); 1349 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1350 .addReg(Dest, RegState::Define | 1351 getDeadRegState(isDead)), 1352 Src, isKill, Src2, isKill2); 1353 if (LV && isKill2) 1354 LV->replaceKillInstruction(Src2, MI, NewMI); 1355 break; 1356 } 1357 case X86::ADD64ri32: 1358 case X86::ADD64ri8: 1359 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1360 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1361 .addReg(Dest, RegState::Define | 1362 getDeadRegState(isDead)), 1363 Src, isKill, MI->getOperand(2).getImm()); 1364 break; 1365 case X86::ADD32ri: 1366 case X86::ADD32ri8: { 1367 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1368 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1369 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1370 .addReg(Dest, RegState::Define | 1371 getDeadRegState(isDead)), 1372 Src, isKill, MI->getOperand(2).getImm()); 1373 break; 1374 } 1375 case X86::ADD16ri: 1376 case X86::ADD16ri8: 1377 if (DisableLEA16) 1378 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1379 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1380 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1381 .addReg(Dest, RegState::Define | 1382 getDeadRegState(isDead)), 1383 Src, isKill, MI->getOperand(2).getImm()); 1384 break; 1385 } 1386 } 1387 } 1388 1389 if (!NewMI) return 0; 1390 1391 if (LV) { // Update live variables 1392 if (isKill) 1393 LV->replaceKillInstruction(Src, MI, NewMI); 1394 if (isDead) 1395 LV->replaceKillInstruction(Dest, MI, NewMI); 1396 } 1397 1398 MFI->insert(MBBI, NewMI); // Insert the new inst 1399 return NewMI; 1400} 1401 1402/// commuteInstruction - We have a few instructions that must be hacked on to 1403/// commute them. 1404/// 1405MachineInstr * 1406X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1407 switch (MI->getOpcode()) { 1408 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1409 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1410 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1411 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1412 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1413 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1414 unsigned Opc; 1415 unsigned Size; 1416 switch (MI->getOpcode()) { 1417 default: llvm_unreachable("Unreachable!"); 1418 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1419 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1420 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1421 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1422 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1423 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1424 } 1425 unsigned Amt = MI->getOperand(3).getImm(); 1426 if (NewMI) { 1427 MachineFunction &MF = *MI->getParent()->getParent(); 1428 MI = MF.CloneMachineInstr(MI); 1429 NewMI = false; 1430 } 1431 MI->setDesc(get(Opc)); 1432 MI->getOperand(3).setImm(Size-Amt); 1433 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1434 } 1435 case X86::CMOVB16rr: 1436 case X86::CMOVB32rr: 1437 case X86::CMOVB64rr: 1438 case X86::CMOVAE16rr: 1439 case X86::CMOVAE32rr: 1440 case X86::CMOVAE64rr: 1441 case X86::CMOVE16rr: 1442 case X86::CMOVE32rr: 1443 case X86::CMOVE64rr: 1444 case X86::CMOVNE16rr: 1445 case X86::CMOVNE32rr: 1446 case X86::CMOVNE64rr: 1447 case X86::CMOVBE16rr: 1448 case X86::CMOVBE32rr: 1449 case X86::CMOVBE64rr: 1450 case X86::CMOVA16rr: 1451 case X86::CMOVA32rr: 1452 case X86::CMOVA64rr: 1453 case X86::CMOVL16rr: 1454 case X86::CMOVL32rr: 1455 case X86::CMOVL64rr: 1456 case X86::CMOVGE16rr: 1457 case X86::CMOVGE32rr: 1458 case X86::CMOVGE64rr: 1459 case X86::CMOVLE16rr: 1460 case X86::CMOVLE32rr: 1461 case X86::CMOVLE64rr: 1462 case X86::CMOVG16rr: 1463 case X86::CMOVG32rr: 1464 case X86::CMOVG64rr: 1465 case X86::CMOVS16rr: 1466 case X86::CMOVS32rr: 1467 case X86::CMOVS64rr: 1468 case X86::CMOVNS16rr: 1469 case X86::CMOVNS32rr: 1470 case X86::CMOVNS64rr: 1471 case X86::CMOVP16rr: 1472 case X86::CMOVP32rr: 1473 case X86::CMOVP64rr: 1474 case X86::CMOVNP16rr: 1475 case X86::CMOVNP32rr: 1476 case X86::CMOVNP64rr: 1477 case X86::CMOVO16rr: 1478 case X86::CMOVO32rr: 1479 case X86::CMOVO64rr: 1480 case X86::CMOVNO16rr: 1481 case X86::CMOVNO32rr: 1482 case X86::CMOVNO64rr: { 1483 unsigned Opc = 0; 1484 switch (MI->getOpcode()) { 1485 default: break; 1486 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1487 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1488 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1489 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1490 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1491 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1492 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1493 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1494 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1495 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1496 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1497 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1498 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1499 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1500 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1501 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1502 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1503 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1504 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1505 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1506 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1507 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1508 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1509 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1510 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1511 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1512 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1513 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1514 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1515 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1516 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1517 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1518 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 1519 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1520 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1521 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1522 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1523 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1524 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 1525 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1526 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1527 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1528 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1529 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1530 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 1531 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1532 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1533 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1534 } 1535 if (NewMI) { 1536 MachineFunction &MF = *MI->getParent()->getParent(); 1537 MI = MF.CloneMachineInstr(MI); 1538 NewMI = false; 1539 } 1540 MI->setDesc(get(Opc)); 1541 // Fallthrough intended. 1542 } 1543 default: 1544 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1545 } 1546} 1547 1548static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1549 switch (BrOpc) { 1550 default: return X86::COND_INVALID; 1551 case X86::JE_4: return X86::COND_E; 1552 case X86::JNE_4: return X86::COND_NE; 1553 case X86::JL_4: return X86::COND_L; 1554 case X86::JLE_4: return X86::COND_LE; 1555 case X86::JG_4: return X86::COND_G; 1556 case X86::JGE_4: return X86::COND_GE; 1557 case X86::JB_4: return X86::COND_B; 1558 case X86::JBE_4: return X86::COND_BE; 1559 case X86::JA_4: return X86::COND_A; 1560 case X86::JAE_4: return X86::COND_AE; 1561 case X86::JS_4: return X86::COND_S; 1562 case X86::JNS_4: return X86::COND_NS; 1563 case X86::JP_4: return X86::COND_P; 1564 case X86::JNP_4: return X86::COND_NP; 1565 case X86::JO_4: return X86::COND_O; 1566 case X86::JNO_4: return X86::COND_NO; 1567 } 1568} 1569 1570unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1571 switch (CC) { 1572 default: llvm_unreachable("Illegal condition code!"); 1573 case X86::COND_E: return X86::JE_4; 1574 case X86::COND_NE: return X86::JNE_4; 1575 case X86::COND_L: return X86::JL_4; 1576 case X86::COND_LE: return X86::JLE_4; 1577 case X86::COND_G: return X86::JG_4; 1578 case X86::COND_GE: return X86::JGE_4; 1579 case X86::COND_B: return X86::JB_4; 1580 case X86::COND_BE: return X86::JBE_4; 1581 case X86::COND_A: return X86::JA_4; 1582 case X86::COND_AE: return X86::JAE_4; 1583 case X86::COND_S: return X86::JS_4; 1584 case X86::COND_NS: return X86::JNS_4; 1585 case X86::COND_P: return X86::JP_4; 1586 case X86::COND_NP: return X86::JNP_4; 1587 case X86::COND_O: return X86::JO_4; 1588 case X86::COND_NO: return X86::JNO_4; 1589 } 1590} 1591 1592/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1593/// e.g. turning COND_E to COND_NE. 1594X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1595 switch (CC) { 1596 default: llvm_unreachable("Illegal condition code!"); 1597 case X86::COND_E: return X86::COND_NE; 1598 case X86::COND_NE: return X86::COND_E; 1599 case X86::COND_L: return X86::COND_GE; 1600 case X86::COND_LE: return X86::COND_G; 1601 case X86::COND_G: return X86::COND_LE; 1602 case X86::COND_GE: return X86::COND_L; 1603 case X86::COND_B: return X86::COND_AE; 1604 case X86::COND_BE: return X86::COND_A; 1605 case X86::COND_A: return X86::COND_BE; 1606 case X86::COND_AE: return X86::COND_B; 1607 case X86::COND_S: return X86::COND_NS; 1608 case X86::COND_NS: return X86::COND_S; 1609 case X86::COND_P: return X86::COND_NP; 1610 case X86::COND_NP: return X86::COND_P; 1611 case X86::COND_O: return X86::COND_NO; 1612 case X86::COND_NO: return X86::COND_O; 1613 } 1614} 1615 1616bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1617 const TargetInstrDesc &TID = MI->getDesc(); 1618 if (!TID.isTerminator()) return false; 1619 1620 // Conditional branch is a special case. 1621 if (TID.isBranch() && !TID.isBarrier()) 1622 return true; 1623 if (!TID.isPredicable()) 1624 return true; 1625 return !isPredicated(MI); 1626} 1627 1628bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1629 MachineBasicBlock *&TBB, 1630 MachineBasicBlock *&FBB, 1631 SmallVectorImpl<MachineOperand> &Cond, 1632 bool AllowModify) const { 1633 // Start from the bottom of the block and work up, examining the 1634 // terminator instructions. 1635 MachineBasicBlock::iterator I = MBB.end(); 1636 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 1637 while (I != MBB.begin()) { 1638 --I; 1639 if (I->isDebugValue()) 1640 continue; 1641 1642 // Working from the bottom, when we see a non-terminator instruction, we're 1643 // done. 1644 if (!isUnpredicatedTerminator(I)) 1645 break; 1646 1647 // A terminator that isn't a branch can't easily be handled by this 1648 // analysis. 1649 if (!I->getDesc().isBranch()) 1650 return true; 1651 1652 // Handle unconditional branches. 1653 if (I->getOpcode() == X86::JMP_4) { 1654 UnCondBrIter = I; 1655 1656 if (!AllowModify) { 1657 TBB = I->getOperand(0).getMBB(); 1658 continue; 1659 } 1660 1661 // If the block has any instructions after a JMP, delete them. 1662 while (llvm::next(I) != MBB.end()) 1663 llvm::next(I)->eraseFromParent(); 1664 1665 Cond.clear(); 1666 FBB = 0; 1667 1668 // Delete the JMP if it's equivalent to a fall-through. 1669 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1670 TBB = 0; 1671 I->eraseFromParent(); 1672 I = MBB.end(); 1673 UnCondBrIter = MBB.end(); 1674 continue; 1675 } 1676 1677 // TBB is used to indicate the unconditional destination. 1678 TBB = I->getOperand(0).getMBB(); 1679 continue; 1680 } 1681 1682 // Handle conditional branches. 1683 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1684 if (BranchCode == X86::COND_INVALID) 1685 return true; // Can't handle indirect branch. 1686 1687 // Working from the bottom, handle the first conditional branch. 1688 if (Cond.empty()) { 1689 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 1690 if (AllowModify && UnCondBrIter != MBB.end() && 1691 MBB.isLayoutSuccessor(TargetBB)) { 1692 // If we can modify the code and it ends in something like: 1693 // 1694 // jCC L1 1695 // jmp L2 1696 // L1: 1697 // ... 1698 // L2: 1699 // 1700 // Then we can change this to: 1701 // 1702 // jnCC L2 1703 // L1: 1704 // ... 1705 // L2: 1706 // 1707 // Which is a bit more efficient. 1708 // We conditionally jump to the fall-through block. 1709 BranchCode = GetOppositeBranchCondition(BranchCode); 1710 unsigned JNCC = GetCondBranchFromCond(BranchCode); 1711 MachineBasicBlock::iterator OldInst = I; 1712 1713 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 1714 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 1715 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 1716 .addMBB(TargetBB); 1717 MBB.addSuccessor(TargetBB); 1718 1719 OldInst->eraseFromParent(); 1720 UnCondBrIter->eraseFromParent(); 1721 1722 // Restart the analysis. 1723 UnCondBrIter = MBB.end(); 1724 I = MBB.end(); 1725 continue; 1726 } 1727 1728 FBB = TBB; 1729 TBB = I->getOperand(0).getMBB(); 1730 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1731 continue; 1732 } 1733 1734 // Handle subsequent conditional branches. Only handle the case where all 1735 // conditional branches branch to the same destination and their condition 1736 // opcodes fit one of the special multi-branch idioms. 1737 assert(Cond.size() == 1); 1738 assert(TBB); 1739 1740 // Only handle the case where all conditional branches branch to the same 1741 // destination. 1742 if (TBB != I->getOperand(0).getMBB()) 1743 return true; 1744 1745 // If the conditions are the same, we can leave them alone. 1746 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1747 if (OldBranchCode == BranchCode) 1748 continue; 1749 1750 // If they differ, see if they fit one of the known patterns. Theoretically, 1751 // we could handle more patterns here, but we shouldn't expect to see them 1752 // if instruction selection has done a reasonable job. 1753 if ((OldBranchCode == X86::COND_NP && 1754 BranchCode == X86::COND_E) || 1755 (OldBranchCode == X86::COND_E && 1756 BranchCode == X86::COND_NP)) 1757 BranchCode = X86::COND_NP_OR_E; 1758 else if ((OldBranchCode == X86::COND_P && 1759 BranchCode == X86::COND_NE) || 1760 (OldBranchCode == X86::COND_NE && 1761 BranchCode == X86::COND_P)) 1762 BranchCode = X86::COND_NE_OR_P; 1763 else 1764 return true; 1765 1766 // Update the MachineOperand. 1767 Cond[0].setImm(BranchCode); 1768 } 1769 1770 return false; 1771} 1772 1773unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1774 MachineBasicBlock::iterator I = MBB.end(); 1775 unsigned Count = 0; 1776 1777 while (I != MBB.begin()) { 1778 --I; 1779 if (I->isDebugValue()) 1780 continue; 1781 if (I->getOpcode() != X86::JMP_4 && 1782 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1783 break; 1784 // Remove the branch. 1785 I->eraseFromParent(); 1786 I = MBB.end(); 1787 ++Count; 1788 } 1789 1790 return Count; 1791} 1792 1793unsigned 1794X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1795 MachineBasicBlock *FBB, 1796 const SmallVectorImpl<MachineOperand> &Cond, 1797 DebugLoc DL) const { 1798 // Shouldn't be a fall through. 1799 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1800 assert((Cond.size() == 1 || Cond.size() == 0) && 1801 "X86 branch conditions have one component!"); 1802 1803 if (Cond.empty()) { 1804 // Unconditional branch? 1805 assert(!FBB && "Unconditional branch with multiple successors!"); 1806 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 1807 return 1; 1808 } 1809 1810 // Conditional branch. 1811 unsigned Count = 0; 1812 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1813 switch (CC) { 1814 case X86::COND_NP_OR_E: 1815 // Synthesize NP_OR_E with two branches. 1816 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 1817 ++Count; 1818 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 1819 ++Count; 1820 break; 1821 case X86::COND_NE_OR_P: 1822 // Synthesize NE_OR_P with two branches. 1823 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 1824 ++Count; 1825 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 1826 ++Count; 1827 break; 1828 default: { 1829 unsigned Opc = GetCondBranchFromCond(CC); 1830 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 1831 ++Count; 1832 } 1833 } 1834 if (FBB) { 1835 // Two-way Conditional branch. Insert the second branch. 1836 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 1837 ++Count; 1838 } 1839 return Count; 1840} 1841 1842/// isHReg - Test if the given register is a physical h register. 1843static bool isHReg(unsigned Reg) { 1844 return X86::GR8_ABCD_HRegClass.contains(Reg); 1845} 1846 1847void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 1848 MachineBasicBlock::iterator MI, DebugLoc DL, 1849 unsigned DestReg, unsigned SrcReg, 1850 bool KillSrc) const { 1851 // First deal with the normal symmetric copies. 1852 unsigned Opc = 0; 1853 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 1854 Opc = X86::MOV64rr; 1855 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 1856 Opc = X86::MOV32rr; 1857 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 1858 Opc = X86::MOV16rr; 1859 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 1860 // Copying to or from a physical H register on x86-64 requires a NOREX 1861 // move. Otherwise use a normal move. 1862 if ((isHReg(DestReg) || isHReg(SrcReg)) && 1863 TM.getSubtarget<X86Subtarget>().is64Bit()) 1864 Opc = X86::MOV8rr_NOREX; 1865 else 1866 Opc = X86::MOV8rr; 1867 } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 1868 Opc = X86::MOVAPSrr; 1869 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 1870 Opc = X86::MMX_MOVQ64rr; 1871 1872 if (Opc) { 1873 BuildMI(MBB, MI, DL, get(Opc), DestReg) 1874 .addReg(SrcReg, getKillRegState(KillSrc)); 1875 return; 1876 } 1877 1878 // Moving EFLAGS to / from another register requires a push and a pop. 1879 if (SrcReg == X86::EFLAGS) { 1880 if (X86::GR64RegClass.contains(DestReg)) { 1881 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 1882 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 1883 return; 1884 } else if (X86::GR32RegClass.contains(DestReg)) { 1885 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 1886 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 1887 return; 1888 } 1889 } 1890 if (DestReg == X86::EFLAGS) { 1891 if (X86::GR64RegClass.contains(SrcReg)) { 1892 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 1893 .addReg(SrcReg, getKillRegState(KillSrc)); 1894 BuildMI(MBB, MI, DL, get(X86::POPF64)); 1895 return; 1896 } else if (X86::GR32RegClass.contains(SrcReg)) { 1897 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 1898 .addReg(SrcReg, getKillRegState(KillSrc)); 1899 BuildMI(MBB, MI, DL, get(X86::POPF32)); 1900 return; 1901 } 1902 } 1903 1904 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 1905 << " to " << RI.getName(DestReg) << '\n'); 1906 llvm_unreachable("Cannot emit physreg copy instruction"); 1907} 1908 1909static unsigned getLoadStoreRegOpcode(unsigned Reg, 1910 const TargetRegisterClass *RC, 1911 bool isStackAligned, 1912 const TargetMachine &TM, 1913 bool load) { 1914 switch (RC->getID()) { 1915 default: 1916 llvm_unreachable("Unknown regclass"); 1917 case X86::GR64RegClassID: 1918 case X86::GR64_NOSPRegClassID: 1919 return load ? X86::MOV64rm : X86::MOV64mr; 1920 case X86::GR32RegClassID: 1921 case X86::GR32_NOSPRegClassID: 1922 case X86::GR32_ADRegClassID: 1923 return load ? X86::MOV32rm : X86::MOV32mr; 1924 case X86::GR16RegClassID: 1925 return load ? X86::MOV16rm : X86::MOV16mr; 1926 case X86::GR8RegClassID: 1927 // Copying to or from a physical H register on x86-64 requires a NOREX 1928 // move. Otherwise use a normal move. 1929 if (isHReg(Reg) && 1930 TM.getSubtarget<X86Subtarget>().is64Bit()) 1931 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 1932 else 1933 return load ? X86::MOV8rm : X86::MOV8mr; 1934 case X86::GR64_ABCDRegClassID: 1935 return load ? X86::MOV64rm : X86::MOV64mr; 1936 case X86::GR32_ABCDRegClassID: 1937 return load ? X86::MOV32rm : X86::MOV32mr; 1938 case X86::GR16_ABCDRegClassID: 1939 return load ? X86::MOV16rm : X86::MOV16mr; 1940 case X86::GR8_ABCD_LRegClassID: 1941 return load ? X86::MOV8rm :X86::MOV8mr; 1942 case X86::GR8_ABCD_HRegClassID: 1943 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 1944 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 1945 else 1946 return load ? X86::MOV8rm : X86::MOV8mr; 1947 case X86::GR64_NOREXRegClassID: 1948 case X86::GR64_NOREX_NOSPRegClassID: 1949 return load ? X86::MOV64rm : X86::MOV64mr; 1950 case X86::GR32_NOREXRegClassID: 1951 return load ? X86::MOV32rm : X86::MOV32mr; 1952 case X86::GR16_NOREXRegClassID: 1953 return load ? X86::MOV16rm : X86::MOV16mr; 1954 case X86::GR8_NOREXRegClassID: 1955 return load ? X86::MOV8rm : X86::MOV8mr; 1956 case X86::GR64_TCRegClassID: 1957 return load ? X86::MOV64rm_TC : X86::MOV64mr_TC; 1958 case X86::GR32_TCRegClassID: 1959 return load ? X86::MOV32rm_TC : X86::MOV32mr_TC; 1960 case X86::RFP80RegClassID: 1961 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 1962 case X86::RFP64RegClassID: 1963 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 1964 case X86::RFP32RegClassID: 1965 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 1966 case X86::FR32RegClassID: 1967 return load ? X86::MOVSSrm : X86::MOVSSmr; 1968 case X86::FR64RegClassID: 1969 return load ? X86::MOVSDrm : X86::MOVSDmr; 1970 case X86::VR128RegClassID: 1971 // If stack is realigned we can use aligned stores. 1972 if (isStackAligned) 1973 return load ? X86::MOVAPSrm : X86::MOVAPSmr; 1974 else 1975 return load ? X86::MOVUPSrm : X86::MOVUPSmr; 1976 case X86::VR64RegClassID: 1977 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 1978 } 1979} 1980 1981static unsigned getStoreRegOpcode(unsigned SrcReg, 1982 const TargetRegisterClass *RC, 1983 bool isStackAligned, 1984 TargetMachine &TM) { 1985 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 1986} 1987 1988 1989static unsigned getLoadRegOpcode(unsigned DestReg, 1990 const TargetRegisterClass *RC, 1991 bool isStackAligned, 1992 const TargetMachine &TM) { 1993 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 1994} 1995 1996void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 1997 MachineBasicBlock::iterator MI, 1998 unsigned SrcReg, bool isKill, int FrameIdx, 1999 const TargetRegisterClass *RC, 2000 const TargetRegisterInfo *TRI) const { 2001 const MachineFunction &MF = *MBB.getParent(); 2002 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 2003 "Stack slot too small for store"); 2004 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2005 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2006 DebugLoc DL = MBB.findDebugLoc(MI); 2007 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2008 .addReg(SrcReg, getKillRegState(isKill)); 2009} 2010 2011void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2012 bool isKill, 2013 SmallVectorImpl<MachineOperand> &Addr, 2014 const TargetRegisterClass *RC, 2015 MachineInstr::mmo_iterator MMOBegin, 2016 MachineInstr::mmo_iterator MMOEnd, 2017 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2018 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; 2019 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2020 DebugLoc DL; 2021 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2022 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2023 MIB.addOperand(Addr[i]); 2024 MIB.addReg(SrcReg, getKillRegState(isKill)); 2025 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2026 NewMIs.push_back(MIB); 2027} 2028 2029 2030void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2031 MachineBasicBlock::iterator MI, 2032 unsigned DestReg, int FrameIdx, 2033 const TargetRegisterClass *RC, 2034 const TargetRegisterInfo *TRI) const { 2035 const MachineFunction &MF = *MBB.getParent(); 2036 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2037 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2038 DebugLoc DL = MBB.findDebugLoc(MI); 2039 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2040} 2041 2042void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2043 SmallVectorImpl<MachineOperand> &Addr, 2044 const TargetRegisterClass *RC, 2045 MachineInstr::mmo_iterator MMOBegin, 2046 MachineInstr::mmo_iterator MMOEnd, 2047 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2048 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; 2049 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2050 DebugLoc DL; 2051 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 2052 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2053 MIB.addOperand(Addr[i]); 2054 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2055 NewMIs.push_back(MIB); 2056} 2057 2058bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 2059 MachineBasicBlock::iterator MI, 2060 const std::vector<CalleeSavedInfo> &CSI, 2061 const TargetRegisterInfo *TRI) const { 2062 if (CSI.empty()) 2063 return false; 2064 2065 DebugLoc DL = MBB.findDebugLoc(MI); 2066 2067 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2068 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2069 unsigned SlotSize = is64Bit ? 8 : 4; 2070 2071 MachineFunction &MF = *MBB.getParent(); 2072 unsigned FPReg = RI.getFrameRegister(MF); 2073 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 2074 unsigned CalleeFrameSize = 0; 2075 2076 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 2077 for (unsigned i = CSI.size(); i != 0; --i) { 2078 unsigned Reg = CSI[i-1].getReg(); 2079 // Add the callee-saved register as live-in. It's killed at the spill. 2080 MBB.addLiveIn(Reg); 2081 if (Reg == FPReg) 2082 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 2083 continue; 2084 if (!X86::VR128RegClass.contains(Reg) && !isWin64) { 2085 CalleeFrameSize += SlotSize; 2086 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill); 2087 } else { 2088 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 2089 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), 2090 RC, &RI); 2091 } 2092 } 2093 2094 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 2095 return true; 2096} 2097 2098bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 2099 MachineBasicBlock::iterator MI, 2100 const std::vector<CalleeSavedInfo> &CSI, 2101 const TargetRegisterInfo *TRI) const { 2102 if (CSI.empty()) 2103 return false; 2104 2105 DebugLoc DL = MBB.findDebugLoc(MI); 2106 2107 MachineFunction &MF = *MBB.getParent(); 2108 unsigned FPReg = RI.getFrameRegister(MF); 2109 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2110 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2111 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 2112 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2113 unsigned Reg = CSI[i].getReg(); 2114 if (Reg == FPReg) 2115 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 2116 continue; 2117 if (!X86::VR128RegClass.contains(Reg) && !isWin64) { 2118 BuildMI(MBB, MI, DL, get(Opc), Reg); 2119 } else { 2120 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 2121 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 2122 RC, &RI); 2123 } 2124 } 2125 return true; 2126} 2127 2128MachineInstr* 2129X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 2130 int FrameIx, uint64_t Offset, 2131 const MDNode *MDPtr, 2132 DebugLoc DL) const { 2133 X86AddressMode AM; 2134 AM.BaseType = X86AddressMode::FrameIndexBase; 2135 AM.Base.FrameIndex = FrameIx; 2136 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 2137 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 2138 return &*MIB; 2139} 2140 2141static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 2142 const SmallVectorImpl<MachineOperand> &MOs, 2143 MachineInstr *MI, 2144 const TargetInstrInfo &TII) { 2145 // Create the base instruction with the memory operand as the first part. 2146 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2147 MI->getDebugLoc(), true); 2148 MachineInstrBuilder MIB(NewMI); 2149 unsigned NumAddrOps = MOs.size(); 2150 for (unsigned i = 0; i != NumAddrOps; ++i) 2151 MIB.addOperand(MOs[i]); 2152 if (NumAddrOps < 4) // FrameIndex only 2153 addOffset(MIB, 0); 2154 2155 // Loop over the rest of the ri operands, converting them over. 2156 unsigned NumOps = MI->getDesc().getNumOperands()-2; 2157 for (unsigned i = 0; i != NumOps; ++i) { 2158 MachineOperand &MO = MI->getOperand(i+2); 2159 MIB.addOperand(MO); 2160 } 2161 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 2162 MachineOperand &MO = MI->getOperand(i); 2163 MIB.addOperand(MO); 2164 } 2165 return MIB; 2166} 2167 2168static MachineInstr *FuseInst(MachineFunction &MF, 2169 unsigned Opcode, unsigned OpNo, 2170 const SmallVectorImpl<MachineOperand> &MOs, 2171 MachineInstr *MI, const TargetInstrInfo &TII) { 2172 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2173 MI->getDebugLoc(), true); 2174 MachineInstrBuilder MIB(NewMI); 2175 2176 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2177 MachineOperand &MO = MI->getOperand(i); 2178 if (i == OpNo) { 2179 assert(MO.isReg() && "Expected to fold into reg operand!"); 2180 unsigned NumAddrOps = MOs.size(); 2181 for (unsigned i = 0; i != NumAddrOps; ++i) 2182 MIB.addOperand(MOs[i]); 2183 if (NumAddrOps < 4) // FrameIndex only 2184 addOffset(MIB, 0); 2185 } else { 2186 MIB.addOperand(MO); 2187 } 2188 } 2189 return MIB; 2190} 2191 2192static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 2193 const SmallVectorImpl<MachineOperand> &MOs, 2194 MachineInstr *MI) { 2195 MachineFunction &MF = *MI->getParent()->getParent(); 2196 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 2197 2198 unsigned NumAddrOps = MOs.size(); 2199 for (unsigned i = 0; i != NumAddrOps; ++i) 2200 MIB.addOperand(MOs[i]); 2201 if (NumAddrOps < 4) // FrameIndex only 2202 addOffset(MIB, 0); 2203 return MIB.addImm(0); 2204} 2205 2206MachineInstr* 2207X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2208 MachineInstr *MI, unsigned i, 2209 const SmallVectorImpl<MachineOperand> &MOs, 2210 unsigned Size, unsigned Align) const { 2211 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2212 bool isTwoAddrFold = false; 2213 unsigned NumOps = MI->getDesc().getNumOperands(); 2214 bool isTwoAddr = NumOps > 1 && 2215 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2216 2217 MachineInstr *NewMI = NULL; 2218 // Folding a memory location into the two-address part of a two-address 2219 // instruction is different than folding it other places. It requires 2220 // replacing the *two* registers with the memory location. 2221 if (isTwoAddr && NumOps >= 2 && i < 2 && 2222 MI->getOperand(0).isReg() && 2223 MI->getOperand(1).isReg() && 2224 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2225 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2226 isTwoAddrFold = true; 2227 } else if (i == 0) { // If operand 0 2228 if (MI->getOpcode() == X86::MOV64r0) 2229 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2230 else if (MI->getOpcode() == X86::MOV32r0) 2231 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2232 else if (MI->getOpcode() == X86::MOV16r0) 2233 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2234 else if (MI->getOpcode() == X86::MOV8r0) 2235 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2236 if (NewMI) 2237 return NewMI; 2238 2239 OpcodeTablePtr = &RegOp2MemOpTable0; 2240 } else if (i == 1) { 2241 OpcodeTablePtr = &RegOp2MemOpTable1; 2242 } else if (i == 2) { 2243 OpcodeTablePtr = &RegOp2MemOpTable2; 2244 } 2245 2246 // If table selected... 2247 if (OpcodeTablePtr) { 2248 // Find the Opcode to fuse 2249 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2250 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2251 if (I != OpcodeTablePtr->end()) { 2252 unsigned Opcode = I->second.first; 2253 unsigned MinAlign = I->second.second; 2254 if (Align < MinAlign) 2255 return NULL; 2256 bool NarrowToMOV32rm = false; 2257 if (Size) { 2258 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); 2259 if (Size < RCSize) { 2260 // Check if it's safe to fold the load. If the size of the object is 2261 // narrower than the load width, then it's not. 2262 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 2263 return NULL; 2264 // If this is a 64-bit load, but the spill slot is 32, then we can do 2265 // a 32-bit load which is implicitly zero-extended. This likely is due 2266 // to liveintervalanalysis remat'ing a load from stack slot. 2267 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 2268 return NULL; 2269 Opcode = X86::MOV32rm; 2270 NarrowToMOV32rm = true; 2271 } 2272 } 2273 2274 if (isTwoAddrFold) 2275 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 2276 else 2277 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 2278 2279 if (NarrowToMOV32rm) { 2280 // If this is the special case where we use a MOV32rm to load a 32-bit 2281 // value and zero-extend the top bits. Change the destination register 2282 // to a 32-bit one. 2283 unsigned DstReg = NewMI->getOperand(0).getReg(); 2284 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 2285 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 2286 X86::sub_32bit)); 2287 else 2288 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 2289 } 2290 return NewMI; 2291 } 2292 } 2293 2294 // No fusion 2295 if (PrintFailedFusing && !MI->isCopy()) 2296 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 2297 return NULL; 2298} 2299 2300 2301MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2302 MachineInstr *MI, 2303 const SmallVectorImpl<unsigned> &Ops, 2304 int FrameIndex) const { 2305 // Check switch flag 2306 if (NoFusing) return NULL; 2307 2308 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2309 switch (MI->getOpcode()) { 2310 case X86::CVTSD2SSrr: 2311 case X86::Int_CVTSD2SSrr: 2312 case X86::CVTSS2SDrr: 2313 case X86::Int_CVTSS2SDrr: 2314 case X86::RCPSSr: 2315 case X86::RCPSSr_Int: 2316 case X86::ROUNDSDr_Int: 2317 case X86::ROUNDSSr_Int: 2318 case X86::RSQRTSSr: 2319 case X86::RSQRTSSr_Int: 2320 case X86::SQRTSSr: 2321 case X86::SQRTSSr_Int: 2322 return 0; 2323 } 2324 2325 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2326 unsigned Size = MFI->getObjectSize(FrameIndex); 2327 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2328 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2329 unsigned NewOpc = 0; 2330 unsigned RCSize = 0; 2331 switch (MI->getOpcode()) { 2332 default: return NULL; 2333 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 2334 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 2335 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 2336 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 2337 } 2338 // Check if it's safe to fold the load. If the size of the object is 2339 // narrower than the load width, then it's not. 2340 if (Size < RCSize) 2341 return NULL; 2342 // Change to CMPXXri r, 0 first. 2343 MI->setDesc(get(NewOpc)); 2344 MI->getOperand(1).ChangeToImmediate(0); 2345 } else if (Ops.size() != 1) 2346 return NULL; 2347 2348 SmallVector<MachineOperand,4> MOs; 2349 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2350 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 2351} 2352 2353MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2354 MachineInstr *MI, 2355 const SmallVectorImpl<unsigned> &Ops, 2356 MachineInstr *LoadMI) const { 2357 // Check switch flag 2358 if (NoFusing) return NULL; 2359 2360 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2361 switch (MI->getOpcode()) { 2362 case X86::CVTSD2SSrr: 2363 case X86::Int_CVTSD2SSrr: 2364 case X86::CVTSS2SDrr: 2365 case X86::Int_CVTSS2SDrr: 2366 case X86::RCPSSr: 2367 case X86::RCPSSr_Int: 2368 case X86::ROUNDSDr_Int: 2369 case X86::ROUNDSSr_Int: 2370 case X86::RSQRTSSr: 2371 case X86::RSQRTSSr_Int: 2372 case X86::SQRTSSr: 2373 case X86::SQRTSSr_Int: 2374 return 0; 2375 } 2376 2377 // Determine the alignment of the load. 2378 unsigned Alignment = 0; 2379 if (LoadMI->hasOneMemOperand()) 2380 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 2381 else 2382 switch (LoadMI->getOpcode()) { 2383 case X86::V_SET0PS: 2384 case X86::V_SET0PD: 2385 case X86::V_SET0PI: 2386 case X86::V_SETALLONES: 2387 Alignment = 16; 2388 break; 2389 case X86::FsFLD0SD: 2390 Alignment = 8; 2391 break; 2392 case X86::FsFLD0SS: 2393 Alignment = 4; 2394 break; 2395 default: 2396 llvm_unreachable("Don't know how to fold this instruction!"); 2397 } 2398 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2399 unsigned NewOpc = 0; 2400 switch (MI->getOpcode()) { 2401 default: return NULL; 2402 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2403 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 2404 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 2405 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 2406 } 2407 // Change to CMPXXri r, 0 first. 2408 MI->setDesc(get(NewOpc)); 2409 MI->getOperand(1).ChangeToImmediate(0); 2410 } else if (Ops.size() != 1) 2411 return NULL; 2412 2413 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 2414 switch (LoadMI->getOpcode()) { 2415 case X86::V_SET0PS: 2416 case X86::V_SET0PD: 2417 case X86::V_SET0PI: 2418 case X86::V_SETALLONES: 2419 case X86::FsFLD0SD: 2420 case X86::FsFLD0SS: { 2421 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure. 2422 // Create a constant-pool entry and operands to load from it. 2423 2424 // Medium and large mode can't fold loads this way. 2425 if (TM.getCodeModel() != CodeModel::Small && 2426 TM.getCodeModel() != CodeModel::Kernel) 2427 return NULL; 2428 2429 // x86-32 PIC requires a PIC base register for constant pools. 2430 unsigned PICBase = 0; 2431 if (TM.getRelocationModel() == Reloc::PIC_) { 2432 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2433 PICBase = X86::RIP; 2434 else 2435 // FIXME: PICBase = getGlobalBaseReg(&MF); 2436 // This doesn't work for several reasons. 2437 // 1. GlobalBaseReg may have been spilled. 2438 // 2. It may not be live at MI. 2439 return NULL; 2440 } 2441 2442 // Create a constant-pool entry. 2443 MachineConstantPool &MCP = *MF.getConstantPool(); 2444 const Type *Ty; 2445 if (LoadMI->getOpcode() == X86::FsFLD0SS) 2446 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 2447 else if (LoadMI->getOpcode() == X86::FsFLD0SD) 2448 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 2449 else 2450 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 2451 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ? 2452 Constant::getAllOnesValue(Ty) : 2453 Constant::getNullValue(Ty); 2454 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 2455 2456 // Create operands to load from the constant pool entry. 2457 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2458 MOs.push_back(MachineOperand::CreateImm(1)); 2459 MOs.push_back(MachineOperand::CreateReg(0, false)); 2460 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2461 MOs.push_back(MachineOperand::CreateReg(0, false)); 2462 break; 2463 } 2464 default: { 2465 // Folding a normal load. Just copy the load's address operands. 2466 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2467 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 2468 MOs.push_back(LoadMI->getOperand(i)); 2469 break; 2470 } 2471 } 2472 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 2473} 2474 2475 2476bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2477 const SmallVectorImpl<unsigned> &Ops) const { 2478 // Check switch flag 2479 if (NoFusing) return 0; 2480 2481 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2482 switch (MI->getOpcode()) { 2483 default: return false; 2484 case X86::TEST8rr: 2485 case X86::TEST16rr: 2486 case X86::TEST32rr: 2487 case X86::TEST64rr: 2488 return true; 2489 } 2490 } 2491 2492 if (Ops.size() != 1) 2493 return false; 2494 2495 unsigned OpNum = Ops[0]; 2496 unsigned Opc = MI->getOpcode(); 2497 unsigned NumOps = MI->getDesc().getNumOperands(); 2498 bool isTwoAddr = NumOps > 1 && 2499 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2500 2501 // Folding a memory location into the two-address part of a two-address 2502 // instruction is different than folding it other places. It requires 2503 // replacing the *two* registers with the memory location. 2504 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2505 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2506 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2507 } else if (OpNum == 0) { // If operand 0 2508 switch (Opc) { 2509 case X86::MOV8r0: 2510 case X86::MOV16r0: 2511 case X86::MOV32r0: 2512 case X86::MOV64r0: 2513 return true; 2514 default: break; 2515 } 2516 OpcodeTablePtr = &RegOp2MemOpTable0; 2517 } else if (OpNum == 1) { 2518 OpcodeTablePtr = &RegOp2MemOpTable1; 2519 } else if (OpNum == 2) { 2520 OpcodeTablePtr = &RegOp2MemOpTable2; 2521 } 2522 2523 if (OpcodeTablePtr) { 2524 // Find the Opcode to fuse 2525 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2526 OpcodeTablePtr->find((unsigned*)Opc); 2527 if (I != OpcodeTablePtr->end()) 2528 return true; 2529 } 2530 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); 2531} 2532 2533bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2534 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2535 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2536 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2537 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2538 if (I == MemOp2RegOpTable.end()) 2539 return false; 2540 unsigned Opc = I->second.first; 2541 unsigned Index = I->second.second & 0xf; 2542 bool FoldedLoad = I->second.second & (1 << 4); 2543 bool FoldedStore = I->second.second & (1 << 5); 2544 if (UnfoldLoad && !FoldedLoad) 2545 return false; 2546 UnfoldLoad &= FoldedLoad; 2547 if (UnfoldStore && !FoldedStore) 2548 return false; 2549 UnfoldStore &= FoldedStore; 2550 2551 const TargetInstrDesc &TID = get(Opc); 2552 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2553 const TargetRegisterClass *RC = TOI.getRegClass(&RI); 2554 if (!MI->hasOneMemOperand() && 2555 RC == &X86::VR128RegClass && 2556 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2557 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 2558 // conservatively assume the address is unaligned. That's bad for 2559 // performance. 2560 return false; 2561 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 2562 SmallVector<MachineOperand,2> BeforeOps; 2563 SmallVector<MachineOperand,2> AfterOps; 2564 SmallVector<MachineOperand,4> ImpOps; 2565 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2566 MachineOperand &Op = MI->getOperand(i); 2567 if (i >= Index && i < Index + X86::AddrNumOperands) 2568 AddrOps.push_back(Op); 2569 else if (Op.isReg() && Op.isImplicit()) 2570 ImpOps.push_back(Op); 2571 else if (i < Index) 2572 BeforeOps.push_back(Op); 2573 else if (i > Index) 2574 AfterOps.push_back(Op); 2575 } 2576 2577 // Emit the load instruction. 2578 if (UnfoldLoad) { 2579 std::pair<MachineInstr::mmo_iterator, 2580 MachineInstr::mmo_iterator> MMOs = 2581 MF.extractLoadMemRefs(MI->memoperands_begin(), 2582 MI->memoperands_end()); 2583 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 2584 if (UnfoldStore) { 2585 // Address operands cannot be marked isKill. 2586 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 2587 MachineOperand &MO = NewMIs[0]->getOperand(i); 2588 if (MO.isReg()) 2589 MO.setIsKill(false); 2590 } 2591 } 2592 } 2593 2594 // Emit the data processing instruction. 2595 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); 2596 MachineInstrBuilder MIB(DataMI); 2597 2598 if (FoldedStore) 2599 MIB.addReg(Reg, RegState::Define); 2600 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2601 MIB.addOperand(BeforeOps[i]); 2602 if (FoldedLoad) 2603 MIB.addReg(Reg); 2604 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2605 MIB.addOperand(AfterOps[i]); 2606 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2607 MachineOperand &MO = ImpOps[i]; 2608 MIB.addReg(MO.getReg(), 2609 getDefRegState(MO.isDef()) | 2610 RegState::Implicit | 2611 getKillRegState(MO.isKill()) | 2612 getDeadRegState(MO.isDead()) | 2613 getUndefRegState(MO.isUndef())); 2614 } 2615 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2616 unsigned NewOpc = 0; 2617 switch (DataMI->getOpcode()) { 2618 default: break; 2619 case X86::CMP64ri32: 2620 case X86::CMP64ri8: 2621 case X86::CMP32ri: 2622 case X86::CMP32ri8: 2623 case X86::CMP16ri: 2624 case X86::CMP16ri8: 2625 case X86::CMP8ri: { 2626 MachineOperand &MO0 = DataMI->getOperand(0); 2627 MachineOperand &MO1 = DataMI->getOperand(1); 2628 if (MO1.getImm() == 0) { 2629 switch (DataMI->getOpcode()) { 2630 default: break; 2631 case X86::CMP64ri8: 2632 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2633 case X86::CMP32ri8: 2634 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2635 case X86::CMP16ri8: 2636 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2637 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2638 } 2639 DataMI->setDesc(get(NewOpc)); 2640 MO1.ChangeToRegister(MO0.getReg(), false); 2641 } 2642 } 2643 } 2644 NewMIs.push_back(DataMI); 2645 2646 // Emit the store instruction. 2647 if (UnfoldStore) { 2648 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI); 2649 std::pair<MachineInstr::mmo_iterator, 2650 MachineInstr::mmo_iterator> MMOs = 2651 MF.extractStoreMemRefs(MI->memoperands_begin(), 2652 MI->memoperands_end()); 2653 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 2654 } 2655 2656 return true; 2657} 2658 2659bool 2660X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2661 SmallVectorImpl<SDNode*> &NewNodes) const { 2662 if (!N->isMachineOpcode()) 2663 return false; 2664 2665 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2666 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2667 if (I == MemOp2RegOpTable.end()) 2668 return false; 2669 unsigned Opc = I->second.first; 2670 unsigned Index = I->second.second & 0xf; 2671 bool FoldedLoad = I->second.second & (1 << 4); 2672 bool FoldedStore = I->second.second & (1 << 5); 2673 const TargetInstrDesc &TID = get(Opc); 2674 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI); 2675 unsigned NumDefs = TID.NumDefs; 2676 std::vector<SDValue> AddrOps; 2677 std::vector<SDValue> BeforeOps; 2678 std::vector<SDValue> AfterOps; 2679 DebugLoc dl = N->getDebugLoc(); 2680 unsigned NumOps = N->getNumOperands(); 2681 for (unsigned i = 0; i != NumOps-1; ++i) { 2682 SDValue Op = N->getOperand(i); 2683 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 2684 AddrOps.push_back(Op); 2685 else if (i < Index-NumDefs) 2686 BeforeOps.push_back(Op); 2687 else if (i > Index-NumDefs) 2688 AfterOps.push_back(Op); 2689 } 2690 SDValue Chain = N->getOperand(NumOps-1); 2691 AddrOps.push_back(Chain); 2692 2693 // Emit the load instruction. 2694 SDNode *Load = 0; 2695 MachineFunction &MF = DAG.getMachineFunction(); 2696 if (FoldedLoad) { 2697 EVT VT = *RC->vt_begin(); 2698 std::pair<MachineInstr::mmo_iterator, 2699 MachineInstr::mmo_iterator> MMOs = 2700 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2701 cast<MachineSDNode>(N)->memoperands_end()); 2702 if (!(*MMOs.first) && 2703 RC == &X86::VR128RegClass && 2704 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2705 // Do not introduce a slow unaligned load. 2706 return false; 2707 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2708 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 2709 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 2710 NewNodes.push_back(Load); 2711 2712 // Preserve memory reference information. 2713 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2714 } 2715 2716 // Emit the data processing instruction. 2717 std::vector<EVT> VTs; 2718 const TargetRegisterClass *DstRC = 0; 2719 if (TID.getNumDefs() > 0) { 2720 DstRC = TID.OpInfo[0].getRegClass(&RI); 2721 VTs.push_back(*DstRC->vt_begin()); 2722 } 2723 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2724 EVT VT = N->getValueType(i); 2725 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2726 VTs.push_back(VT); 2727 } 2728 if (Load) 2729 BeforeOps.push_back(SDValue(Load, 0)); 2730 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2731 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 2732 BeforeOps.size()); 2733 NewNodes.push_back(NewNode); 2734 2735 // Emit the store instruction. 2736 if (FoldedStore) { 2737 AddrOps.pop_back(); 2738 AddrOps.push_back(SDValue(NewNode, 0)); 2739 AddrOps.push_back(Chain); 2740 std::pair<MachineInstr::mmo_iterator, 2741 MachineInstr::mmo_iterator> MMOs = 2742 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2743 cast<MachineSDNode>(N)->memoperands_end()); 2744 if (!(*MMOs.first) && 2745 RC == &X86::VR128RegClass && 2746 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2747 // Do not introduce a slow unaligned store. 2748 return false; 2749 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2750 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 2751 isAligned, TM), 2752 dl, MVT::Other, 2753 &AddrOps[0], AddrOps.size()); 2754 NewNodes.push_back(Store); 2755 2756 // Preserve memory reference information. 2757 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2758 } 2759 2760 return true; 2761} 2762 2763unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2764 bool UnfoldLoad, bool UnfoldStore, 2765 unsigned *LoadRegIndex) const { 2766 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2767 MemOp2RegOpTable.find((unsigned*)Opc); 2768 if (I == MemOp2RegOpTable.end()) 2769 return 0; 2770 bool FoldedLoad = I->second.second & (1 << 4); 2771 bool FoldedStore = I->second.second & (1 << 5); 2772 if (UnfoldLoad && !FoldedLoad) 2773 return 0; 2774 if (UnfoldStore && !FoldedStore) 2775 return 0; 2776 if (LoadRegIndex) 2777 *LoadRegIndex = I->second.second & 0xf; 2778 return I->second.first; 2779} 2780 2781bool 2782X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 2783 int64_t &Offset1, int64_t &Offset2) const { 2784 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 2785 return false; 2786 unsigned Opc1 = Load1->getMachineOpcode(); 2787 unsigned Opc2 = Load2->getMachineOpcode(); 2788 switch (Opc1) { 2789 default: return false; 2790 case X86::MOV8rm: 2791 case X86::MOV16rm: 2792 case X86::MOV32rm: 2793 case X86::MOV64rm: 2794 case X86::LD_Fp32m: 2795 case X86::LD_Fp64m: 2796 case X86::LD_Fp80m: 2797 case X86::MOVSSrm: 2798 case X86::MOVSDrm: 2799 case X86::MMX_MOVD64rm: 2800 case X86::MMX_MOVQ64rm: 2801 case X86::FsMOVAPSrm: 2802 case X86::FsMOVAPDrm: 2803 case X86::MOVAPSrm: 2804 case X86::MOVUPSrm: 2805 case X86::MOVUPSrm_Int: 2806 case X86::MOVAPDrm: 2807 case X86::MOVDQArm: 2808 case X86::MOVDQUrm: 2809 case X86::MOVDQUrm_Int: 2810 break; 2811 } 2812 switch (Opc2) { 2813 default: return false; 2814 case X86::MOV8rm: 2815 case X86::MOV16rm: 2816 case X86::MOV32rm: 2817 case X86::MOV64rm: 2818 case X86::LD_Fp32m: 2819 case X86::LD_Fp64m: 2820 case X86::LD_Fp80m: 2821 case X86::MOVSSrm: 2822 case X86::MOVSDrm: 2823 case X86::MMX_MOVD64rm: 2824 case X86::MMX_MOVQ64rm: 2825 case X86::FsMOVAPSrm: 2826 case X86::FsMOVAPDrm: 2827 case X86::MOVAPSrm: 2828 case X86::MOVUPSrm: 2829 case X86::MOVUPSrm_Int: 2830 case X86::MOVAPDrm: 2831 case X86::MOVDQArm: 2832 case X86::MOVDQUrm: 2833 case X86::MOVDQUrm_Int: 2834 break; 2835 } 2836 2837 // Check if chain operands and base addresses match. 2838 if (Load1->getOperand(0) != Load2->getOperand(0) || 2839 Load1->getOperand(5) != Load2->getOperand(5)) 2840 return false; 2841 // Segment operands should match as well. 2842 if (Load1->getOperand(4) != Load2->getOperand(4)) 2843 return false; 2844 // Scale should be 1, Index should be Reg0. 2845 if (Load1->getOperand(1) == Load2->getOperand(1) && 2846 Load1->getOperand(2) == Load2->getOperand(2)) { 2847 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 2848 return false; 2849 2850 // Now let's examine the displacements. 2851 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 2852 isa<ConstantSDNode>(Load2->getOperand(3))) { 2853 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 2854 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 2855 return true; 2856 } 2857 } 2858 return false; 2859} 2860 2861bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 2862 int64_t Offset1, int64_t Offset2, 2863 unsigned NumLoads) const { 2864 assert(Offset2 > Offset1); 2865 if ((Offset2 - Offset1) / 8 > 64) 2866 return false; 2867 2868 unsigned Opc1 = Load1->getMachineOpcode(); 2869 unsigned Opc2 = Load2->getMachineOpcode(); 2870 if (Opc1 != Opc2) 2871 return false; // FIXME: overly conservative? 2872 2873 switch (Opc1) { 2874 default: break; 2875 case X86::LD_Fp32m: 2876 case X86::LD_Fp64m: 2877 case X86::LD_Fp80m: 2878 case X86::MMX_MOVD64rm: 2879 case X86::MMX_MOVQ64rm: 2880 return false; 2881 } 2882 2883 EVT VT = Load1->getValueType(0); 2884 switch (VT.getSimpleVT().SimpleTy) { 2885 default: 2886 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 2887 // have 16 of them to play with. 2888 if (TM.getSubtargetImpl()->is64Bit()) { 2889 if (NumLoads >= 3) 2890 return false; 2891 } else if (NumLoads) { 2892 return false; 2893 } 2894 break; 2895 case MVT::i8: 2896 case MVT::i16: 2897 case MVT::i32: 2898 case MVT::i64: 2899 case MVT::f32: 2900 case MVT::f64: 2901 if (NumLoads) 2902 return false; 2903 break; 2904 } 2905 2906 return true; 2907} 2908 2909 2910bool X86InstrInfo:: 2911ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2912 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 2913 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 2914 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 2915 return true; 2916 Cond[0].setImm(GetOppositeBranchCondition(CC)); 2917 return false; 2918} 2919 2920bool X86InstrInfo:: 2921isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 2922 // FIXME: Return false for x87 stack register classes for now. We can't 2923 // allow any loads of these registers before FpGet_ST0_80. 2924 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 2925 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 2926} 2927 2928 2929/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) 2930/// register? e.g. r8, xmm8, xmm13, etc. 2931bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) { 2932 switch (RegNo) { 2933 default: break; 2934 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 2935 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 2936 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 2937 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 2938 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 2939 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 2940 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 2941 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 2942 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 2943 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 2944 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 2945 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 2946 return true; 2947 } 2948 return false; 2949} 2950 2951/// getGlobalBaseReg - Return a virtual register initialized with the 2952/// the global base register value. Output instructions required to 2953/// initialize the register in the function entry block, if necessary. 2954/// 2955/// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 2956/// 2957unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 2958 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 2959 "X86-64 PIC uses RIP relative addressing"); 2960 2961 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 2962 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 2963 if (GlobalBaseReg != 0) 2964 return GlobalBaseReg; 2965 2966 // Create the register. The code to initialize it is inserted 2967 // later, by the CGBR pass (below). 2968 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 2969 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 2970 X86FI->setGlobalBaseReg(GlobalBaseReg); 2971 return GlobalBaseReg; 2972} 2973 2974// These are the replaceable SSE instructions. Some of these have Int variants 2975// that we don't include here. We don't want to replace instructions selected 2976// by intrinsics. 2977static const unsigned ReplaceableInstrs[][3] = { 2978 //PackedInt PackedSingle PackedDouble 2979 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 2980 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 2981 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 2982 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 2983 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 2984 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 2985 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 2986 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 2987 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 2988 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 2989 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 2990 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 2991 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI }, 2992 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 2993 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 2994}; 2995 2996// FIXME: Some shuffle and unpack instructions have equivalents in different 2997// domains, but they require a bit more work than just switching opcodes. 2998 2999static const unsigned *lookup(unsigned opcode, unsigned domain) { 3000 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 3001 if (ReplaceableInstrs[i][domain-1] == opcode) 3002 return ReplaceableInstrs[i]; 3003 return 0; 3004} 3005 3006std::pair<uint16_t, uint16_t> 3007X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const { 3008 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3009 return std::make_pair(domain, 3010 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0); 3011} 3012 3013void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const { 3014 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 3015 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3016 assert(dom && "Not an SSE instruction"); 3017 const unsigned *table = lookup(MI->getOpcode(), dom); 3018 assert(table && "Cannot change domain"); 3019 MI->setDesc(get(table[Domain-1])); 3020} 3021 3022/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 3023void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 3024 NopInst.setOpcode(X86::NOOP); 3025} 3026 3027namespace { 3028 /// CGBR - Create Global Base Reg pass. This initializes the PIC 3029 /// global base register for x86-32. 3030 struct CGBR : public MachineFunctionPass { 3031 static char ID; 3032 CGBR() : MachineFunctionPass(ID) {} 3033 3034 virtual bool runOnMachineFunction(MachineFunction &MF) { 3035 const X86TargetMachine *TM = 3036 static_cast<const X86TargetMachine *>(&MF.getTarget()); 3037 3038 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 3039 "X86-64 PIC uses RIP relative addressing"); 3040 3041 // Only emit a global base reg in PIC mode. 3042 if (TM->getRelocationModel() != Reloc::PIC_) 3043 return false; 3044 3045 // Insert the set of GlobalBaseReg into the first MBB of the function 3046 MachineBasicBlock &FirstMBB = MF.front(); 3047 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3048 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 3049 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3050 const X86InstrInfo *TII = TM->getInstrInfo(); 3051 3052 unsigned PC; 3053 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 3054 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3055 else 3056 PC = TII->getGlobalBaseReg(&MF); 3057 3058 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3059 // only used in JIT code emission as displacement to pc. 3060 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 3061 3062 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3063 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 3064 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3065 unsigned GlobalBaseReg = TII->getGlobalBaseReg(&MF); 3066 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 3067 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 3068 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 3069 X86II::MO_GOT_ABSOLUTE_ADDRESS); 3070 } 3071 3072 return true; 3073 } 3074 3075 virtual const char *getPassName() const { 3076 return "X86 PIC Global Base Reg Initialization"; 3077 } 3078 3079 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 3080 AU.setPreservesCFG(); 3081 MachineFunctionPass::getAnalysisUsage(AU); 3082 } 3083 }; 3084} 3085 3086char CGBR::ID = 0; 3087FunctionPass* 3088llvm::createGlobalBaseRegPass() { return new CGBR(); } 3089