X86InstrInfo.h revision 0d8db8e0a8492ab2d4bef725ec61b519471b97ec
11e60a9165dc4d6ce5650dacc026f2942696af920Chris Lattner//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 20e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 3856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// The LLVM Compiler Infrastructure 4856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 70e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 8856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//===----------------------------------------------------------------------===// 9726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 103501feab811c86c9659248a4875fc31a3165f84dChris Lattner// This file contains the X86 implementation of the TargetInstrInfo class. 11726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 12726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//===----------------------------------------------------------------------===// 13726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 14726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#ifndef X86INSTRUCTIONINFO_H 15726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#define X86INSTRUCTIONINFO_H 16726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 173501feab811c86c9659248a4875fc31a3165f84dChris Lattner#include "llvm/Target/TargetInstrInfo.h" 1852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray#include "X86.h" 19726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#include "X86RegisterInfo.h" 20d68a07650cdb2e18f18f362ba533459aa10e01b6Dan Gohman#include "llvm/ADT/DenseMap.h" 21726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 2325ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng class X86RegisterInfo; 24aa3c1410b427909da350f2b5e8d4ec3db62a3618Evan Cheng class X86TargetMachine; 25d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 267fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattnernamespace X86 { 277fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // X86 specific condition code. These correspond to X86_*_COND in 287fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // X86InstrInfo.td. They must be kept in synch. 297fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner enum CondCode { 307fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_A = 0, 317fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_AE = 1, 327fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_B = 2, 337fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_BE = 3, 347fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_E = 4, 357fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_G = 5, 367fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_GE = 6, 377fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_L = 7, 387fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_LE = 8, 397fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NE = 9, 407fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NO = 10, 417fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NP = 11, 427fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_NS = 12, 43653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman COND_O = 13, 44653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman COND_P = 14, 45653456c351d9bf908ebd982f6ae9df3449c5f34bDan Gohman COND_S = 15, 46279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman 47279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // Artificial condition codes. These are used by AnalyzeBranch 48279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // to indicate a block terminated with two conditional branches to 49279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 50279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // which can't be represented on x86 with a single condition. These 51279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman // are never used in MachineInstrs. 52279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman COND_NE_OR_P, 53279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman COND_NP_OR_E, 54279c22e6da2612f024b70e5509ffb0cad32f38b2Dan Gohman 557fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner COND_INVALID 567fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner }; 576634e26aa11b0e2eabde8b3b463bb943364f8d9dChristopher Lamb 587fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // Turn condition code into conditional branch opcode. 597fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner unsigned GetCondBranchFromCond(CondCode CC); 609cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner 619cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner /// GetOppositeBranchCondition - Return the inverse of the specified cond, 629cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner /// e.g. turning COND_E to COND_NE. 639cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner CondCode GetOppositeBranchCondition(X86::CondCode CC); 649cd68759178f9fe25c72253d338e78e414f1d770Chris Lattner 657fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner} 667fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner 679d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// X86II - This namespace holds all of the target specific flags that 689d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// instruction info tracks. 699d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// 709d17740295838f94120646ef619b2e187f2d71bdChris Lattnernamespace X86II { 713b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner /// Target Operand Flag enum. 723b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner enum TOF { 736aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 74ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner // X86 Specific MachineOperand flags. 75ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner 7601a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_NO_FLAG, 77ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner 78ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner /// relocation of: 8055e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// SYMBOL_LABEL + [. - PICBASELABEL] 8101a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOT_ABSOLUTE_ADDRESS, 82ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner 8355e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 8455e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// immediate should get the value of the symbol minus the PIC base label: 8555e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// SYMBOL_LABEL - PICBASELABEL 8601a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_PIC_BASE_OFFSET, 8755e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner 88b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOT - On a symbol operand this indicates that the immediate is the 89b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// offset to the GOT entry for the symbol name from the base of the GOT. 90b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 91b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See the X86-64 ELF ABI supplement for more details. 92b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @GOT 9301a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOT, 94b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner 95b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 96b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// the offset to the location of the symbol name from the base of the GOT. 97b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 98b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See the X86-64 ELF ABI supplement for more details. 9955e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner /// SYMBOL_LABEL @GOTOFF 10001a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOTOFF, 101b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner 102b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 103b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// offset to the GOT entry for the symbol name from the current code 104b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// location. 105b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 106b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See the X86-64 ELF ABI supplement for more details. 107b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @GOTPCREL 10801a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOTPCREL, 109b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner 110b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_PLT - On a symbol operand this indicates that the immediate is 111b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// offset to the PLT entry of symbol name from the current code location. 112b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 113b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See the X86-64 ELF ABI supplement for more details. 114b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @PLT 11501a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_PLT, 116b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner 117b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_TLSGD - On a symbol operand this indicates that the immediate is 118b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 119b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 120b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See 'ELF Handling for Thread-Local Storage' for more details. 121b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @TLSGD 12201a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_TLSGD, 123b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner 124b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 125b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 126b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 127b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See 'ELF Handling for Thread-Local Storage' for more details. 128b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @GOTTPOFF 12901a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_GOTTPOFF, 130b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner 131b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 132b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 133b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 134b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See 'ELF Handling for Thread-Local Storage' for more details. 135b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @INDNTPOFF 13601a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_INDNTPOFF, 137b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner 138b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_TPOFF - On a symbol operand this indicates that the immediate is 139b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 140b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 141b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See 'ELF Handling for Thread-Local Storage' for more details. 142b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @TPOFF 14301a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_TPOFF, 14455e7c827301da0e5e03b26835bff259c320b3bf7Chris Lattner 145b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 146b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// some TLS offset. 147b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// 148b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// See 'ELF Handling for Thread-Local Storage' for more details. 149b903bed0feaa35a2b5e404923db724a62b433787Chris Lattner /// SYMBOL_LABEL @NTPOFF 15001a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_NTPOFF, 151ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner 1524aa21aa6d13b8ea00eb0817e53f24e5416ed3038Chris Lattner /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 1534aa21aa6d13b8ea00eb0817e53f24e5416ed3038Chris Lattner /// reference is actually to the "__imp_FOO" symbol. This is used for 1544aa21aa6d13b8ea00eb0817e53f24e5416ed3038Chris Lattner /// dllimport linkage on windows. 15501a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DLLIMPORT, 1564aa21aa6d13b8ea00eb0817e53f24e5416ed3038Chris Lattner 15774e726e3270c99169cc90fb3c676eeaae273f48cChris Lattner /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 15874e726e3270c99169cc90fb3c676eeaae273f48cChris Lattner /// reference is actually to the "FOO$stub" symbol. This is used for calls 15974e726e3270c99169cc90fb3c676eeaae273f48cChris Lattner /// and jumps to external functions on Tiger and before. 16001a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DARWIN_STUB, 16174e726e3270c99169cc90fb3c676eeaae273f48cChris Lattner 16275cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 16375cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 16475cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 16501a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DARWIN_NONLAZY, 16675cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner 16775cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 16875cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 16975cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 17001a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DARWIN_NONLAZY_PIC_BASE, 17175cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner 17275cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 17375cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 17475cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 17575cdf27f48f0b81f778b6aa50efcefa0497a9daeChris Lattner /// stub. 17601a76ce8d910c0ffee89beaa3819d3448791950fDan Gohman MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE 177281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner }; 178281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner} 179281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner 1803b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner/// isGlobalStubReference - Return true if the specified TargetFlag operand is 181281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// a reference to a stub for a global, not the global itself. 1823b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattnerinline static bool isGlobalStubReference(unsigned char TargetFlag) { 1833b6b36d6f54e780a2947cb1b9efe4eed7c40dc11Chris Lattner switch (TargetFlag) { 184281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DLLIMPORT: // dllimport stub. 185281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_GOTPCREL: // rip-relative GOT reference. 186281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_GOT: // normal GOT reference. 187281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 188281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 189281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 190281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner return true; 191281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner default: 192281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner return false; 193281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner } 194281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner} 1957478ab8502a52815413d8b388898f719484ab1a9Chris Lattner 1967478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// isGlobalRelativeToPICBase - Return true if the specified global value 1977478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 1987478ab8502a52815413d8b388898f719484ab1a9Chris Lattner/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 1997478ab8502a52815413d8b388898f719484ab1a9Chris Lattnerinline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 2007478ab8502a52815413d8b388898f719484ab1a9Chris Lattner switch (TargetFlag) { 2017478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 2027478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_GOT: // isPICStyleGOT: other global. 2037478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 2047478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 2057478ab8502a52815413d8b388898f719484ab1a9Chris Lattner case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 2067478ab8502a52815413d8b388898f719484ab1a9Chris Lattner return true; 2077478ab8502a52815413d8b388898f719484ab1a9Chris Lattner default: 2087478ab8502a52815413d8b388898f719484ab1a9Chris Lattner return false; 2097478ab8502a52815413d8b388898f719484ab1a9Chris Lattner } 2107478ab8502a52815413d8b388898f719484ab1a9Chris Lattner} 211281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner 212281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// X86II - This namespace holds all of the target specific flags that 213281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// instruction info tracks. 214281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner/// 215281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattnernamespace X86II { 216281bada3b03b97dad0ac9890706a057ab31a5dd3Chris Lattner enum { 217ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner //===------------------------------------------------------------------===// 218ac5e887a6cf0a6182664d8c11beb0d2270272b02Chris Lattner // Instruction encodings. These are the standard/most common forms for X86 2196aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // instructions. 2206aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // 2216aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2224c299f5da1013cd36563a82f188c731b2758074dChris Lattner // PseudoFrm - This represents an instruction that is a pseudo instruction 2234c299f5da1013cd36563a82f188c731b2758074dChris Lattner // or one that has not been implemented yet. It is illegal to code generate 2244c299f5da1013cd36563a82f188c731b2758074dChris Lattner // it, but tolerated for intermediate implementation stages. 2254c299f5da1013cd36563a82f188c731b2758074dChris Lattner Pseudo = 0, 2264c299f5da1013cd36563a82f188c731b2758074dChris Lattner 2276aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// Raw - This form is for instructions that don't have any operands, so 2286aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// they are just a fixed opcode value, like 'leave'. 2294c299f5da1013cd36563a82f188c731b2758074dChris Lattner RawFrm = 1, 2300e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 2316aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// AddRegFrm - This form is used for instructions like 'push r32' that have 2326aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// their one register operand added to their opcode. 2334c299f5da1013cd36563a82f188c731b2758074dChris Lattner AddRegFrm = 2, 2346aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2356aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 2366aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is a register. 2376aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2384c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestReg = 3, 2396aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2406aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 2416aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is memory. 2426aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2434c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestMem = 4, 2446aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2456aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 2466aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is a register. 2476aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2484c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcReg = 5, 2496aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2506aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 2516aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is memory. 2526aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 2534c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcMem = 6, 2540e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 255169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos /// MRM[0-7][rm] - These forms are used to represent instructions that use 25685b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// a Mod/RM byte, and use the middle field to hold extended opcode 25785b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// information. In the intel manual these are represented as /0, /1, ... 25885b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// 25985b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 26085b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // First, instructions that operate on a register r/m operand... 261169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 262169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 26385b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 26485b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // Next, instructions that operate on a memory r/m operand... 265169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 266169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 2676aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2683c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // MRMInitReg - This form is used for instructions whose source and 2693c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // destinations are the same register. 2703c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng MRMInitReg = 32, 2710d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner 2720d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner //// MRM_C1 - A mod/rm byte of exactly 0xC1. 2730d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner MRM_C1 = 33, 2740d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner MRM_C8 = 34, 2750d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner MRM_C9 = 35, 2760d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner MRM_E8 = 36, 2770d8db8e0a8492ab2d4bef725ec61b519471b97ecChris Lattner MRM_F0 = 37, 2783c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng 2793c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng FormMask = 63, 2806aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 2816aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 2826aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Actual flags... 2836aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 28411e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // OpSize - Set if this instruction requires an operand size prefix (0x66), 28511e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // which most often indicates that the instruction operates on 16 bit data 28611e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // instead of 32 bit data. 2873c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng OpSize = 1 << 6, 2884c299f5da1013cd36563a82f188c731b2758074dChris Lattner 28925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // AsSize - Set if this instruction requires an operand size prefix (0x67), 29025ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // which most often indicates that the instruction address 16 bit address 29125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // instead of 32 bit address (or 32 bit address in 64 bit mode). 29225ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng AdSize = 1 << 7, 29325ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng 29425ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng //===------------------------------------------------------------------===// 2954c299f5da1013cd36563a82f188c731b2758074dChris Lattner // Op0Mask - There are several prefix bytes that are used to form two byte 296915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 297915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // used to obtain the setting of this field. If no bits in this field is 298915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // set, there is no prefix byte for obtaining a multibyte opcode. 2994c299f5da1013cd36563a82f188c731b2758074dChris Lattner // 30025ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng Op0Shift = 8, 301c96f6d606fb243f36046767b7a2c6a0dedffb139Chris Lattner Op0Mask = 0xF << Op0Shift, 3024c299f5da1013cd36563a82f188c731b2758074dChris Lattner 3034c299f5da1013cd36563a82f188c731b2758074dChris Lattner // TB - TwoByte - Set if this instruction has a two byte opcode, which 3044c299f5da1013cd36563a82f188c731b2758074dChris Lattner // starts with a 0x0F byte before the real opcode. 3052959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TB = 1 << Op0Shift, 3064c299f5da1013cd36563a82f188c731b2758074dChris Lattner 307915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // REP - The 0xF3 prefix byte indicating repetition of the following 308915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // instruction. 309915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner REP = 2 << Op0Shift, 310915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner 3114c299f5da1013cd36563a82f188c731b2758074dChris Lattner // D8-DF - These escape opcodes are used by the floating point unit. These 3124c299f5da1013cd36563a82f188c731b2758074dChris Lattner // values must remain sequential. 313915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 314915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DA = 5 << Op0Shift, DB = 6 << Op0Shift, 315915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DC = 7 << Op0Shift, DD = 8 << Op0Shift, 316915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DE = 9 << Op0Shift, DF = 10 << Op0Shift, 3179eb59ec548b861d6ede05b4e6dc22aabf645e665Jeff Cohen 318f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // XS, XD - These prefix codes are for single and double precision scalar 319f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // floating point operations performed in the SSE registers. 320bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling XD = 11 << Op0Shift, XS = 12 << Op0Shift, 321bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling 322bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling // T8, TA - Prefix after the 0x0F prefix. 323bb1ee05253d965e0944351a21e9970c02b1aebfeBill Wendling T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 324b4dc13cab7ef894d3bb17657fa993b9f09af476bEric Christopher 325b4dc13cab7ef894d3bb17657fa993b9f09af476bEric Christopher // TF - Prefix before and after 0x0F 326b4dc13cab7ef894d3bb17657fa993b9f09af476bEric Christopher TF = 15 << Op0Shift, 3274c299f5da1013cd36563a82f188c731b2758074dChris Lattner 3280c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 32925ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 33025ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // They are used to specify GPRs and SSE registers, 64-bit operand size, 33125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // etc. We only cares about REX.W and REX.R bits and only the former is 33225ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // statically determined. 33325ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // 334c96f6d606fb243f36046767b7a2c6a0dedffb139Chris Lattner REXShift = 12, 33525ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng REX_W = 1 << REXShift, 33625ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng 33725ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng //===------------------------------------------------------------------===// 33825ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng // This three-bit field describes the size of an immediate operand. Zero is 3395ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos // unused so that we can tell if we forgot to set a value. 340c96f6d606fb243f36046767b7a2c6a0dedffb139Chris Lattner ImmShift = 13, 34125ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng ImmMask = 7 << ImmShift, 3425ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm8 = 1 << ImmShift, 3435ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm16 = 2 << ImmShift, 3445ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm32 = 3 << ImmShift, 34525ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng Imm64 = 4 << ImmShift, 3464c299f5da1013cd36563a82f188c731b2758074dChris Lattner 3470c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 3480c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // FP Instruction Classification... Zero is non-fp instruction. 3490c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 3502959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner // FPTypeMask - Mask for all of the FP types... 351c96f6d606fb243f36046767b7a2c6a0dedffb139Chris Lattner FPTypeShift = 16, 3522959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner FPTypeMask = 7 << FPTypeShift, 3532959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner 35479b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner // NotFP - The default, set for instructions that do not use FP registers. 35579b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner NotFP = 0 << FPTypeShift, 35679b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner 3570c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 3582959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ZeroArgFP = 1 << FPTypeShift, 3590c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 3600c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 3612959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFP = 2 << FPTypeShift, 3620c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 3630c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 3640c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // result back to ST(0). For example, fcos, fsqrt, etc. 3650c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // 3662959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFPRW = 3 << FPTypeShift, 3670c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 3680c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 3690c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // explicit argument, storing the result to either ST(0) or the implicit 3700c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // argument. For example: fadd, fsub, fmul, etc... 3712959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TwoArgFP = 4 << FPTypeShift, 3720c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 373ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 374ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // explicit argument, but have no destination. Example: fucom, fucomi, ... 375ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CompareFP = 5 << FPTypeShift, 376ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner 3771c54a8544788156d6864430182a3a79b8839b7daChris Lattner // CondMovFP - "2 operand" floating point conditional move instructions. 378ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CondMovFP = 6 << FPTypeShift, 3791c54a8544788156d6864430182a3a79b8839b7daChris Lattner 3800c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 381ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner SpecialFP = 7 << FPTypeShift, 3821c54a8544788156d6864430182a3a79b8839b7daChris Lattner 383ea7da50e5a7f291295c10d91fc3fdba76d339579Andrew Lenharth // Lock prefix 384c96f6d606fb243f36046767b7a2c6a0dedffb139Chris Lattner LOCKShift = 19, 385ea7da50e5a7f291295c10d91fc3fdba76d339579Andrew Lenharth LOCK = 1 << LOCKShift, 386ea7da50e5a7f291295c10d91fc3fdba76d339579Andrew Lenharth 387ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov // Segment override prefixes. Currently we just need ability to address 388ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov // stuff in gs and fs segments. 389c96f6d606fb243f36046767b7a2c6a0dedffb139Chris Lattner SegOvrShift = 20, 390ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov SegOvrMask = 3 << SegOvrShift, 391ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov FS = 1 << SegOvrShift, 392ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov GS = 2 << SegOvrShift, 393ef93cecd80ebdecb0ea2b2c316370998151308e2Anton Korobeynikov 394c96f6d606fb243f36046767b7a2c6a0dedffb139Chris Lattner // Bits 22 -> 23 are unused 39525ab690a43cbbb591b76d49e3595b019c32f4b3fEvan Cheng OpcodeShift = 24, 396d74ea2bbd8bb630331f35ead42d385249bd42af8Chris Lattner OpcodeMask = 0xFF << OpcodeShift 3979d17740295838f94120646ef619b2e187f2d71bdChris Lattner }; 39874a2151392a08e202f497ece7a3129663526d431Chris Lattner 39974a2151392a08e202f497ece7a3129663526d431Chris Lattner // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 40074a2151392a08e202f497ece7a3129663526d431Chris Lattner // specified machine instruction. 40174a2151392a08e202f497ece7a3129663526d431Chris Lattner // 40274a2151392a08e202f497ece7a3129663526d431Chris Lattner static inline unsigned char getBaseOpcodeFor(unsigned TSFlags) { 40374a2151392a08e202f497ece7a3129663526d431Chris Lattner return TSFlags >> X86II::OpcodeShift; 40474a2151392a08e202f497ece7a3129663526d431Chris Lattner } 40574a2151392a08e202f497ece7a3129663526d431Chris Lattner 40674a2151392a08e202f497ece7a3129663526d431Chris Lattner /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 40774a2151392a08e202f497ece7a3129663526d431Chris Lattner /// of the specified instruction. 40874a2151392a08e202f497ece7a3129663526d431Chris Lattner static inline unsigned getSizeOfImm(unsigned TSFlags) { 40974a2151392a08e202f497ece7a3129663526d431Chris Lattner switch (TSFlags & X86II::ImmMask) { 41074a2151392a08e202f497ece7a3129663526d431Chris Lattner default: assert(0 && "Unknown immediate size"); 41174a2151392a08e202f497ece7a3129663526d431Chris Lattner case X86II::Imm8: return 1; 41274a2151392a08e202f497ece7a3129663526d431Chris Lattner case X86II::Imm16: return 2; 41374a2151392a08e202f497ece7a3129663526d431Chris Lattner case X86II::Imm32: return 4; 41474a2151392a08e202f497ece7a3129663526d431Chris Lattner case X86II::Imm64: return 8; 41574a2151392a08e202f497ece7a3129663526d431Chris Lattner } 41674a2151392a08e202f497ece7a3129663526d431Chris Lattner } 4179d17740295838f94120646ef619b2e187f2d71bdChris Lattner} 4189d17740295838f94120646ef619b2e187f2d71bdChris Lattner 419094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindolaconst int X86AddrNumOperands = 5; 420da945e3bb2069c1a7194bcd10579a03ff925a031Rafael Espindola 4211c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikovinline static bool isScale(const MachineOperand &MO) { 422d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman return MO.isImm() && 4231c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov (MO.getImm() == 1 || MO.getImm() == 2 || 4241c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov MO.getImm() == 4 || MO.getImm() == 8); 4251c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov} 4261c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov 427094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindolainline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 428d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(Op).isFI()) return true; 4291c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov return Op+4 <= MI->getNumOperands() && 430d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 431d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+2).isReg() && 432d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman (MI->getOperand(Op+3).isImm() || 433d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+3).isGlobal() || 434d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+3).isCPI() || 435d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(Op+3).isJTI()); 4361c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov} 4371c4b5eaa4628935c4db3e422aa10f2031e6d1679Anton Korobeynikov 438094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindolainline static bool isMem(const MachineInstr *MI, unsigned Op) { 439094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola if (MI->getOperand(Op).isFI()) return true; 440094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola return Op+5 <= MI->getNumOperands() && 441094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola MI->getOperand(Op+4).isReg() && 442094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola isLeaMem(MI, Op); 443094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola} 444094fad37b90946c91a09eb9270a0dbe800f49d87Rafael Espindola 445641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass X86InstrInfo : public TargetInstrInfoImpl { 446aa3c1410b427909da350f2b5e8d4ec3db62a3618Evan Cheng X86TargetMachine &TM; 447726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner const X86RegisterInfo RI; 44843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 44943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 45043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// RegOp2MemOpTable2 - Load / store folding opcode maps. 45143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// 452f9b36f08efbc66670910a8a85dd89f03d36196d4Evan Cheng DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 453f9b36f08efbc66670910a8a85dd89f03d36196d4Evan Cheng DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 454f9b36f08efbc66670910a8a85dd89f03d36196d4Evan Cheng DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 455f9b36f08efbc66670910a8a85dd89f03d36196d4Evan Cheng DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 45643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 45743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// MemOp2RegOpTable - Load / store unfolding opcode map. 45843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// 45943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 46043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 461726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattnerpublic: 462950a4c40b823cd4f09dc71be635229246dfd6cacDan Gohman explicit X86InstrInfo(X86TargetMachine &tm); 463726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 4643501feab811c86c9659248a4875fc31a3165f84dChris Lattner /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 465726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// such, whenever a client has an instance of instruction info, it should 466726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// always be able to get register info as well (through this method). 467726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// 468c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6Dan Gohman virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 469726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 47004ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// Return true if the instruction is a register to register move and return 47104ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// the source and dest operands and their sub-register indices by reference. 47204ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng virtual bool isMoveInstr(const MachineInstr &MI, 47304ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcReg, unsigned &DstReg, 47404ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 47504ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng 4767da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 4777da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// extension instruction. That is, it's like a copy where it's legal for the 4787da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 4797da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// true, then it's expected the pre-extension value is available as a subreg 4807da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// of the result register. This also returns the sub-register index in 4817da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// SubIdx. 4827da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng virtual bool isCoalescableExtInstr(const MachineInstr &MI, 4837da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SrcReg, unsigned &DstReg, 4847da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SubIdx) const; 485a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng 486cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 487dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 488dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 489dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 490dda3978d7877d2d60390833c73ed24857295e89cDavid Greene unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 491dda3978d7877d2d60390833c73ed24857295e89cDavid Greene int &FrameIndex) const; 492b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 493b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasLoadFromStackSlot - If the specified machine instruction has 494b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// a load from a stack slot, return true along with the FrameIndex 49529dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// of the loaded stack slot and the machine mem operand containing 49629dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// the reference. If not, return false. Unlike 497b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// isLoadFromStackSlot, this returns true for any instructions that 498b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// loads from the stack. This is a hint only and may not catch all 499b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// cases. 50029dbf50b180bb3342af84ff042a3ff06405c5071David Greene bool hasLoadFromStackSlot(const MachineInstr *MI, 50129dbf50b180bb3342af84ff042a3ff06405c5071David Greene const MachineMemOperand *&MMO, 50229dbf50b180bb3342af84ff042a3ff06405c5071David Greene int &FrameIndex) const; 503b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 504cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 505dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 506dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 507dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 508dda3978d7877d2d60390833c73ed24857295e89cDavid Greene unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 509dda3978d7877d2d60390833c73ed24857295e89cDavid Greene int &FrameIndex) const; 510ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 511b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasStoreToStackSlot - If the specified machine instruction has a 512b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// store to a stack slot, return true along with the FrameIndex of 51329dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// the loaded stack slot and the machine mem operand containing the 51429dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// reference. If not, return false. Unlike isStoreToStackSlot, 51529dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// this returns true for any instructions that loads from the 51629dbf50b180bb3342af84ff042a3ff06405c5071David Greene /// stack. This is a hint only and may not catch all cases. 51729dbf50b180bb3342af84ff042a3ff06405c5071David Greene bool hasStoreToStackSlot(const MachineInstr *MI, 51829dbf50b180bb3342af84ff042a3ff06405c5071David Greene const MachineMemOperand *&MMO, 51929dbf50b180bb3342af84ff042a3ff06405c5071David Greene int &FrameIndex) const; 520b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 5213731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 5223731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman AliasAnalysis *AA) const; 523ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 524378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, 525d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 526d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const TargetRegisterInfo *TRI) const; 527ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 528bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 529bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 530bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// may be able to convert a two-address instruction into a true 531bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// three-address instruction on demand. This allows the X86 target (for 532bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 533bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// would require register copies due to two-addressness. 534bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 535bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// This method returns a null pointer if the transformation cannot be 536bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// performed, otherwise it returns the new instruction. 537bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 538ba59a1e453e110f7b84233f07613f9c5d9a39b87Evan Cheng virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 539ba59a1e453e110f7b84233f07613f9c5d9a39b87Evan Cheng MachineBasicBlock::iterator &MBBI, 540f660c171c838793b87b7e58e91609cecf256378dOwen Anderson LiveVariables *LV) const; 541bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner 54241e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commuteInstruction - We have a few instructions that must be hacked on to 54341e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commute them. 54441e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// 54558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 54641e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 5477fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner // Branch analysis. 548318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 5497fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 5507fbe9723e32ff35c4ad765c88209ef9321475a1bChris Lattner MachineBasicBlock *&FBB, 551dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 552dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify) const; 5536ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 5546ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 5556ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng MachineBasicBlock *FBB, 55644eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond) const; 557940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson virtual bool copyRegToReg(MachineBasicBlock &MBB, 558d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 559d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 560d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 561d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const; 562f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 563f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 564f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 565f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const; 566f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 567f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 568f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 569f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 57091e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOBegin, 57191e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOEnd, 572f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 573f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 574f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 575f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 576f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 577f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const; 578f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 579f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 580f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 581f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 58291e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOBegin, 58391e69c37153eb7d8cd149d9c2484c3115027b90fDan Gohman MachineInstr::mmo_iterator MMOEnd, 584f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 585d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 586d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 587d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 588d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const; 589d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 590d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 591d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 592d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const; 593d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 59443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - If this target supports it, fold a load or store of 59543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// the specified stack slot into the specified machine instruction for the 59643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified operand(s). If this is possible, the target should perform the 59743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding and return true, otherwise it should return false. If it folds 59843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// the instruction, it is likely that the MachineInstruction the iterator 59943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// references has been changed. 600c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 601c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 602c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 603c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 60443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 60543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 60643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 60743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 608c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 609c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 610c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 611c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 61243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 61343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// canFoldMemoryOperand - Returns true if the specified load / store is 61443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 6158e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman virtual bool canFoldMemoryOperand(const MachineInstr*, 6168e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &) const; 61743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 61843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 61943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 62043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 62143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 62243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 62343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 62443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 62543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 62643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const; 62743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 62843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 62943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 63043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 6310115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// possible. If LoadRegIndex is non-null, it is filled in with the operand 6320115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// index of the operand which will hold the register holding the loaded 6330115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// value. 63443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 6350115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman bool UnfoldLoad, bool UnfoldStore, 6360115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman unsigned *LoadRegIndex = 0) const; 63743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 63896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 63996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to determine if two loads are loading from the same base address. It 64096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// should only return true if the base pointers are the same and the 64196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// only differences between the two addresses are the offset. It also returns 64296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// the offsets by reference. 64396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 64496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t &Offset1, int64_t &Offset2) const; 64596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 64696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 64796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 64896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// be scheduled togther. On some targets if two loads are loading from 64996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// addresses in the same cache line, it's better if they are scheduled 65096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// together. This function takes two integers that represent the load offsets 65196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// from the common base address. It returns true if it decides it's desirable 65296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to schedule the two loads together. "NumLoads" is the number of loads that 65396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// have already been scheduled after Load1. 65496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 65596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t Offset1, int64_t Offset2, 65696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng unsigned NumLoads) const; 65796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 65844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 65944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 66041e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 6614350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 6624350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// instruction that defines the specified register class. 6634350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 66423066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 66552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray static bool isX86_64NonExtLowByteReg(unsigned reg) { 66652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return (reg == X86::SPL || reg == X86::BPL || 66752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray reg == X86::SIL || reg == X86::DIL); 66852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 66952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 67039a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner static bool isX86_64ExtendedReg(const MachineOperand &MO) { 67139a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner if (!MO.isReg()) return false; 67239a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner return isX86_64ExtendedReg(MO.getReg()); 67339a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner } 67452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray static unsigned determineREX(const MachineInstr &MI); 67552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 67639a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 67739a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner /// higher) register? e.g. r8, xmm8, xmm13, etc. 67839a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner static bool isX86_64ExtendedReg(unsigned RegNo); 67939a612e6f9e63806af410a0ab0d81895391e4c79Chris Lattner 68052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetInstSize - Returns the size of the specified MachineInstr. 68152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 68252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 68343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 68457c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman /// getGlobalBaseReg - Return a virtual register initialized with the 68557c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman /// the global base register value. Output instructions required to 68657c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman /// initialize the register in the function entry block, if necessary. 6878b746969baee26237e4c52de9862d06795eabcdaDan Gohman /// 68857c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37cDan Gohman unsigned getGlobalBaseReg(MachineFunction *MF) const; 6898b746969baee26237e4c52de9862d06795eabcdaDan Gohman 69043dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonprivate: 691656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 692656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng MachineFunction::iterator &MFI, 693656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng MachineBasicBlock::iterator &MBBI, 694656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng LiveVariables *LV) const; 695656e51454ac70f5d500565fd33c883f6dea549f2Evan Cheng 696c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 697f9b36f08efbc66670910a8a85dd89f03d36196d4Evan Cheng MachineInstr* MI, 698f9b36f08efbc66670910a8a85dd89f03d36196d4Evan Cheng unsigned OpNum, 699f9b36f08efbc66670910a8a85dd89f03d36196d4Evan Cheng const SmallVectorImpl<MachineOperand> &MOs, 7009cef48eae9a4776ef2f42687072e7c61cb33e10dEvan Cheng unsigned Size, unsigned Alignment) const; 701b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 702b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// isFrameOperand - Return true and the FrameIndex if the specified 703b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// operand and follow operands form a reference to the stack frame. 704b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 705b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene int &FrameIndex) const; 706726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner}; 707726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 708d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 709d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 710726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#endif 711