X86InstrInfo.h revision d74ea2bbd8bb630331f35ead42d385249bd42af8
11e60a9165dc4d6ce5650dacc026f2942696af920Chris Lattner//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 20e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 3856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// The LLVM Compiler Infrastructure 4856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// 5856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// This file was developed by the LLVM research group and is distributed under 6856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell// the University of Illinois Open Source License. See LICENSE.TXT for details. 70e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman// 8856ba76200ec2302f2fe500bc507f426c7d566c8John Criswell//===----------------------------------------------------------------------===// 9726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 103501feab811c86c9659248a4875fc31a3165f84dChris Lattner// This file contains the X86 implementation of the TargetInstrInfo class. 11726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner// 12726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner//===----------------------------------------------------------------------===// 13726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 14726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#ifndef X86INSTRUCTIONINFO_H 15726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#define X86INSTRUCTIONINFO_H 16726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 173501feab811c86c9659248a4875fc31a3165f84dChris Lattner#include "llvm/Target/TargetInstrInfo.h" 18726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#include "X86RegisterInfo.h" 19726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 229d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// X86II - This namespace holds all of the target specific flags that 239d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// instruction info tracks. 249d17740295838f94120646ef619b2e187f2d71bdChris Lattner/// 259d17740295838f94120646ef619b2e187f2d71bdChris Lattnernamespace X86II { 269d17740295838f94120646ef619b2e187f2d71bdChris Lattner enum { 276aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 286aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Instruction types. These are the standard/most common forms for X86 296aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // instructions. 306aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // 316aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 324c299f5da1013cd36563a82f188c731b2758074dChris Lattner // PseudoFrm - This represents an instruction that is a pseudo instruction 334c299f5da1013cd36563a82f188c731b2758074dChris Lattner // or one that has not been implemented yet. It is illegal to code generate 344c299f5da1013cd36563a82f188c731b2758074dChris Lattner // it, but tolerated for intermediate implementation stages. 354c299f5da1013cd36563a82f188c731b2758074dChris Lattner Pseudo = 0, 364c299f5da1013cd36563a82f188c731b2758074dChris Lattner 376aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// Raw - This form is for instructions that don't have any operands, so 386aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// they are just a fixed opcode value, like 'leave'. 394c299f5da1013cd36563a82f188c731b2758074dChris Lattner RawFrm = 1, 400e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 416aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// AddRegFrm - This form is used for instructions like 'push r32' that have 426aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// their one register operand added to their opcode. 434c299f5da1013cd36563a82f188c731b2758074dChris Lattner AddRegFrm = 2, 446aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 456aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 466aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is a register. 476aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 484c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestReg = 3, 496aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 506aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 516aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a destination, which in this case is memory. 526aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 534c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMDestMem = 4, 546aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 556aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 566aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is a register. 576aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 584c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcReg = 5, 596aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 606aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 616aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// to specify a source, which in this case is memory. 626aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner /// 634c299f5da1013cd36563a82f188c731b2758074dChris Lattner MRMSrcMem = 6, 640e0a7a45d3d0a8c865a078459d2e1c6d8967a100Misha Brukman 65169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos /// MRM[0-7][rm] - These forms are used to represent instructions that use 6685b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// a Mod/RM byte, and use the middle field to hold extended opcode 6785b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// information. In the intel manual these are represented as /0, /1, ... 6885b39f229f3146e57d059f1c774400e4bde23987Chris Lattner /// 6985b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 7085b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // First, instructions that operate on a register r/m operand... 71169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 72169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 7385b39f229f3146e57d059f1c774400e4bde23987Chris Lattner 7485b39f229f3146e57d059f1c774400e4bde23987Chris Lattner // Next, instructions that operate on a memory r/m operand... 75169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 76169584ed45f62f91599bed3d019640e168d815eaAlkis Evlogimenos MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 776aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 783c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // MRMInitReg - This form is used for instructions whose source and 793c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // destinations are the same register. 803c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng MRMInitReg = 32, 813c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng 823c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng FormMask = 63, 836aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 846aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner //===------------------------------------------------------------------===// 856aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner // Actual flags... 866aab9cf65cd1e96f9d0fa99f8453da454648bba1Chris Lattner 8711e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // OpSize - Set if this instruction requires an operand size prefix (0x66), 8811e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // which most often indicates that the instruction operates on 16 bit data 8911e53e3c384e9e25f53a0aec3acf0a725efafeabChris Lattner // instead of 32 bit data. 903c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng OpSize = 1 << 6, 914c299f5da1013cd36563a82f188c731b2758074dChris Lattner 924c299f5da1013cd36563a82f188c731b2758074dChris Lattner // Op0Mask - There are several prefix bytes that are used to form two byte 93915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 94915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // used to obtain the setting of this field. If no bits in this field is 95915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // set, there is no prefix byte for obtaining a multibyte opcode. 964c299f5da1013cd36563a82f188c731b2758074dChris Lattner // 973c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng Op0Shift = 7, 982959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner Op0Mask = 0xF << Op0Shift, 994c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1004c299f5da1013cd36563a82f188c731b2758074dChris Lattner // TB - TwoByte - Set if this instruction has a two byte opcode, which 1014c299f5da1013cd36563a82f188c731b2758074dChris Lattner // starts with a 0x0F byte before the real opcode. 1022959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TB = 1 << Op0Shift, 1034c299f5da1013cd36563a82f188c731b2758074dChris Lattner 104915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // REP - The 0xF3 prefix byte indicating repetition of the following 105915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner // instruction. 106915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner REP = 2 << Op0Shift, 107915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner 1084c299f5da1013cd36563a82f188c731b2758074dChris Lattner // D8-DF - These escape opcodes are used by the floating point unit. These 1094c299f5da1013cd36563a82f188c731b2758074dChris Lattner // values must remain sequential. 110915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 111915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DA = 5 << Op0Shift, DB = 6 << Op0Shift, 112915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DC = 7 << Op0Shift, DD = 8 << Op0Shift, 113915e5e56d7cc8e140d33202eed6244ed0356ed1fChris Lattner DE = 9 << Op0Shift, DF = 10 << Op0Shift, 1149eb59ec548b861d6ede05b4e6dc22aabf645e665Jeff Cohen 115f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // XS, XD - These prefix codes are for single and double precision scalar 116f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman // floating point operations performed in the SSE registers. 117f63be7d3959939b2ffaf0bba5519b71216ec9ee6Nate Begeman XD = 11 << Op0Shift, XS = 12 << Op0Shift, 1184c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1190c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 1204ffff9e2fa97a99d6e7de84bcb0866f70d330260John Criswell // This two-bit field describes the size of an immediate operand. Zero is 1215ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos // unused so that we can tell if we forgot to set a value. 1223c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng ImmShift = 11, 123751458dac9fec1c9436065a6e1ea0dd0a9cf3ec3Evan Cheng ImmMask = 3 << ImmShift, 1245ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm8 = 1 << ImmShift, 1255ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm16 = 2 << ImmShift, 1265ab29b504d49d3fa84d76f79e73704260f900682Alkis Evlogimenos Imm32 = 3 << ImmShift, 1274c299f5da1013cd36563a82f188c731b2758074dChris Lattner 1280c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner //===------------------------------------------------------------------===// 1290c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // FP Instruction Classification... Zero is non-fp instruction. 1300c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1312959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner // FPTypeMask - Mask for all of the FP types... 1323c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng FPTypeShift = 13, 1332959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner FPTypeMask = 7 << FPTypeShift, 1342959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner 13579b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner // NotFP - The default, set for instructions that do not use FP registers. 13679b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner NotFP = 0 << FPTypeShift, 13779b13735adcc034a6869f1fd5670051c6dd0a28aChris Lattner 1380c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 1392959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner ZeroArgFP = 1 << FPTypeShift, 1400c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1410c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 1422959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFP = 2 << FPTypeShift, 1430c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1440c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 1450c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // result back to ST(0). For example, fcos, fsqrt, etc. 1460c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // 1472959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner OneArgFPRW = 3 << FPTypeShift, 1480c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 1490c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 1500c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // explicit argument, storing the result to either ST(0) or the implicit 1510c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // argument. For example: fadd, fsub, fmul, etc... 1522959b6ec49be09096cf0a5e7504d2a1ec15ef2b3Chris Lattner TwoArgFP = 4 << FPTypeShift, 1530c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner 154ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 155ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner // explicit argument, but have no destination. Example: fucom, fucomi, ... 156ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CompareFP = 5 << FPTypeShift, 157ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner 1581c54a8544788156d6864430182a3a79b8839b7daChris Lattner // CondMovFP - "2 operand" floating point conditional move instructions. 159ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner CondMovFP = 6 << FPTypeShift, 1601c54a8544788156d6864430182a3a79b8839b7daChris Lattner 1610c514f4e2711ab57bf75f26806f7b8584dfbee6fChris Lattner // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 162ab8deccb82460527562d1c36a787537e4edaa9ddChris Lattner SpecialFP = 7 << FPTypeShift, 1631c54a8544788156d6864430182a3a79b8839b7daChris Lattner 164751458dac9fec1c9436065a6e1ea0dd0a9cf3ec3Evan Cheng OpcodeShift = 16, 165d74ea2bbd8bb630331f35ead42d385249bd42af8Chris Lattner OpcodeMask = 0xFF << OpcodeShift 1663c55c54a877b3e5a79053df8f6080f505c9d1ff4Evan Cheng // Bits 25 -> 31 are unused 1679d17740295838f94120646ef619b2e187f2d71bdChris Lattner }; 1689d17740295838f94120646ef619b2e187f2d71bdChris Lattner} 1699d17740295838f94120646ef619b2e187f2d71bdChris Lattner 1703501feab811c86c9659248a4875fc31a3165f84dChris Lattnerclass X86InstrInfo : public TargetInstrInfo { 171726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner const X86RegisterInfo RI; 172726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattnerpublic: 173055c965bff7c8567e7fae90ffe1e10e109856064Chris Lattner X86InstrInfo(); 174726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 1753501feab811c86c9659248a4875fc31a3165f84dChris Lattner /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 176726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// such, whenever a client has an instance of instruction info, it should 177726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// always be able to get register info as well (through this method). 178726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner /// 179726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 180726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 1815e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // Return true if the instruction is a register to register move and 1825e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // leave the source and dest operands in the passed parameters. 1835e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos // 184408396014742a05cad1c91949d2226169e3f9d80Chris Lattner bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 185408396014742a05cad1c91949d2226169e3f9d80Chris Lattner unsigned& destReg) const; 186408396014742a05cad1c91949d2226169e3f9d80Chris Lattner unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 187408396014742a05cad1c91949d2226169e3f9d80Chris Lattner unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 188408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 189bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 190bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 191bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// may be able to convert a two-address instruction into a true 192bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// three-address instruction on demand. This allows the X86 target (for 193bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 194bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// would require register copies due to two-addressness. 195bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 196bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// This method returns a null pointer if the transformation cannot be 197bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// performed, otherwise it returns the new instruction. 198bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner /// 199bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; 200bcea4d6f283a5ae6f93dc8e10898311fe53d23a3Chris Lattner 20141e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commuteInstruction - We have a few instructions that must be hacked on to 20241e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// commute them. 20341e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner /// 20441e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 20541e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 20641e431ba045eb317ebf0ec45b563a5d96c212f5cChris Lattner 20736f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos /// Insert a goto (unconditional branch) sequence to TMBB, at the 20836f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos /// end of MBB 20936f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos virtual void insertGoto(MachineBasicBlock& MBB, 21036f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos MachineBasicBlock& TMBB) const; 21136f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos 21236f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos /// Reverses the branch condition of the MachineInstr pointed by 21336f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos /// MI. The instruction is replaced and the new MI is returned. 21436f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos virtual MachineBasicBlock::iterator 21536f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos reverseBranchCondition(MachineBasicBlock::iterator MI) const; 21636f506eddb25d5198240a1e3fabcb0912111c7eeAlkis Evlogimenos 217f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 218f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // specified opcode number. 219f21dfcddcf199444440004bfa74bb222e2d3ce9eChris Lattner // 2204d18d5ce1e62779e7736ca0811e2e1cb06e4ea36Chris Lattner unsigned char getBaseOpcodeFor(unsigned Opcode) const { 2214d18d5ce1e62779e7736ca0811e2e1cb06e4ea36Chris Lattner return get(Opcode).TSFlags >> X86II::OpcodeShift; 2224d18d5ce1e62779e7736ca0811e2e1cb06e4ea36Chris Lattner } 223726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner}; 224726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner 225d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 226d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 227726140821f96e3472a8eccef0c67c0b5ad65a1d9Chris Lattner#endif 228