X86Subtarget.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/ADT/Triple.h"
18#include "llvm/IR/CallingConv.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "X86GenSubtargetInfo.inc"
24
25namespace llvm {
26class GlobalValue;
27class StringRef;
28class TargetMachine;
29
30/// PICStyles - The X86 backend supports a number of different styles of PIC.
31///
32namespace PICStyles {
33enum Style {
34  StubPIC,          // Used on i386-darwin in -fPIC mode.
35  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36  GOT,              // Used on many 32-bit unices in -fPIC mode.
37  RIPRel,           // Used on X86-64 when not in -static mode.
38  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
39};
40}
41
42class X86Subtarget final : public X86GenSubtargetInfo {
43protected:
44  enum X86SSEEnum {
45    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
46  };
47
48  enum X863DNowEnum {
49    NoThreeDNow, ThreeDNow, ThreeDNowA
50  };
51
52  enum X86ProcFamilyEnum {
53    Others, IntelAtom, IntelSLM
54  };
55
56  /// X86ProcFamily - X86 processor family: Intel Atom, and others
57  X86ProcFamilyEnum X86ProcFamily;
58
59  /// PICStyle - Which PIC style to use
60  ///
61  PICStyles::Style PICStyle;
62
63  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
64  /// none supported.
65  X86SSEEnum X86SSELevel;
66
67  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
68  ///
69  X863DNowEnum X863DNowLevel;
70
71  /// HasCMov - True if this processor has conditional move instructions
72  /// (generally pentium pro+).
73  bool HasCMov;
74
75  /// HasX86_64 - True if the processor supports X86-64 instructions.
76  ///
77  bool HasX86_64;
78
79  /// HasPOPCNT - True if the processor supports POPCNT.
80  bool HasPOPCNT;
81
82  /// HasSSE4A - True if the processor supports SSE4A instructions.
83  bool HasSSE4A;
84
85  /// HasAES - Target has AES instructions
86  bool HasAES;
87
88  /// HasPCLMUL - Target has carry-less multiplication
89  bool HasPCLMUL;
90
91  /// HasFMA - Target has 3-operand fused multiply-add
92  bool HasFMA;
93
94  /// HasFMA4 - Target has 4-operand fused multiply-add
95  bool HasFMA4;
96
97  /// HasXOP - Target has XOP instructions
98  bool HasXOP;
99
100  /// HasTBM - Target has TBM instructions.
101  bool HasTBM;
102
103  /// HasMOVBE - True if the processor has the MOVBE instruction.
104  bool HasMOVBE;
105
106  /// HasRDRAND - True if the processor has the RDRAND instruction.
107  bool HasRDRAND;
108
109  /// HasF16C - Processor has 16-bit floating point conversion instructions.
110  bool HasF16C;
111
112  /// HasFSGSBase - Processor has FS/GS base insturctions.
113  bool HasFSGSBase;
114
115  /// HasLZCNT - Processor has LZCNT instruction.
116  bool HasLZCNT;
117
118  /// HasBMI - Processor has BMI1 instructions.
119  bool HasBMI;
120
121  /// HasBMI2 - Processor has BMI2 instructions.
122  bool HasBMI2;
123
124  /// HasRTM - Processor has RTM instructions.
125  bool HasRTM;
126
127  /// HasHLE - Processor has HLE.
128  bool HasHLE;
129
130  /// HasADX - Processor has ADX instructions.
131  bool HasADX;
132
133  /// HasSHA - Processor has SHA instructions.
134  bool HasSHA;
135
136  /// HasPRFCHW - Processor has PRFCHW instructions.
137  bool HasPRFCHW;
138
139  /// HasRDSEED - Processor has RDSEED instructions.
140  bool HasRDSEED;
141
142  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
143  bool IsBTMemSlow;
144
145  /// IsSHLDSlow - True if SHLD instructions are slow.
146  bool IsSHLDSlow;
147
148  /// IsUAMemFast - True if unaligned memory access is fast.
149  bool IsUAMemFast;
150
151  /// HasVectorUAMem - True if SIMD operations can have unaligned memory
152  /// operands. This may require setting a feature bit in the processor.
153  bool HasVectorUAMem;
154
155  /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
156  /// this is true for most x86-64 chips, but not the first AMD chips.
157  bool HasCmpxchg16b;
158
159  /// UseLeaForSP - True if the LEA instruction should be used for adjusting
160  /// the stack pointer. This is an optimization for Intel Atom processors.
161  bool UseLeaForSP;
162
163  /// HasSlowDivide - True if smaller divides are significantly faster than
164  /// full divides and should be used when possible.
165  bool HasSlowDivide;
166
167  /// PostRAScheduler - True if using post-register-allocation scheduler.
168  bool PostRAScheduler;
169
170  /// PadShortFunctions - True if the short functions should be padded to prevent
171  /// a stall when returning too early.
172  bool PadShortFunctions;
173
174  /// CallRegIndirect - True if the Calls with memory reference should be converted
175  /// to a register-based indirect call.
176  bool CallRegIndirect;
177  /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
178  ///             address generation (AG) time.
179  bool LEAUsesAG;
180
181  /// Processor has AVX-512 PreFetch Instructions
182  bool HasPFI;
183
184  /// Processor has AVX-512 Exponential and Reciprocal Instructions
185  bool HasERI;
186
187  /// Processor has AVX-512 Conflict Detection Instructions
188  bool HasCDI;
189
190  /// stackAlignment - The minimum alignment known to hold of the stack frame on
191  /// entry to the function and which must be maintained by every function.
192  unsigned stackAlignment;
193
194  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
195  ///
196  unsigned MaxInlineSizeThreshold;
197
198  /// TargetTriple - What processor and OS we're targeting.
199  Triple TargetTriple;
200
201  /// Instruction itineraries for scheduling
202  InstrItineraryData InstrItins;
203
204private:
205  /// StackAlignOverride - Override the stack alignment.
206  unsigned StackAlignOverride;
207
208  /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
209  bool In64BitMode;
210
211  /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
212  bool In32BitMode;
213
214  /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
215  bool In16BitMode;
216
217public:
218  /// This constructor initializes the data members to match that
219  /// of the specified triple.
220  ///
221  X86Subtarget(const std::string &TT, const std::string &CPU,
222               const std::string &FS,
223               unsigned StackAlignOverride);
224
225  /// getStackAlignment - Returns the minimum alignment known to hold of the
226  /// stack frame on entry to the function and which must be maintained by every
227  /// function for this subtarget.
228  unsigned getStackAlignment() const { return stackAlignment; }
229
230  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
231  /// that still makes it profitable to inline the call.
232  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
233
234  /// ParseSubtargetFeatures - Parses features string setting specified
235  /// subtarget options.  Definition of function is auto generated by tblgen.
236  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
237
238  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
239  /// instruction.
240  void AutoDetectSubtargetFeatures();
241
242  /// \brief Reset the features for the X86 target.
243  void resetSubtargetFeatures(const MachineFunction *MF) override;
244private:
245  void initializeEnvironment();
246  void resetSubtargetFeatures(StringRef CPU, StringRef FS);
247public:
248  /// Is this x86_64? (disregarding specific ABI / programming model)
249  bool is64Bit() const {
250    return In64BitMode;
251  }
252
253  bool is32Bit() const {
254    return In32BitMode;
255  }
256
257  bool is16Bit() const {
258    return In16BitMode;
259  }
260
261  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
262  bool isTarget64BitILP32() const {
263    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
264                           TargetTriple.getOS() == Triple::NaCl);
265  }
266
267  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
268  bool isTarget64BitLP64() const {
269    return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
270  }
271
272  PICStyles::Style getPICStyle() const { return PICStyle; }
273  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
274
275  bool hasCMov() const { return HasCMov; }
276  bool hasMMX() const { return X86SSELevel >= MMX; }
277  bool hasSSE1() const { return X86SSELevel >= SSE1; }
278  bool hasSSE2() const { return X86SSELevel >= SSE2; }
279  bool hasSSE3() const { return X86SSELevel >= SSE3; }
280  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
281  bool hasSSE41() const { return X86SSELevel >= SSE41; }
282  bool hasSSE42() const { return X86SSELevel >= SSE42; }
283  bool hasAVX() const { return X86SSELevel >= AVX; }
284  bool hasAVX2() const { return X86SSELevel >= AVX2; }
285  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
286  bool hasFp256() const { return hasAVX(); }
287  bool hasInt256() const { return hasAVX2(); }
288  bool hasSSE4A() const { return HasSSE4A; }
289  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
290  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
291  bool hasPOPCNT() const { return HasPOPCNT; }
292  bool hasAES() const { return HasAES; }
293  bool hasPCLMUL() const { return HasPCLMUL; }
294  bool hasFMA() const { return HasFMA; }
295  // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
296  bool hasFMA4() const { return HasFMA4 && !HasFMA; }
297  bool hasXOP() const { return HasXOP; }
298  bool hasTBM() const { return HasTBM; }
299  bool hasMOVBE() const { return HasMOVBE; }
300  bool hasRDRAND() const { return HasRDRAND; }
301  bool hasF16C() const { return HasF16C; }
302  bool hasFSGSBase() const { return HasFSGSBase; }
303  bool hasLZCNT() const { return HasLZCNT; }
304  bool hasBMI() const { return HasBMI; }
305  bool hasBMI2() const { return HasBMI2; }
306  bool hasRTM() const { return HasRTM; }
307  bool hasHLE() const { return HasHLE; }
308  bool hasADX() const { return HasADX; }
309  bool hasSHA() const { return HasSHA; }
310  bool hasPRFCHW() const { return HasPRFCHW; }
311  bool hasRDSEED() const { return HasRDSEED; }
312  bool isBTMemSlow() const { return IsBTMemSlow; }
313  bool isSHLDSlow() const { return IsSHLDSlow; }
314  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
315  bool hasVectorUAMem() const { return HasVectorUAMem; }
316  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
317  bool useLeaForSP() const { return UseLeaForSP; }
318  bool hasSlowDivide() const { return HasSlowDivide; }
319  bool padShortFunctions() const { return PadShortFunctions; }
320  bool callRegIndirect() const { return CallRegIndirect; }
321  bool LEAusesAG() const { return LEAUsesAG; }
322  bool hasCDI() const { return HasCDI; }
323  bool hasPFI() const { return HasPFI; }
324  bool hasERI() const { return HasERI; }
325
326  bool isAtom() const { return X86ProcFamily == IntelAtom; }
327
328  const Triple &getTargetTriple() const { return TargetTriple; }
329
330  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
331  bool isTargetFreeBSD() const {
332    return TargetTriple.getOS() == Triple::FreeBSD;
333  }
334  bool isTargetSolaris() const {
335    return TargetTriple.getOS() == Triple::Solaris;
336  }
337
338  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
339  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
340  bool isTargetMacho() const { return TargetTriple.isOSBinFormatMachO(); }
341
342  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
343  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
344  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
345  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
346
347  bool isTargetWindowsMSVC() const {
348    return TargetTriple.isWindowsMSVCEnvironment();
349  }
350
351  bool isTargetKnownWindowsMSVC() const {
352    return TargetTriple.isKnownWindowsMSVCEnvironment();
353  }
354
355  bool isTargetWindowsCygwin() const {
356    return TargetTriple.isWindowsCygwinEnvironment();
357  }
358
359  bool isTargetWindowsGNU() const {
360    return TargetTriple.isWindowsGNUEnvironment();
361  }
362
363  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
364
365  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
366
367  bool isTargetWin64() const {
368    return In64BitMode && TargetTriple.isOSWindows();
369  }
370
371  bool isTargetWin32() const {
372    return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
373  }
374
375  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
376  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
377  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
378
379  bool isPICStyleStubPIC() const {
380    return PICStyle == PICStyles::StubPIC;
381  }
382
383  bool isPICStyleStubNoDynamic() const {
384    return PICStyle == PICStyles::StubDynamicNoPIC;
385  }
386  bool isPICStyleStubAny() const {
387    return PICStyle == PICStyles::StubDynamicNoPIC ||
388           PICStyle == PICStyles::StubPIC;
389  }
390
391  bool isCallingConvWin64(CallingConv::ID CC) const {
392    return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
393           CC == CallingConv::X86_64_Win64;
394  }
395
396  /// ClassifyGlobalReference - Classify a global variable reference for the
397  /// current subtarget according to how we should reference it in a non-pcrel
398  /// context.
399  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
400                                        const TargetMachine &TM)const;
401
402  /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
403  /// current subtarget according to how we should reference it in a non-pcrel
404  /// context.
405  unsigned char ClassifyBlockAddressReference() const;
406
407  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
408  /// to immediate address.
409  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
410
411  /// This function returns the name of a function which has an interface
412  /// like the non-standard bzero function, if such a function exists on
413  /// the current subtarget and it is considered prefereable over
414  /// memset with zero passed as the second argument. Otherwise it
415  /// returns null.
416  const char *getBZeroEntry() const;
417
418  /// This function returns true if the target has sincos() routine in its
419  /// compiler runtime or math libraries.
420  bool hasSinCos() const;
421
422  /// Enable the MachineScheduler pass for all X86 subtargets.
423  bool enableMachineScheduler() const override { return true; }
424
425  /// enablePostRAScheduler - run for Atom optimization.
426  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
427                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
428                             RegClassVector& CriticalPathRCs) const override;
429
430  bool postRAScheduler() const { return PostRAScheduler; }
431
432  /// getInstrItins = Return the instruction itineraries based on the
433  /// subtarget selection.
434  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
435};
436
437} // End llvm namespace
438
439#endif
440