X86Subtarget.h revision c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 
1//=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/Target/TargetSubtarget.h"
18#include <string>
19
20namespace llvm {
21class GlobalValue;
22class TargetMachine;
23
24/// PICStyles - The X86 backend supports a number of different styles of PIC.
25///
26namespace PICStyles {
27enum Style {
28  StubPIC,          // Used on i386-darwin in -fPIC mode.
29  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
30  GOT,              // Used on many 32-bit unices in -fPIC mode.
31  RIPRel,           // Used on X86-64 when not in -static mode.
32  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
33};
34}
35
36class X86Subtarget : public TargetSubtarget {
37protected:
38  enum X86SSEEnum {
39    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42
40  };
41
42  enum X863DNowEnum {
43    NoThreeDNow, ThreeDNow, ThreeDNowA
44  };
45
46  /// PICStyle - Which PIC style to use
47  ///
48  PICStyles::Style PICStyle;
49
50  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
51  /// none supported.
52  X86SSEEnum X86SSELevel;
53
54  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
55  ///
56  X863DNowEnum X863DNowLevel;
57
58  /// HasCMov - True if this processor has conditional move instructions
59  /// (generally pentium pro+).
60  bool HasCMov;
61
62  /// HasX86_64 - True if the processor supports X86-64 instructions.
63  ///
64  bool HasX86_64;
65
66  /// HasSSE4A - True if the processor supports SSE4A instructions.
67  bool HasSSE4A;
68
69  /// HasAVX - Target has AVX instructions
70  bool HasAVX;
71
72  /// HasFMA3 - Target has 3-operand fused multiply-add
73  bool HasFMA3;
74
75  /// HasFMA4 - Target has 4-operand fused multiply-add
76  bool HasFMA4;
77
78  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
79  bool IsBTMemSlow;
80
81  /// DarwinVers - Nonzero if this is a darwin platform: the numeric
82  /// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
83  unsigned char DarwinVers; // Is any darwin-x86 platform.
84
85  /// stackAlignment - The minimum alignment known to hold of the stack frame on
86  /// entry to the function and which must be maintained by every function.
87  unsigned stackAlignment;
88
89  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
90  ///
91  unsigned MaxInlineSizeThreshold;
92
93private:
94  /// Is64Bit - True if the processor supports 64-bit instructions and
95  /// pointer size is 64 bit.
96  bool Is64Bit;
97
98public:
99  enum {
100    isELF, isCygwin, isDarwin, isWindows, isMingw
101  } TargetType;
102
103  /// This constructor initializes the data members to match that
104  /// of the specified triple.
105  ///
106  X86Subtarget(const std::string &TT, const std::string &FS, bool is64Bit);
107
108  /// getStackAlignment - Returns the minimum alignment known to hold of the
109  /// stack frame on entry to the function and which must be maintained by every
110  /// function for this subtarget.
111  unsigned getStackAlignment() const { return stackAlignment; }
112
113  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
114  /// that still makes it profitable to inline the call.
115  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
116
117  /// ParseSubtargetFeatures - Parses features string setting specified
118  /// subtarget options.  Definition of function is auto generated by tblgen.
119  std::string ParseSubtargetFeatures(const std::string &FS,
120                                     const std::string &CPU);
121
122  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
123  /// instruction.
124  void AutoDetectSubtargetFeatures();
125
126  bool is64Bit() const { return Is64Bit; }
127
128  PICStyles::Style getPICStyle() const { return PICStyle; }
129  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
130
131  bool hasMMX() const { return X86SSELevel >= MMX; }
132  bool hasSSE1() const { return X86SSELevel >= SSE1; }
133  bool hasSSE2() const { return X86SSELevel >= SSE2; }
134  bool hasSSE3() const { return X86SSELevel >= SSE3; }
135  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
136  bool hasSSE41() const { return X86SSELevel >= SSE41; }
137  bool hasSSE42() const { return X86SSELevel >= SSE42; }
138  bool hasSSE4A() const { return HasSSE4A; }
139  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
140  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
141  bool hasAVX() const { return HasAVX; }
142  bool hasFMA3() const { return HasFMA3; }
143  bool hasFMA4() const { return HasFMA4; }
144  bool isBTMemSlow() const { return IsBTMemSlow; }
145
146  bool isTargetDarwin() const { return TargetType == isDarwin; }
147  bool isTargetELF() const { return TargetType == isELF; }
148
149  bool isTargetWindows() const { return TargetType == isWindows; }
150  bool isTargetMingw() const { return TargetType == isMingw; }
151  bool isTargetCygwin() const { return TargetType == isCygwin; }
152  bool isTargetCygMing() const {
153    return TargetType == isMingw || TargetType == isCygwin;
154  }
155
156  /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
157  bool isTargetCOFF() const {
158    return TargetType == isMingw || TargetType == isCygwin ||
159           TargetType == isWindows;
160  }
161
162  bool isTargetWin64() const {
163    return Is64Bit && (TargetType == isMingw || TargetType == isWindows);
164  }
165
166  std::string getDataLayout() const {
167    const char *p;
168    if (is64Bit())
169      p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-n8:16:32:64";
170    else if (isTargetDarwin())
171      p = "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-n8:16:32";
172    else
173      p = "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-n8:16:32";
174    return std::string(p);
175  }
176
177  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
178  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
179  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
180
181  bool isPICStyleStubPIC() const {
182    return PICStyle == PICStyles::StubPIC;
183  }
184
185  bool isPICStyleStubNoDynamic() const {
186    return PICStyle == PICStyles::StubDynamicNoPIC;
187  }
188  bool isPICStyleStubAny() const {
189    return PICStyle == PICStyles::StubDynamicNoPIC ||
190           PICStyle == PICStyles::StubPIC; }
191
192  /// getDarwinVers - Return the darwin version number, 8 = Tiger, 9 = Leopard,
193  /// 10 = Snow Leopard, etc.
194  unsigned getDarwinVers() const { return DarwinVers; }
195
196  /// ClassifyGlobalReference - Classify a global variable reference for the
197  /// current subtarget according to how we should reference it in a non-pcrel
198  /// context.
199  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
200                                        const TargetMachine &TM)const;
201
202  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
203  /// to immediate address.
204  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
205
206  /// This function returns the name of a function which has an interface
207  /// like the non-standard bzero function, if such a function exists on
208  /// the current subtarget and it is considered prefereable over
209  /// memset with zero passed as the second argument. Otherwise it
210  /// returns null.
211  const char *getBZeroEntry() const;
212
213  /// getSpecialAddressLatency - For targets where it is beneficial to
214  /// backschedule instructions that compute addresses, return a value
215  /// indicating the number of scheduling cycles of backscheduling that
216  /// should be attempted.
217  unsigned getSpecialAddressLatency() const;
218
219  /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
220  /// at 'More' optimization level.
221  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
222                             TargetSubtarget::AntiDepBreakMode& Mode,
223                             ExcludedRCVector& ExcludedRCs) const;
224};
225
226} // End llvm namespace
227
228#endif
229