XCoreISelLowering.cpp revision 2fabcb27761e0f07368f065fda0144d824e1e51c 
1//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation   ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the XCoreTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "xcore-lower"
15
16#include "XCoreISelLowering.h"
17#include "XCoreMachineFunctionInfo.h"
18#include "XCore.h"
19#include "XCoreTargetMachine.h"
20#include "XCoreSubtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/ADT/VectorExtras.h"
36#include <queue>
37#include <set>
38using namespace llvm;
39
40const char *XCoreTargetLowering::
41getTargetNodeName(unsigned Opcode) const
42{
43  switch (Opcode)
44  {
45    case XCoreISD::BL                : return "XCoreISD::BL";
46    case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
47    case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
48    case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
49    case XCoreISD::STWSP             : return "XCoreISD::STWSP";
50    case XCoreISD::RETSP             : return "XCoreISD::RETSP";
51    default                           : return NULL;
52  }
53}
54
55XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
56  : TargetLowering(XTM),
57    TM(XTM),
58    Subtarget(*XTM.getSubtargetImpl()) {
59
60  // Set up the register classes.
61  addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
62
63  // Compute derived properties from the register classes
64  computeRegisterProperties();
65
66  // Division is expensive
67  setIntDivIsCheap(false);
68
69  setShiftAmountType(MVT::i32);
70  // shl X, 32 == 0
71  setShiftAmountFlavor(Extend);
72  setStackPointerRegisterToSaveRestore(XCore::SP);
73
74  setSchedulingPreference(SchedulingForRegPressure);
75
76  // Use i32 for setcc operations results (slt, sgt, ...).
77  setBooleanContents(ZeroOrOneBooleanContent);
78
79  // XCore does not have the NodeTypes below.
80  setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
81  setOperationAction(ISD::SELECT_CC, MVT::i32,   Custom);
82  setOperationAction(ISD::ADDC, MVT::i32, Expand);
83  setOperationAction(ISD::ADDE, MVT::i32, Expand);
84  setOperationAction(ISD::SUBC, MVT::i32, Expand);
85  setOperationAction(ISD::SUBE, MVT::i32, Expand);
86
87  // Stop the combiner recombining select and set_cc
88  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
89
90  // 64bit
91  if (!Subtarget.isXS1A()) {
92    setOperationAction(ISD::ADD, MVT::i64, Custom);
93    setOperationAction(ISD::SUB, MVT::i64, Custom);
94  }
95  if (Subtarget.isXS1A()) {
96    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
97  }
98  setOperationAction(ISD::MULHS, MVT::i32, Expand);
99  setOperationAction(ISD::MULHU, MVT::i32, Expand);
100  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
101  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
102  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
103
104  // Bit Manipulation
105  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
106  setOperationAction(ISD::ROTL , MVT::i32, Expand);
107  setOperationAction(ISD::ROTR , MVT::i32, Expand);
108
109  setOperationAction(ISD::TRAP, MVT::Other, Legal);
110
111  // Expand jump tables for now
112  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
113  setOperationAction(ISD::JumpTable, MVT::i32, Custom);
114
115  // RET must be custom lowered, to meet ABI requirements
116  setOperationAction(ISD::RET,           MVT::Other, Custom);
117
118  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
119
120  // Thread Local Storage
121  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
122
123  // Conversion of i64 -> double produces constantpool nodes
124  setOperationAction(ISD::ConstantPool, MVT::i32,   Custom);
125
126  // Loads
127  setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
128  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
129  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
130
131  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
132  setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
133
134  // Varargs
135  setOperationAction(ISD::VAEND, MVT::Other, Expand);
136  setOperationAction(ISD::VACOPY, MVT::Other, Expand);
137  setOperationAction(ISD::VAARG, MVT::Other, Custom);
138  setOperationAction(ISD::VASTART, MVT::Other, Custom);
139
140  // Dynamic stack
141  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
142  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
143  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
144
145  // Debug
146  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
147  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
148}
149
150SDValue XCoreTargetLowering::
151LowerOperation(SDValue Op, SelectionDAG &DAG) {
152  switch (Op.getOpcode())
153  {
154  case ISD::CALL:             return LowerCALL(Op, DAG);
155  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
156  case ISD::RET:              return LowerRET(Op, DAG);
157  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
158  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
159  case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);
160  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
161  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
162  case ISD::VAARG:            return LowerVAARG(Op, DAG);
163  case ISD::VASTART:          return LowerVASTART(Op, DAG);
164  // FIXME: Remove these when LegalizeDAGTypes lands.
165  case ISD::ADD:
166  case ISD::SUB:              return ExpandADDSUB(Op.getNode(), DAG);
167  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
168  default:
169    assert(0 && "unimplemented operand");
170    return SDValue();
171  }
172}
173
174/// ReplaceNodeResults - Replace the results of node with an illegal result
175/// type with new values built out of custom code.
176void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
177                                             SmallVectorImpl<SDValue>&Results,
178                                             SelectionDAG &DAG) {
179  switch (N->getOpcode()) {
180  default:
181    assert(0 && "Don't know how to custom expand this!");
182    return;
183  case ISD::ADD:
184  case ISD::SUB:
185    Results.push_back(ExpandADDSUB(N, DAG));
186    return;
187  }
188}
189
190//===----------------------------------------------------------------------===//
191//  Misc Lower Operation implementation
192//===----------------------------------------------------------------------===//
193
194SDValue XCoreTargetLowering::
195LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
196{
197  SDValue Cond = DAG.getNode(ISD::SETCC, MVT::i32, Op.getOperand(2),
198                             Op.getOperand(3), Op.getOperand(4));
199  return DAG.getNode(ISD::SELECT, MVT::i32, Cond, Op.getOperand(0),
200                     Op.getOperand(1));
201}
202
203SDValue XCoreTargetLowering::
204getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG)
205{
206  if (isa<Function>(GV)) {
207    return DAG.getNode(XCoreISD::PCRelativeWrapper, MVT::i32, GA);
208  } else if (!Subtarget.isXS1A()) {
209    const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
210    if (!GVar) {
211      // If GV is an alias then use the aliasee to determine constness
212      if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
213        GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
214    }
215    bool isConst = GVar && GVar->isConstant();
216    if (isConst) {
217      return DAG.getNode(XCoreISD::CPRelativeWrapper, MVT::i32, GA);
218    }
219  }
220  return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, GA);
221}
222
223SDValue XCoreTargetLowering::
224LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
225{
226  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
227  SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
228  // If it's a debug information descriptor, don't mess with it.
229  if (DAG.isVerifiedDebugInfoDesc(Op))
230    return GA;
231  return getGlobalAddressWrapper(GA, GV, DAG);
232}
233
234static inline SDValue BuildGetId(SelectionDAG &DAG) {
235  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32,
236                     DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
237}
238
239static inline bool isZeroLengthArray(const Type *Ty) {
240  const ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty);
241  return AT && (AT->getNumElements() == 0);
242}
243
244SDValue XCoreTargetLowering::
245LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
246{
247  // transform to label + getid() * size
248  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
249  SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
250  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
251  if (!GVar) {
252    // If GV is an alias then use the aliasee to determine size
253    if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
254      GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
255  }
256  if (! GVar) {
257    assert(0 && "Thread local object not a GlobalVariable?");
258    return SDValue();
259  }
260  const Type *Ty = cast<PointerType>(GV->getType())->getElementType();
261  if (!Ty->isSized() || isZeroLengthArray(Ty)) {
262    cerr << "Size of thread local object " << GVar->getName()
263         << " is unknown\n";
264    abort();
265  }
266  SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
267  const TargetData *TD = TM.getTargetData();
268  unsigned Size = TD->getTypePaddedSize(Ty);
269  SDValue offset = DAG.getNode(ISD::MUL, MVT::i32, BuildGetId(DAG),
270                       DAG.getConstant(Size, MVT::i32));
271  return DAG.getNode(ISD::ADD, MVT::i32, base, offset);
272}
273
274SDValue XCoreTargetLowering::
275LowerConstantPool(SDValue Op, SelectionDAG &DAG)
276{
277  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
278  if (Subtarget.isXS1A()) {
279    assert(0 && "Lowering of constant pool unimplemented");
280    return SDValue();
281  } else {
282    MVT PtrVT = Op.getValueType();
283    SDValue Res;
284    if (CP->isMachineConstantPoolEntry()) {
285      Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
286                                      CP->getAlignment());
287    } else {
288      Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
289                                      CP->getAlignment());
290    }
291    return DAG.getNode(XCoreISD::CPRelativeWrapper, MVT::i32, Res);
292  }
293}
294
295SDValue XCoreTargetLowering::
296LowerJumpTable(SDValue Op, SelectionDAG &DAG)
297{
298  MVT PtrVT = Op.getValueType();
299  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
300  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
301  return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, JTI);
302}
303
304SDValue XCoreTargetLowering::
305ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
306{
307  assert(N->getValueType(0) == MVT::i64 &&
308         (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
309        "Unknown operand to lower!");
310  assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a");
311  DebugLoc dl = N->getDebugLoc();
312
313  // Extract components
314  SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
315                            N->getOperand(0),  DAG.getConstant(0, MVT::i32));
316  SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
317                            N->getOperand(0),  DAG.getConstant(1, MVT::i32));
318  SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
319                             N->getOperand(1), DAG.getConstant(0, MVT::i32));
320  SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
321                             N->getOperand(1), DAG.getConstant(1, MVT::i32));
322
323  // Expand
324  unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
325                                                   XCoreISD::LSUB;
326  SDValue Zero = DAG.getConstant(0, MVT::i32);
327  SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
328                                  LHSL, RHSL, Zero);
329  SDValue Lo(Carry.getNode(), 1);
330
331  SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
332                                  LHSH, RHSH, Carry);
333  SDValue Hi(Ignored.getNode(), 1);
334  // Merge the pieces
335  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
336}
337
338SDValue XCoreTargetLowering::
339LowerVAARG(SDValue Op, SelectionDAG &DAG)
340{
341  assert(0 && "unimplemented");
342  // FIX Arguments passed by reference need a extra dereference.
343  SDNode *Node = Op.getNode();
344  DebugLoc dl = Node->getDebugLoc();
345  const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
346  MVT VT = Node->getValueType(0);
347  SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
348                               Node->getOperand(1), V, 0);
349  // Increment the pointer, VAList, to the next vararg
350  SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
351                     DAG.getConstant(VT.getSizeInBits(),
352                                     getPointerTy()));
353  // Store the incremented VAList to the legalized pointer
354  Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0);
355  // Load the actual argument out of the pointer VAList
356  return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
357}
358
359SDValue XCoreTargetLowering::
360LowerVASTART(SDValue Op, SelectionDAG &DAG)
361{
362  DebugLoc dl = Op.getDebugLoc();
363  // vastart stores the address of the VarArgsFrameIndex slot into the
364  // memory location argument
365  MachineFunction &MF = DAG.getMachineFunction();
366  XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
367  SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
368  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
369  return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0);
370}
371
372SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
373  DebugLoc dl = Op.getDebugLoc();
374  // Depths > 0 not supported yet!
375  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
376    return SDValue();
377
378  MachineFunction &MF = DAG.getMachineFunction();
379  const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
380  return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
381                            RegInfo->getFrameRegister(MF), MVT::i32);
382}
383
384//===----------------------------------------------------------------------===//
385//                      Calling Convention Implementation
386//
387//  The lower operations present on calling convention works on this order:
388//      LowerCALL (virt regs --> phys regs, virt regs --> stack)
389//      LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
390//      LowerRET (virt regs --> phys regs)
391//      LowerCALL (phys regs --> virt regs)
392//
393//===----------------------------------------------------------------------===//
394
395#include "XCoreGenCallingConv.inc"
396
397//===----------------------------------------------------------------------===//
398//                  CALL Calling Convention Implementation
399//===----------------------------------------------------------------------===//
400
401/// XCore custom CALL implementation
402SDValue XCoreTargetLowering::
403LowerCALL(SDValue Op, SelectionDAG &DAG)
404{
405  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
406  unsigned CallingConv = TheCall->getCallingConv();
407  // For now, only CallingConv::C implemented
408  switch (CallingConv)
409  {
410    default:
411      assert(0 && "Unsupported calling convention");
412    case CallingConv::Fast:
413    case CallingConv::C:
414      return LowerCCCCallTo(Op, DAG, CallingConv);
415  }
416}
417
418/// LowerCCCCallTo - functions arguments are copied from virtual
419/// regs to (physical regs)/(stack frame), CALLSEQ_START and
420/// CALLSEQ_END are emitted.
421/// TODO: isTailCall, sret.
422SDValue XCoreTargetLowering::
423LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
424{
425  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
426  SDValue Chain  = TheCall->getChain();
427  SDValue Callee = TheCall->getCallee();
428  bool isVarArg  = TheCall->isVarArg();
429  DebugLoc dl = Op.getDebugLoc();
430
431  // Analyze operands of the call, assigning locations to each operand.
432  SmallVector<CCValAssign, 16> ArgLocs;
433  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
434
435  // The ABI dictates there should be one stack slot available to the callee
436  // on function entry (for saving lr).
437  CCInfo.AllocateStack(4, 4);
438
439  CCInfo.AnalyzeCallOperands(TheCall, CC_XCore);
440
441  // Get a count of how many bytes are to be pushed on the stack.
442  unsigned NumBytes = CCInfo.getNextStackOffset();
443
444  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
445                                 getPointerTy(), true));
446
447  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
448  SmallVector<SDValue, 12> MemOpChains;
449
450  // Walk the register/memloc assignments, inserting copies/loads.
451  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
452    CCValAssign &VA = ArgLocs[i];
453
454    // Arguments start after the 5 first operands of ISD::CALL
455    SDValue Arg = TheCall->getArg(i);
456
457    // Promote the value if needed.
458    switch (VA.getLocInfo()) {
459      default: assert(0 && "Unknown loc info!");
460      case CCValAssign::Full: break;
461      case CCValAssign::SExt:
462        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
463        break;
464      case CCValAssign::ZExt:
465        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
466        break;
467      case CCValAssign::AExt:
468        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
469        break;
470    }
471
472    // Arguments that can be passed on register must be kept at
473    // RegsToPass vector
474    if (VA.isRegLoc()) {
475      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
476    } else {
477      assert(VA.isMemLoc());
478
479      int Offset = VA.getLocMemOffset();
480
481      MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
482                                        Chain, Arg,
483                                        DAG.getConstant(Offset/4, MVT::i32)));
484    }
485  }
486
487  // Transform all store nodes into one single node because
488  // all store nodes are independent of each other.
489  if (!MemOpChains.empty())
490    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
491                        &MemOpChains[0], MemOpChains.size());
492
493  // Build a sequence of copy-to-reg nodes chained together with token
494  // chain and flag operands which copy the outgoing args into registers.
495  // The InFlag in necessary since all emited instructions must be
496  // stuck together.
497  SDValue InFlag;
498  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
499    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
500                             RegsToPass[i].second, InFlag);
501    InFlag = Chain.getValue(1);
502  }
503
504  // If the callee is a GlobalAddress node (quite common, every direct call is)
505  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
506  // Likewise ExternalSymbol -> TargetExternalSymbol.
507  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
508    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
509  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
510    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
511
512  // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
513  //             = Chain, Callee, Reg#1, Reg#2, ...
514  //
515  // Returns a chain & a flag for retval copy to use.
516  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
517  SmallVector<SDValue, 8> Ops;
518  Ops.push_back(Chain);
519  Ops.push_back(Callee);
520
521  // Add argument registers to the end of the list so that they are
522  // known live into the call.
523  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
524    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
525                                  RegsToPass[i].second.getValueType()));
526
527  if (InFlag.getNode())
528    Ops.push_back(InFlag);
529
530  Chain  = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
531  InFlag = Chain.getValue(1);
532
533  // Create the CALLSEQ_END node.
534  Chain = DAG.getCALLSEQ_END(Chain,
535                             DAG.getConstant(NumBytes, getPointerTy(), true),
536                             DAG.getConstant(0, getPointerTy(), true),
537                             InFlag);
538  InFlag = Chain.getValue(1);
539
540  // Handle result values, copying them out of physregs into vregs that we
541  // return.
542  return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
543                 Op.getResNo());
544}
545
546/// LowerCallResult - Lower the result values of an ISD::CALL into the
547/// appropriate copies out of appropriate physical registers.  This assumes that
548/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
549/// being lowered. Returns a SDNode with the same number of values as the
550/// ISD::CALL.
551SDNode *XCoreTargetLowering::
552LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
553        unsigned CallingConv, SelectionDAG &DAG) {
554  bool isVarArg = TheCall->isVarArg();
555  DebugLoc dl = TheCall->getDebugLoc();
556
557  // Assign locations to each value returned by this call.
558  SmallVector<CCValAssign, 16> RVLocs;
559  CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
560
561  CCInfo.AnalyzeCallResult(TheCall, RetCC_XCore);
562  SmallVector<SDValue, 8> ResultVals;
563
564  // Copy all of the result registers out of their specified physreg.
565  for (unsigned i = 0; i != RVLocs.size(); ++i) {
566    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
567                                 RVLocs[i].getValVT(), InFlag).getValue(1);
568    InFlag = Chain.getValue(2);
569    ResultVals.push_back(Chain.getValue(0));
570  }
571
572  ResultVals.push_back(Chain);
573
574  // Merge everything together with a MERGE_VALUES node.
575  return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
576                     &ResultVals[0], ResultVals.size()).getNode();
577}
578
579//===----------------------------------------------------------------------===//
580//             FORMAL_ARGUMENTS Calling Convention Implementation
581//===----------------------------------------------------------------------===//
582
583/// XCore custom FORMAL_ARGUMENTS implementation
584SDValue XCoreTargetLowering::
585LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
586{
587  unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
588  switch(CC)
589  {
590    default:
591      assert(0 && "Unsupported calling convention");
592    case CallingConv::C:
593    case CallingConv::Fast:
594      return LowerCCCArguments(Op, DAG);
595  }
596}
597
598/// LowerCCCArguments - transform physical registers into
599/// virtual registers and generate load operations for
600/// arguments places on the stack.
601/// TODO: sret
602SDValue XCoreTargetLowering::
603LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
604{
605  MachineFunction &MF = DAG.getMachineFunction();
606  MachineFrameInfo *MFI = MF.getFrameInfo();
607  MachineRegisterInfo &RegInfo = MF.getRegInfo();
608  SDValue Root = Op.getOperand(0);
609  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
610  unsigned CC = MF.getFunction()->getCallingConv();
611  DebugLoc dl = Op.getDebugLoc();
612
613  // Assign locations to all of the incoming arguments.
614  SmallVector<CCValAssign, 16> ArgLocs;
615  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
616
617  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_XCore);
618
619  unsigned StackSlotSize = XCoreFrameInfo::stackSlotSize();
620
621  SmallVector<SDValue, 16> ArgValues;
622
623  unsigned LRSaveSize = StackSlotSize;
624
625  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
626
627    CCValAssign &VA = ArgLocs[i];
628
629    if (VA.isRegLoc()) {
630      // Arguments passed in registers
631      MVT RegVT = VA.getLocVT();
632      switch (RegVT.getSimpleVT()) {
633      default:
634        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
635             << RegVT.getSimpleVT()
636             << "\n";
637        abort();
638      case MVT::i32:
639        unsigned VReg = RegInfo.createVirtualRegister(
640                          XCore::GRRegsRegisterClass);
641        RegInfo.addLiveIn(VA.getLocReg(), VReg);
642        ArgValues.push_back(DAG.getCopyFromReg(Root, dl, VReg, RegVT));
643      }
644    } else {
645      // sanity check
646      assert(VA.isMemLoc());
647      // Load the argument to a virtual register
648      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
649      if (ObjSize > StackSlotSize) {
650        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
651             << VA.getLocVT().getSimpleVT()
652             << "\n";
653      }
654      // Create the frame index object for this incoming parameter...
655      int FI = MFI->CreateFixedObject(ObjSize,
656                                      LRSaveSize + VA.getLocMemOffset());
657
658      // Create the SelectionDAG nodes corresponding to a load
659      //from this parameter
660      SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
661      ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN, NULL, 0));
662    }
663  }
664
665  if (isVarArg) {
666    /* Argument registers */
667    static const unsigned ArgRegs[] = {
668      XCore::R0, XCore::R1, XCore::R2, XCore::R3
669    };
670    XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
671    unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
672                                                     array_lengthof(ArgRegs));
673    if (FirstVAReg < array_lengthof(ArgRegs)) {
674      SmallVector<SDValue, 4> MemOps;
675      int offset = 0;
676      // Save remaining registers, storing higher register numbers at a higher
677      // address
678      for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) {
679        // Create a stack slot
680        int FI = MFI->CreateFixedObject(4, offset);
681        if (i == FirstVAReg) {
682          XFI->setVarArgsFrameIndex(FI);
683        }
684        offset -= StackSlotSize;
685        SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
686        // Move argument from phys reg -> virt reg
687        unsigned VReg = RegInfo.createVirtualRegister(
688                          XCore::GRRegsRegisterClass);
689        RegInfo.addLiveIn(ArgRegs[i], VReg);
690        SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
691        // Move argument from virt reg -> stack
692        SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
693        MemOps.push_back(Store);
694      }
695      if (!MemOps.empty())
696        Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
697                           &MemOps[0], MemOps.size());
698    } else {
699      // This will point to the next argument passed via stack.
700      XFI->setVarArgsFrameIndex(
701          MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset()));
702    }
703  }
704
705  ArgValues.push_back(Root);
706
707  // Return the new list of results.
708  std::vector<MVT> RetVT(Op.getNode()->value_begin(),
709                                    Op.getNode()->value_end());
710  return DAG.getNode(ISD::MERGE_VALUES, dl, RetVT,
711                     &ArgValues[0], ArgValues.size());
712}
713
714//===----------------------------------------------------------------------===//
715//               Return Value Calling Convention Implementation
716//===----------------------------------------------------------------------===//
717
718SDValue XCoreTargetLowering::
719LowerRET(SDValue Op, SelectionDAG &DAG)
720{
721  // CCValAssign - represent the assignment of
722  // the return value to a location
723  SmallVector<CCValAssign, 16> RVLocs;
724  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
725  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
726  DebugLoc dl = Op.getDebugLoc();
727
728  // CCState - Info about the registers and stack slot.
729  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
730
731  // Analize return values of ISD::RET
732  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_XCore);
733
734  // If this is the first return lowered for this function, add
735  // the regs to the liveout set for the function.
736  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
737    for (unsigned i = 0; i != RVLocs.size(); ++i)
738      if (RVLocs[i].isRegLoc())
739        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
740  }
741
742  // The chain is always operand #0
743  SDValue Chain = Op.getOperand(0);
744  SDValue Flag;
745
746  // Copy the result values into the output registers.
747  for (unsigned i = 0; i != RVLocs.size(); ++i) {
748    CCValAssign &VA = RVLocs[i];
749    assert(VA.isRegLoc() && "Can only return in registers!");
750
751    // ISD::RET => ret chain, (regnum1,val1), ...
752    // So i*2+1 index only the regnums
753    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
754                             Op.getOperand(i*2+1), Flag);
755
756    // guarantee that all emitted copies are
757    // stuck together, avoiding something bad
758    Flag = Chain.getValue(1);
759  }
760
761  // Return on XCore is always a "retsp 0"
762  if (Flag.getNode())
763    return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
764                       Chain, DAG.getConstant(0, MVT::i32), Flag);
765  else // Return Void
766    return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
767                       Chain, DAG.getConstant(0, MVT::i32));
768}
769
770//===----------------------------------------------------------------------===//
771//  Other Lowering Code
772//===----------------------------------------------------------------------===//
773
774MachineBasicBlock *
775XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
776                                               MachineBasicBlock *BB) {
777  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
778  assert((MI->getOpcode() == XCore::SELECT_CC) &&
779         "Unexpected instr type to insert");
780
781  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
782  // control-flow pattern.  The incoming instruction knows the destination vreg
783  // to set, the condition code register to branch on, the true/false values to
784  // select between, and a branch opcode to use.
785  const BasicBlock *LLVM_BB = BB->getBasicBlock();
786  MachineFunction::iterator It = BB;
787  ++It;
788
789  //  thisMBB:
790  //  ...
791  //   TrueVal = ...
792  //   cmpTY ccX, r1, r2
793  //   bCC copy1MBB
794  //   fallthrough --> copy0MBB
795  MachineBasicBlock *thisMBB = BB;
796  MachineFunction *F = BB->getParent();
797  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
798  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
799  BuildMI(BB, TII.get(XCore::BRFT_lru6))
800    .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
801  F->insert(It, copy0MBB);
802  F->insert(It, sinkMBB);
803  // Update machine-CFG edges by transferring all successors of the current
804  // block to the new block which will contain the Phi node for the select.
805  sinkMBB->transferSuccessors(BB);
806  // Next, add the true and fallthrough blocks as its successors.
807  BB->addSuccessor(copy0MBB);
808  BB->addSuccessor(sinkMBB);
809
810  //  copy0MBB:
811  //   %FalseValue = ...
812  //   # fallthrough to sinkMBB
813  BB = copy0MBB;
814
815  // Update machine-CFG edges
816  BB->addSuccessor(sinkMBB);
817
818  //  sinkMBB:
819  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
820  //  ...
821  BB = sinkMBB;
822  BuildMI(BB, TII.get(XCore::PHI), MI->getOperand(0).getReg())
823    .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
824    .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
825
826  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
827  return BB;
828}
829
830//===----------------------------------------------------------------------===//
831//  Addressing mode description hooks
832//===----------------------------------------------------------------------===//
833
834static inline bool isImmUs(int64_t val)
835{
836  return (val >= 0 && val <= 11);
837}
838
839static inline bool isImmUs2(int64_t val)
840{
841  return (val%2 == 0 && isImmUs(val/2));
842}
843
844static inline bool isImmUs4(int64_t val)
845{
846  return (val%4 == 0 && isImmUs(val/4));
847}
848
849/// isLegalAddressingMode - Return true if the addressing mode represented
850/// by AM is legal for this target, for a load/store of the specified type.
851bool
852XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
853                                              const Type *Ty) const {
854  MVT VT = getValueType(Ty, true);
855  // Get expected value type after legalization
856  switch (VT.getSimpleVT()) {
857  // Legal load / stores
858  case MVT::i8:
859  case MVT::i16:
860  case MVT::i32:
861    break;
862  // Expand i1 -> i8
863  case MVT::i1:
864    VT = MVT::i8;
865    break;
866  // Everything else is lowered to words
867  default:
868    VT = MVT::i32;
869    break;
870  }
871  if (AM.BaseGV) {
872    return VT == MVT::i32 && !AM.HasBaseReg && AM.Scale == 0 &&
873                 AM.BaseOffs%4 == 0;
874  }
875
876  switch (VT.getSimpleVT()) {
877  default:
878    return false;
879  case MVT::i8:
880    // reg + imm
881    if (AM.Scale == 0) {
882      return isImmUs(AM.BaseOffs);
883    }
884    return AM.Scale == 1 && AM.BaseOffs == 0;
885  case MVT::i16:
886    // reg + imm
887    if (AM.Scale == 0) {
888      return isImmUs2(AM.BaseOffs);
889    }
890    return AM.Scale == 2 && AM.BaseOffs == 0;
891  case MVT::i32:
892    // reg + imm
893    if (AM.Scale == 0) {
894      return isImmUs4(AM.BaseOffs);
895    }
896    // reg + reg<<2
897    return AM.Scale == 4 && AM.BaseOffs == 0;
898  }
899
900  return false;
901}
902
903//===----------------------------------------------------------------------===//
904//                           XCore Inline Assembly Support
905//===----------------------------------------------------------------------===//
906
907std::vector<unsigned> XCoreTargetLowering::
908getRegClassForInlineAsmConstraint(const std::string &Constraint,
909                                  MVT VT) const
910{
911  if (Constraint.size() != 1)
912    return std::vector<unsigned>();
913
914  switch (Constraint[0]) {
915    default : break;
916    case 'r':
917      return make_vector<unsigned>(XCore::R0, XCore::R1,  XCore::R2,
918                                   XCore::R3, XCore::R4,  XCore::R5,
919                                   XCore::R6, XCore::R7,  XCore::R8,
920                                   XCore::R9, XCore::R10, XCore::R11, 0);
921      break;
922  }
923  return std::vector<unsigned>();
924}
925