XCoreISelLowering.cpp revision ccc015d4314e966253668deec2b18a0d3e0cf4c0 
1//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the XCoreTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "xcore-lower"
15
16#include "XCoreISelLowering.h"
17#include "XCoreMachineFunctionInfo.h"
18#include "XCore.h"
19#include "XCoreTargetObjectFile.h"
20#include "XCoreTargetMachine.h"
21#include "XCoreSubtarget.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/CallingConv.h"
26#include "llvm/GlobalVariable.h"
27#include "llvm/GlobalAlias.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/MachineJumpTableInfo.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/SelectionDAGISel.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41const char *XCoreTargetLowering::
42getTargetNodeName(unsigned Opcode) const
43{
44  switch (Opcode)
45  {
46    case XCoreISD::BL                : return "XCoreISD::BL";
47    case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
48    case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
49    case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
50    case XCoreISD::STWSP             : return "XCoreISD::STWSP";
51    case XCoreISD::RETSP             : return "XCoreISD::RETSP";
52    case XCoreISD::LADD              : return "XCoreISD::LADD";
53    case XCoreISD::LSUB              : return "XCoreISD::LSUB";
54    case XCoreISD::LMUL              : return "XCoreISD::LMUL";
55    case XCoreISD::MACCU             : return "XCoreISD::MACCU";
56    case XCoreISD::MACCS             : return "XCoreISD::MACCS";
57    case XCoreISD::BR_JT             : return "XCoreISD::BR_JT";
58    case XCoreISD::BR_JT32           : return "XCoreISD::BR_JT32";
59    default                          : return NULL;
60  }
61}
62
63XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
64  : TargetLowering(XTM, new XCoreTargetObjectFile()),
65    TM(XTM),
66    Subtarget(*XTM.getSubtargetImpl()) {
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
70
71  // Compute derived properties from the register classes
72  computeRegisterProperties();
73
74  // Division is expensive
75  setIntDivIsCheap(false);
76
77  setStackPointerRegisterToSaveRestore(XCore::SP);
78
79  setSchedulingPreference(Sched::RegPressure);
80
81  // Use i32 for setcc operations results (slt, sgt, ...).
82  setBooleanContents(ZeroOrOneBooleanContent);
83  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
84
85  // XCore does not have the NodeTypes below.
86  setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
87  setOperationAction(ISD::SELECT_CC, MVT::i32,   Custom);
88  setOperationAction(ISD::ADDC, MVT::i32, Expand);
89  setOperationAction(ISD::ADDE, MVT::i32, Expand);
90  setOperationAction(ISD::SUBC, MVT::i32, Expand);
91  setOperationAction(ISD::SUBE, MVT::i32, Expand);
92
93  // Stop the combiner recombining select and set_cc
94  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
95
96  // 64bit
97  setOperationAction(ISD::ADD, MVT::i64, Custom);
98  setOperationAction(ISD::SUB, MVT::i64, Custom);
99  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
100  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
101  setOperationAction(ISD::MULHS, MVT::i32, Expand);
102  setOperationAction(ISD::MULHU, MVT::i32, Expand);
103  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
104  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
105  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
106
107  // Bit Manipulation
108  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
109  setOperationAction(ISD::ROTL , MVT::i32, Expand);
110  setOperationAction(ISD::ROTR , MVT::i32, Expand);
111  setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
112  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
113
114  setOperationAction(ISD::TRAP, MVT::Other, Legal);
115
116  // Jump tables.
117  setOperationAction(ISD::BR_JT, MVT::Other, Custom);
118
119  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
120  setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
121
122  // Thread Local Storage
123  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
124
125  // Conversion of i64 -> double produces constantpool nodes
126  setOperationAction(ISD::ConstantPool, MVT::i32,   Custom);
127
128  // Loads
129  setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
130  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
131  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
132
133  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
134  setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
135
136  // Custom expand misaligned loads / stores.
137  setOperationAction(ISD::LOAD, MVT::i32, Custom);
138  setOperationAction(ISD::STORE, MVT::i32, Custom);
139
140  // Varargs
141  setOperationAction(ISD::VAEND, MVT::Other, Expand);
142  setOperationAction(ISD::VACOPY, MVT::Other, Expand);
143  setOperationAction(ISD::VAARG, MVT::Other, Custom);
144  setOperationAction(ISD::VASTART, MVT::Other, Custom);
145
146  // Dynamic stack
147  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
148  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
149  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
150
151  // TRAMPOLINE is custom lowered.
152  setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
153  setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
154
155  maxStoresPerMemset = maxStoresPerMemsetOptSize = 4;
156  maxStoresPerMemmove = maxStoresPerMemmoveOptSize
157    = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2;
158
159  // We have target-specific dag combine patterns for the following nodes:
160  setTargetDAGCombine(ISD::STORE);
161  setTargetDAGCombine(ISD::ADD);
162
163  setMinFunctionAlignment(1);
164}
165
166SDValue XCoreTargetLowering::
167LowerOperation(SDValue Op, SelectionDAG &DAG) const {
168  switch (Op.getOpcode())
169  {
170  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
171  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
172  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
173  case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);
174  case ISD::BR_JT:            return LowerBR_JT(Op, DAG);
175  case ISD::LOAD:             return LowerLOAD(Op, DAG);
176  case ISD::STORE:            return LowerSTORE(Op, DAG);
177  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
178  case ISD::VAARG:            return LowerVAARG(Op, DAG);
179  case ISD::VASTART:          return LowerVASTART(Op, DAG);
180  case ISD::SMUL_LOHI:        return LowerSMUL_LOHI(Op, DAG);
181  case ISD::UMUL_LOHI:        return LowerUMUL_LOHI(Op, DAG);
182  // FIXME: Remove these when LegalizeDAGTypes lands.
183  case ISD::ADD:
184  case ISD::SUB:              return ExpandADDSUB(Op.getNode(), DAG);
185  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
186  case ISD::INIT_TRAMPOLINE:  return LowerINIT_TRAMPOLINE(Op, DAG);
187  case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
188  default:
189    llvm_unreachable("unimplemented operand");
190  }
191}
192
193/// ReplaceNodeResults - Replace the results of node with an illegal result
194/// type with new values built out of custom code.
195void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
196                                             SmallVectorImpl<SDValue>&Results,
197                                             SelectionDAG &DAG) const {
198  switch (N->getOpcode()) {
199  default:
200    llvm_unreachable("Don't know how to custom expand this!");
201  case ISD::ADD:
202  case ISD::SUB:
203    Results.push_back(ExpandADDSUB(N, DAG));
204    return;
205  }
206}
207
208//===----------------------------------------------------------------------===//
209//  Misc Lower Operation implementation
210//===----------------------------------------------------------------------===//
211
212SDValue XCoreTargetLowering::
213LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
214{
215  DebugLoc dl = Op.getDebugLoc();
216  SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
217                             Op.getOperand(3), Op.getOperand(4));
218  return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
219                     Op.getOperand(1));
220}
221
222SDValue XCoreTargetLowering::
223getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
224                        SelectionDAG &DAG) const
225{
226  // FIXME there is no actual debug info here
227  DebugLoc dl = GA.getDebugLoc();
228  const GlobalValue *UnderlyingGV = GV;
229  // If GV is an alias then use the aliasee to determine the wrapper type
230  if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
231    UnderlyingGV = GA->resolveAliasedGlobal();
232  if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(UnderlyingGV)) {
233    if (GVar->isConstant())
234      return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
235    return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
236  }
237  return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
238}
239
240SDValue XCoreTargetLowering::
241LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
242{
243  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
244  SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), MVT::i32);
245  return getGlobalAddressWrapper(GA, GV, DAG);
246}
247
248static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
249  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
250                     DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
251}
252
253static inline bool isZeroLengthArray(Type *Ty) {
254  ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty);
255  return AT && (AT->getNumElements() == 0);
256}
257
258SDValue XCoreTargetLowering::
259LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
260{
261  // FIXME there isn't really debug info here
262  DebugLoc dl = Op.getDebugLoc();
263  // transform to label + getid() * size
264  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
265  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
266  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
267  if (!GVar) {
268    // If GV is an alias then use the aliasee to determine size
269    if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
270      GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
271  }
272  if (!GVar) {
273    llvm_unreachable("Thread local object not a GlobalVariable?");
274  }
275  Type *Ty = cast<PointerType>(GV->getType())->getElementType();
276  if (!Ty->isSized() || isZeroLengthArray(Ty)) {
277#ifndef NDEBUG
278    errs() << "Size of thread local object " << GVar->getName()
279           << " is unknown\n";
280#endif
281    llvm_unreachable(0);
282  }
283  SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
284  const DataLayout *TD = TM.getDataLayout();
285  unsigned Size = TD->getTypeAllocSize(Ty);
286  SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
287                       DAG.getConstant(Size, MVT::i32));
288  return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
289}
290
291SDValue XCoreTargetLowering::
292LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
293{
294  DebugLoc DL = Op.getDebugLoc();
295
296  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
297  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
298
299  return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
300}
301
302SDValue XCoreTargetLowering::
303LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
304{
305  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
306  // FIXME there isn't really debug info here
307  DebugLoc dl = CP->getDebugLoc();
308  EVT PtrVT = Op.getValueType();
309  SDValue Res;
310  if (CP->isMachineConstantPoolEntry()) {
311    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
312                                    CP->getAlignment());
313  } else {
314    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
315                                    CP->getAlignment());
316  }
317  return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
318}
319
320unsigned XCoreTargetLowering::getJumpTableEncoding() const {
321  return MachineJumpTableInfo::EK_Inline;
322}
323
324SDValue XCoreTargetLowering::
325LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
326{
327  SDValue Chain = Op.getOperand(0);
328  SDValue Table = Op.getOperand(1);
329  SDValue Index = Op.getOperand(2);
330  DebugLoc dl = Op.getDebugLoc();
331  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
332  unsigned JTI = JT->getIndex();
333  MachineFunction &MF = DAG.getMachineFunction();
334  const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
335  SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
336
337  unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
338  if (NumEntries <= 32) {
339    return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
340  }
341  assert((NumEntries >> 31) == 0);
342  SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
343                                    DAG.getConstant(1, MVT::i32));
344  return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
345                     ScaledIndex);
346}
347
348static bool
349IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase,
350                                    int64_t &Offset)
351{
352  if (Addr.getOpcode() != ISD::ADD) {
353    return false;
354  }
355  ConstantSDNode *CN = 0;
356  if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
357    return false;
358  }
359  int64_t off = CN->getSExtValue();
360  const SDValue &Base = Addr.getOperand(0);
361  const SDValue *Root = &Base;
362  if (Base.getOpcode() == ISD::ADD &&
363      Base.getOperand(1).getOpcode() == ISD::SHL) {
364    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1)
365                                                      .getOperand(1));
366    if (CN && (CN->getSExtValue() >= 2)) {
367      Root = &Base.getOperand(0);
368    }
369  }
370  if (isa<FrameIndexSDNode>(*Root)) {
371    // All frame indicies are word aligned
372    AlignedBase = Base;
373    Offset = off;
374    return true;
375  }
376  if (Root->getOpcode() == XCoreISD::DPRelativeWrapper ||
377      Root->getOpcode() == XCoreISD::CPRelativeWrapper) {
378    // All dp / cp relative addresses are word aligned
379    AlignedBase = Base;
380    Offset = off;
381    return true;
382  }
383  // Check for an aligned global variable.
384  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) {
385    const GlobalValue *GV = GA->getGlobal();
386    if (GA->getOffset() == 0 && GV->getAlignment() >= 4) {
387      AlignedBase = Base;
388      Offset = off;
389      return true;
390    }
391  }
392  return false;
393}
394
395SDValue XCoreTargetLowering::
396LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
397  LoadSDNode *LD = cast<LoadSDNode>(Op);
398  assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
399         "Unexpected extension type");
400  assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
401  if (allowsUnalignedMemoryAccesses(LD->getMemoryVT()))
402    return SDValue();
403
404  unsigned ABIAlignment = getDataLayout()->
405    getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
406  // Leave aligned load alone.
407  if (LD->getAlignment() >= ABIAlignment)
408    return SDValue();
409
410  SDValue Chain = LD->getChain();
411  SDValue BasePtr = LD->getBasePtr();
412  DebugLoc DL = Op.getDebugLoc();
413
414  SDValue Base;
415  int64_t Offset;
416  if (!LD->isVolatile() &&
417      IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) {
418    if (Offset % 4 == 0) {
419      // We've managed to infer better alignment information than the load
420      // already has. Use an aligned load.
421      //
422      return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
423                         MachinePointerInfo(),
424                         false, false, false, 0);
425    }
426    // Lower to
427    // ldw low, base[offset >> 2]
428    // ldw high, base[(offset >> 2) + 1]
429    // shr low_shifted, low, (offset & 0x3) * 8
430    // shl high_shifted, high, 32 - (offset & 0x3) * 8
431    // or result, low_shifted, high_shifted
432    SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32);
433    SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32);
434    SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
435    SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
436
437    SDValue LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowOffset);
438    SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset);
439
440    SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
441                              LowAddr, MachinePointerInfo(),
442                              false, false, false, 0);
443    SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
444                               HighAddr, MachinePointerInfo(),
445                               false, false, false, 0);
446    SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
447    SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
448    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
449    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
450                             High.getValue(1));
451    SDValue Ops[] = { Result, Chain };
452    return DAG.getMergeValues(Ops, 2, DL);
453  }
454
455  if (LD->getAlignment() == 2) {
456    SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
457                                 BasePtr, LD->getPointerInfo(), MVT::i16,
458                                 LD->isVolatile(), LD->isNonTemporal(), 2);
459    SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
460                                   DAG.getConstant(2, MVT::i32));
461    SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
462                                  HighAddr,
463                                  LD->getPointerInfo().getWithOffset(2),
464                                  MVT::i16, LD->isVolatile(),
465                                  LD->isNonTemporal(), 2);
466    SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
467                                      DAG.getConstant(16, MVT::i32));
468    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
469    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
470                             High.getValue(1));
471    SDValue Ops[] = { Result, Chain };
472    return DAG.getMergeValues(Ops, 2, DL);
473  }
474
475  // Lower to a call to __misaligned_load(BasePtr).
476  Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
477  TargetLowering::ArgListTy Args;
478  TargetLowering::ArgListEntry Entry;
479
480  Entry.Ty = IntPtrTy;
481  Entry.Node = BasePtr;
482  Args.push_back(Entry);
483
484  TargetLowering::CallLoweringInfo CLI(Chain, IntPtrTy, false, false,
485                    false, false, 0, CallingConv::C, /*isTailCall=*/false,
486                    /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
487                    DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
488                    Args, DAG, DL);
489  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
490
491  SDValue Ops[] =
492    { CallResult.first, CallResult.second };
493
494  return DAG.getMergeValues(Ops, 2, DL);
495}
496
497SDValue XCoreTargetLowering::
498LowerSTORE(SDValue Op, SelectionDAG &DAG) const
499{
500  StoreSDNode *ST = cast<StoreSDNode>(Op);
501  assert(!ST->isTruncatingStore() && "Unexpected store type");
502  assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
503  if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
504    return SDValue();
505  }
506  unsigned ABIAlignment = getDataLayout()->
507    getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
508  // Leave aligned store alone.
509  if (ST->getAlignment() >= ABIAlignment) {
510    return SDValue();
511  }
512  SDValue Chain = ST->getChain();
513  SDValue BasePtr = ST->getBasePtr();
514  SDValue Value = ST->getValue();
515  DebugLoc dl = Op.getDebugLoc();
516
517  if (ST->getAlignment() == 2) {
518    SDValue Low = Value;
519    SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
520                                      DAG.getConstant(16, MVT::i32));
521    SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
522                                         ST->getPointerInfo(), MVT::i16,
523                                         ST->isVolatile(), ST->isNonTemporal(),
524                                         2);
525    SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
526                                   DAG.getConstant(2, MVT::i32));
527    SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
528                                          ST->getPointerInfo().getWithOffset(2),
529                                          MVT::i16, ST->isVolatile(),
530                                          ST->isNonTemporal(), 2);
531    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
532  }
533
534  // Lower to a call to __misaligned_store(BasePtr, Value).
535  Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
536  TargetLowering::ArgListTy Args;
537  TargetLowering::ArgListEntry Entry;
538
539  Entry.Ty = IntPtrTy;
540  Entry.Node = BasePtr;
541  Args.push_back(Entry);
542
543  Entry.Node = Value;
544  Args.push_back(Entry);
545
546  TargetLowering::CallLoweringInfo CLI(Chain,
547                    Type::getVoidTy(*DAG.getContext()), false, false,
548                    false, false, 0, CallingConv::C, /*isTailCall=*/false,
549                    /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
550                    DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
551                    Args, DAG, dl);
552  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
553
554  return CallResult.second;
555}
556
557SDValue XCoreTargetLowering::
558LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
559{
560  assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
561         "Unexpected operand to lower!");
562  DebugLoc dl = Op.getDebugLoc();
563  SDValue LHS = Op.getOperand(0);
564  SDValue RHS = Op.getOperand(1);
565  SDValue Zero = DAG.getConstant(0, MVT::i32);
566  SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
567                           DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
568                           LHS, RHS);
569  SDValue Lo(Hi.getNode(), 1);
570  SDValue Ops[] = { Lo, Hi };
571  return DAG.getMergeValues(Ops, 2, dl);
572}
573
574SDValue XCoreTargetLowering::
575LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
576{
577  assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
578         "Unexpected operand to lower!");
579  DebugLoc dl = Op.getDebugLoc();
580  SDValue LHS = Op.getOperand(0);
581  SDValue RHS = Op.getOperand(1);
582  SDValue Zero = DAG.getConstant(0, MVT::i32);
583  SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
584                           DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
585                           Zero, Zero);
586  SDValue Lo(Hi.getNode(), 1);
587  SDValue Ops[] = { Lo, Hi };
588  return DAG.getMergeValues(Ops, 2, dl);
589}
590
591/// isADDADDMUL - Return whether Op is in a form that is equivalent to
592/// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
593/// each intermediate result in the calculation must also have a single use.
594/// If the Op is in the correct form the constituent parts are written to Mul0,
595/// Mul1, Addend0 and Addend1.
596static bool
597isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
598            SDValue &Addend1, bool requireIntermediatesHaveOneUse)
599{
600  if (Op.getOpcode() != ISD::ADD)
601    return false;
602  SDValue N0 = Op.getOperand(0);
603  SDValue N1 = Op.getOperand(1);
604  SDValue AddOp;
605  SDValue OtherOp;
606  if (N0.getOpcode() == ISD::ADD) {
607    AddOp = N0;
608    OtherOp = N1;
609  } else if (N1.getOpcode() == ISD::ADD) {
610    AddOp = N1;
611    OtherOp = N0;
612  } else {
613    return false;
614  }
615  if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
616    return false;
617  if (OtherOp.getOpcode() == ISD::MUL) {
618    // add(add(a,b),mul(x,y))
619    if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
620      return false;
621    Mul0 = OtherOp.getOperand(0);
622    Mul1 = OtherOp.getOperand(1);
623    Addend0 = AddOp.getOperand(0);
624    Addend1 = AddOp.getOperand(1);
625    return true;
626  }
627  if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
628    // add(add(mul(x,y),a),b)
629    if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
630      return false;
631    Mul0 = AddOp.getOperand(0).getOperand(0);
632    Mul1 = AddOp.getOperand(0).getOperand(1);
633    Addend0 = AddOp.getOperand(1);
634    Addend1 = OtherOp;
635    return true;
636  }
637  if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
638    // add(add(a,mul(x,y)),b)
639    if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
640      return false;
641    Mul0 = AddOp.getOperand(1).getOperand(0);
642    Mul1 = AddOp.getOperand(1).getOperand(1);
643    Addend0 = AddOp.getOperand(0);
644    Addend1 = OtherOp;
645    return true;
646  }
647  return false;
648}
649
650SDValue XCoreTargetLowering::
651TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
652{
653  SDValue Mul;
654  SDValue Other;
655  if (N->getOperand(0).getOpcode() == ISD::MUL) {
656    Mul = N->getOperand(0);
657    Other = N->getOperand(1);
658  } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
659    Mul = N->getOperand(1);
660    Other = N->getOperand(0);
661  } else {
662    return SDValue();
663  }
664  DebugLoc dl = N->getDebugLoc();
665  SDValue LL, RL, AddendL, AddendH;
666  LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
667                   Mul.getOperand(0),  DAG.getConstant(0, MVT::i32));
668  RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
669                   Mul.getOperand(1),  DAG.getConstant(0, MVT::i32));
670  AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
671                        Other,  DAG.getConstant(0, MVT::i32));
672  AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
673                        Other,  DAG.getConstant(1, MVT::i32));
674  APInt HighMask = APInt::getHighBitsSet(64, 32);
675  unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
676  unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
677  if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
678      DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
679    // The inputs are both zero-extended.
680    SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
681                             DAG.getVTList(MVT::i32, MVT::i32), AddendH,
682                             AddendL, LL, RL);
683    SDValue Lo(Hi.getNode(), 1);
684    return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
685  }
686  if (LHSSB > 32 && RHSSB > 32) {
687    // The inputs are both sign-extended.
688    SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
689                             DAG.getVTList(MVT::i32, MVT::i32), AddendH,
690                             AddendL, LL, RL);
691    SDValue Lo(Hi.getNode(), 1);
692    return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
693  }
694  SDValue LH, RH;
695  LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
696                   Mul.getOperand(0),  DAG.getConstant(1, MVT::i32));
697  RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
698                   Mul.getOperand(1),  DAG.getConstant(1, MVT::i32));
699  SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
700                           DAG.getVTList(MVT::i32, MVT::i32), AddendH,
701                           AddendL, LL, RL);
702  SDValue Lo(Hi.getNode(), 1);
703  RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
704  LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
705  Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
706  Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
707  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
708}
709
710SDValue XCoreTargetLowering::
711ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
712{
713  assert(N->getValueType(0) == MVT::i64 &&
714         (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
715        "Unknown operand to lower!");
716
717  if (N->getOpcode() == ISD::ADD) {
718    SDValue Result = TryExpandADDWithMul(N, DAG);
719    if (Result.getNode() != 0)
720      return Result;
721  }
722
723  DebugLoc dl = N->getDebugLoc();
724
725  // Extract components
726  SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
727                            N->getOperand(0),  DAG.getConstant(0, MVT::i32));
728  SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
729                            N->getOperand(0),  DAG.getConstant(1, MVT::i32));
730  SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
731                             N->getOperand(1), DAG.getConstant(0, MVT::i32));
732  SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
733                             N->getOperand(1), DAG.getConstant(1, MVT::i32));
734
735  // Expand
736  unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
737                                                   XCoreISD::LSUB;
738  SDValue Zero = DAG.getConstant(0, MVT::i32);
739  SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
740                                  LHSL, RHSL, Zero);
741  SDValue Lo(Carry.getNode(), 1);
742
743  SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
744                                  LHSH, RHSH, Carry);
745  SDValue Hi(Ignored.getNode(), 1);
746  // Merge the pieces
747  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
748}
749
750SDValue XCoreTargetLowering::
751LowerVAARG(SDValue Op, SelectionDAG &DAG) const
752{
753  llvm_unreachable("unimplemented");
754  // FIXME Arguments passed by reference need a extra dereference.
755  SDNode *Node = Op.getNode();
756  DebugLoc dl = Node->getDebugLoc();
757  const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
758  EVT VT = Node->getValueType(0);
759  SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
760                               Node->getOperand(1), MachinePointerInfo(V),
761                               false, false, false, 0);
762  // Increment the pointer, VAList, to the next vararg
763  SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
764                     DAG.getConstant(VT.getSizeInBits(),
765                                     getPointerTy()));
766  // Store the incremented VAList to the legalized pointer
767  Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1),
768                      MachinePointerInfo(V), false, false, 0);
769  // Load the actual argument out of the pointer VAList
770  return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
771                     false, false, false, 0);
772}
773
774SDValue XCoreTargetLowering::
775LowerVASTART(SDValue Op, SelectionDAG &DAG) const
776{
777  DebugLoc dl = Op.getDebugLoc();
778  // vastart stores the address of the VarArgsFrameIndex slot into the
779  // memory location argument
780  MachineFunction &MF = DAG.getMachineFunction();
781  XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
782  SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
783  return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
784                      MachinePointerInfo(), false, false, 0);
785}
786
787SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
788                                            SelectionDAG &DAG) const {
789  DebugLoc dl = Op.getDebugLoc();
790  // Depths > 0 not supported yet!
791  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
792    return SDValue();
793
794  MachineFunction &MF = DAG.getMachineFunction();
795  const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
796  return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
797                            RegInfo->getFrameRegister(MF), MVT::i32);
798}
799
800SDValue XCoreTargetLowering::
801LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
802  return Op.getOperand(0);
803}
804
805SDValue XCoreTargetLowering::
806LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
807  SDValue Chain = Op.getOperand(0);
808  SDValue Trmp = Op.getOperand(1); // trampoline
809  SDValue FPtr = Op.getOperand(2); // nested function
810  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
811
812  const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
813
814  // .align 4
815  // LDAPF_u10 r11, nest
816  // LDW_2rus r11, r11[0]
817  // STWSP_ru6 r11, sp[0]
818  // LDAPF_u10 r11, fptr
819  // LDW_2rus r11, r11[0]
820  // BAU_1r r11
821  // nest:
822  // .word nest
823  // fptr:
824  // .word fptr
825  SDValue OutChains[5];
826
827  SDValue Addr = Trmp;
828
829  DebugLoc dl = Op.getDebugLoc();
830  OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
831                              Addr, MachinePointerInfo(TrmpAddr), false, false,
832                              0);
833
834  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
835                     DAG.getConstant(4, MVT::i32));
836  OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
837                              Addr, MachinePointerInfo(TrmpAddr, 4), false,
838                              false, 0);
839
840  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
841                     DAG.getConstant(8, MVT::i32));
842  OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
843                              Addr, MachinePointerInfo(TrmpAddr, 8), false,
844                              false, 0);
845
846  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
847                     DAG.getConstant(12, MVT::i32));
848  OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
849                              MachinePointerInfo(TrmpAddr, 12), false, false,
850                              0);
851
852  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
853                     DAG.getConstant(16, MVT::i32));
854  OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
855                              MachinePointerInfo(TrmpAddr, 16), false, false,
856                              0);
857
858  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5);
859}
860
861//===----------------------------------------------------------------------===//
862//                      Calling Convention Implementation
863//===----------------------------------------------------------------------===//
864
865#include "XCoreGenCallingConv.inc"
866
867//===----------------------------------------------------------------------===//
868//                  Call Calling Convention Implementation
869//===----------------------------------------------------------------------===//
870
871/// XCore call implementation
872SDValue
873XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
874                               SmallVectorImpl<SDValue> &InVals) const {
875  SelectionDAG &DAG                     = CLI.DAG;
876  DebugLoc &dl                          = CLI.DL;
877  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
878  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
879  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
880  SDValue Chain                         = CLI.Chain;
881  SDValue Callee                        = CLI.Callee;
882  bool &isTailCall                      = CLI.IsTailCall;
883  CallingConv::ID CallConv              = CLI.CallConv;
884  bool isVarArg                         = CLI.IsVarArg;
885
886  // XCore target does not yet support tail call optimization.
887  isTailCall = false;
888
889  // For now, only CallingConv::C implemented
890  switch (CallConv)
891  {
892    default:
893      llvm_unreachable("Unsupported calling convention");
894    case CallingConv::Fast:
895    case CallingConv::C:
896      return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
897                            Outs, OutVals, Ins, dl, DAG, InVals);
898  }
899}
900
901/// LowerCCCCallTo - functions arguments are copied from virtual
902/// regs to (physical regs)/(stack frame), CALLSEQ_START and
903/// CALLSEQ_END are emitted.
904/// TODO: isTailCall, sret.
905SDValue
906XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
907                                    CallingConv::ID CallConv, bool isVarArg,
908                                    bool isTailCall,
909                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
910                                    const SmallVectorImpl<SDValue> &OutVals,
911                                    const SmallVectorImpl<ISD::InputArg> &Ins,
912                                    DebugLoc dl, SelectionDAG &DAG,
913                                    SmallVectorImpl<SDValue> &InVals) const {
914
915  // Analyze operands of the call, assigning locations to each operand.
916  SmallVector<CCValAssign, 16> ArgLocs;
917  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
918                 getTargetMachine(), ArgLocs, *DAG.getContext());
919
920  // The ABI dictates there should be one stack slot available to the callee
921  // on function entry (for saving lr).
922  CCInfo.AllocateStack(4, 4);
923
924  CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
925
926  // Get a count of how many bytes are to be pushed on the stack.
927  unsigned NumBytes = CCInfo.getNextStackOffset();
928
929  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
930                                 getPointerTy(), true));
931
932  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
933  SmallVector<SDValue, 12> MemOpChains;
934
935  // Walk the register/memloc assignments, inserting copies/loads.
936  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
937    CCValAssign &VA = ArgLocs[i];
938    SDValue Arg = OutVals[i];
939
940    // Promote the value if needed.
941    switch (VA.getLocInfo()) {
942      default: llvm_unreachable("Unknown loc info!");
943      case CCValAssign::Full: break;
944      case CCValAssign::SExt:
945        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
946        break;
947      case CCValAssign::ZExt:
948        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
949        break;
950      case CCValAssign::AExt:
951        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
952        break;
953    }
954
955    // Arguments that can be passed on register must be kept at
956    // RegsToPass vector
957    if (VA.isRegLoc()) {
958      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
959    } else {
960      assert(VA.isMemLoc());
961
962      int Offset = VA.getLocMemOffset();
963
964      MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
965                                        Chain, Arg,
966                                        DAG.getConstant(Offset/4, MVT::i32)));
967    }
968  }
969
970  // Transform all store nodes into one single node because
971  // all store nodes are independent of each other.
972  if (!MemOpChains.empty())
973    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
974                        &MemOpChains[0], MemOpChains.size());
975
976  // Build a sequence of copy-to-reg nodes chained together with token
977  // chain and flag operands which copy the outgoing args into registers.
978  // The InFlag in necessary since all emitted instructions must be
979  // stuck together.
980  SDValue InFlag;
981  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
982    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
983                             RegsToPass[i].second, InFlag);
984    InFlag = Chain.getValue(1);
985  }
986
987  // If the callee is a GlobalAddress node (quite common, every direct call is)
988  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
989  // Likewise ExternalSymbol -> TargetExternalSymbol.
990  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
991    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
992  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
993    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
994
995  // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
996  //             = Chain, Callee, Reg#1, Reg#2, ...
997  //
998  // Returns a chain & a flag for retval copy to use.
999  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1000  SmallVector<SDValue, 8> Ops;
1001  Ops.push_back(Chain);
1002  Ops.push_back(Callee);
1003
1004  // Add argument registers to the end of the list so that they are
1005  // known live into the call.
1006  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1007    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1008                                  RegsToPass[i].second.getValueType()));
1009
1010  if (InFlag.getNode())
1011    Ops.push_back(InFlag);
1012
1013  Chain  = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
1014  InFlag = Chain.getValue(1);
1015
1016  // Create the CALLSEQ_END node.
1017  Chain = DAG.getCALLSEQ_END(Chain,
1018                             DAG.getConstant(NumBytes, getPointerTy(), true),
1019                             DAG.getConstant(0, getPointerTy(), true),
1020                             InFlag);
1021  InFlag = Chain.getValue(1);
1022
1023  // Handle result values, copying them out of physregs into vregs that we
1024  // return.
1025  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1026                         Ins, dl, DAG, InVals);
1027}
1028
1029/// LowerCallResult - Lower the result values of a call into the
1030/// appropriate copies out of appropriate physical registers.
1031SDValue
1032XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1033                                     CallingConv::ID CallConv, bool isVarArg,
1034                                     const SmallVectorImpl<ISD::InputArg> &Ins,
1035                                     DebugLoc dl, SelectionDAG &DAG,
1036                                     SmallVectorImpl<SDValue> &InVals) const {
1037
1038  // Assign locations to each value returned by this call.
1039  SmallVector<CCValAssign, 16> RVLocs;
1040  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1041                 getTargetMachine(), RVLocs, *DAG.getContext());
1042
1043  CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1044
1045  // Copy all of the result registers out of their specified physreg.
1046  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1047    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1048                                 RVLocs[i].getValVT(), InFlag).getValue(1);
1049    InFlag = Chain.getValue(2);
1050    InVals.push_back(Chain.getValue(0));
1051  }
1052
1053  return Chain;
1054}
1055
1056//===----------------------------------------------------------------------===//
1057//             Formal Arguments Calling Convention Implementation
1058//===----------------------------------------------------------------------===//
1059
1060/// XCore formal arguments implementation
1061SDValue
1062XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
1063                                          CallingConv::ID CallConv,
1064                                          bool isVarArg,
1065                                      const SmallVectorImpl<ISD::InputArg> &Ins,
1066                                          DebugLoc dl,
1067                                          SelectionDAG &DAG,
1068                                          SmallVectorImpl<SDValue> &InVals)
1069                                            const {
1070  switch (CallConv)
1071  {
1072    default:
1073      llvm_unreachable("Unsupported calling convention");
1074    case CallingConv::C:
1075    case CallingConv::Fast:
1076      return LowerCCCArguments(Chain, CallConv, isVarArg,
1077                               Ins, dl, DAG, InVals);
1078  }
1079}
1080
1081/// LowerCCCArguments - transform physical registers into
1082/// virtual registers and generate load operations for
1083/// arguments places on the stack.
1084/// TODO: sret
1085SDValue
1086XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
1087                                       CallingConv::ID CallConv,
1088                                       bool isVarArg,
1089                                       const SmallVectorImpl<ISD::InputArg>
1090                                         &Ins,
1091                                       DebugLoc dl,
1092                                       SelectionDAG &DAG,
1093                                       SmallVectorImpl<SDValue> &InVals) const {
1094  MachineFunction &MF = DAG.getMachineFunction();
1095  MachineFrameInfo *MFI = MF.getFrameInfo();
1096  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1097
1098  // Assign locations to all of the incoming arguments.
1099  SmallVector<CCValAssign, 16> ArgLocs;
1100  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1101                 getTargetMachine(), ArgLocs, *DAG.getContext());
1102
1103  CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1104
1105  unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1106
1107  unsigned LRSaveSize = StackSlotSize;
1108
1109  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1110
1111    CCValAssign &VA = ArgLocs[i];
1112
1113    if (VA.isRegLoc()) {
1114      // Arguments passed in registers
1115      EVT RegVT = VA.getLocVT();
1116      switch (RegVT.getSimpleVT().SimpleTy) {
1117      default:
1118        {
1119#ifndef NDEBUG
1120          errs() << "LowerFormalArguments Unhandled argument type: "
1121                 << RegVT.getSimpleVT().SimpleTy << "\n";
1122#endif
1123          llvm_unreachable(0);
1124        }
1125      case MVT::i32:
1126        unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1127        RegInfo.addLiveIn(VA.getLocReg(), VReg);
1128        InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1129      }
1130    } else {
1131      // sanity check
1132      assert(VA.isMemLoc());
1133      // Load the argument to a virtual register
1134      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1135      if (ObjSize > StackSlotSize) {
1136        errs() << "LowerFormalArguments Unhandled argument type: "
1137               << EVT(VA.getLocVT()).getEVTString()
1138               << "\n";
1139      }
1140      // Create the frame index object for this incoming parameter...
1141      int FI = MFI->CreateFixedObject(ObjSize,
1142                                      LRSaveSize + VA.getLocMemOffset(),
1143                                      true);
1144
1145      // Create the SelectionDAG nodes corresponding to a load
1146      //from this parameter
1147      SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1148      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1149                                   MachinePointerInfo::getFixedStack(FI),
1150                                   false, false, false, 0));
1151    }
1152  }
1153
1154  if (isVarArg) {
1155    /* Argument registers */
1156    static const uint16_t ArgRegs[] = {
1157      XCore::R0, XCore::R1, XCore::R2, XCore::R3
1158    };
1159    XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1160    unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
1161                                                     array_lengthof(ArgRegs));
1162    if (FirstVAReg < array_lengthof(ArgRegs)) {
1163      SmallVector<SDValue, 4> MemOps;
1164      int offset = 0;
1165      // Save remaining registers, storing higher register numbers at a higher
1166      // address
1167      for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1168        // Create a stack slot
1169        int FI = MFI->CreateFixedObject(4, offset, true);
1170        if (i == (int)FirstVAReg) {
1171          XFI->setVarArgsFrameIndex(FI);
1172        }
1173        offset -= StackSlotSize;
1174        SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1175        // Move argument from phys reg -> virt reg
1176        unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1177        RegInfo.addLiveIn(ArgRegs[i], VReg);
1178        SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1179        // Move argument from virt reg -> stack
1180        SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1181                                     MachinePointerInfo(), false, false, 0);
1182        MemOps.push_back(Store);
1183      }
1184      if (!MemOps.empty())
1185        Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1186                            &MemOps[0], MemOps.size());
1187    } else {
1188      // This will point to the next argument passed via stack.
1189      XFI->setVarArgsFrameIndex(
1190        MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1191                               true));
1192    }
1193  }
1194
1195  return Chain;
1196}
1197
1198//===----------------------------------------------------------------------===//
1199//               Return Value Calling Convention Implementation
1200//===----------------------------------------------------------------------===//
1201
1202bool XCoreTargetLowering::
1203CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1204               bool isVarArg,
1205               const SmallVectorImpl<ISD::OutputArg> &Outs,
1206               LLVMContext &Context) const {
1207  SmallVector<CCValAssign, 16> RVLocs;
1208  CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
1209  return CCInfo.CheckReturn(Outs, RetCC_XCore);
1210}
1211
1212SDValue
1213XCoreTargetLowering::LowerReturn(SDValue Chain,
1214                                 CallingConv::ID CallConv, bool isVarArg,
1215                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
1216                                 const SmallVectorImpl<SDValue> &OutVals,
1217                                 DebugLoc dl, SelectionDAG &DAG) const {
1218
1219  // CCValAssign - represent the assignment of
1220  // the return value to a location
1221  SmallVector<CCValAssign, 16> RVLocs;
1222
1223  // CCState - Info about the registers and stack slot.
1224  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1225                 getTargetMachine(), RVLocs, *DAG.getContext());
1226
1227  // Analyze return values.
1228  CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1229
1230  // If this is the first return lowered for this function, add
1231  // the regs to the liveout set for the function.
1232  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1233    for (unsigned i = 0; i != RVLocs.size(); ++i)
1234      if (RVLocs[i].isRegLoc())
1235        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1236  }
1237
1238  SDValue Flag;
1239
1240  // Copy the result values into the output registers.
1241  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1242    CCValAssign &VA = RVLocs[i];
1243    assert(VA.isRegLoc() && "Can only return in registers!");
1244
1245    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1246                             OutVals[i], Flag);
1247
1248    // guarantee that all emitted copies are
1249    // stuck together, avoiding something bad
1250    Flag = Chain.getValue(1);
1251  }
1252
1253  // Return on XCore is always a "retsp 0"
1254  if (Flag.getNode())
1255    return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1256                       Chain, DAG.getConstant(0, MVT::i32), Flag);
1257  else // Return Void
1258    return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1259                       Chain, DAG.getConstant(0, MVT::i32));
1260}
1261
1262//===----------------------------------------------------------------------===//
1263//  Other Lowering Code
1264//===----------------------------------------------------------------------===//
1265
1266MachineBasicBlock *
1267XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1268                                                 MachineBasicBlock *BB) const {
1269  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1270  DebugLoc dl = MI->getDebugLoc();
1271  assert((MI->getOpcode() == XCore::SELECT_CC) &&
1272         "Unexpected instr type to insert");
1273
1274  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1275  // control-flow pattern.  The incoming instruction knows the destination vreg
1276  // to set, the condition code register to branch on, the true/false values to
1277  // select between, and a branch opcode to use.
1278  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1279  MachineFunction::iterator It = BB;
1280  ++It;
1281
1282  //  thisMBB:
1283  //  ...
1284  //   TrueVal = ...
1285  //   cmpTY ccX, r1, r2
1286  //   bCC copy1MBB
1287  //   fallthrough --> copy0MBB
1288  MachineBasicBlock *thisMBB = BB;
1289  MachineFunction *F = BB->getParent();
1290  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1291  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1292  F->insert(It, copy0MBB);
1293  F->insert(It, sinkMBB);
1294
1295  // Transfer the remainder of BB and its successor edges to sinkMBB.
1296  sinkMBB->splice(sinkMBB->begin(), BB,
1297                  llvm::next(MachineBasicBlock::iterator(MI)),
1298                  BB->end());
1299  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1300
1301  // Next, add the true and fallthrough blocks as its successors.
1302  BB->addSuccessor(copy0MBB);
1303  BB->addSuccessor(sinkMBB);
1304
1305  BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1306    .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1307
1308  //  copy0MBB:
1309  //   %FalseValue = ...
1310  //   # fallthrough to sinkMBB
1311  BB = copy0MBB;
1312
1313  // Update machine-CFG edges
1314  BB->addSuccessor(sinkMBB);
1315
1316  //  sinkMBB:
1317  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1318  //  ...
1319  BB = sinkMBB;
1320  BuildMI(*BB, BB->begin(), dl,
1321          TII.get(XCore::PHI), MI->getOperand(0).getReg())
1322    .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1323    .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1324
1325  MI->eraseFromParent();   // The pseudo instruction is gone now.
1326  return BB;
1327}
1328
1329//===----------------------------------------------------------------------===//
1330// Target Optimization Hooks
1331//===----------------------------------------------------------------------===//
1332
1333SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1334                                             DAGCombinerInfo &DCI) const {
1335  SelectionDAG &DAG = DCI.DAG;
1336  DebugLoc dl = N->getDebugLoc();
1337  switch (N->getOpcode()) {
1338  default: break;
1339  case XCoreISD::LADD: {
1340    SDValue N0 = N->getOperand(0);
1341    SDValue N1 = N->getOperand(1);
1342    SDValue N2 = N->getOperand(2);
1343    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1344    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1345    EVT VT = N0.getValueType();
1346
1347    // canonicalize constant to RHS
1348    if (N0C && !N1C)
1349      return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1350
1351    // fold (ladd 0, 0, x) -> 0, x & 1
1352    if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1353      SDValue Carry = DAG.getConstant(0, VT);
1354      SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1355                                   DAG.getConstant(1, VT));
1356      SDValue Ops [] = { Carry, Result };
1357      return DAG.getMergeValues(Ops, 2, dl);
1358    }
1359
1360    // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1361    // low bit set
1362    if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1363      APInt KnownZero, KnownOne;
1364      APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1365                                         VT.getSizeInBits() - 1);
1366      DAG.ComputeMaskedBits(N2, KnownZero, KnownOne);
1367      if ((KnownZero & Mask) == Mask) {
1368        SDValue Carry = DAG.getConstant(0, VT);
1369        SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1370        SDValue Ops [] = { Carry, Result };
1371        return DAG.getMergeValues(Ops, 2, dl);
1372      }
1373    }
1374  }
1375  break;
1376  case XCoreISD::LSUB: {
1377    SDValue N0 = N->getOperand(0);
1378    SDValue N1 = N->getOperand(1);
1379    SDValue N2 = N->getOperand(2);
1380    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1381    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1382    EVT VT = N0.getValueType();
1383
1384    // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1385    if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1386      APInt KnownZero, KnownOne;
1387      APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1388                                         VT.getSizeInBits() - 1);
1389      DAG.ComputeMaskedBits(N2, KnownZero, KnownOne);
1390      if ((KnownZero & Mask) == Mask) {
1391        SDValue Borrow = N2;
1392        SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1393                                     DAG.getConstant(0, VT), N2);
1394        SDValue Ops [] = { Borrow, Result };
1395        return DAG.getMergeValues(Ops, 2, dl);
1396      }
1397    }
1398
1399    // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1400    // low bit set
1401    if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1402      APInt KnownZero, KnownOne;
1403      APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1404                                         VT.getSizeInBits() - 1);
1405      DAG.ComputeMaskedBits(N2, KnownZero, KnownOne);
1406      if ((KnownZero & Mask) == Mask) {
1407        SDValue Borrow = DAG.getConstant(0, VT);
1408        SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1409        SDValue Ops [] = { Borrow, Result };
1410        return DAG.getMergeValues(Ops, 2, dl);
1411      }
1412    }
1413  }
1414  break;
1415  case XCoreISD::LMUL: {
1416    SDValue N0 = N->getOperand(0);
1417    SDValue N1 = N->getOperand(1);
1418    SDValue N2 = N->getOperand(2);
1419    SDValue N3 = N->getOperand(3);
1420    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1421    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1422    EVT VT = N0.getValueType();
1423    // Canonicalize multiplicative constant to RHS. If both multiplicative
1424    // operands are constant canonicalize smallest to RHS.
1425    if ((N0C && !N1C) ||
1426        (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1427      return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1428                         N1, N0, N2, N3);
1429
1430    // lmul(x, 0, a, b)
1431    if (N1C && N1C->isNullValue()) {
1432      // If the high result is unused fold to add(a, b)
1433      if (N->hasNUsesOfValue(0, 0)) {
1434        SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1435        SDValue Ops [] = { Lo, Lo };
1436        return DAG.getMergeValues(Ops, 2, dl);
1437      }
1438      // Otherwise fold to ladd(a, b, 0)
1439      return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1440    }
1441  }
1442  break;
1443  case ISD::ADD: {
1444    // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1445    // lmul(x, y, a, b). The high result of lmul will be ignored.
1446    // This is only profitable if the intermediate results are unused
1447    // elsewhere.
1448    SDValue Mul0, Mul1, Addend0, Addend1;
1449    if (N->getValueType(0) == MVT::i32 &&
1450        isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1451      SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1452                                    DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1453                                    Mul1, Addend0, Addend1);
1454      SDValue Result(Ignored.getNode(), 1);
1455      return Result;
1456    }
1457    APInt HighMask = APInt::getHighBitsSet(64, 32);
1458    // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1459    // lmul(x, y, a, b) if all operands are zero-extended. We do this
1460    // before type legalization as it is messy to match the operands after
1461    // that.
1462    if (N->getValueType(0) == MVT::i64 &&
1463        isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1464        DAG.MaskedValueIsZero(Mul0, HighMask) &&
1465        DAG.MaskedValueIsZero(Mul1, HighMask) &&
1466        DAG.MaskedValueIsZero(Addend0, HighMask) &&
1467        DAG.MaskedValueIsZero(Addend1, HighMask)) {
1468      SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1469                                  Mul0, DAG.getConstant(0, MVT::i32));
1470      SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1471                                  Mul1, DAG.getConstant(0, MVT::i32));
1472      SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1473                                     Addend0, DAG.getConstant(0, MVT::i32));
1474      SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1475                                     Addend1, DAG.getConstant(0, MVT::i32));
1476      SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1477                               DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1478                               Addend0L, Addend1L);
1479      SDValue Lo(Hi.getNode(), 1);
1480      return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1481    }
1482  }
1483  break;
1484  case ISD::STORE: {
1485    // Replace unaligned store of unaligned load with memmove.
1486    StoreSDNode *ST  = cast<StoreSDNode>(N);
1487    if (!DCI.isBeforeLegalize() ||
1488        allowsUnalignedMemoryAccesses(ST->getMemoryVT()) ||
1489        ST->isVolatile() || ST->isIndexed()) {
1490      break;
1491    }
1492    SDValue Chain = ST->getChain();
1493
1494    unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1495    if (StoreBits % 8) {
1496      break;
1497    }
1498    unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(
1499        ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1500    unsigned Alignment = ST->getAlignment();
1501    if (Alignment >= ABIAlignment) {
1502      break;
1503    }
1504
1505    if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1506      if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1507        LD->getAlignment() == Alignment &&
1508        !LD->isVolatile() && !LD->isIndexed() &&
1509        Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1510        return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1511                              LD->getBasePtr(),
1512                              DAG.getConstant(StoreBits/8, MVT::i32),
1513                              Alignment, false, ST->getPointerInfo(),
1514                              LD->getPointerInfo());
1515      }
1516    }
1517    break;
1518  }
1519  }
1520  return SDValue();
1521}
1522
1523void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1524                                                         APInt &KnownZero,
1525                                                         APInt &KnownOne,
1526                                                         const SelectionDAG &DAG,
1527                                                         unsigned Depth) const {
1528  KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1529  switch (Op.getOpcode()) {
1530  default: break;
1531  case XCoreISD::LADD:
1532  case XCoreISD::LSUB:
1533    if (Op.getResNo() == 0) {
1534      // Top bits of carry / borrow are clear.
1535      KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
1536                                        KnownZero.getBitWidth() - 1);
1537    }
1538    break;
1539  }
1540}
1541
1542//===----------------------------------------------------------------------===//
1543//  Addressing mode description hooks
1544//===----------------------------------------------------------------------===//
1545
1546static inline bool isImmUs(int64_t val)
1547{
1548  return (val >= 0 && val <= 11);
1549}
1550
1551static inline bool isImmUs2(int64_t val)
1552{
1553  return (val%2 == 0 && isImmUs(val/2));
1554}
1555
1556static inline bool isImmUs4(int64_t val)
1557{
1558  return (val%4 == 0 && isImmUs(val/4));
1559}
1560
1561/// isLegalAddressingMode - Return true if the addressing mode represented
1562/// by AM is legal for this target, for a load/store of the specified type.
1563bool
1564XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1565                                              Type *Ty) const {
1566  if (Ty->getTypeID() == Type::VoidTyID)
1567    return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1568
1569  const DataLayout *TD = TM.getDataLayout();
1570  unsigned Size = TD->getTypeAllocSize(Ty);
1571  if (AM.BaseGV) {
1572    return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1573                 AM.BaseOffs%4 == 0;
1574  }
1575
1576  switch (Size) {
1577  case 1:
1578    // reg + imm
1579    if (AM.Scale == 0) {
1580      return isImmUs(AM.BaseOffs);
1581    }
1582    // reg + reg
1583    return AM.Scale == 1 && AM.BaseOffs == 0;
1584  case 2:
1585  case 3:
1586    // reg + imm
1587    if (AM.Scale == 0) {
1588      return isImmUs2(AM.BaseOffs);
1589    }
1590    // reg + reg<<1
1591    return AM.Scale == 2 && AM.BaseOffs == 0;
1592  default:
1593    // reg + imm
1594    if (AM.Scale == 0) {
1595      return isImmUs4(AM.BaseOffs);
1596    }
1597    // reg + reg<<2
1598    return AM.Scale == 4 && AM.BaseOffs == 0;
1599  }
1600}
1601
1602//===----------------------------------------------------------------------===//
1603//                           XCore Inline Assembly Support
1604//===----------------------------------------------------------------------===//
1605
1606std::pair<unsigned, const TargetRegisterClass*>
1607XCoreTargetLowering::
1608getRegForInlineAsmConstraint(const std::string &Constraint,
1609                             EVT VT) const {
1610  if (Constraint.size() == 1) {
1611    switch (Constraint[0]) {
1612    default : break;
1613    case 'r':
1614      return std::make_pair(0U, &XCore::GRRegsRegClass);
1615    }
1616  }
1617  // Use the default implementation in TargetLowering to convert the register
1618  // constraint into a member of a register class.
1619  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1620}
1621