1//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the XCore instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// Uses of CP, DP are not currently reflected in the patterns, since 15// having a physical register as an operand prevents loop hoisting and 16// since the value of these registers never changes during the life of the 17// function. 18 19//===----------------------------------------------------------------------===// 20// Instruction format superclass. 21//===----------------------------------------------------------------------===// 22 23include "XCoreInstrFormats.td" 24 25//===----------------------------------------------------------------------===// 26// XCore specific DAG Nodes. 27// 28 29// Call 30def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33 SDNPVariadic]>; 34 35def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; 37 38def SDT_XCoreEhRet : SDTypeProfile<0, 2, 39 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 40def XCoreEhRet : SDNode<"XCoreISD::EH_RETURN", SDT_XCoreEhRet, 41 [SDNPHasChain, SDNPOptInGlue]>; 42 43def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 44 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 45 46def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 47 [SDNPHasChain]>; 48 49def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 50 [SDNPHasChain]>; 51 52def SDT_XCoreAddress : SDTypeProfile<1, 1, 53 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 54 55def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 56 []>; 57 58def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 59 []>; 60 61def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 62 []>; 63 64def frametoargsoffset : SDNode<"XCoreISD::FRAME_TO_ARGS_OFFSET", SDTIntLeaf, 65 []>; 66 67def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 68def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 69 [SDNPHasChain, SDNPMayStore]>; 70 71def SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>; 72def XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp, 73 [SDNPHasChain, SDNPMayLoad]>; 74 75// These are target-independent nodes, but have target-specific formats. 76def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 77def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 78 SDTCisVT<1, i32> ]>; 79 80def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 81 [SDNPHasChain, SDNPOutGlue]>; 82def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 83 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 84 85def SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>; 86 87def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER, 88 [SDNPHasChain]>; 89 90//===----------------------------------------------------------------------===// 91// Instruction Pattern Stuff 92//===----------------------------------------------------------------------===// 93 94def div4_xform : SDNodeXForm<imm, [{ 95 // Transformation function: imm/4 96 assert(N->getZExtValue() % 4 == 0); 97 return getI32Imm(N->getZExtValue()/4); 98}]>; 99 100def msksize_xform : SDNodeXForm<imm, [{ 101 // Transformation function: get the size of a mask 102 assert(isMask_32(N->getZExtValue())); 103 // look for the first non-zero bit 104 return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue())); 105}]>; 106 107def neg_xform : SDNodeXForm<imm, [{ 108 // Transformation function: -imm 109 uint32_t value = N->getZExtValue(); 110 return getI32Imm(-value); 111}]>; 112 113def bpwsub_xform : SDNodeXForm<imm, [{ 114 // Transformation function: 32-imm 115 uint32_t value = N->getZExtValue(); 116 return getI32Imm(32-value); 117}]>; 118 119def div4neg_xform : SDNodeXForm<imm, [{ 120 // Transformation function: -imm/4 121 uint32_t value = N->getZExtValue(); 122 assert(-value % 4 == 0); 123 return getI32Imm(-value/4); 124}]>; 125 126def immUs4Neg : PatLeaf<(imm), [{ 127 uint32_t value = (uint32_t)N->getZExtValue(); 128 return (-value)%4 == 0 && (-value)/4 <= 11; 129}]>; 130 131def immUs4 : PatLeaf<(imm), [{ 132 uint32_t value = (uint32_t)N->getZExtValue(); 133 return value%4 == 0 && value/4 <= 11; 134}]>; 135 136def immUsNeg : PatLeaf<(imm), [{ 137 return -((uint32_t)N->getZExtValue()) <= 11; 138}]>; 139 140def immUs : PatLeaf<(imm), [{ 141 return (uint32_t)N->getZExtValue() <= 11; 142}]>; 143 144def immU6 : PatLeaf<(imm), [{ 145 return (uint32_t)N->getZExtValue() < (1 << 6); 146}]>; 147 148def immU10 : PatLeaf<(imm), [{ 149 return (uint32_t)N->getZExtValue() < (1 << 10); 150}]>; 151 152def immU16 : PatLeaf<(imm), [{ 153 return (uint32_t)N->getZExtValue() < (1 << 16); 154}]>; 155 156def immU20 : PatLeaf<(imm), [{ 157 return (uint32_t)N->getZExtValue() < (1 << 20); 158}]>; 159 160def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 161 162def immBitp : PatLeaf<(imm), [{ 163 uint32_t value = (uint32_t)N->getZExtValue(); 164 return (value >= 1 && value <= 8) 165 || value == 16 166 || value == 24 167 || value == 32; 168}]>; 169 170def immBpwSubBitp : PatLeaf<(imm), [{ 171 uint32_t value = (uint32_t)N->getZExtValue(); 172 return (value >= 24 && value <= 31) 173 || value == 16 174 || value == 8 175 || value == 0; 176}]>; 177 178def lda16f : PatFrag<(ops node:$addr, node:$offset), 179 (add node:$addr, (shl node:$offset, 1))>; 180def lda16b : PatFrag<(ops node:$addr, node:$offset), 181 (sub node:$addr, (shl node:$offset, 1))>; 182def ldawf : PatFrag<(ops node:$addr, node:$offset), 183 (add node:$addr, (shl node:$offset, 2))>; 184def ldawb : PatFrag<(ops node:$addr, node:$offset), 185 (sub node:$addr, (shl node:$offset, 2))>; 186 187// Instruction operand types 188def pcrel_imm : Operand<i32>; 189def pcrel_imm_neg : Operand<i32> { 190 let DecoderMethod = "DecodeNegImmOperand"; 191} 192def brtarget : Operand<OtherVT>; 193def brtarget_neg : Operand<OtherVT> { 194 let DecoderMethod = "DecodeNegImmOperand"; 195} 196 197// Addressing modes 198def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 199 200// Address operands 201def MEMii : Operand<i32> { 202 let MIOperandInfo = (ops i32imm, i32imm); 203} 204 205// Jump tables. 206def InlineJT : Operand<i32> { 207 let PrintMethod = "printInlineJT"; 208} 209 210def InlineJT32 : Operand<i32> { 211 let PrintMethod = "printInlineJT32"; 212} 213 214//===----------------------------------------------------------------------===// 215// Instruction Class Templates 216//===----------------------------------------------------------------------===// 217 218// Three operand short 219 220multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 222 !strconcat(OpcStr, " $dst, $b, $c"), 223 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 224 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 225 !strconcat(OpcStr, " $dst, $b, $c"), 226 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 227} 228 229multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 230 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 231 !strconcat(OpcStr, " $dst, $b, $c"), []>; 232 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 233 !strconcat(OpcStr, " $dst, $b, $c"), []>; 234} 235 236multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 237 SDNode OpNode> { 238 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 239 !strconcat(OpcStr, " $dst, $b, $c"), 240 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 241 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 242 !strconcat(OpcStr, " $dst, $b, $c"), 243 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 244} 245 246class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : 247 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 248 !strconcat(OpcStr, " $dst, $b, $c"), 249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 250 251class F3R_np<bits<5> opc, string OpcStr> : 252 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 253 !strconcat(OpcStr, " $dst, $b, $c"), []>; 254// Three operand long 255 256/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 257multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 258 SDNode OpNode> { 259 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 260 !strconcat(OpcStr, " $dst, $b, $c"), 261 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 262 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 263 !strconcat(OpcStr, " $dst, $b, $c"), 264 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 265} 266 267/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 268multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 269 SDNode OpNode> { 270 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 271 !strconcat(OpcStr, " $dst, $b, $c"), 272 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 273 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 274 !strconcat(OpcStr, " $dst, $b, $c"), 275 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 276} 277 278class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : 279 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 280 !strconcat(OpcStr, " $dst, $b, $c"), 281 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 282 283// Register - U6 284// Operand register - U6 285multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { 286 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 287 !strconcat(OpcStr, " $a, $b"), []>; 288 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 289 !strconcat(OpcStr, " $a, $b"), []>; 290} 291 292multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { 293 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 294 !strconcat(OpcStr, " $a, $b"), []>; 295 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 296 !strconcat(OpcStr, " $a, $b"), []>; 297} 298 299 300// U6 301multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { 302 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 303 [(OpNode immU6:$a)]>; 304 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 305 [(OpNode immU16:$a)]>; 306} 307 308multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { 309 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 310 [(Int immU6:$a)]>; 311 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 312 [(Int immU16:$a)]>; 313} 314 315multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { 316 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 317 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 318} 319 320// Two operand short 321 322class F2R_np<bits<6> opc, string OpcStr> : 323 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), 324 !strconcat(OpcStr, " $dst, $b"), []>; 325 326// Two operand long 327 328//===----------------------------------------------------------------------===// 329// Pseudo Instructions 330//===----------------------------------------------------------------------===// 331 332let Defs = [SP], Uses = [SP] in { 333def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 334 "# ADJCALLSTACKDOWN $amt", 335 [(callseq_start timm:$amt)]>; 336def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 337 "# ADJCALLSTACKUP $amt1", 338 [(callseq_end timm:$amt1, timm:$amt2)]>; 339} 340 341let isReMaterializable = 1 in 342def FRAME_TO_ARGS_OFFSET : PseudoInstXCore<(outs GRRegs:$dst), (ins), 343 "# FRAME_TO_ARGS_OFFSET $dst", 344 [(set GRRegs:$dst, (frametoargsoffset))]>; 345 346let isReturn = 1, isTerminator = 1, isBarrier = 1 in 347def EH_RETURN : PseudoInstXCore<(outs), (ins GRRegs:$s, GRRegs:$handler), 348 "# EH_RETURN $s, $handler", 349 [(XCoreEhRet GRRegs:$s, GRRegs:$handler)]>; 350 351def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 352 "# LDWFI $dst, $addr", 353 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 354 355def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 356 "# LDAWFI $dst, $addr", 357 [(set GRRegs:$dst, ADDRspii:$addr)]>; 358 359def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 360 "# STWFI $src, $addr", 361 [(store GRRegs:$src, ADDRspii:$addr)]>; 362 363// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 364// instruction selection into a branch sequence. 365let usesCustomInserter = 1 in { 366 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 367 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 368 "# SELECT_CC PSEUDO!", 369 [(set GRRegs:$dst, 370 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 371} 372 373let hasSideEffects = 1 in 374def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER", 375 [(XCoreMemBarrier)]>; 376 377//===----------------------------------------------------------------------===// 378// Instructions 379//===----------------------------------------------------------------------===// 380 381// Three operand short 382defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; 383defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; 384let neverHasSideEffects = 1 in { 385defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; 386def LSS_3r : F3R_np<0b11000, "lss">; 387def LSU_3r : F3R_np<0b11001, "lsu">; 388} 389def AND_3r : F3R<0b00111, "and", and>; 390def OR_3r : F3R<0b01000, "or", or>; 391 392let mayLoad=1 in { 393def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), 394 (ins GRRegs:$addr, GRRegs:$offset), 395 "ldw $dst, $addr[$offset]", []>; 396 397def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), 398 (ins GRRegs:$addr, i32imm:$offset), 399 "ldw $dst, $addr[$offset]", []>; 400 401def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), 402 (ins GRRegs:$addr, GRRegs:$offset), 403 "ld16s $dst, $addr[$offset]", []>; 404 405def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), 406 (ins GRRegs:$addr, GRRegs:$offset), 407 "ld8u $dst, $addr[$offset]", []>; 408} 409 410let mayStore=1 in { 411def STW_l3r : _FL3R<0b000001100, (outs), 412 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 413 "stw $val, $addr[$offset]", []>; 414 415def STW_2rus : _F2RUS<0b0000, (outs), 416 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 417 "stw $val, $addr[$offset]", []>; 418} 419 420defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; 421defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; 422 423// The first operand is treated as an immediate since it refers to a register 424// number in another thread. 425def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), 426 "set t[$c]:r$a, $b", []>; 427 428// Three operand long 429def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), 430 (ins GRRegs:$addr, GRRegs:$offset), 431 "ldaw $dst, $addr[$offset]", 432 [(set GRRegs:$dst, 433 (ldawf GRRegs:$addr, GRRegs:$offset))]>; 434 435let neverHasSideEffects = 1 in 436def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), 437 (ins GRRegs:$addr, i32imm:$offset), 438 "ldaw $dst, $addr[$offset]", []>; 439 440def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), 441 (ins GRRegs:$addr, GRRegs:$offset), 442 "ldaw $dst, $addr[-$offset]", 443 [(set GRRegs:$dst, 444 (ldawb GRRegs:$addr, GRRegs:$offset))]>; 445 446let neverHasSideEffects = 1 in 447def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), 448 (ins GRRegs:$addr, i32imm:$offset), 449 "ldaw $dst, $addr[-$offset]", []>; 450 451def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), 452 (ins GRRegs:$addr, GRRegs:$offset), 453 "lda16 $dst, $addr[$offset]", 454 [(set GRRegs:$dst, 455 (lda16f GRRegs:$addr, GRRegs:$offset))]>; 456 457def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), 458 (ins GRRegs:$addr, GRRegs:$offset), 459 "lda16 $dst, $addr[-$offset]", 460 [(set GRRegs:$dst, 461 (lda16b GRRegs:$addr, GRRegs:$offset))]>; 462 463def MUL_l3r : FL3R<0b001111100, "mul", mul>; 464// Instructions which may trap are marked as side effecting. 465let hasSideEffects = 1 in { 466def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; 467def DIVU_l3r : FL3R<0b010011100, "divu", udiv>; 468def REMS_l3r : FL3R<0b110001100, "rems", srem>; 469def REMU_l3r : FL3R<0b110011100, "remu", urem>; 470} 471def XOR_l3r : FL3R<0b000011100, "xor", xor>; 472defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; 473 474let Constraints = "$src1 = $dst" in 475def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), 476 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 477 "crc32 $dst, $src2, $src3", 478 [(set GRRegs:$dst, 479 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 480 GRRegs:$src3))]>; 481 482let mayStore=1 in { 483def ST16_l3r : _FL3R<0b100001100, (outs), 484 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 485 "st16 $val, $addr[$offset]", []>; 486 487def ST8_l3r : _FL3R<0b100011100, (outs), 488 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 489 "st8 $val, $addr[$offset]", []>; 490} 491 492def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), 493 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", 494 []>; 495 496def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), 497 (ins GRRegs:$a, GRRegs:$b, i32imm:$c), 498 "outpw res[$b], $a, $c", []>; 499 500// Four operand long 501let Constraints = "$e = $a,$f = $b" in { 502def MACCU_l4r : _FL4RSrcDstSrcDst< 503 0b000001, (outs GRRegs:$a, GRRegs:$b), 504 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; 505 506def MACCS_l4r : _FL4RSrcDstSrcDst< 507 0b000010, (outs GRRegs:$a, GRRegs:$b), 508 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; 509} 510 511let Constraints = "$e = $b" in 512def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), 513 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), 514 "crc8 $b, $a, $c, $d", []>; 515 516// Five operand long 517 518def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), 519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 520 "ladd $dst2, $dst1, $src1, $src2, $src3", 521 []>; 522 523def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), 524 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 525 "lsub $dst2, $dst1, $src1, $src2, $src3", []>; 526 527def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), 528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 529 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; 530 531// Six operand long 532 533def LMUL_l6r : _FL6R< 534 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), 535 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 536 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; 537 538// Register - U6 539 540//let Uses = [DP] in ... 541let neverHasSideEffects = 1, isReMaterializable = 1 in 542def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 543 "ldaw $a, dp[$b]", []>; 544 545let isReMaterializable = 1 in 546def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 547 "ldaw $a, dp[$b]", 548 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 549 550let mayLoad=1 in 551def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 552 "ldw $a, dp[$b]", []>; 553 554def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 555 "ldw $a, dp[$b]", 556 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>; 557 558let mayStore=1 in 559def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 560 "stw $a, dp[$b]", []>; 561 562def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 563 "stw $a, dp[$b]", 564 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 565 566//let Uses = [CP] in .. 567let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in { 568def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 569 "ldw $a, cp[$b]", []>; 570def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 571 "ldw $a, cp[$b]", 572 [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>; 573} 574 575let Uses = [SP] in { 576let mayStore=1 in { 577def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 578 "stw $a, sp[$b]", 579 [(XCoreStwsp RRegs:$a, immU6:$b)]>; 580 581def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 582 "stw $a, sp[$b]", 583 [(XCoreStwsp RRegs:$a, immU16:$b)]>; 584} 585 586let mayLoad=1 in { 587def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 588 "ldw $a, sp[$b]", 589 [(set RRegs:$a, (XCoreLdwsp immU6:$b))]>; 590 591def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 592 "ldw $a, sp[$b]", 593 [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>; 594} 595 596let neverHasSideEffects = 1 in { 597def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 598 "ldaw $a, sp[$b]", []>; 599 600def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 601 "ldaw $a, sp[$b]", []>; 602} 603} 604 605let isReMaterializable = 1 in { 606def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 607 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>; 608 609def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 610 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>; 611} 612 613def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 614 "setc res[$a], $b", 615 [(int_xcore_setc GRRegs:$a, immU6:$b)]>; 616 617def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 618 "setc res[$a], $b", 619 [(int_xcore_setc GRRegs:$a, immU16:$b)]>; 620 621// Operand register - U6 622let isBranch = 1, isTerminator = 1 in { 623defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; 624defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; 625defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; 626defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; 627} 628 629// U6 630let Defs = [SP], Uses = [SP] in { 631let neverHasSideEffects = 1 in 632defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; 633 634let mayStore = 1 in 635defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; 636 637let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 638defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; 639} 640} 641 642let neverHasSideEffects = 1 in 643defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; 644 645let Uses = [R11], isCall=1 in 646defm BLAT : FU6_LU6_np<0b0111001101, "blat">; 647 648let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 649def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 650 651def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 652 653def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 654 655def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 656} 657 658//let Uses = [CP] in ... 659let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 660def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 661 []>; 662 663let Defs = [R11], isReMaterializable = 1 in 664def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 665 [(set R11, (cprelwrapper tglobaladdr:$a))]>; 666 667let Defs = [R11] in 668defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; 669 670defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; 671 672defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; 673 674// setsr may cause a branch if it is used to enable events. clrsr may 675// branch if it is executed while events are enabled. 676let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 677 isCodeGenOnly = 1 in { 678defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; 679defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; 680} 681 682defm KCALL : FU6_LU6_np<0b0111001111, "kcall">; 683 684let Uses = [SP], Defs = [SP], mayStore = 1 in 685defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; 686 687let Uses = [SP], Defs = [SP], mayLoad = 1 in 688defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; 689 690// U10 691 692let Defs = [R11], isReMaterializable = 1 in { 693let neverHasSideEffects = 1 in 694def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>; 695 696def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 697 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 698 699let neverHasSideEffects = 1 in 700def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a", 701 []>; 702 703let neverHasSideEffects = 1 in 704def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a), 705 "ldap r11, $a", 706 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 707 708let isCodeGenOnly = 1 in 709def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 710 [(set R11, (pcrelwrapper tblockaddress:$a))]>; 711} 712 713let isCall=1, 714// All calls clobber the link register and the non-callee-saved registers: 715Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 716def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 717 718def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 719 720def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 721 []>; 722 723def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 724 [(XCoreBranchLink tglobaladdr:$a)]>; 725 726def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 727 728def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 729} 730 731let Defs = [R11], mayLoad = 1, isReMaterializable = 1, 732 neverHasSideEffects = 1 in { 733def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; 734 735def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", 736 []>; 737} 738 739// Two operand short 740def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), 741 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; 742 743def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), 744 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 745 746let Constraints = "$src1 = $dst" in { 747def SEXT_rus : 748 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 749 "sext $dst, $src2", 750 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 751 immBitp:$src2))]>; 752 753def SEXT_2r : 754 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 755 "sext $dst, $src2", 756 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; 757 758def ZEXT_rus : 759 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 760 "zext $dst, $src2", 761 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 762 immBitp:$src2))]>; 763 764def ZEXT_2r : 765 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 766 "zext $dst, $src2", 767 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; 768 769def ANDNOT_2r : 770 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 771 "andnot $dst, $src2", 772 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 773} 774 775let isReMaterializable = 1, neverHasSideEffects = 1 in 776def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), 777 "mkmsk $dst, $size", []>; 778 779def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), 780 "mkmsk $dst, $size", 781 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 782 783def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), 784 "getr $dst, $type", 785 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 786 787def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), 788 "getts $dst, res[$r]", 789 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 790 791def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), 792 "setpt res[$r], $val", 793 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 794 795def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), 796 "outct res[$r], $val", 797 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 798 799def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), 800 "outct res[$r], $val", 801 [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 802 803def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), 804 "outt res[$r], $val", 805 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 806 807def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), 808 "out res[$r], $val", 809 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 810 811let Constraints = "$src = $dst" in 812def OUTSHR_2r : 813 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 814 "outshr res[$r], $src", 815 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 816 817def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), 818 "inct $dst, res[$r]", 819 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 820 821def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), 822 "int $dst, res[$r]", 823 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 824 825def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), 826 "in $dst, res[$r]", 827 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 828 829let Constraints = "$src = $dst" in 830def INSHR_2r : 831 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 832 "inshr $dst, res[$r]", 833 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 834 835def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), 836 "chkct res[$r], $val", 837 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 838 839def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), 840 "chkct res[$r], $val", 841 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 842 843def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), 844 "testct $dst, res[$src]", 845 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 846 847def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), 848 "testwct $dst, res[$src]", 849 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 850 851def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), 852 "setd res[$r], $val", 853 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 854 855def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 856 "setpsc res[$src1], $src2", 857 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 858 859def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), 860 "getst $dst, res[$r]", 861 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 862 863def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), 864 "init t[$t]:sp, $src", 865 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 866 867def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), 868 "init t[$t]:pc, $src", 869 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 870 871def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), 872 "init t[$t]:cp, $src", 873 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 874 875def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), 876 "init t[$t]:dp, $src", 877 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 878 879def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), 880 "peek $dst, res[$src]", 881 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 882 883def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), 884 "endin $dst, res[$src]", 885 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 886 887def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), 888 "eef $a, res[$b]", []>; 889 890def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), 891 "eet $a, res[$b]", []>; 892 893def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), 894 "tsetmr r$a, $b", []>; 895 896// Two operand long 897def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), 898 "bitrev $dst, $src", 899 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 900 901def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), 902 "byterev $dst, $src", 903 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 904 905def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), 906 "clz $dst, $src", 907 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 908 909def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), 910 "getd $dst, res[$src]", []>; 911 912def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), 913 "getn $dst, res[$src]", []>; 914 915def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), 916 "setc res[$r], $val", 917 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 918 919def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), 920 "settw res[$r], $val", 921 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 922 923def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), 924 "get $dst, ps[$src]", 925 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 926 927def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 928 "set ps[$src1], $src2", 929 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 930 931def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), 932 "init t[$t]:lr, $src", 933 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 934 935def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), 936 "setclk res[$src1], $src2", 937 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 938 939def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 940 "setn res[$src1], $src2", []>; 941 942def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 943 "setrdy res[$src1], $src2", 944 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 945 946def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), 947 "testlcl $dst, res[$src]", []>; 948 949// One operand short 950def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), 951 "msync res[$a]", 952 [(int_xcore_msync GRRegs:$a)]>; 953def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), 954 "mjoin res[$a]", 955 [(int_xcore_mjoin GRRegs:$a)]>; 956 957let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 958def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), 959 "bau $a", 960 [(brind GRRegs:$a)]>; 961 962let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 963def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 964 "bru $i\n$t", 965 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 966 967let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 968def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 969 "bru $i\n$t", 970 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 971 972let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 973def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; 974 975let Defs=[SP], neverHasSideEffects=1 in 976def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; 977 978let neverHasSideEffects=1 in 979def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; 980 981let neverHasSideEffects=1 in 982def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; 983 984let hasCtrlDep = 1 in 985def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), 986 "ecallt $a", 987 []>; 988 989let hasCtrlDep = 1 in 990def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), 991 "ecallf $a", 992 []>; 993 994let isCall=1, 995// All calls clobber the link register and the non-callee-saved registers: 996Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 997def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), 998 "bla $a", 999 [(XCoreBranchLink GRRegs:$a)]>; 1000} 1001 1002def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), 1003 "syncr res[$a]", 1004 [(int_xcore_syncr GRRegs:$a)]>; 1005 1006def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), 1007 "freer res[$a]", 1008 [(int_xcore_freer GRRegs:$a)]>; 1009 1010let Uses=[R11] in { 1011def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), 1012 "setv res[$a], r11", 1013 [(int_xcore_setv GRRegs:$a, R11)]>; 1014 1015def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), 1016 "setev res[$a], r11", 1017 [(int_xcore_setev GRRegs:$a, R11)]>; 1018} 1019 1020def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; 1021 1022def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", 1023 [(int_xcore_edu GRRegs:$a)]>; 1024 1025def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), 1026 "eeu res[$a]", 1027 [(int_xcore_eeu GRRegs:$a)]>; 1028 1029def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; 1030 1031def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; 1032 1033def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; 1034 1035def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; 1036 1037def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", 1038 [(int_xcore_clrpt GRRegs:$a)]>; 1039 1040// Zero operand short 1041 1042def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; 1043 1044def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; 1045 1046let Defs = [SP], Uses = [SP] in 1047def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; 1048 1049let Defs = [SP] in 1050def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; 1051 1052def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; 1053 1054def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; 1055 1056let Defs = [R11] in { 1057def GETID_0R : _F0R<0b0001001110, (outs), (ins), 1058 "get r11, id", 1059 [(set R11, (int_xcore_getid))]>; 1060 1061def GETED_0R : _F0R<0b0000111110, (outs), (ins), 1062 "get r11, ed", 1063 [(set R11, (int_xcore_geted))]>; 1064 1065def GETET_0R : _F0R<0b0000111111, (outs), (ins), 1066 "get r11, et", 1067 [(set R11, (int_xcore_getet))]>; 1068 1069def GETKEP_0R : _F0R<0b0001001111, (outs), (ins), 1070 "get r11, kep", []>; 1071 1072def GETKSP_0R : _F0R<0b0001011100, (outs), (ins), 1073 "get r11, ksp", []>; 1074} 1075 1076let Defs = [SP] in 1077def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; 1078 1079let Uses = [SP], mayLoad = 1 in { 1080def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; 1081 1082def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; 1083 1084def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; 1085 1086def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; 1087} 1088 1089let Uses=[R11] in 1090def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; 1091 1092def SSYNC_0r : _F0R<0b0000001110, (outs), (ins), 1093 "ssync", 1094 [(int_xcore_ssync)]>; 1095 1096let Uses = [SP], mayStore = 1 in { 1097def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; 1098 1099def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; 1100 1101def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; 1102 1103def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; 1104} 1105 1106let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1107 hasSideEffects = 1 in 1108def WAITEU_0R : _F0R<0b0000001100, (outs), (ins), 1109 "waiteu", 1110 [(brind (int_xcore_waitevent))]>; 1111 1112//===----------------------------------------------------------------------===// 1113// Non-Instruction Patterns 1114//===----------------------------------------------------------------------===// 1115 1116def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; 1117 1118/// sext_inreg 1119def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1120def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1121def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1122 1123/// loads 1124def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1125 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1126def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1127 1128def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1129 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1130def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1131 1132def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1133 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1134def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1135 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1136def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1137 1138/// anyext 1139def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1140 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1141def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1142def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1143 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1144def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1145 1146/// stores 1147def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1148 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1149def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1150 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1151 1152def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1153 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1154def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1155 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1156 1157def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1158 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1159def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1160 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1161def : Pat<(store GRRegs:$val, GRRegs:$addr), 1162 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1163 1164/// cttz 1165def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1166 1167/// trap 1168def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1169 1170/// 1171/// branch patterns 1172/// 1173 1174// unconditional branch 1175def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1176 1177// direct match equal/notequal zero brcond 1178def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1179 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1180def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1181 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1182 1183def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1184 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1185def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1186 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1187def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1188 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1189def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1190 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1191def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1192 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1193def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1194 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1195 1196// generic brcond pattern 1197def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1198 1199 1200/// 1201/// Select patterns 1202/// 1203 1204// direct match equal/notequal zero select 1205def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1206 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1207 1208def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1209 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1210 1211def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1212 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1213def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1214 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1215def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1216 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1217def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1218 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1219def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1220 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1221def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1222 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1223 1224/// 1225/// setcc patterns, only matched when none of the above brcond 1226/// patterns match 1227/// 1228 1229// setcc 2 register operands 1230def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1231 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1232def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1233 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1234 1235def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1236 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1237def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1238 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1239 1240def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1241 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1242def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1243 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1244 1245def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1246 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1247def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1248 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1249 1250def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1251 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1252 1253def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1254 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1255 1256// setcc reg/imm operands 1257def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1258 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1259def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1260 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1261 1262// misc 1263def : Pat<(add GRRegs:$addr, immUs4:$offset), 1264 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1265 1266def : Pat<(sub GRRegs:$addr, immUs4:$offset), 1267 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1268 1269def : Pat<(and GRRegs:$val, immMskBitp:$mask), 1270 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1271 1272// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1273def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1274 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1275 1276def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1277 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1278 1279/// 1280/// Some peepholes 1281/// 1282 1283def : Pat<(mul GRRegs:$src, 3), 1284 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1285 1286def : Pat<(mul GRRegs:$src, 5), 1287 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1288 1289def : Pat<(mul GRRegs:$src, -3), 1290 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1291 1292// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1293def : Pat<(sra GRRegs:$src, 31), 1294 (ASHR_l2rus GRRegs:$src, 32)>; 1295 1296def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1297 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1298 1299// setge X, 0 is canonicalized to setgt X, -1 1300def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1301 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1302 1303def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1304 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1305 1306def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1307 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1308 1309def : Pat<(setgt GRRegs:$lhs, -1), 1310 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1311 1312def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1313 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1314 1315def : Pat<(load (cprelwrapper tconstpool:$b)), 1316 (LDWCP_lru6 tconstpool:$b)>; 1317 1318def : Pat<(cprelwrapper tconstpool:$b), 1319 (LDAWCP_lu6 tconstpool:$b)>; 1320