1; Test SETCC for every floating-point condition.  The tests here assume that
2; RISBLG isn't available.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
5
6; Test CC in { 0 }
7define i32 @f1(float %a, float %b) {
8; CHECK-LABEL: f1:
9; CHECK: ipm %r2
10; CHECK-NEXT: afi %r2, -268435456
11; CHECK-NEXT: srl %r2, 31
12; CHECK: br %r14
13  %cond = fcmp oeq float %a, %b
14  %res = zext i1 %cond to i32
15  ret i32 %res
16}
17
18; Test CC in { 1 }
19define i32 @f2(float %a, float %b) {
20; CHECK-LABEL: f2:
21; CHECK: ipm %r2
22; CHECK-NEXT: xilf %r2, 268435456
23; CHECK-NEXT: afi %r2, -268435456
24; CHECK-NEXT: srl %r2, 31
25; CHECK: br %r14
26  %cond = fcmp olt float %a, %b
27  %res = zext i1 %cond to i32
28  ret i32 %res
29}
30
31; Test CC in { 0, 1 }
32define i32 @f3(float %a, float %b) {
33; CHECK-LABEL: f3:
34; CHECK: ipm %r2
35; CHECK-NEXT: afi %r2, -536870912
36; CHECK-NEXT: srl %r2, 31
37; CHECK: br %r14
38  %cond = fcmp ole float %a, %b
39  %res = zext i1 %cond to i32
40  ret i32 %res
41}
42
43; Test CC in { 2 }
44define i32 @f4(float %a, float %b) {
45; CHECK-LABEL: f4:
46; CHECK: ipm %r2
47; CHECK-NEXT: xilf %r2, 268435456
48; CHECK-NEXT: afi %r2, 1342177280
49; CHECK-NEXT: srl %r2, 31
50; CHECK: br %r14
51  %cond = fcmp ogt float %a, %b
52  %res = zext i1 %cond to i32
53  ret i32 %res
54}
55
56; Test CC in { 0, 2 }
57define i32 @f5(float %a, float %b) {
58; CHECK-LABEL: f5:
59; CHECK: ipm [[REG:%r[0-5]]]
60; CHECK-NEXT: xilf [[REG]], 4294967295
61; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
62; CHECK: br %r14
63  %cond = fcmp oge float %a, %b
64  %res = zext i1 %cond to i32
65  ret i32 %res
66}
67
68; Test CC in { 1, 2 }
69define i32 @f6(float %a, float %b) {
70; CHECK-LABEL: f6:
71; CHECK: ipm [[REG:%r[0-5]]]
72; CHECK-NEXT: afi [[REG]], 268435456
73; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
74; CHECK: br %r14
75  %cond = fcmp one float %a, %b
76  %res = zext i1 %cond to i32
77  ret i32 %res
78}
79
80; Test CC in { 0, 1, 2 }
81define i32 @f7(float %a, float %b) {
82; CHECK-LABEL: f7:
83; CHECK: ipm %r2
84; CHECK-NEXT: afi %r2, -805306368
85; CHECK-NEXT: srl %r2, 31
86; CHECK: br %r14
87  %cond = fcmp ord float %a, %b
88  %res = zext i1 %cond to i32
89  ret i32 %res
90}
91
92; Test CC in { 3 }
93define i32 @f8(float %a, float %b) {
94; CHECK-LABEL: f8:
95; CHECK: ipm %r2
96; CHECK-NEXT: afi %r2, 1342177280
97; CHECK-NEXT: srl %r2, 31
98; CHECK: br %r14
99  %cond = fcmp uno float %a, %b
100  %res = zext i1 %cond to i32
101  ret i32 %res
102}
103
104; Test CC in { 0, 3 }
105define i32 @f9(float %a, float %b) {
106; CHECK-LABEL: f9:
107; CHECK: ipm [[REG:%r[0-5]]]
108; CHECK-NEXT: afi [[REG]], -268435456
109; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
110; CHECK: br %r14
111  %cond = fcmp ueq float %a, %b
112  %res = zext i1 %cond to i32
113  ret i32 %res
114}
115
116; Test CC in { 1, 3 }
117define i32 @f10(float %a, float %b) {
118; CHECK-LABEL: f10:
119; CHECK: ipm [[REG:%r[0-5]]]
120; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
121; CHECK: br %r14
122  %cond = fcmp ult float %a, %b
123  %res = zext i1 %cond to i32
124  ret i32 %res
125}
126
127; Test CC in { 0, 1, 3 }
128define i32 @f11(float %a, float %b) {
129; CHECK-LABEL: f11:
130; CHECK: ipm %r2
131; CHECK-NEXT: xilf %r2, 268435456
132; CHECK-NEXT: afi %r2, -805306368
133; CHECK-NEXT: srl %r2, 31
134; CHECK: br %r14
135  %cond = fcmp ule float %a, %b
136  %res = zext i1 %cond to i32
137  ret i32 %res
138}
139
140; Test CC in { 2, 3 }
141define i32 @f12(float %a, float %b) {
142; CHECK-LABEL: f12:
143; CHECK: ipm [[REG:%r[0-5]]]
144; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
145; CHECK: br %r14
146  %cond = fcmp ugt float %a, %b
147  %res = zext i1 %cond to i32
148  ret i32 %res
149}
150
151; Test CC in { 0, 2, 3 }
152define i32 @f13(float %a, float %b) {
153; CHECK-LABEL: f13:
154; CHECK: ipm %r2
155; CHECK-NEXT: xilf %r2, 268435456
156; CHECK-NEXT: afi %r2, 1879048192
157; CHECK-NEXT: srl %r2, 31
158; CHECK: br %r14
159  %cond = fcmp uge float %a, %b
160  %res = zext i1 %cond to i32
161  ret i32 %res
162}
163
164; Test CC in { 1, 2, 3 }
165define i32 @f14(float %a, float %b) {
166; CHECK-LABEL: f14:
167; CHECK: ipm %r2
168; CHECK-NEXT: afi %r2, 1879048192
169; CHECK-NEXT: srl %r2, 31
170; CHECK: br %r14
171  %cond = fcmp une float %a, %b
172  %res = zext i1 %cond to i32
173  ret i32 %res
174}
175