1; Test compound shifts.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Test a shift right followed by a sign extension.  This can use two shifts.
6define i64 @f1(i32 %a) {
7; CHECK-LABEL: f1:
8; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
9; CHECK: srag %r2, [[REG]], 63
10; CHECK: br %r14
11  %shr = lshr i32 %a, 1
12  %trunc = trunc i32 %shr to i1
13  %ext = sext i1 %trunc to i64
14  ret i64 %ext
15}
16
17; ...and again with the highest shift count that doesn't reduce to an
18; ashr/sext pair.
19define i64 @f2(i32 %a) {
20; CHECK-LABEL: f2:
21; CHECK: sllg [[REG:%r[0-5]]], %r2, 33
22; CHECK: srag %r2, [[REG]], 63
23; CHECK: br %r14
24  %shr = lshr i32 %a, 30
25  %trunc = trunc i32 %shr to i1
26  %ext = sext i1 %trunc to i64
27  ret i64 %ext
28}
29
30; Test a left shift that of an extended right shift in a case where folding
31; is possible.
32define i64 @f3(i32 %a) {
33; CHECK-LABEL: f3:
34; CHECK: risbg %r2, %r2, 27, 181, 9
35; CHECK: br %r14
36  %shr = lshr i32 %a, 1
37  %ext = zext i32 %shr to i64
38  %shl = shl i64 %ext, 10
39  %and = and i64 %shl, 137438952960
40  ret i64 %and
41}
42
43; ...and again with a larger right shift.
44define i64 @f4(i32 %a) {
45; CHECK-LABEL: f4:
46; CHECK: risbg %r2, %r2, 30, 158, 3
47; CHECK: br %r14
48  %shr = lshr i32 %a, 30
49  %ext = sext i32 %shr to i64
50  %shl = shl i64 %ext, 33
51  %and = and i64 %shl, 8589934592
52  ret i64 %and
53}
54
55; Repeat the previous test in a case where all bits outside the
56; bottom 3 matter.
57define i64 @f5(i32 %a) {
58; CHECK-LABEL: f5:
59; CHECK: risbg %r2, %r2, 29, 158, 3
60; CHECK: lhi %r2, 7
61; CHECK: br %r14
62  %shr = lshr i32 %a, 30
63  %ext = sext i32 %shr to i64
64  %shl = shl i64 %ext, 33
65  %or = or i64 %shl, 7
66  ret i64 %or
67}
68
69; Test that SRA gets replaced with SRL if the sign bit is the only one
70; that matters.
71define i64 @f6(i64 %a) {
72; CHECK-LABEL: f6:
73; CHECK: risbg %r2, %r2, 55, 183, 19
74; CHECK: br %r14
75  %shl = shl i64 %a, 10
76  %shr = ashr i64 %shl, 60
77  %and = and i64 %shr, 256
78  ret i64 %and
79}
80
81; Test another form of f1.
82define i64 @f7(i32 %a) {
83; CHECK-LABEL: f7:
84; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
85; CHECK: srag %r2, [[REG]], 63
86; CHECK: br %r14
87  %1 = shl i32 %a, 30
88  %sext = ashr i32 %1, 31
89  %ext = sext i32 %sext to i64
90  ret i64 %ext
91}
92