1; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
2; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
3
4foo:
5
6; The first should encode as an expression. The second should error expecting
7; a register.
8  ldr x3, (foo + 4)
9  ldr x3, [foo + 4]
10; CHECK:  ldr x3, foo+4               ; encoding: [0bAAA00011,A,A,0x58]
11; CHECK:                              ;   fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19
12; CHECK-ERRORS: error: invalid operand for instruction
13
14; The last argument should be flagged as an error.  rdar://9576009
15  ld4.8b	{v0, v1, v2, v3}, [x0], #33
16; CHECK-ERRORS: error: invalid operand for instruction
17; CHECK-ERRORS: ld4.8b	{v0, v1, v2, v3}, [x0], #33
18
19
20        ldr x0, [x0, #804]
21        ldr w0, [x0, #802]
22        ldr x0, [x0, #804]!
23        ldr w0, [w0, #301]!
24        ldr x0, [x0], #804
25        ldr w0, [w0], #301
26
27        ldp w3, w4, [x5, #11]!
28        ldp x3, x4, [x5, #12]!
29        ldp q3, q4, [x5, #12]!
30        ldp w3, w4, [x5], #11
31        ldp x3, x4, [x5], #12
32        ldp q3, q4, [x5], #12
33
34        ldur x0, [x1, #-257]
35
36; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
37; CHECK-ERRORS:         ldr x0, [x0, #804]
38; CHECK-ERRORS:                 ^
39; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
40; CHECK-ERRORS:         ldr w0, [x0, #802]
41; CHECK-ERRORS:                 ^
42; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
43; CHECK-ERRORS:         ldr x0, [x0, #804]!
44; CHECK-ERRORS:                 ^
45; CHECK-ERRORS: error: invalid operand for instruction
46; CHECK-ERRORS:         ldr w0, [w0, #301]!
47; CHECK-ERRORS:                  ^
48; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
49; CHECK-ERRORS:         ldr x0, [x0], #804
50; CHECK-ERRORS:                       ^
51; CHECK-ERRORS: error: invalid operand for instruction
52; CHECK-ERRORS:         ldr w0, [w0], #301
53; CHECK-ERRORS:                  ^
54; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
55; CHECK-ERRORS:         ldp w3, w4, [x5, #11]!
56; CHECK-ERRORS:                     ^
57; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
58; CHECK-ERRORS:         ldp x3, x4, [x5, #12]!
59; CHECK-ERRORS:                     ^
60; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
61; CHECK-ERRORS:         ldp q3, q4, [x5, #12]!
62; CHECK-ERRORS:                     ^
63; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
64; CHECK-ERRORS:         ldp w3, w4, [x5], #11
65; CHECK-ERRORS:                           ^
66; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
67; CHECK-ERRORS:         ldp x3, x4, [x5], #12
68; CHECK-ERRORS:                           ^
69; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
70; CHECK-ERRORS:         ldp q3, q4, [x5], #12
71; CHECK-ERRORS:                           ^
72; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
73; CHECK-ERRORS:         ldur x0, [x1, #-257]
74; CHECK-ERRORS:                   ^
75
76
77ldrb   w1, [x3, w3, sxtw #4]
78ldrh   w1, [x3, w3, sxtw #4]
79ldr    w1, [x3, w3, sxtw #4]
80ldr    x1, [x3, w3, sxtw #4]
81ldr    b1, [x3, w3, sxtw #4]
82ldr    h1, [x3, w3, sxtw #4]
83ldr    s1, [x3, w3, sxtw #4]
84ldr    d1, [x3, w3, sxtw #4]
85ldr    q1, [x3, w3, sxtw #1]
86
87; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
88; CHECK-ERRORS:ldrb   w1, [x3, w3, sxtw #4]
89; CHECK-ERRORS:           ^
90; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
91; CHECK-ERRORS:ldrh   w1, [x3, w3, sxtw #4]
92; CHECK-ERRORS:           ^
93; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
94; CHECK-ERRORS:ldr    w1, [x3, w3, sxtw #4]
95; CHECK-ERRORS:           ^
96; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
97; CHECK-ERRORS:ldr    x1, [x3, w3, sxtw #4]
98; CHECK-ERRORS:           ^
99; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
100; CHECK-ERRORS:ldr    b1, [x3, w3, sxtw #4]
101; CHECK-ERRORS:           ^
102; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
103; CHECK-ERRORS:ldr    h1, [x3, w3, sxtw #4]
104; CHECK-ERRORS:           ^
105; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
106; CHECK-ERRORS:ldr    s1, [x3, w3, sxtw #4]
107; CHECK-ERRORS:           ^
108; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
109; CHECK-ERRORS:ldr    d1, [x3, w3, sxtw #4]
110; CHECK-ERRORS:           ^
111; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
112; CHECK-ERRORS:ldr    q1, [x3, w3, sxtw #1]
113; CHECK-ERRORS:           ^
114
115; Check that register offset addressing modes only accept 32-bit offset
116; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
117; register.
118  str    d1, [x3, w3, sxtx #3]
119  ldr    s1, [x3, d3, sxtx #2]
120
121; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
122; CHECK-ERRORS:   str    d1, [x3, w3, sxtx #3]
123; CHECK-ERRORS:                       ^
124; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
125; CHECK-ERRORS:   ldr    s1, [x3, d3, sxtx #2]
126; CHECK-ERRORS:                   ^
127
128; Shift immediates range checking.
129  sqrshrn b4, h9, #10
130  rshrn v9.8b, v11.8h, #17
131  sqrshrn v7.4h, v8.4s, #39
132  uqshrn2 v4.4s, v5.2d, #67
133
134; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
135; CHECK-ERRORS:   sqrshrn b4, h9, #10
136; CHECK-ERRORS:                   ^
137; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
138; CHECK-ERRORS:   rshrn v9.8b, v11.8h, #17
139; CHECK-ERRORS:                        ^
140; CHECK-ERRORS: error: immediate must be an integer in range [1, 16].
141; CHECK-ERRORS:   sqrshrn v7.4h, v8.4s, #39
142; CHECK-ERRORS:                         ^
143; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
144; CHECK-ERRORS:   uqshrn2 v4.4s, v5.2d, #67
145; CHECK-ERRORS:                         ^
146
147
148  st1.s4 {v14, v15}, [x2], #32
149; CHECK-ERRORS: error: invalid type suffix for instruction
150; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32
151; CHECK-ERRORS:     ^
152
153
154
155; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156; where Rt==Rn or Rt2==Rn are unpredicatable.
157  ldp x1, x2, [x2], #16
158  ldp x2, x2, [x2], #16
159  ldp w1, w2, [x2], #16
160  ldp w2, w2, [x2], #16
161  ldp x1, x1, [x2]
162
163  ldr x2, [x2], #8
164  ldr x2, [x2, #8]!
165  ldr w2, [x2], #8
166  ldr w2, [x2, #8]!
167
168  str x2, [x2], #8
169  str x2, [x2, #8]!
170  str w2, [x2], #8
171  str w2, [x2, #8]!
172
173; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
174; CHECK-ERRORS:   ldp x1, x2, [x2], #16
175; CHECK-ERRORS:           ^
176; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
177; CHECK-ERRORS:   ldp x2, x2, [x2], #16
178; CHECK-ERRORS:       ^
179; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
180; CHECK-ERRORS:   ldp w1, w2, [x2], #16
181; CHECK-ERRORS:           ^
182; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
183; CHECK-ERRORS:   ldp w2, w2, [x2], #16
184; CHECK-ERRORS:       ^
185; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
186; CHECK-ERRORS:   ldp x1, x1, [x2]
187; CHECK-ERRORS:           ^
188; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
189; CHECK-ERRORS:   ldr x2, [x2], #8
190; CHECK-ERRORS:       ^
191; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
192; CHECK-ERRORS:   ldr x2, [x2, #8]!
193; CHECK-ERRORS:       ^
194; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
195; CHECK-ERRORS:   ldr w2, [x2], #8
196; CHECK-ERRORS:       ^
197; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
198; CHECK-ERRORS:   ldr w2, [x2, #8]!
199; CHECK-ERRORS:       ^
200; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
201; CHECK-ERRORS:   str x2, [x2], #8
202; CHECK-ERRORS:       ^
203; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
204; CHECK-ERRORS:   str x2, [x2, #8]!
205; CHECK-ERRORS:       ^
206; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
207; CHECK-ERRORS:   str w2, [x2], #8
208; CHECK-ERRORS:       ^
209; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
210; CHECK-ERRORS:   str w2, [x2, #8]!
211; CHECK-ERRORS:       ^
212
213; The validity checking for shifted-immediate operands.  rdar://13174476
214; Where the immediate is out of range.
215  add w1, w2, w3, lsr #75
216
217; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
218; CHECK-ERRORS: add w1, w2, w3, lsr #75
219; CHECK-ERRORS:                      ^
220
221; logical instructions on 32-bit regs with shift > 31 is not legal
222orr w0, w0, w0, lsl #32
223; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
224; CHECK-ERRORS:        orr w0, w0, w0, lsl #32
225; CHECK-ERRORS:                        ^
226eor w0, w0, w0, lsl #32
227; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
228; CHECK-ERRORS:        eor w0, w0, w0, lsl #32
229; CHECK-ERRORS:                        ^
230and w0, w0, w0, lsl #32
231; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
232; CHECK-ERRORS:        and w0, w0, w0, lsl #32
233; CHECK-ERRORS:                        ^
234ands w0, w0, w0, lsl #32
235; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
236; CHECK-ERRORS:        ands w0, w0, w0, lsl #32
237; CHECK-ERRORS:                        ^
238
239; Relocated expressions should not be accepted for 32-bit adds or sub (imm)
240add w3, w5, sym@PAGEOFF
241; CHECK-ERRORS: error: invalid immediate expression
242; CHECK-ERRORS: add w3, w5, sym@PAGEOFF
243; CHECK-ERRORS:             ^
244
245adds w3, w5, sym@PAGEOFF
246adds x9, x12, sym@PAGEOFF
247; CHECK-ERRORS: error: invalid immediate expression
248; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF
249; CHECK-ERRORS:              ^
250; CHECK-ERRORS: error: invalid immediate expression
251; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF
252; CHECK-ERRORS:               ^
253
254sub x3, x5, sym@PAGEOFF
255sub w20, w30, sym@PAGEOFF
256; CHECK-ERRORS: error: invalid immediate expression
257; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF
258; CHECK-ERRORS:             ^
259; CHECK-ERRORS: error: invalid immediate expression
260; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF
261; CHECK-ERRORS:               ^
262
263subs w9, w10, sym@PAGEOFF
264subs x20, x30, sym@PAGEOFF
265; CHECK-ERRORS: error: invalid immediate expression
266; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF
267; CHECK-ERRORS:               ^
268; CHECK-ERRORS: error: invalid immediate expression
269; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF
270; CHECK-ERRORS:                ^
271
272tbl v0.8b, { v1 }, v0.8b
273tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
274tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
275tbx v2.8b, { v0 }, v6.8b
276; CHECK-ERRORS: error: invalid operand for instruction
277; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b
278; CHECK-ERRORS:            ^
279; CHECK-ERRORS: error: invalid operand for instruction
280; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
281; CHECK-ERRORS:             ^
282; CHECK-ERRORS: error: invalid operand for instruction
283; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
284; CHECK-ERRORS:             ^
285; CHECK-ERRORS: error: invalid operand for instruction
286; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b
287; CHECK-ERRORS:            ^
288
289b.c #0x4
290; CHECK-ERRORS: error: invalid condition code
291; CHECK-ERRORS: b.c #0x4
292; CHECK-ERRORS:   ^
293
294ic ialluis, x0
295; CHECK-ERRORS: error: specified ic op does not use a register
296ic iallu, x0
297; CHECK-ERRORS: error: specified ic op does not use a register
298ic ivau
299; CHECK-ERRORS: error: specified ic op requires a register
300
301dc zva
302; CHECK-ERRORS: error: specified dc op requires a register
303dc ivac
304; CHECK-ERRORS: error: specified dc op requires a register
305dc isw
306; CHECK-ERRORS: error: specified dc op requires a register
307dc cvac
308; CHECK-ERRORS: error: specified dc op requires a register
309dc csw
310; CHECK-ERRORS: error: specified dc op requires a register
311dc cvau
312; CHECK-ERRORS: error: specified dc op requires a register
313dc civac
314; CHECK-ERRORS: error: specified dc op requires a register
315dc cisw
316; CHECK-ERRORS: error: specified dc op requires a register
317
318at s1e1r
319; CHECK-ERRORS: error: specified at op requires a register
320at s1e2r
321; CHECK-ERRORS: error: specified at op requires a register
322at s1e3r
323; CHECK-ERRORS: error: specified at op requires a register
324at s1e1w
325; CHECK-ERRORS: error: specified at op requires a register
326at s1e2w
327; CHECK-ERRORS: error: specified at op requires a register
328at s1e3w
329; CHECK-ERRORS: error: specified at op requires a register
330at s1e0r
331; CHECK-ERRORS: error: specified at op requires a register
332at s1e0w
333; CHECK-ERRORS: error: specified at op requires a register
334at s12e1r
335; CHECK-ERRORS: error: specified at op requires a register
336at s12e1w
337; CHECK-ERRORS: error: specified at op requires a register
338at s12e0r
339; CHECK-ERRORS: error: specified at op requires a register
340at s12e0w
341; CHECK-ERRORS: error: specified at op requires a register
342
343tlbi vmalle1is, x0
344; CHECK-ERRORS: error: specified tlbi op does not use a register
345tlbi vmalle1, x0
346; CHECK-ERRORS: error: specified tlbi op does not use a register
347tlbi alle1is, x0
348; CHECK-ERRORS: error: specified tlbi op does not use a register
349tlbi alle2is, x0
350; CHECK-ERRORS: error: specified tlbi op does not use a register
351tlbi alle3is, x0
352; CHECK-ERRORS: error: specified tlbi op does not use a register
353tlbi alle1, x0
354; CHECK-ERRORS: error: specified tlbi op does not use a register
355tlbi alle2, x0
356; CHECK-ERRORS: error: specified tlbi op does not use a register
357tlbi alle3, x0
358; CHECK-ERRORS: error: specified tlbi op does not use a register
359tlbi vae1is
360; CHECK-ERRORS: error: specified tlbi op requires a register
361tlbi vae2is
362; CHECK-ERRORS: error: specified tlbi op requires a register
363tlbi vae3is
364; CHECK-ERRORS: error: specified tlbi op requires a register
365tlbi aside1is
366; CHECK-ERRORS: error: specified tlbi op requires a register
367tlbi vaae1is
368; CHECK-ERRORS: error: specified tlbi op requires a register
369tlbi vale1is
370; CHECK-ERRORS: error: specified tlbi op requires a register
371tlbi vaale1is
372; CHECK-ERRORS: error: specified tlbi op requires a register
373tlbi vale2is
374; CHECK-ERRORS: error: specified tlbi op requires a register
375tlbi vale3is
376; CHECK-ERRORS: error: specified tlbi op requires a register
377tlbi vae1
378; CHECK-ERRORS: error: specified tlbi op requires a register
379tlbi vae2
380; CHECK-ERRORS: error: specified tlbi op requires a register
381tlbi vae3
382; CHECK-ERRORS: error: specified tlbi op requires a register
383tlbi aside1
384; CHECK-ERRORS: error: specified tlbi op requires a register
385tlbi vaae1
386; CHECK-ERRORS: error: specified tlbi op requires a register
387tlbi vale1
388; CHECK-ERRORS: error: specified tlbi op requires a register
389tlbi vale2
390; CHECK-ERRORS: error: specified tlbi op requires a register
391tlbi vale3
392; CHECK-ERRORS: error: specified tlbi op requires a register
393