X86RecognizableInstr.cpp revision 50c5c8275e576c2129a4ab6146ca4226dcdfe6fe
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file is part of the X86 Disassembler Emitter. 11// It contains the implementation of a single recognizable instruction. 12// Documentation for the disassembler emitter in general can be found in 13// X86DisasemblerEmitter.h. 14// 15//===----------------------------------------------------------------------===// 16 17#include "X86DisassemblerShared.h" 18#include "X86RecognizableInstr.h" 19#include "X86ModRMFilters.h" 20 21#include "llvm/Support/ErrorHandling.h" 22 23#include <string> 24 25using namespace llvm; 26 27#define MRM_MAPPING \ 28 MAP(C1, 33) \ 29 MAP(C2, 34) \ 30 MAP(C3, 35) \ 31 MAP(C4, 36) \ 32 MAP(C8, 37) \ 33 MAP(C9, 38) \ 34 MAP(E8, 39) \ 35 MAP(F0, 40) \ 36 MAP(F8, 41) \ 37 MAP(F9, 42) \ 38 MAP(D0, 45) \ 39 MAP(D1, 46) \ 40 MAP(D4, 47) \ 41 MAP(D8, 48) \ 42 MAP(D9, 49) \ 43 MAP(DA, 50) \ 44 MAP(DB, 51) \ 45 MAP(DC, 52) \ 46 MAP(DD, 53) \ 47 MAP(DE, 54) \ 48 MAP(DF, 55) 49 50// A clone of X86 since we can't depend on something that is generated. 51namespace X86Local { 52 enum { 53 Pseudo = 0, 54 RawFrm = 1, 55 AddRegFrm = 2, 56 MRMDestReg = 3, 57 MRMDestMem = 4, 58 MRMSrcReg = 5, 59 MRMSrcMem = 6, 60 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 61 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 62 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 63 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 64 MRMInitReg = 32, 65 RawFrmImm8 = 43, 66 RawFrmImm16 = 44, 67#define MAP(from, to) MRM_##from = to, 68 MRM_MAPPING 69#undef MAP 70 lastMRM 71 }; 72 73 enum { 74 TB = 1, 75 REP = 2, 76 D8 = 3, D9 = 4, DA = 5, DB = 6, 77 DC = 7, DD = 8, DE = 9, DF = 10, 78 XD = 11, XS = 12, 79 T8 = 13, P_TA = 14, 80 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19 81 }; 82} 83 84// If rows are added to the opcode extension tables, then corresponding entries 85// must be added here. 86// 87// If the row corresponds to a single byte (i.e., 8f), then add an entry for 88// that byte to ONE_BYTE_EXTENSION_TABLES. 89// 90// If the row corresponds to two bytes where the first is 0f, add an entry for 91// the second byte to TWO_BYTE_EXTENSION_TABLES. 92// 93// If the row corresponds to some other set of bytes, you will need to modify 94// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes 95// to the X86 TD files, except in two cases: if the first two bytes of such a 96// new combination are 0f 38 or 0f 3a, you just have to add maps called 97// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a 98// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line 99// in RecognizableInstr::emitDecodePath(). 100 101#define ONE_BYTE_EXTENSION_TABLES \ 102 EXTENSION_TABLE(80) \ 103 EXTENSION_TABLE(81) \ 104 EXTENSION_TABLE(82) \ 105 EXTENSION_TABLE(83) \ 106 EXTENSION_TABLE(8f) \ 107 EXTENSION_TABLE(c0) \ 108 EXTENSION_TABLE(c1) \ 109 EXTENSION_TABLE(c6) \ 110 EXTENSION_TABLE(c7) \ 111 EXTENSION_TABLE(d0) \ 112 EXTENSION_TABLE(d1) \ 113 EXTENSION_TABLE(d2) \ 114 EXTENSION_TABLE(d3) \ 115 EXTENSION_TABLE(f6) \ 116 EXTENSION_TABLE(f7) \ 117 EXTENSION_TABLE(fe) \ 118 EXTENSION_TABLE(ff) 119 120#define TWO_BYTE_EXTENSION_TABLES \ 121 EXTENSION_TABLE(00) \ 122 EXTENSION_TABLE(01) \ 123 EXTENSION_TABLE(18) \ 124 EXTENSION_TABLE(71) \ 125 EXTENSION_TABLE(72) \ 126 EXTENSION_TABLE(73) \ 127 EXTENSION_TABLE(ae) \ 128 EXTENSION_TABLE(ba) \ 129 EXTENSION_TABLE(c7) 130 131#define THREE_BYTE_38_EXTENSION_TABLES \ 132 EXTENSION_TABLE(F3) 133 134using namespace X86Disassembler; 135 136/// needsModRMForDecode - Indicates whether a particular instruction requires a 137/// ModR/M byte for the instruction to be properly decoded. For example, a 138/// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to 139/// 0b11. 140/// 141/// @param form - The form of the instruction. 142/// @return - true if the form implies that a ModR/M byte is required, false 143/// otherwise. 144static bool needsModRMForDecode(uint8_t form) { 145 if (form == X86Local::MRMDestReg || 146 form == X86Local::MRMDestMem || 147 form == X86Local::MRMSrcReg || 148 form == X86Local::MRMSrcMem || 149 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || 150 (form >= X86Local::MRM0m && form <= X86Local::MRM7m)) 151 return true; 152 else 153 return false; 154} 155 156/// isRegFormat - Indicates whether a particular form requires the Mod field of 157/// the ModR/M byte to be 0b11. 158/// 159/// @param form - The form of the instruction. 160/// @return - true if the form implies that Mod must be 0b11, false 161/// otherwise. 162static bool isRegFormat(uint8_t form) { 163 if (form == X86Local::MRMDestReg || 164 form == X86Local::MRMSrcReg || 165 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) 166 return true; 167 else 168 return false; 169} 170 171/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 172/// Useful for switch statements and the like. 173/// 174/// @param init - A reference to the BitsInit to be decoded. 175/// @return - The field, with the first bit in the BitsInit as the lowest 176/// order bit. 177static uint8_t byteFromBitsInit(BitsInit &init) { 178 int width = init.getNumBits(); 179 180 assert(width <= 8 && "Field is too large for uint8_t!"); 181 182 int index; 183 uint8_t mask = 0x01; 184 185 uint8_t ret = 0; 186 187 for (index = 0; index < width; index++) { 188 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 189 ret |= mask; 190 191 mask <<= 1; 192 } 193 194 return ret; 195} 196 197/// byteFromRec - Extract a value at most 8 bits in with from a Record given the 198/// name of the field. 199/// 200/// @param rec - The record from which to extract the value. 201/// @param name - The name of the field in the record. 202/// @return - The field, as translated by byteFromBitsInit(). 203static uint8_t byteFromRec(const Record* rec, const std::string &name) { 204 BitsInit* bits = rec->getValueAsBitsInit(name); 205 return byteFromBitsInit(*bits); 206} 207 208RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 209 const CodeGenInstruction &insn, 210 InstrUID uid) { 211 UID = uid; 212 213 Rec = insn.TheDef; 214 Name = Rec->getName(); 215 Spec = &tables.specForUID(UID); 216 217 if (!Rec->isSubClassOf("X86Inst")) { 218 ShouldBeEmitted = false; 219 return; 220 } 221 222 Prefix = byteFromRec(Rec, "Prefix"); 223 Opcode = byteFromRec(Rec, "Opcode"); 224 Form = byteFromRec(Rec, "FormBits"); 225 SegOvr = byteFromRec(Rec, "SegOvrBits"); 226 227 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); 228 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix"); 229 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 230 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix"); 231 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); 232 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix"); 233 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 234 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); 235 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 236 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); 237 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 238 239 Name = Rec->getName(); 240 AsmString = Rec->getValueAsString("AsmString"); 241 242 Operands = &insn.Operands.OperandList; 243 244 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) || 245 (Name.find("CRC32") != Name.npos); 246 HasFROperands = hasFROperands(); 247 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); 248 249 // Check for 64-bit inst which does not require REX 250 Is32Bit = false; 251 Is64Bit = false; 252 // FIXME: Is there some better way to check for In64BitMode? 253 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 254 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 255 if (Predicates[i]->getName().find("32Bit") != Name.npos) { 256 Is32Bit = true; 257 break; 258 } 259 if (Predicates[i]->getName().find("64Bit") != Name.npos) { 260 Is64Bit = true; 261 break; 262 } 263 } 264 // FIXME: These instructions aren't marked as 64-bit in any way 265 Is64Bit |= Rec->getName() == "JMP64pcrel32" || 266 Rec->getName() == "MASKMOVDQU64" || 267 Rec->getName() == "POPFS64" || 268 Rec->getName() == "POPGS64" || 269 Rec->getName() == "PUSHFS64" || 270 Rec->getName() == "PUSHGS64" || 271 Rec->getName() == "REX64_PREFIX" || 272 Rec->getName().find("MOV64") != Name.npos || 273 Rec->getName().find("PUSH64") != Name.npos || 274 Rec->getName().find("POP64") != Name.npos; 275 276 ShouldBeEmitted = true; 277} 278 279void RecognizableInstr::processInstr(DisassemblerTables &tables, 280 const CodeGenInstruction &insn, 281 InstrUID uid) 282{ 283 // Ignore "asm parser only" instructions. 284 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 285 return; 286 287 RecognizableInstr recogInstr(tables, insn, uid); 288 289 recogInstr.emitInstructionSpecifier(tables); 290 291 if (recogInstr.shouldBeEmitted()) 292 recogInstr.emitDecodePath(tables); 293} 294 295InstructionContext RecognizableInstr::insnContext() const { 296 InstructionContext insnContext; 297 298 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) { 299 if (HasVEX_LPrefix && HasVEX_WPrefix) { 300 if (HasOpSizePrefix) 301 insnContext = IC_VEX_L_W_OPSIZE; 302 else 303 llvm_unreachable("Don't support VEX.L and VEX.W together"); 304 } else if (HasOpSizePrefix && HasVEX_LPrefix) 305 insnContext = IC_VEX_L_OPSIZE; 306 else if (HasOpSizePrefix && HasVEX_WPrefix) 307 insnContext = IC_VEX_W_OPSIZE; 308 else if (HasOpSizePrefix) 309 insnContext = IC_VEX_OPSIZE; 310 else if (HasVEX_LPrefix && 311 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 312 insnContext = IC_VEX_L_XS; 313 else if (HasVEX_LPrefix && (Prefix == X86Local::XD || 314 Prefix == X86Local::T8XD || 315 Prefix == X86Local::TAXD)) 316 insnContext = IC_VEX_L_XD; 317 else if (HasVEX_WPrefix && 318 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 319 insnContext = IC_VEX_W_XS; 320 else if (HasVEX_WPrefix && (Prefix == X86Local::XD || 321 Prefix == X86Local::T8XD || 322 Prefix == X86Local::TAXD)) 323 insnContext = IC_VEX_W_XD; 324 else if (HasVEX_WPrefix) 325 insnContext = IC_VEX_W; 326 else if (HasVEX_LPrefix) 327 insnContext = IC_VEX_L; 328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || 329 Prefix == X86Local::TAXD) 330 insnContext = IC_VEX_XD; 331 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) 332 insnContext = IC_VEX_XS; 333 else 334 insnContext = IC_VEX; 335 } else if (Is64Bit || HasREX_WPrefix) { 336 if (HasREX_WPrefix && HasOpSizePrefix) 337 insnContext = IC_64BIT_REXW_OPSIZE; 338 else if (HasOpSizePrefix && (Prefix == X86Local::XD || 339 Prefix == X86Local::T8XD || 340 Prefix == X86Local::TAXD)) 341 insnContext = IC_64BIT_XD_OPSIZE; 342 else if (HasOpSizePrefix && 343 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 344 insnContext = IC_64BIT_XS_OPSIZE; 345 else if (HasOpSizePrefix) 346 insnContext = IC_64BIT_OPSIZE; 347 else if (HasAdSizePrefix) 348 insnContext = IC_64BIT_ADSIZE; 349 else if (HasREX_WPrefix && 350 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 351 insnContext = IC_64BIT_REXW_XS; 352 else if (HasREX_WPrefix && (Prefix == X86Local::XD || 353 Prefix == X86Local::T8XD || 354 Prefix == X86Local::TAXD)) 355 insnContext = IC_64BIT_REXW_XD; 356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || 357 Prefix == X86Local::TAXD) 358 insnContext = IC_64BIT_XD; 359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) 360 insnContext = IC_64BIT_XS; 361 else if (HasREX_WPrefix) 362 insnContext = IC_64BIT_REXW; 363 else 364 insnContext = IC_64BIT; 365 } else { 366 if (HasOpSizePrefix && (Prefix == X86Local::XD || 367 Prefix == X86Local::T8XD || 368 Prefix == X86Local::TAXD)) 369 insnContext = IC_XD_OPSIZE; 370 else if (HasOpSizePrefix && 371 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) 372 insnContext = IC_XS_OPSIZE; 373 else if (HasOpSizePrefix) 374 insnContext = IC_OPSIZE; 375 else if (HasAdSizePrefix) 376 insnContext = IC_ADSIZE; 377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || 378 Prefix == X86Local::TAXD) 379 insnContext = IC_XD; 380 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS || 381 Prefix == X86Local::REP) 382 insnContext = IC_XS; 383 else 384 insnContext = IC; 385 } 386 387 return insnContext; 388} 389 390RecognizableInstr::filter_ret RecognizableInstr::filter() const { 391 /////////////////// 392 // FILTER_STRONG 393 // 394 395 // Filter out intrinsics 396 397 if (!Rec->isSubClassOf("X86Inst")) 398 return FILTER_STRONG; 399 400 if (Form == X86Local::Pseudo || 401 (IsCodeGenOnly && Name.find("_REV") == Name.npos)) 402 return FILTER_STRONG; 403 404 if (Form == X86Local::MRMInitReg) 405 return FILTER_STRONG; 406 407 408 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is 409 // printed as a separate "instruction". 410 411 if (Name.find("_Int") != Name.npos || 412 Name.find("Int_") != Name.npos || 413 Name.find("_NOREX") != Name.npos) 414 return FILTER_STRONG; 415 416 // Filter out instructions with segment override prefixes. 417 // They're too messy to handle now and we'll special case them if needed. 418 419 if (SegOvr) 420 return FILTER_STRONG; 421 422 // Filter out instructions that can't be printed. 423 424 if (AsmString.size() == 0) 425 return FILTER_STRONG; 426 427 // Filter out instructions with subreg operands. 428 429 if (AsmString.find("subreg") != AsmString.npos) 430 return FILTER_STRONG; 431 432 ///////////////// 433 // FILTER_WEAK 434 // 435 436 437 // Filter out instructions with a LOCK prefix; 438 // prefer forms that do not have the prefix 439 if (HasLockPrefix) 440 return FILTER_WEAK; 441 442 // Filter out alternate forms of AVX instructions 443 if (Name.find("_alt") != Name.npos || 444 Name.find("XrYr") != Name.npos || 445 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) || 446 Name.find("_64mr") != Name.npos || 447 Name.find("Xrr") != Name.npos || 448 Name.find("rr64") != Name.npos) 449 return FILTER_WEAK; 450 451 // Special cases. 452 453 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI") 454 return FILTER_WEAK; 455 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI") 456 return FILTER_WEAK; 457 458 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos) 459 return FILTER_WEAK; 460 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos) 461 return FILTER_WEAK; 462 if (Name.find("Fs") != Name.npos) 463 return FILTER_WEAK; 464 if (Name == "PUSH64i16" || 465 Name == "MOVPQI2QImr" || 466 Name == "VMOVPQI2QImr" || 467 Name == "MMX_MOVD64rrv164" || 468 Name == "MOV64ri64i32" || 469 Name == "VMASKMOVDQU64" || 470 Name == "VEXTRACTPSrr64" || 471 Name == "VMOVQd64rr" || 472 Name == "VMOVQs64rr") 473 return FILTER_WEAK; 474 475 if (HasFROperands && Name.find("MOV") != Name.npos && 476 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || 477 (Name.find("to") != Name.npos))) 478 return FILTER_STRONG; 479 480 return FILTER_NORMAL; 481} 482 483bool RecognizableInstr::hasFROperands() const { 484 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 485 unsigned numOperands = OperandList.size(); 486 487 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 488 const std::string &recName = OperandList[operandIndex].Rec->getName(); 489 490 if (recName.find("FR") != recName.npos) 491 return true; 492 } 493 return false; 494} 495 496bool RecognizableInstr::has256BitOperands() const { 497 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 498 unsigned numOperands = OperandList.size(); 499 500 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 501 const std::string &recName = OperandList[operandIndex].Rec->getName(); 502 503 if (!recName.compare("VR256")) { 504 return true; 505 } 506 } 507 return false; 508} 509 510void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 511 unsigned &physicalOperandIndex, 512 unsigned &numPhysicalOperands, 513 const unsigned *operandMapping, 514 OperandEncoding (*encodingFromString) 515 (const std::string&, 516 bool hasOpSizePrefix)) { 517 if (optional) { 518 if (physicalOperandIndex >= numPhysicalOperands) 519 return; 520 } else { 521 assert(physicalOperandIndex < numPhysicalOperands); 522 } 523 524 while (operandMapping[operandIndex] != operandIndex) { 525 Spec->operands[operandIndex].encoding = ENCODING_DUP; 526 Spec->operands[operandIndex].type = 527 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 528 ++operandIndex; 529 } 530 531 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 532 533 Spec->operands[operandIndex].encoding = encodingFromString(typeName, 534 HasOpSizePrefix); 535 Spec->operands[operandIndex].type = typeFromString(typeName, 536 IsSSE, 537 HasREX_WPrefix, 538 HasOpSizePrefix); 539 540 ++operandIndex; 541 ++physicalOperandIndex; 542} 543 544void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { 545 Spec->name = Name; 546 547 if (!Rec->isSubClassOf("X86Inst")) 548 return; 549 550 switch (filter()) { 551 case FILTER_WEAK: 552 Spec->filtered = true; 553 break; 554 case FILTER_STRONG: 555 ShouldBeEmitted = false; 556 return; 557 case FILTER_NORMAL: 558 break; 559 } 560 561 Spec->insnContext = insnContext(); 562 563 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 564 565 unsigned numOperands = OperandList.size(); 566 unsigned numPhysicalOperands = 0; 567 568 // operandMapping maps from operands in OperandList to their originals. 569 // If operandMapping[i] != i, then the entry is a duplicate. 570 unsigned operandMapping[X86_MAX_OPERANDS]; 571 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 572 573 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 574 if (OperandList[operandIndex].Constraints.size()) { 575 const CGIOperandList::ConstraintInfo &Constraint = 576 OperandList[operandIndex].Constraints[0]; 577 if (Constraint.isTied()) { 578 operandMapping[operandIndex] = operandIndex; 579 operandMapping[Constraint.getTiedOperand()] = operandIndex; 580 } else { 581 ++numPhysicalOperands; 582 operandMapping[operandIndex] = operandIndex; 583 } 584 } else { 585 ++numPhysicalOperands; 586 operandMapping[operandIndex] = operandIndex; 587 } 588 } 589 590 if (!ShouldBeEmitted) 591 return; 592 593#define HANDLE_OPERAND(class) \ 594 handleOperand(false, \ 595 operandIndex, \ 596 physicalOperandIndex, \ 597 numPhysicalOperands, \ 598 operandMapping, \ 599 class##EncodingFromString); 600 601#define HANDLE_OPTIONAL(class) \ 602 handleOperand(true, \ 603 operandIndex, \ 604 physicalOperandIndex, \ 605 numPhysicalOperands, \ 606 operandMapping, \ 607 class##EncodingFromString); 608 609 // operandIndex should always be < numOperands 610 unsigned operandIndex = 0; 611 // physicalOperandIndex should always be < numPhysicalOperands 612 unsigned physicalOperandIndex = 0; 613 614 switch (Form) { 615 case X86Local::RawFrm: 616 // Operand 1 (optional) is an address or immediate. 617 // Operand 2 (optional) is an immediate. 618 assert(numPhysicalOperands <= 2 && 619 "Unexpected number of operands for RawFrm"); 620 HANDLE_OPTIONAL(relocation) 621 HANDLE_OPTIONAL(immediate) 622 break; 623 case X86Local::AddRegFrm: 624 // Operand 1 is added to the opcode. 625 // Operand 2 (optional) is an address. 626 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 627 "Unexpected number of operands for AddRegFrm"); 628 HANDLE_OPERAND(opcodeModifier) 629 HANDLE_OPTIONAL(relocation) 630 break; 631 case X86Local::MRMDestReg: 632 // Operand 1 is a register operand in the R/M field. 633 // Operand 2 is a register operand in the Reg/Opcode field. 634 // - In AVX, there is a register operand in the VEX.vvvv field here - 635 // Operand 3 (optional) is an immediate. 636 if (HasVEX_4VPrefix) 637 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 638 "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); 639 else 640 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 641 "Unexpected number of operands for MRMDestRegFrm"); 642 643 HANDLE_OPERAND(rmRegister) 644 645 if (HasVEX_4VPrefix) 646 // FIXME: In AVX, the register below becomes the one encoded 647 // in ModRMVEX and the one above the one in the VEX.VVVV field 648 HANDLE_OPERAND(vvvvRegister) 649 650 HANDLE_OPERAND(roRegister) 651 HANDLE_OPTIONAL(immediate) 652 break; 653 case X86Local::MRMDestMem: 654 // Operand 1 is a memory operand (possibly SIB-extended) 655 // Operand 2 is a register operand in the Reg/Opcode field. 656 // - In AVX, there is a register operand in the VEX.vvvv field here - 657 // Operand 3 (optional) is an immediate. 658 if (HasVEX_4VPrefix) 659 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 660 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 661 else 662 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 663 "Unexpected number of operands for MRMDestMemFrm"); 664 HANDLE_OPERAND(memory) 665 666 if (HasVEX_4VPrefix) 667 // FIXME: In AVX, the register below becomes the one encoded 668 // in ModRMVEX and the one above the one in the VEX.VVVV field 669 HANDLE_OPERAND(vvvvRegister) 670 671 HANDLE_OPERAND(roRegister) 672 HANDLE_OPTIONAL(immediate) 673 break; 674 case X86Local::MRMSrcReg: 675 // Operand 1 is a register operand in the Reg/Opcode field. 676 // Operand 2 is a register operand in the R/M field. 677 // - In AVX, there is a register operand in the VEX.vvvv field here - 678 // Operand 3 (optional) is an immediate. 679 // Operand 4 (optional) is an immediate. 680 681 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) 682 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 683 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 684 else 685 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 && 686 "Unexpected number of operands for MRMSrcRegFrm"); 687 688 HANDLE_OPERAND(roRegister) 689 690 if (HasVEX_4VPrefix) 691 // FIXME: In AVX, the register below becomes the one encoded 692 // in ModRMVEX and the one above the one in the VEX.VVVV field 693 HANDLE_OPERAND(vvvvRegister) 694 695 if (HasMemOp4Prefix) 696 HANDLE_OPERAND(immediate) 697 698 HANDLE_OPERAND(rmRegister) 699 700 if (HasVEX_4VOp3Prefix) 701 HANDLE_OPERAND(vvvvRegister) 702 703 if (!HasMemOp4Prefix) 704 HANDLE_OPTIONAL(immediate) 705 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 706 HANDLE_OPTIONAL(immediate) 707 break; 708 case X86Local::MRMSrcMem: 709 // Operand 1 is a register operand in the Reg/Opcode field. 710 // Operand 2 is a memory operand (possibly SIB-extended) 711 // - In AVX, there is a register operand in the VEX.vvvv field here - 712 // Operand 3 (optional) is an immediate. 713 714 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) 715 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 716 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 717 else 718 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 719 "Unexpected number of operands for MRMSrcMemFrm"); 720 721 HANDLE_OPERAND(roRegister) 722 723 if (HasVEX_4VPrefix) 724 // FIXME: In AVX, the register below becomes the one encoded 725 // in ModRMVEX and the one above the one in the VEX.VVVV field 726 HANDLE_OPERAND(vvvvRegister) 727 728 if (HasMemOp4Prefix) 729 HANDLE_OPERAND(immediate) 730 731 HANDLE_OPERAND(memory) 732 733 if (HasVEX_4VOp3Prefix) 734 HANDLE_OPERAND(vvvvRegister) 735 736 if (!HasMemOp4Prefix) 737 HANDLE_OPTIONAL(immediate) 738 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 739 break; 740 case X86Local::MRM0r: 741 case X86Local::MRM1r: 742 case X86Local::MRM2r: 743 case X86Local::MRM3r: 744 case X86Local::MRM4r: 745 case X86Local::MRM5r: 746 case X86Local::MRM6r: 747 case X86Local::MRM7r: 748 // Operand 1 is a register operand in the R/M field. 749 // Operand 2 (optional) is an immediate or relocation. 750 // Operand 3 (optional) is an immediate. 751 if (HasVEX_4VPrefix) 752 assert(numPhysicalOperands <= 3 && 753 "Unexpected number of operands for MRMnRFrm with VEX_4V"); 754 else 755 assert(numPhysicalOperands <= 3 && 756 "Unexpected number of operands for MRMnRFrm"); 757 if (HasVEX_4VPrefix) 758 HANDLE_OPERAND(vvvvRegister) 759 HANDLE_OPTIONAL(rmRegister) 760 HANDLE_OPTIONAL(relocation) 761 HANDLE_OPTIONAL(immediate) 762 break; 763 case X86Local::MRM0m: 764 case X86Local::MRM1m: 765 case X86Local::MRM2m: 766 case X86Local::MRM3m: 767 case X86Local::MRM4m: 768 case X86Local::MRM5m: 769 case X86Local::MRM6m: 770 case X86Local::MRM7m: 771 // Operand 1 is a memory operand (possibly SIB-extended) 772 // Operand 2 (optional) is an immediate or relocation. 773 if (HasVEX_4VPrefix) 774 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 775 "Unexpected number of operands for MRMnMFrm"); 776 else 777 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 778 "Unexpected number of operands for MRMnMFrm"); 779 if (HasVEX_4VPrefix) 780 HANDLE_OPERAND(vvvvRegister) 781 HANDLE_OPERAND(memory) 782 HANDLE_OPTIONAL(relocation) 783 break; 784 case X86Local::RawFrmImm8: 785 // operand 1 is a 16-bit immediate 786 // operand 2 is an 8-bit immediate 787 assert(numPhysicalOperands == 2 && 788 "Unexpected number of operands for X86Local::RawFrmImm8"); 789 HANDLE_OPERAND(immediate) 790 HANDLE_OPERAND(immediate) 791 break; 792 case X86Local::RawFrmImm16: 793 // operand 1 is a 16-bit immediate 794 // operand 2 is a 16-bit immediate 795 HANDLE_OPERAND(immediate) 796 HANDLE_OPERAND(immediate) 797 break; 798 case X86Local::MRMInitReg: 799 // Ignored. 800 break; 801 } 802 803 #undef HANDLE_OPERAND 804 #undef HANDLE_OPTIONAL 805} 806 807void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 808 // Special cases where the LLVM tables are not complete 809 810#define MAP(from, to) \ 811 case X86Local::MRM_##from: \ 812 filter = new ExactFilter(0x##from); \ 813 break; 814 815 OpcodeType opcodeType = (OpcodeType)-1; 816 817 ModRMFilter* filter = NULL; 818 uint8_t opcodeToSet = 0; 819 820 switch (Prefix) { 821 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f 822 case X86Local::XD: 823 case X86Local::XS: 824 case X86Local::TB: 825 opcodeType = TWOBYTE; 826 827 switch (Opcode) { 828 default: 829 if (needsModRMForDecode(Form)) 830 filter = new ModFilter(isRegFormat(Form)); 831 else 832 filter = new DumbFilter(); 833 break; 834#define EXTENSION_TABLE(n) case 0x##n: 835 TWO_BYTE_EXTENSION_TABLES 836#undef EXTENSION_TABLE 837 switch (Form) { 838 default: 839 llvm_unreachable("Unhandled two-byte extended opcode"); 840 case X86Local::MRM0r: 841 case X86Local::MRM1r: 842 case X86Local::MRM2r: 843 case X86Local::MRM3r: 844 case X86Local::MRM4r: 845 case X86Local::MRM5r: 846 case X86Local::MRM6r: 847 case X86Local::MRM7r: 848 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 849 break; 850 case X86Local::MRM0m: 851 case X86Local::MRM1m: 852 case X86Local::MRM2m: 853 case X86Local::MRM3m: 854 case X86Local::MRM4m: 855 case X86Local::MRM5m: 856 case X86Local::MRM6m: 857 case X86Local::MRM7m: 858 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 859 break; 860 MRM_MAPPING 861 } // switch (Form) 862 break; 863 } // switch (Opcode) 864 opcodeToSet = Opcode; 865 break; 866 case X86Local::T8: 867 case X86Local::T8XD: 868 case X86Local::T8XS: 869 opcodeType = THREEBYTE_38; 870 switch (Opcode) { 871 default: 872 if (needsModRMForDecode(Form)) 873 filter = new ModFilter(isRegFormat(Form)); 874 else 875 filter = new DumbFilter(); 876 break; 877#define EXTENSION_TABLE(n) case 0x##n: 878 THREE_BYTE_38_EXTENSION_TABLES 879#undef EXTENSION_TABLE 880 switch (Form) { 881 default: 882 llvm_unreachable("Unhandled two-byte extended opcode"); 883 case X86Local::MRM0r: 884 case X86Local::MRM1r: 885 case X86Local::MRM2r: 886 case X86Local::MRM3r: 887 case X86Local::MRM4r: 888 case X86Local::MRM5r: 889 case X86Local::MRM6r: 890 case X86Local::MRM7r: 891 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 892 break; 893 case X86Local::MRM0m: 894 case X86Local::MRM1m: 895 case X86Local::MRM2m: 896 case X86Local::MRM3m: 897 case X86Local::MRM4m: 898 case X86Local::MRM5m: 899 case X86Local::MRM6m: 900 case X86Local::MRM7m: 901 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 902 break; 903 MRM_MAPPING 904 } // switch (Form) 905 break; 906 } // switch (Opcode) 907 opcodeToSet = Opcode; 908 break; 909 case X86Local::P_TA: 910 case X86Local::TAXD: 911 opcodeType = THREEBYTE_3A; 912 if (needsModRMForDecode(Form)) 913 filter = new ModFilter(isRegFormat(Form)); 914 else 915 filter = new DumbFilter(); 916 opcodeToSet = Opcode; 917 break; 918 case X86Local::A6: 919 opcodeType = THREEBYTE_A6; 920 if (needsModRMForDecode(Form)) 921 filter = new ModFilter(isRegFormat(Form)); 922 else 923 filter = new DumbFilter(); 924 opcodeToSet = Opcode; 925 break; 926 case X86Local::A7: 927 opcodeType = THREEBYTE_A7; 928 if (needsModRMForDecode(Form)) 929 filter = new ModFilter(isRegFormat(Form)); 930 else 931 filter = new DumbFilter(); 932 opcodeToSet = Opcode; 933 break; 934 case X86Local::D8: 935 case X86Local::D9: 936 case X86Local::DA: 937 case X86Local::DB: 938 case X86Local::DC: 939 case X86Local::DD: 940 case X86Local::DE: 941 case X86Local::DF: 942 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); 943 opcodeType = ONEBYTE; 944 if (Form == X86Local::AddRegFrm) { 945 Spec->modifierType = MODIFIER_MODRM; 946 Spec->modifierBase = Opcode; 947 filter = new AddRegEscapeFilter(Opcode); 948 } else { 949 filter = new EscapeFilter(true, Opcode); 950 } 951 opcodeToSet = 0xd8 + (Prefix - X86Local::D8); 952 break; 953 case X86Local::REP: 954 default: 955 opcodeType = ONEBYTE; 956 switch (Opcode) { 957#define EXTENSION_TABLE(n) case 0x##n: 958 ONE_BYTE_EXTENSION_TABLES 959#undef EXTENSION_TABLE 960 switch (Form) { 961 default: 962 llvm_unreachable("Fell through the cracks of a single-byte " 963 "extended opcode"); 964 case X86Local::MRM0r: 965 case X86Local::MRM1r: 966 case X86Local::MRM2r: 967 case X86Local::MRM3r: 968 case X86Local::MRM4r: 969 case X86Local::MRM5r: 970 case X86Local::MRM6r: 971 case X86Local::MRM7r: 972 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 973 break; 974 case X86Local::MRM0m: 975 case X86Local::MRM1m: 976 case X86Local::MRM2m: 977 case X86Local::MRM3m: 978 case X86Local::MRM4m: 979 case X86Local::MRM5m: 980 case X86Local::MRM6m: 981 case X86Local::MRM7m: 982 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 983 break; 984 MRM_MAPPING 985 } // switch (Form) 986 break; 987 case 0xd8: 988 case 0xd9: 989 case 0xda: 990 case 0xdb: 991 case 0xdc: 992 case 0xdd: 993 case 0xde: 994 case 0xdf: 995 filter = new EscapeFilter(false, Form - X86Local::MRM0m); 996 break; 997 default: 998 if (needsModRMForDecode(Form)) 999 filter = new ModFilter(isRegFormat(Form)); 1000 else 1001 filter = new DumbFilter(); 1002 break; 1003 } // switch (Opcode) 1004 opcodeToSet = Opcode; 1005 } // switch (Prefix) 1006 1007 assert(opcodeType != (OpcodeType)-1 && 1008 "Opcode type not set"); 1009 assert(filter && "Filter not set"); 1010 1011 if (Form == X86Local::AddRegFrm) { 1012 if(Spec->modifierType != MODIFIER_MODRM) { 1013 assert(opcodeToSet < 0xf9 && 1014 "Not enough room for all ADDREG_FRM operands"); 1015 1016 uint8_t currentOpcode; 1017 1018 for (currentOpcode = opcodeToSet; 1019 currentOpcode < opcodeToSet + 8; 1020 ++currentOpcode) 1021 tables.setTableFields(opcodeType, 1022 insnContext(), 1023 currentOpcode, 1024 *filter, 1025 UID, Is32Bit, IgnoresVEX_L); 1026 1027 Spec->modifierType = MODIFIER_OPCODE; 1028 Spec->modifierBase = opcodeToSet; 1029 } else { 1030 // modifierBase was set where MODIFIER_MODRM was set 1031 tables.setTableFields(opcodeType, 1032 insnContext(), 1033 opcodeToSet, 1034 *filter, 1035 UID, Is32Bit, IgnoresVEX_L); 1036 } 1037 } else { 1038 tables.setTableFields(opcodeType, 1039 insnContext(), 1040 opcodeToSet, 1041 *filter, 1042 UID, Is32Bit, IgnoresVEX_L); 1043 1044 Spec->modifierType = MODIFIER_NONE; 1045 Spec->modifierBase = opcodeToSet; 1046 } 1047 1048 delete filter; 1049 1050#undef MAP 1051} 1052 1053#define TYPE(str, type) if (s == str) return type; 1054OperandType RecognizableInstr::typeFromString(const std::string &s, 1055 bool isSSE, 1056 bool hasREX_WPrefix, 1057 bool hasOpSizePrefix) { 1058 if (isSSE) { 1059 // For SSE instructions, we ignore the OpSize prefix and force operand 1060 // sizes. 1061 TYPE("GR16", TYPE_R16) 1062 TYPE("GR32", TYPE_R32) 1063 TYPE("GR64", TYPE_R64) 1064 } 1065 if(hasREX_WPrefix) { 1066 // For instructions with a REX_W prefix, a declared 32-bit register encoding 1067 // is special. 1068 TYPE("GR32", TYPE_R32) 1069 } 1070 if(!hasOpSizePrefix) { 1071 // For instructions without an OpSize prefix, a declared 16-bit register or 1072 // immediate encoding is special. 1073 TYPE("GR16", TYPE_R16) 1074 TYPE("i16imm", TYPE_IMM16) 1075 } 1076 TYPE("i16mem", TYPE_Mv) 1077 TYPE("i16imm", TYPE_IMMv) 1078 TYPE("i16i8imm", TYPE_IMMv) 1079 TYPE("GR16", TYPE_Rv) 1080 TYPE("i32mem", TYPE_Mv) 1081 TYPE("i32imm", TYPE_IMMv) 1082 TYPE("i32i8imm", TYPE_IMM32) 1083 TYPE("u32u8imm", TYPE_IMM32) 1084 TYPE("GR32", TYPE_Rv) 1085 TYPE("i64mem", TYPE_Mv) 1086 TYPE("i64i32imm", TYPE_IMM64) 1087 TYPE("i64i8imm", TYPE_IMM64) 1088 TYPE("GR64", TYPE_R64) 1089 TYPE("i8mem", TYPE_M8) 1090 TYPE("i8imm", TYPE_IMM8) 1091 TYPE("GR8", TYPE_R8) 1092 TYPE("VR128", TYPE_XMM128) 1093 TYPE("f128mem", TYPE_M128) 1094 TYPE("f256mem", TYPE_M256) 1095 TYPE("FR64", TYPE_XMM64) 1096 TYPE("f64mem", TYPE_M64FP) 1097 TYPE("sdmem", TYPE_M64FP) 1098 TYPE("FR32", TYPE_XMM32) 1099 TYPE("f32mem", TYPE_M32FP) 1100 TYPE("ssmem", TYPE_M32FP) 1101 TYPE("RST", TYPE_ST) 1102 TYPE("i128mem", TYPE_M128) 1103 TYPE("i256mem", TYPE_M256) 1104 TYPE("i64i32imm_pcrel", TYPE_REL64) 1105 TYPE("i16imm_pcrel", TYPE_REL16) 1106 TYPE("i32imm_pcrel", TYPE_REL32) 1107 TYPE("SSECC", TYPE_IMM3) 1108 TYPE("AVXCC", TYPE_IMM5) 1109 TYPE("brtarget", TYPE_RELv) 1110 TYPE("uncondbrtarget", TYPE_RELv) 1111 TYPE("brtarget8", TYPE_REL8) 1112 TYPE("f80mem", TYPE_M80FP) 1113 TYPE("lea32mem", TYPE_LEA) 1114 TYPE("lea64_32mem", TYPE_LEA) 1115 TYPE("lea64mem", TYPE_LEA) 1116 TYPE("VR64", TYPE_MM64) 1117 TYPE("i64imm", TYPE_IMMv) 1118 TYPE("opaque32mem", TYPE_M1616) 1119 TYPE("opaque48mem", TYPE_M1632) 1120 TYPE("opaque80mem", TYPE_M1664) 1121 TYPE("opaque512mem", TYPE_M512) 1122 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 1123 TYPE("DEBUG_REG", TYPE_DEBUGREG) 1124 TYPE("CONTROL_REG", TYPE_CONTROLREG) 1125 TYPE("offset8", TYPE_MOFFS8) 1126 TYPE("offset16", TYPE_MOFFS16) 1127 TYPE("offset32", TYPE_MOFFS32) 1128 TYPE("offset64", TYPE_MOFFS64) 1129 TYPE("VR256", TYPE_XMM256) 1130 TYPE("GR16_NOAX", TYPE_Rv) 1131 TYPE("GR32_NOAX", TYPE_Rv) 1132 TYPE("GR64_NOAX", TYPE_R64) 1133 TYPE("vx32mem", TYPE_M32) 1134 TYPE("vy32mem", TYPE_M32) 1135 TYPE("vx64mem", TYPE_M64) 1136 TYPE("vy64mem", TYPE_M64) 1137 errs() << "Unhandled type string " << s << "\n"; 1138 llvm_unreachable("Unhandled type string"); 1139} 1140#undef TYPE 1141 1142#define ENCODING(str, encoding) if (s == str) return encoding; 1143OperandEncoding RecognizableInstr::immediateEncodingFromString 1144 (const std::string &s, 1145 bool hasOpSizePrefix) { 1146 if(!hasOpSizePrefix) { 1147 // For instructions without an OpSize prefix, a declared 16-bit register or 1148 // immediate encoding is special. 1149 ENCODING("i16imm", ENCODING_IW) 1150 } 1151 ENCODING("i32i8imm", ENCODING_IB) 1152 ENCODING("u32u8imm", ENCODING_IB) 1153 ENCODING("SSECC", ENCODING_IB) 1154 ENCODING("AVXCC", ENCODING_IB) 1155 ENCODING("i16imm", ENCODING_Iv) 1156 ENCODING("i16i8imm", ENCODING_IB) 1157 ENCODING("i32imm", ENCODING_Iv) 1158 ENCODING("i64i32imm", ENCODING_ID) 1159 ENCODING("i64i8imm", ENCODING_IB) 1160 ENCODING("i8imm", ENCODING_IB) 1161 // This is not a typo. Instructions like BLENDVPD put 1162 // register IDs in 8-bit immediates nowadays. 1163 ENCODING("VR256", ENCODING_IB) 1164 ENCODING("VR128", ENCODING_IB) 1165 errs() << "Unhandled immediate encoding " << s << "\n"; 1166 llvm_unreachable("Unhandled immediate encoding"); 1167} 1168 1169OperandEncoding RecognizableInstr::rmRegisterEncodingFromString 1170 (const std::string &s, 1171 bool hasOpSizePrefix) { 1172 ENCODING("GR16", ENCODING_RM) 1173 ENCODING("GR32", ENCODING_RM) 1174 ENCODING("GR64", ENCODING_RM) 1175 ENCODING("GR8", ENCODING_RM) 1176 ENCODING("VR128", ENCODING_RM) 1177 ENCODING("FR64", ENCODING_RM) 1178 ENCODING("FR32", ENCODING_RM) 1179 ENCODING("VR64", ENCODING_RM) 1180 ENCODING("VR256", ENCODING_RM) 1181 errs() << "Unhandled R/M register encoding " << s << "\n"; 1182 llvm_unreachable("Unhandled R/M register encoding"); 1183} 1184 1185OperandEncoding RecognizableInstr::roRegisterEncodingFromString 1186 (const std::string &s, 1187 bool hasOpSizePrefix) { 1188 ENCODING("GR16", ENCODING_REG) 1189 ENCODING("GR32", ENCODING_REG) 1190 ENCODING("GR64", ENCODING_REG) 1191 ENCODING("GR8", ENCODING_REG) 1192 ENCODING("VR128", ENCODING_REG) 1193 ENCODING("FR64", ENCODING_REG) 1194 ENCODING("FR32", ENCODING_REG) 1195 ENCODING("VR64", ENCODING_REG) 1196 ENCODING("SEGMENT_REG", ENCODING_REG) 1197 ENCODING("DEBUG_REG", ENCODING_REG) 1198 ENCODING("CONTROL_REG", ENCODING_REG) 1199 ENCODING("VR256", ENCODING_REG) 1200 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1201 llvm_unreachable("Unhandled reg/opcode register encoding"); 1202} 1203 1204OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString 1205 (const std::string &s, 1206 bool hasOpSizePrefix) { 1207 ENCODING("GR32", ENCODING_VVVV) 1208 ENCODING("GR64", ENCODING_VVVV) 1209 ENCODING("FR32", ENCODING_VVVV) 1210 ENCODING("FR64", ENCODING_VVVV) 1211 ENCODING("VR128", ENCODING_VVVV) 1212 ENCODING("VR256", ENCODING_VVVV) 1213 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1214 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1215} 1216 1217OperandEncoding RecognizableInstr::memoryEncodingFromString 1218 (const std::string &s, 1219 bool hasOpSizePrefix) { 1220 ENCODING("i16mem", ENCODING_RM) 1221 ENCODING("i32mem", ENCODING_RM) 1222 ENCODING("i64mem", ENCODING_RM) 1223 ENCODING("i8mem", ENCODING_RM) 1224 ENCODING("ssmem", ENCODING_RM) 1225 ENCODING("sdmem", ENCODING_RM) 1226 ENCODING("f128mem", ENCODING_RM) 1227 ENCODING("f256mem", ENCODING_RM) 1228 ENCODING("f64mem", ENCODING_RM) 1229 ENCODING("f32mem", ENCODING_RM) 1230 ENCODING("i128mem", ENCODING_RM) 1231 ENCODING("i256mem", ENCODING_RM) 1232 ENCODING("f80mem", ENCODING_RM) 1233 ENCODING("lea32mem", ENCODING_RM) 1234 ENCODING("lea64_32mem", ENCODING_RM) 1235 ENCODING("lea64mem", ENCODING_RM) 1236 ENCODING("opaque32mem", ENCODING_RM) 1237 ENCODING("opaque48mem", ENCODING_RM) 1238 ENCODING("opaque80mem", ENCODING_RM) 1239 ENCODING("opaque512mem", ENCODING_RM) 1240 ENCODING("vx32mem", ENCODING_RM) 1241 ENCODING("vy32mem", ENCODING_RM) 1242 ENCODING("vx64mem", ENCODING_RM) 1243 ENCODING("vy64mem", ENCODING_RM) 1244 errs() << "Unhandled memory encoding " << s << "\n"; 1245 llvm_unreachable("Unhandled memory encoding"); 1246} 1247 1248OperandEncoding RecognizableInstr::relocationEncodingFromString 1249 (const std::string &s, 1250 bool hasOpSizePrefix) { 1251 if(!hasOpSizePrefix) { 1252 // For instructions without an OpSize prefix, a declared 16-bit register or 1253 // immediate encoding is special. 1254 ENCODING("i16imm", ENCODING_IW) 1255 } 1256 ENCODING("i16imm", ENCODING_Iv) 1257 ENCODING("i16i8imm", ENCODING_IB) 1258 ENCODING("i32imm", ENCODING_Iv) 1259 ENCODING("i32i8imm", ENCODING_IB) 1260 ENCODING("i64i32imm", ENCODING_ID) 1261 ENCODING("i64i8imm", ENCODING_IB) 1262 ENCODING("i8imm", ENCODING_IB) 1263 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1264 ENCODING("i16imm_pcrel", ENCODING_IW) 1265 ENCODING("i32imm_pcrel", ENCODING_ID) 1266 ENCODING("brtarget", ENCODING_Iv) 1267 ENCODING("brtarget8", ENCODING_IB) 1268 ENCODING("i64imm", ENCODING_IO) 1269 ENCODING("offset8", ENCODING_Ia) 1270 ENCODING("offset16", ENCODING_Ia) 1271 ENCODING("offset32", ENCODING_Ia) 1272 ENCODING("offset64", ENCODING_Ia) 1273 errs() << "Unhandled relocation encoding " << s << "\n"; 1274 llvm_unreachable("Unhandled relocation encoding"); 1275} 1276 1277OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString 1278 (const std::string &s, 1279 bool hasOpSizePrefix) { 1280 ENCODING("RST", ENCODING_I) 1281 ENCODING("GR32", ENCODING_Rv) 1282 ENCODING("GR64", ENCODING_RO) 1283 ENCODING("GR16", ENCODING_Rv) 1284 ENCODING("GR8", ENCODING_RB) 1285 ENCODING("GR16_NOAX", ENCODING_Rv) 1286 ENCODING("GR32_NOAX", ENCODING_Rv) 1287 ENCODING("GR64_NOAX", ENCODING_RO) 1288 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1289 llvm_unreachable("Unhandled opcode modifier encoding"); 1290} 1291#undef ENCODING 1292