X86RecognizableInstr.cpp revision 7f76cb6666194d7269bbd6ee0966eacc709dd10a 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86DisassemblerShared.h"
18#include "X86RecognizableInstr.h"
19#include "X86ModRMFilters.h"
20
21#include "llvm/Support/ErrorHandling.h"
22
23#include <string>
24
25using namespace llvm;
26
27#define MRM_MAPPING     \
28  MAP(C1, 33)           \
29  MAP(C2, 34)           \
30  MAP(C3, 35)           \
31  MAP(C4, 36)           \
32  MAP(C8, 37)           \
33  MAP(C9, 38)           \
34  MAP(E8, 39)           \
35  MAP(F0, 40)           \
36  MAP(F8, 41)           \
37  MAP(F9, 42)           \
38  MAP(D0, 45)           \
39  MAP(D1, 46)           \
40  MAP(D4, 47)           \
41  MAP(D8, 48)           \
42  MAP(D9, 49)           \
43  MAP(DA, 50)           \
44  MAP(DB, 51)           \
45  MAP(DC, 52)           \
46  MAP(DD, 53)           \
47  MAP(DE, 54)           \
48  MAP(DF, 55)
49
50// A clone of X86 since we can't depend on something that is generated.
51namespace X86Local {
52  enum {
53    Pseudo      = 0,
54    RawFrm      = 1,
55    AddRegFrm   = 2,
56    MRMDestReg  = 3,
57    MRMDestMem  = 4,
58    MRMSrcReg   = 5,
59    MRMSrcMem   = 6,
60    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
61    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
62    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
63    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
64    MRMInitReg  = 32,
65    RawFrmImm8  = 43,
66    RawFrmImm16 = 44,
67#define MAP(from, to) MRM_##from = to,
68    MRM_MAPPING
69#undef MAP
70    lastMRM
71  };
72
73  enum {
74    TB  = 1,
75    REP = 2,
76    D8 = 3, D9 = 4, DA = 5, DB = 6,
77    DC = 7, DD = 8, DE = 9, DF = 10,
78    XD = 11,  XS = 12,
79    T8 = 13,  P_TA = 14,
80    A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
81  };
82}
83
84// If rows are added to the opcode extension tables, then corresponding entries
85// must be added here.
86//
87// If the row corresponds to a single byte (i.e., 8f), then add an entry for
88// that byte to ONE_BYTE_EXTENSION_TABLES.
89//
90// If the row corresponds to two bytes where the first is 0f, add an entry for
91// the second byte to TWO_BYTE_EXTENSION_TABLES.
92//
93// If the row corresponds to some other set of bytes, you will need to modify
94// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
95// to the X86 TD files, except in two cases: if the first two bytes of such a
96// new combination are 0f 38 or 0f 3a, you just have to add maps called
97// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
98// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
99// in RecognizableInstr::emitDecodePath().
100
101#define ONE_BYTE_EXTENSION_TABLES \
102  EXTENSION_TABLE(80)             \
103  EXTENSION_TABLE(81)             \
104  EXTENSION_TABLE(82)             \
105  EXTENSION_TABLE(83)             \
106  EXTENSION_TABLE(8f)             \
107  EXTENSION_TABLE(c0)             \
108  EXTENSION_TABLE(c1)             \
109  EXTENSION_TABLE(c6)             \
110  EXTENSION_TABLE(c7)             \
111  EXTENSION_TABLE(d0)             \
112  EXTENSION_TABLE(d1)             \
113  EXTENSION_TABLE(d2)             \
114  EXTENSION_TABLE(d3)             \
115  EXTENSION_TABLE(f6)             \
116  EXTENSION_TABLE(f7)             \
117  EXTENSION_TABLE(fe)             \
118  EXTENSION_TABLE(ff)
119
120#define TWO_BYTE_EXTENSION_TABLES \
121  EXTENSION_TABLE(00)             \
122  EXTENSION_TABLE(01)             \
123  EXTENSION_TABLE(18)             \
124  EXTENSION_TABLE(71)             \
125  EXTENSION_TABLE(72)             \
126  EXTENSION_TABLE(73)             \
127  EXTENSION_TABLE(ae)             \
128  EXTENSION_TABLE(ba)             \
129  EXTENSION_TABLE(c7)
130
131#define THREE_BYTE_38_EXTENSION_TABLES \
132  EXTENSION_TABLE(F3)
133
134using namespace X86Disassembler;
135
136/// needsModRMForDecode - Indicates whether a particular instruction requires a
137///   ModR/M byte for the instruction to be properly decoded.  For example, a
138///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
139///   0b11.
140///
141/// @param form - The form of the instruction.
142/// @return     - true if the form implies that a ModR/M byte is required, false
143///               otherwise.
144static bool needsModRMForDecode(uint8_t form) {
145  if (form == X86Local::MRMDestReg    ||
146     form == X86Local::MRMDestMem    ||
147     form == X86Local::MRMSrcReg     ||
148     form == X86Local::MRMSrcMem     ||
149     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
150     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
151    return true;
152  else
153    return false;
154}
155
156/// isRegFormat - Indicates whether a particular form requires the Mod field of
157///   the ModR/M byte to be 0b11.
158///
159/// @param form - The form of the instruction.
160/// @return     - true if the form implies that Mod must be 0b11, false
161///               otherwise.
162static bool isRegFormat(uint8_t form) {
163  if (form == X86Local::MRMDestReg ||
164     form == X86Local::MRMSrcReg  ||
165     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
166    return true;
167  else
168    return false;
169}
170
171/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
172///   Useful for switch statements and the like.
173///
174/// @param init - A reference to the BitsInit to be decoded.
175/// @return     - The field, with the first bit in the BitsInit as the lowest
176///               order bit.
177static uint8_t byteFromBitsInit(BitsInit &init) {
178  int width = init.getNumBits();
179
180  assert(width <= 8 && "Field is too large for uint8_t!");
181
182  int     index;
183  uint8_t mask = 0x01;
184
185  uint8_t ret = 0;
186
187  for (index = 0; index < width; index++) {
188    if (static_cast<BitInit*>(init.getBit(index))->getValue())
189      ret |= mask;
190
191    mask <<= 1;
192  }
193
194  return ret;
195}
196
197/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
198///   name of the field.
199///
200/// @param rec  - The record from which to extract the value.
201/// @param name - The name of the field in the record.
202/// @return     - The field, as translated by byteFromBitsInit().
203static uint8_t byteFromRec(const Record* rec, const std::string &name) {
204  BitsInit* bits = rec->getValueAsBitsInit(name);
205  return byteFromBitsInit(*bits);
206}
207
208RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
209                                     const CodeGenInstruction &insn,
210                                     InstrUID uid) {
211  UID = uid;
212
213  Rec = insn.TheDef;
214  Name = Rec->getName();
215  Spec = &tables.specForUID(UID);
216
217  if (!Rec->isSubClassOf("X86Inst")) {
218    ShouldBeEmitted = false;
219    return;
220  }
221
222  Prefix   = byteFromRec(Rec, "Prefix");
223  Opcode   = byteFromRec(Rec, "Opcode");
224  Form     = byteFromRec(Rec, "FormBits");
225  SegOvr   = byteFromRec(Rec, "SegOvrBits");
226
227  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
228  HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
229  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
230  HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
231  HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
232  HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
233  HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
234  HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
235  IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
236  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
237  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
238
239  Name      = Rec->getName();
240  AsmString = Rec->getValueAsString("AsmString");
241
242  Operands = &insn.Operands.OperandList;
243
244  IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
245                     (Name.find("CRC32") != Name.npos);
246  HasFROperands    = hasFROperands();
247  HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
248
249  // Check for 64-bit inst which does not require REX
250  Is32Bit = false;
251  Is64Bit = false;
252  // FIXME: Is there some better way to check for In64BitMode?
253  std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
254  for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
255    if (Predicates[i]->getName().find("32Bit") != Name.npos) {
256      Is32Bit = true;
257      break;
258    }
259    if (Predicates[i]->getName().find("64Bit") != Name.npos) {
260      Is64Bit = true;
261      break;
262    }
263  }
264  // FIXME: These instructions aren't marked as 64-bit in any way
265  Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
266             Rec->getName() == "MASKMOVDQU64" ||
267             Rec->getName() == "POPFS64" ||
268             Rec->getName() == "POPGS64" ||
269             Rec->getName() == "PUSHFS64" ||
270             Rec->getName() == "PUSHGS64" ||
271             Rec->getName() == "REX64_PREFIX" ||
272             Rec->getName().find("MOV64") != Name.npos ||
273             Rec->getName().find("PUSH64") != Name.npos ||
274             Rec->getName().find("POP64") != Name.npos;
275
276  ShouldBeEmitted  = true;
277}
278
279void RecognizableInstr::processInstr(DisassemblerTables &tables,
280                                     const CodeGenInstruction &insn,
281                                     InstrUID uid)
282{
283  // Ignore "asm parser only" instructions.
284  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
285    return;
286
287  RecognizableInstr recogInstr(tables, insn, uid);
288
289  recogInstr.emitInstructionSpecifier(tables);
290
291  if (recogInstr.shouldBeEmitted())
292    recogInstr.emitDecodePath(tables);
293}
294
295InstructionContext RecognizableInstr::insnContext() const {
296  InstructionContext insnContext;
297
298  if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
299    if (HasVEX_LPrefix && HasVEX_WPrefix) {
300      if (HasOpSizePrefix)
301        insnContext = IC_VEX_L_W_OPSIZE;
302      else
303        llvm_unreachable("Don't support VEX.L and VEX.W together");
304    } else if (HasOpSizePrefix && HasVEX_LPrefix)
305      insnContext = IC_VEX_L_OPSIZE;
306    else if (HasOpSizePrefix && HasVEX_WPrefix)
307      insnContext = IC_VEX_W_OPSIZE;
308    else if (HasOpSizePrefix)
309      insnContext = IC_VEX_OPSIZE;
310    else if (HasVEX_LPrefix &&
311             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
312      insnContext = IC_VEX_L_XS;
313    else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
314                                Prefix == X86Local::T8XD ||
315                                Prefix == X86Local::TAXD))
316      insnContext = IC_VEX_L_XD;
317    else if (HasVEX_WPrefix &&
318             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
319      insnContext = IC_VEX_W_XS;
320    else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
321                                Prefix == X86Local::T8XD ||
322                                Prefix == X86Local::TAXD))
323      insnContext = IC_VEX_W_XD;
324    else if (HasVEX_WPrefix)
325      insnContext = IC_VEX_W;
326    else if (HasVEX_LPrefix)
327      insnContext = IC_VEX_L;
328    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329             Prefix == X86Local::TAXD)
330      insnContext = IC_VEX_XD;
331    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
332      insnContext = IC_VEX_XS;
333    else
334      insnContext = IC_VEX;
335  } else if (Is64Bit || HasREX_WPrefix) {
336    if (HasREX_WPrefix && HasOpSizePrefix)
337      insnContext = IC_64BIT_REXW_OPSIZE;
338    else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
339                                 Prefix == X86Local::T8XD ||
340                                 Prefix == X86Local::TAXD))
341      insnContext = IC_64BIT_XD_OPSIZE;
342    else if (HasOpSizePrefix &&
343             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
344      insnContext = IC_64BIT_XS_OPSIZE;
345    else if (HasOpSizePrefix)
346      insnContext = IC_64BIT_OPSIZE;
347    else if (HasAdSizePrefix)
348      insnContext = IC_64BIT_ADSIZE;
349    else if (HasREX_WPrefix &&
350             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
351      insnContext = IC_64BIT_REXW_XS;
352    else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
353                                Prefix == X86Local::T8XD ||
354                                Prefix == X86Local::TAXD))
355      insnContext = IC_64BIT_REXW_XD;
356    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357             Prefix == X86Local::TAXD)
358      insnContext = IC_64BIT_XD;
359    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360      insnContext = IC_64BIT_XS;
361    else if (HasREX_WPrefix)
362      insnContext = IC_64BIT_REXW;
363    else
364      insnContext = IC_64BIT;
365  } else {
366    if (HasOpSizePrefix && (Prefix == X86Local::XD ||
367                            Prefix == X86Local::T8XD ||
368                            Prefix == X86Local::TAXD))
369      insnContext = IC_XD_OPSIZE;
370    else if (HasOpSizePrefix &&
371             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
372      insnContext = IC_XS_OPSIZE;
373    else if (HasOpSizePrefix)
374      insnContext = IC_OPSIZE;
375    else if (HasAdSizePrefix)
376      insnContext = IC_ADSIZE;
377    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
378             Prefix == X86Local::TAXD)
379      insnContext = IC_XD;
380    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
381             Prefix == X86Local::REP)
382      insnContext = IC_XS;
383    else
384      insnContext = IC;
385  }
386
387  return insnContext;
388}
389
390RecognizableInstr::filter_ret RecognizableInstr::filter() const {
391  ///////////////////
392  // FILTER_STRONG
393  //
394
395  // Filter out intrinsics
396
397  if (!Rec->isSubClassOf("X86Inst"))
398    return FILTER_STRONG;
399
400  if (Form == X86Local::Pseudo ||
401      (IsCodeGenOnly && Name.find("_REV") == Name.npos))
402    return FILTER_STRONG;
403
404  if (Form == X86Local::MRMInitReg)
405    return FILTER_STRONG;
406
407
408  // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
409  // printed as a separate "instruction".
410
411  if (Name.find("_Int") != Name.npos       ||
412      Name.find("Int_") != Name.npos       ||
413      Name.find("_NOREX") != Name.npos)
414    return FILTER_STRONG;
415
416  // Filter out instructions with segment override prefixes.
417  // They're too messy to handle now and we'll special case them if needed.
418
419  if (SegOvr)
420    return FILTER_STRONG;
421
422  // Filter out instructions that can't be printed.
423
424  if (AsmString.size() == 0)
425    return FILTER_STRONG;
426
427  // Filter out instructions with subreg operands.
428
429  if (AsmString.find("subreg") != AsmString.npos)
430    return FILTER_STRONG;
431
432  /////////////////
433  // FILTER_WEAK
434  //
435
436
437  // Filter out instructions with a LOCK prefix;
438  //   prefer forms that do not have the prefix
439  if (HasLockPrefix)
440    return FILTER_WEAK;
441
442  // Filter out alternate forms of AVX instructions
443  if (Name.find("_alt") != Name.npos ||
444      Name.find("XrYr") != Name.npos ||
445      (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
446      Name.find("_64mr") != Name.npos ||
447      Name.find("Xrr") != Name.npos ||
448      Name.find("rr64") != Name.npos)
449    return FILTER_WEAK;
450
451  // Special cases.
452
453  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
454    return FILTER_WEAK;
455  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
456    return FILTER_WEAK;
457
458  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
459    return FILTER_WEAK;
460  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
461    return FILTER_WEAK;
462  if (Name.find("Fs") != Name.npos)
463    return FILTER_WEAK;
464  if (Name == "PUSH64i16"         ||
465      Name == "MOVPQI2QImr"       ||
466      Name == "VMOVPQI2QImr"      ||
467      Name == "MMX_MOVD64rrv164"  ||
468      Name == "MOV64ri64i32"      ||
469      Name == "VMASKMOVDQU64"     ||
470      Name == "VEXTRACTPSrr64"    ||
471      Name == "VMOVQd64rr"        ||
472      Name == "VMOVQs64rr")
473    return FILTER_WEAK;
474
475  if (HasFROperands && Name.find("MOV") != Name.npos &&
476     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
477      (Name.find("to") != Name.npos)))
478    return FILTER_WEAK;
479
480  return FILTER_NORMAL;
481}
482
483bool RecognizableInstr::hasFROperands() const {
484  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
485  unsigned numOperands = OperandList.size();
486
487  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
488    const std::string &recName = OperandList[operandIndex].Rec->getName();
489
490    if (recName.find("FR") != recName.npos)
491      return true;
492  }
493  return false;
494}
495
496bool RecognizableInstr::has256BitOperands() const {
497  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
498  unsigned numOperands = OperandList.size();
499
500  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
501    const std::string &recName = OperandList[operandIndex].Rec->getName();
502
503    if (!recName.compare("VR256") || !recName.compare("f256mem")) {
504      return true;
505    }
506  }
507  return false;
508}
509
510void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
511                                      unsigned &physicalOperandIndex,
512                                      unsigned &numPhysicalOperands,
513                                      const unsigned *operandMapping,
514                                      OperandEncoding (*encodingFromString)
515                                        (const std::string&,
516                                         bool hasOpSizePrefix)) {
517  if (optional) {
518    if (physicalOperandIndex >= numPhysicalOperands)
519      return;
520  } else {
521    assert(physicalOperandIndex < numPhysicalOperands);
522  }
523
524  while (operandMapping[operandIndex] != operandIndex) {
525    Spec->operands[operandIndex].encoding = ENCODING_DUP;
526    Spec->operands[operandIndex].type =
527      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
528    ++operandIndex;
529  }
530
531  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
532
533  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
534                                                              HasOpSizePrefix);
535  Spec->operands[operandIndex].type = typeFromString(typeName,
536                                                     IsSSE,
537                                                     HasREX_WPrefix,
538                                                     HasOpSizePrefix);
539
540  ++operandIndex;
541  ++physicalOperandIndex;
542}
543
544void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
545  Spec->name       = Name;
546
547  if (!Rec->isSubClassOf("X86Inst"))
548    return;
549
550  switch (filter()) {
551  case FILTER_WEAK:
552    Spec->filtered = true;
553    break;
554  case FILTER_STRONG:
555    ShouldBeEmitted = false;
556    return;
557  case FILTER_NORMAL:
558    break;
559  }
560
561  Spec->insnContext = insnContext();
562
563  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
564
565  unsigned numOperands = OperandList.size();
566  unsigned numPhysicalOperands = 0;
567
568  // operandMapping maps from operands in OperandList to their originals.
569  // If operandMapping[i] != i, then the entry is a duplicate.
570  unsigned operandMapping[X86_MAX_OPERANDS];
571
572  bool hasFROperands = false;
573
574  assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
575
576  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
577    if (OperandList[operandIndex].Constraints.size()) {
578      const CGIOperandList::ConstraintInfo &Constraint =
579        OperandList[operandIndex].Constraints[0];
580      if (Constraint.isTied()) {
581        operandMapping[operandIndex] = operandIndex;
582        operandMapping[Constraint.getTiedOperand()] = operandIndex;
583      } else {
584        ++numPhysicalOperands;
585        operandMapping[operandIndex] = operandIndex;
586      }
587    } else {
588      ++numPhysicalOperands;
589      operandMapping[operandIndex] = operandIndex;
590    }
591
592    const std::string &recName = OperandList[operandIndex].Rec->getName();
593
594    if (recName.find("FR") != recName.npos)
595      hasFROperands = true;
596  }
597
598  if (hasFROperands && Name.find("MOV") != Name.npos &&
599     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
600      (Name.find("to") != Name.npos)))
601    ShouldBeEmitted = false;
602
603  if (!ShouldBeEmitted)
604    return;
605
606#define HANDLE_OPERAND(class)               \
607  handleOperand(false,                      \
608                operandIndex,               \
609                physicalOperandIndex,       \
610                numPhysicalOperands,        \
611                operandMapping,             \
612                class##EncodingFromString);
613
614#define HANDLE_OPTIONAL(class)              \
615  handleOperand(true,                       \
616                operandIndex,               \
617                physicalOperandIndex,       \
618                numPhysicalOperands,        \
619                operandMapping,             \
620                class##EncodingFromString);
621
622  // operandIndex should always be < numOperands
623  unsigned operandIndex = 0;
624  // physicalOperandIndex should always be < numPhysicalOperands
625  unsigned physicalOperandIndex = 0;
626
627  switch (Form) {
628  case X86Local::RawFrm:
629    // Operand 1 (optional) is an address or immediate.
630    // Operand 2 (optional) is an immediate.
631    assert(numPhysicalOperands <= 2 &&
632           "Unexpected number of operands for RawFrm");
633    HANDLE_OPTIONAL(relocation)
634    HANDLE_OPTIONAL(immediate)
635    break;
636  case X86Local::AddRegFrm:
637    // Operand 1 is added to the opcode.
638    // Operand 2 (optional) is an address.
639    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
640           "Unexpected number of operands for AddRegFrm");
641    HANDLE_OPERAND(opcodeModifier)
642    HANDLE_OPTIONAL(relocation)
643    break;
644  case X86Local::MRMDestReg:
645    // Operand 1 is a register operand in the R/M field.
646    // Operand 2 is a register operand in the Reg/Opcode field.
647    // - In AVX, there is a register operand in the VEX.vvvv field here -
648    // Operand 3 (optional) is an immediate.
649    if (HasVEX_4VPrefix)
650      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
651             "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
652    else
653      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
654             "Unexpected number of operands for MRMDestRegFrm");
655
656    HANDLE_OPERAND(rmRegister)
657
658    if (HasVEX_4VPrefix)
659      // FIXME: In AVX, the register below becomes the one encoded
660      // in ModRMVEX and the one above the one in the VEX.VVVV field
661      HANDLE_OPERAND(vvvvRegister)
662
663    HANDLE_OPERAND(roRegister)
664    HANDLE_OPTIONAL(immediate)
665    break;
666  case X86Local::MRMDestMem:
667    // Operand 1 is a memory operand (possibly SIB-extended)
668    // Operand 2 is a register operand in the Reg/Opcode field.
669    // - In AVX, there is a register operand in the VEX.vvvv field here -
670    // Operand 3 (optional) is an immediate.
671    if (HasVEX_4VPrefix)
672      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
673             "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
674    else
675      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
676             "Unexpected number of operands for MRMDestMemFrm");
677    HANDLE_OPERAND(memory)
678
679    if (HasVEX_4VPrefix)
680      // FIXME: In AVX, the register below becomes the one encoded
681      // in ModRMVEX and the one above the one in the VEX.VVVV field
682      HANDLE_OPERAND(vvvvRegister)
683
684    HANDLE_OPERAND(roRegister)
685    HANDLE_OPTIONAL(immediate)
686    break;
687  case X86Local::MRMSrcReg:
688    // Operand 1 is a register operand in the Reg/Opcode field.
689    // Operand 2 is a register operand in the R/M field.
690    // - In AVX, there is a register operand in the VEX.vvvv field here -
691    // Operand 3 (optional) is an immediate.
692    // Operand 4 (optional) is an immediate.
693
694    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
695      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
696             "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
697    else
698      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
699             "Unexpected number of operands for MRMSrcRegFrm");
700
701    HANDLE_OPERAND(roRegister)
702
703    if (HasVEX_4VPrefix)
704      // FIXME: In AVX, the register below becomes the one encoded
705      // in ModRMVEX and the one above the one in the VEX.VVVV field
706      HANDLE_OPERAND(vvvvRegister)
707
708    if (HasMemOp4Prefix)
709      HANDLE_OPERAND(immediate)
710
711    HANDLE_OPERAND(rmRegister)
712
713    if (HasVEX_4VOp3Prefix)
714      HANDLE_OPERAND(vvvvRegister)
715
716    if (!HasMemOp4Prefix)
717      HANDLE_OPTIONAL(immediate)
718    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
719    HANDLE_OPTIONAL(immediate)
720    break;
721  case X86Local::MRMSrcMem:
722    // Operand 1 is a register operand in the Reg/Opcode field.
723    // Operand 2 is a memory operand (possibly SIB-extended)
724    // - In AVX, there is a register operand in the VEX.vvvv field here -
725    // Operand 3 (optional) is an immediate.
726
727    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
728      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
729             "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
730    else
731      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
732             "Unexpected number of operands for MRMSrcMemFrm");
733
734    HANDLE_OPERAND(roRegister)
735
736    if (HasVEX_4VPrefix)
737      // FIXME: In AVX, the register below becomes the one encoded
738      // in ModRMVEX and the one above the one in the VEX.VVVV field
739      HANDLE_OPERAND(vvvvRegister)
740
741    if (HasMemOp4Prefix)
742      HANDLE_OPERAND(immediate)
743
744    HANDLE_OPERAND(memory)
745
746    if (HasVEX_4VOp3Prefix)
747      HANDLE_OPERAND(vvvvRegister)
748
749    if (!HasMemOp4Prefix)
750      HANDLE_OPTIONAL(immediate)
751    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
752    break;
753  case X86Local::MRM0r:
754  case X86Local::MRM1r:
755  case X86Local::MRM2r:
756  case X86Local::MRM3r:
757  case X86Local::MRM4r:
758  case X86Local::MRM5r:
759  case X86Local::MRM6r:
760  case X86Local::MRM7r:
761    // Operand 1 is a register operand in the R/M field.
762    // Operand 2 (optional) is an immediate or relocation.
763    // Operand 3 (optional) is an immediate.
764    if (HasVEX_4VPrefix)
765      assert(numPhysicalOperands <= 3 &&
766             "Unexpected number of operands for MRMnRFrm with VEX_4V");
767    else
768      assert(numPhysicalOperands <= 3 &&
769             "Unexpected number of operands for MRMnRFrm");
770    if (HasVEX_4VPrefix)
771      HANDLE_OPERAND(vvvvRegister)
772    HANDLE_OPTIONAL(rmRegister)
773    HANDLE_OPTIONAL(relocation)
774    HANDLE_OPTIONAL(immediate)
775    break;
776  case X86Local::MRM0m:
777  case X86Local::MRM1m:
778  case X86Local::MRM2m:
779  case X86Local::MRM3m:
780  case X86Local::MRM4m:
781  case X86Local::MRM5m:
782  case X86Local::MRM6m:
783  case X86Local::MRM7m:
784    // Operand 1 is a memory operand (possibly SIB-extended)
785    // Operand 2 (optional) is an immediate or relocation.
786    if (HasVEX_4VPrefix)
787      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
788             "Unexpected number of operands for MRMnMFrm");
789    else
790      assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
791             "Unexpected number of operands for MRMnMFrm");
792    if (HasVEX_4VPrefix)
793      HANDLE_OPERAND(vvvvRegister)
794    HANDLE_OPERAND(memory)
795    HANDLE_OPTIONAL(relocation)
796    break;
797  case X86Local::RawFrmImm8:
798    // operand 1 is a 16-bit immediate
799    // operand 2 is an 8-bit immediate
800    assert(numPhysicalOperands == 2 &&
801           "Unexpected number of operands for X86Local::RawFrmImm8");
802    HANDLE_OPERAND(immediate)
803    HANDLE_OPERAND(immediate)
804    break;
805  case X86Local::RawFrmImm16:
806    // operand 1 is a 16-bit immediate
807    // operand 2 is a 16-bit immediate
808    HANDLE_OPERAND(immediate)
809    HANDLE_OPERAND(immediate)
810    break;
811  case X86Local::MRMInitReg:
812    // Ignored.
813    break;
814  }
815
816  #undef HANDLE_OPERAND
817  #undef HANDLE_OPTIONAL
818}
819
820void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
821  // Special cases where the LLVM tables are not complete
822
823#define MAP(from, to)                     \
824  case X86Local::MRM_##from:              \
825    filter = new ExactFilter(0x##from);   \
826    break;
827
828  OpcodeType    opcodeType  = (OpcodeType)-1;
829
830  ModRMFilter*  filter      = NULL;
831  uint8_t       opcodeToSet = 0;
832
833  switch (Prefix) {
834  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
835  case X86Local::XD:
836  case X86Local::XS:
837  case X86Local::TB:
838    opcodeType = TWOBYTE;
839
840    switch (Opcode) {
841    default:
842      if (needsModRMForDecode(Form))
843        filter = new ModFilter(isRegFormat(Form));
844      else
845        filter = new DumbFilter();
846      break;
847#define EXTENSION_TABLE(n) case 0x##n:
848    TWO_BYTE_EXTENSION_TABLES
849#undef EXTENSION_TABLE
850      switch (Form) {
851      default:
852        llvm_unreachable("Unhandled two-byte extended opcode");
853      case X86Local::MRM0r:
854      case X86Local::MRM1r:
855      case X86Local::MRM2r:
856      case X86Local::MRM3r:
857      case X86Local::MRM4r:
858      case X86Local::MRM5r:
859      case X86Local::MRM6r:
860      case X86Local::MRM7r:
861        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
862        break;
863      case X86Local::MRM0m:
864      case X86Local::MRM1m:
865      case X86Local::MRM2m:
866      case X86Local::MRM3m:
867      case X86Local::MRM4m:
868      case X86Local::MRM5m:
869      case X86Local::MRM6m:
870      case X86Local::MRM7m:
871        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
872        break;
873      MRM_MAPPING
874      } // switch (Form)
875      break;
876    } // switch (Opcode)
877    opcodeToSet = Opcode;
878    break;
879  case X86Local::T8:
880  case X86Local::T8XD:
881  case X86Local::T8XS:
882    opcodeType = THREEBYTE_38;
883    switch (Opcode) {
884    default:
885      if (needsModRMForDecode(Form))
886        filter = new ModFilter(isRegFormat(Form));
887      else
888        filter = new DumbFilter();
889      break;
890#define EXTENSION_TABLE(n) case 0x##n:
891    THREE_BYTE_38_EXTENSION_TABLES
892#undef EXTENSION_TABLE
893      switch (Form) {
894      default:
895        llvm_unreachable("Unhandled two-byte extended opcode");
896      case X86Local::MRM0r:
897      case X86Local::MRM1r:
898      case X86Local::MRM2r:
899      case X86Local::MRM3r:
900      case X86Local::MRM4r:
901      case X86Local::MRM5r:
902      case X86Local::MRM6r:
903      case X86Local::MRM7r:
904        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
905        break;
906      case X86Local::MRM0m:
907      case X86Local::MRM1m:
908      case X86Local::MRM2m:
909      case X86Local::MRM3m:
910      case X86Local::MRM4m:
911      case X86Local::MRM5m:
912      case X86Local::MRM6m:
913      case X86Local::MRM7m:
914        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
915        break;
916      MRM_MAPPING
917      } // switch (Form)
918      break;
919    } // switch (Opcode)
920    opcodeToSet = Opcode;
921    break;
922  case X86Local::P_TA:
923  case X86Local::TAXD:
924    opcodeType = THREEBYTE_3A;
925    if (needsModRMForDecode(Form))
926      filter = new ModFilter(isRegFormat(Form));
927    else
928      filter = new DumbFilter();
929    opcodeToSet = Opcode;
930    break;
931  case X86Local::A6:
932    opcodeType = THREEBYTE_A6;
933    if (needsModRMForDecode(Form))
934      filter = new ModFilter(isRegFormat(Form));
935    else
936      filter = new DumbFilter();
937    opcodeToSet = Opcode;
938    break;
939  case X86Local::A7:
940    opcodeType = THREEBYTE_A7;
941    if (needsModRMForDecode(Form))
942      filter = new ModFilter(isRegFormat(Form));
943    else
944      filter = new DumbFilter();
945    opcodeToSet = Opcode;
946    break;
947  case X86Local::D8:
948  case X86Local::D9:
949  case X86Local::DA:
950  case X86Local::DB:
951  case X86Local::DC:
952  case X86Local::DD:
953  case X86Local::DE:
954  case X86Local::DF:
955    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
956    opcodeType = ONEBYTE;
957    if (Form == X86Local::AddRegFrm) {
958      Spec->modifierType = MODIFIER_MODRM;
959      Spec->modifierBase = Opcode;
960      filter = new AddRegEscapeFilter(Opcode);
961    } else {
962      filter = new EscapeFilter(true, Opcode);
963    }
964    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
965    break;
966  case X86Local::REP:
967  default:
968    opcodeType = ONEBYTE;
969    switch (Opcode) {
970#define EXTENSION_TABLE(n) case 0x##n:
971    ONE_BYTE_EXTENSION_TABLES
972#undef EXTENSION_TABLE
973      switch (Form) {
974      default:
975        llvm_unreachable("Fell through the cracks of a single-byte "
976                         "extended opcode");
977      case X86Local::MRM0r:
978      case X86Local::MRM1r:
979      case X86Local::MRM2r:
980      case X86Local::MRM3r:
981      case X86Local::MRM4r:
982      case X86Local::MRM5r:
983      case X86Local::MRM6r:
984      case X86Local::MRM7r:
985        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
986        break;
987      case X86Local::MRM0m:
988      case X86Local::MRM1m:
989      case X86Local::MRM2m:
990      case X86Local::MRM3m:
991      case X86Local::MRM4m:
992      case X86Local::MRM5m:
993      case X86Local::MRM6m:
994      case X86Local::MRM7m:
995        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
996        break;
997      MRM_MAPPING
998      } // switch (Form)
999      break;
1000    case 0xd8:
1001    case 0xd9:
1002    case 0xda:
1003    case 0xdb:
1004    case 0xdc:
1005    case 0xdd:
1006    case 0xde:
1007    case 0xdf:
1008      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1009      break;
1010    default:
1011      if (needsModRMForDecode(Form))
1012        filter = new ModFilter(isRegFormat(Form));
1013      else
1014        filter = new DumbFilter();
1015      break;
1016    } // switch (Opcode)
1017    opcodeToSet = Opcode;
1018  } // switch (Prefix)
1019
1020  assert(opcodeType != (OpcodeType)-1 &&
1021         "Opcode type not set");
1022  assert(filter && "Filter not set");
1023
1024  if (Form == X86Local::AddRegFrm) {
1025    if(Spec->modifierType != MODIFIER_MODRM) {
1026      assert(opcodeToSet < 0xf9 &&
1027             "Not enough room for all ADDREG_FRM operands");
1028
1029      uint8_t currentOpcode;
1030
1031      for (currentOpcode = opcodeToSet;
1032           currentOpcode < opcodeToSet + 8;
1033           ++currentOpcode)
1034        tables.setTableFields(opcodeType,
1035                              insnContext(),
1036                              currentOpcode,
1037                              *filter,
1038                              UID, Is32Bit, IgnoresVEX_L);
1039
1040      Spec->modifierType = MODIFIER_OPCODE;
1041      Spec->modifierBase = opcodeToSet;
1042    } else {
1043      // modifierBase was set where MODIFIER_MODRM was set
1044      tables.setTableFields(opcodeType,
1045                            insnContext(),
1046                            opcodeToSet,
1047                            *filter,
1048                            UID, Is32Bit, IgnoresVEX_L);
1049    }
1050  } else {
1051    tables.setTableFields(opcodeType,
1052                          insnContext(),
1053                          opcodeToSet,
1054                          *filter,
1055                          UID, Is32Bit, IgnoresVEX_L);
1056
1057    Spec->modifierType = MODIFIER_NONE;
1058    Spec->modifierBase = opcodeToSet;
1059  }
1060
1061  delete filter;
1062
1063#undef MAP
1064}
1065
1066#define TYPE(str, type) if (s == str) return type;
1067OperandType RecognizableInstr::typeFromString(const std::string &s,
1068                                              bool isSSE,
1069                                              bool hasREX_WPrefix,
1070                                              bool hasOpSizePrefix) {
1071  if (isSSE) {
1072    // For SSE instructions, we ignore the OpSize prefix and force operand
1073    // sizes.
1074    TYPE("GR16",              TYPE_R16)
1075    TYPE("GR32",              TYPE_R32)
1076    TYPE("GR64",              TYPE_R64)
1077  }
1078  if(hasREX_WPrefix) {
1079    // For instructions with a REX_W prefix, a declared 32-bit register encoding
1080    // is special.
1081    TYPE("GR32",              TYPE_R32)
1082  }
1083  if(!hasOpSizePrefix) {
1084    // For instructions without an OpSize prefix, a declared 16-bit register or
1085    // immediate encoding is special.
1086    TYPE("GR16",              TYPE_R16)
1087    TYPE("i16imm",            TYPE_IMM16)
1088  }
1089  TYPE("i16mem",              TYPE_Mv)
1090  TYPE("i16imm",              TYPE_IMMv)
1091  TYPE("i16i8imm",            TYPE_IMMv)
1092  TYPE("GR16",                TYPE_Rv)
1093  TYPE("i32mem",              TYPE_Mv)
1094  TYPE("i32imm",              TYPE_IMMv)
1095  TYPE("i32i8imm",            TYPE_IMM32)
1096  TYPE("u32u8imm",            TYPE_IMM32)
1097  TYPE("GR32",                TYPE_Rv)
1098  TYPE("i64mem",              TYPE_Mv)
1099  TYPE("i64i32imm",           TYPE_IMM64)
1100  TYPE("i64i8imm",            TYPE_IMM64)
1101  TYPE("GR64",                TYPE_R64)
1102  TYPE("i8mem",               TYPE_M8)
1103  TYPE("i8imm",               TYPE_IMM8)
1104  TYPE("GR8",                 TYPE_R8)
1105  TYPE("VR128",               TYPE_XMM128)
1106  TYPE("f128mem",             TYPE_M128)
1107  TYPE("f256mem",             TYPE_M256)
1108  TYPE("FR64",                TYPE_XMM64)
1109  TYPE("f64mem",              TYPE_M64FP)
1110  TYPE("sdmem",               TYPE_M64FP)
1111  TYPE("FR32",                TYPE_XMM32)
1112  TYPE("f32mem",              TYPE_M32FP)
1113  TYPE("ssmem",               TYPE_M32FP)
1114  TYPE("RST",                 TYPE_ST)
1115  TYPE("i128mem",             TYPE_M128)
1116  TYPE("i256mem",             TYPE_M256)
1117  TYPE("i64i32imm_pcrel",     TYPE_REL64)
1118  TYPE("i16imm_pcrel",        TYPE_REL16)
1119  TYPE("i32imm_pcrel",        TYPE_REL32)
1120  TYPE("SSECC",               TYPE_IMM3)
1121  TYPE("AVXCC",               TYPE_IMM5)
1122  TYPE("brtarget",            TYPE_RELv)
1123  TYPE("uncondbrtarget",      TYPE_RELv)
1124  TYPE("brtarget8",           TYPE_REL8)
1125  TYPE("f80mem",              TYPE_M80FP)
1126  TYPE("lea32mem",            TYPE_LEA)
1127  TYPE("lea64_32mem",         TYPE_LEA)
1128  TYPE("lea64mem",            TYPE_LEA)
1129  TYPE("VR64",                TYPE_MM64)
1130  TYPE("i64imm",              TYPE_IMMv)
1131  TYPE("opaque32mem",         TYPE_M1616)
1132  TYPE("opaque48mem",         TYPE_M1632)
1133  TYPE("opaque80mem",         TYPE_M1664)
1134  TYPE("opaque512mem",        TYPE_M512)
1135  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1136  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1137  TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1138  TYPE("offset8",             TYPE_MOFFS8)
1139  TYPE("offset16",            TYPE_MOFFS16)
1140  TYPE("offset32",            TYPE_MOFFS32)
1141  TYPE("offset64",            TYPE_MOFFS64)
1142  TYPE("VR256",               TYPE_XMM256)
1143  TYPE("GR16_NOAX",           TYPE_Rv)
1144  TYPE("GR32_NOAX",           TYPE_Rv)
1145  TYPE("GR64_NOAX",           TYPE_R64)
1146  TYPE("vx32mem",             TYPE_M32)
1147  TYPE("vy32mem",             TYPE_M32)
1148  TYPE("vx64mem",             TYPE_M64)
1149  TYPE("vy64mem",             TYPE_M64)
1150  errs() << "Unhandled type string " << s << "\n";
1151  llvm_unreachable("Unhandled type string");
1152}
1153#undef TYPE
1154
1155#define ENCODING(str, encoding) if (s == str) return encoding;
1156OperandEncoding RecognizableInstr::immediateEncodingFromString
1157  (const std::string &s,
1158   bool hasOpSizePrefix) {
1159  if(!hasOpSizePrefix) {
1160    // For instructions without an OpSize prefix, a declared 16-bit register or
1161    // immediate encoding is special.
1162    ENCODING("i16imm",        ENCODING_IW)
1163  }
1164  ENCODING("i32i8imm",        ENCODING_IB)
1165  ENCODING("u32u8imm",        ENCODING_IB)
1166  ENCODING("SSECC",           ENCODING_IB)
1167  ENCODING("AVXCC",           ENCODING_IB)
1168  ENCODING("i16imm",          ENCODING_Iv)
1169  ENCODING("i16i8imm",        ENCODING_IB)
1170  ENCODING("i32imm",          ENCODING_Iv)
1171  ENCODING("i64i32imm",       ENCODING_ID)
1172  ENCODING("i64i8imm",        ENCODING_IB)
1173  ENCODING("i8imm",           ENCODING_IB)
1174  // This is not a typo.  Instructions like BLENDVPD put
1175  // register IDs in 8-bit immediates nowadays.
1176  ENCODING("VR256",           ENCODING_IB)
1177  ENCODING("VR128",           ENCODING_IB)
1178  errs() << "Unhandled immediate encoding " << s << "\n";
1179  llvm_unreachable("Unhandled immediate encoding");
1180}
1181
1182OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1183  (const std::string &s,
1184   bool hasOpSizePrefix) {
1185  ENCODING("GR16",            ENCODING_RM)
1186  ENCODING("GR32",            ENCODING_RM)
1187  ENCODING("GR64",            ENCODING_RM)
1188  ENCODING("GR8",             ENCODING_RM)
1189  ENCODING("VR128",           ENCODING_RM)
1190  ENCODING("FR64",            ENCODING_RM)
1191  ENCODING("FR32",            ENCODING_RM)
1192  ENCODING("VR64",            ENCODING_RM)
1193  ENCODING("VR256",           ENCODING_RM)
1194  errs() << "Unhandled R/M register encoding " << s << "\n";
1195  llvm_unreachable("Unhandled R/M register encoding");
1196}
1197
1198OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1199  (const std::string &s,
1200   bool hasOpSizePrefix) {
1201  ENCODING("GR16",            ENCODING_REG)
1202  ENCODING("GR32",            ENCODING_REG)
1203  ENCODING("GR64",            ENCODING_REG)
1204  ENCODING("GR8",             ENCODING_REG)
1205  ENCODING("VR128",           ENCODING_REG)
1206  ENCODING("FR64",            ENCODING_REG)
1207  ENCODING("FR32",            ENCODING_REG)
1208  ENCODING("VR64",            ENCODING_REG)
1209  ENCODING("SEGMENT_REG",     ENCODING_REG)
1210  ENCODING("DEBUG_REG",       ENCODING_REG)
1211  ENCODING("CONTROL_REG",     ENCODING_REG)
1212  ENCODING("VR256",           ENCODING_REG)
1213  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1214  llvm_unreachable("Unhandled reg/opcode register encoding");
1215}
1216
1217OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1218  (const std::string &s,
1219   bool hasOpSizePrefix) {
1220  ENCODING("GR32",            ENCODING_VVVV)
1221  ENCODING("GR64",            ENCODING_VVVV)
1222  ENCODING("FR32",            ENCODING_VVVV)
1223  ENCODING("FR64",            ENCODING_VVVV)
1224  ENCODING("VR128",           ENCODING_VVVV)
1225  ENCODING("VR256",           ENCODING_VVVV)
1226  errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1227  llvm_unreachable("Unhandled VEX.vvvv register encoding");
1228}
1229
1230OperandEncoding RecognizableInstr::memoryEncodingFromString
1231  (const std::string &s,
1232   bool hasOpSizePrefix) {
1233  ENCODING("i16mem",          ENCODING_RM)
1234  ENCODING("i32mem",          ENCODING_RM)
1235  ENCODING("i64mem",          ENCODING_RM)
1236  ENCODING("i8mem",           ENCODING_RM)
1237  ENCODING("ssmem",           ENCODING_RM)
1238  ENCODING("sdmem",           ENCODING_RM)
1239  ENCODING("f128mem",         ENCODING_RM)
1240  ENCODING("f256mem",         ENCODING_RM)
1241  ENCODING("f64mem",          ENCODING_RM)
1242  ENCODING("f32mem",          ENCODING_RM)
1243  ENCODING("i128mem",         ENCODING_RM)
1244  ENCODING("i256mem",         ENCODING_RM)
1245  ENCODING("f80mem",          ENCODING_RM)
1246  ENCODING("lea32mem",        ENCODING_RM)
1247  ENCODING("lea64_32mem",     ENCODING_RM)
1248  ENCODING("lea64mem",        ENCODING_RM)
1249  ENCODING("opaque32mem",     ENCODING_RM)
1250  ENCODING("opaque48mem",     ENCODING_RM)
1251  ENCODING("opaque80mem",     ENCODING_RM)
1252  ENCODING("opaque512mem",    ENCODING_RM)
1253  ENCODING("vx32mem",         ENCODING_RM)
1254  ENCODING("vy32mem",         ENCODING_RM)
1255  ENCODING("vx64mem",         ENCODING_RM)
1256  ENCODING("vy64mem",         ENCODING_RM)
1257  errs() << "Unhandled memory encoding " << s << "\n";
1258  llvm_unreachable("Unhandled memory encoding");
1259}
1260
1261OperandEncoding RecognizableInstr::relocationEncodingFromString
1262  (const std::string &s,
1263   bool hasOpSizePrefix) {
1264  if(!hasOpSizePrefix) {
1265    // For instructions without an OpSize prefix, a declared 16-bit register or
1266    // immediate encoding is special.
1267    ENCODING("i16imm",        ENCODING_IW)
1268  }
1269  ENCODING("i16imm",          ENCODING_Iv)
1270  ENCODING("i16i8imm",        ENCODING_IB)
1271  ENCODING("i32imm",          ENCODING_Iv)
1272  ENCODING("i32i8imm",        ENCODING_IB)
1273  ENCODING("i64i32imm",       ENCODING_ID)
1274  ENCODING("i64i8imm",        ENCODING_IB)
1275  ENCODING("i8imm",           ENCODING_IB)
1276  ENCODING("i64i32imm_pcrel", ENCODING_ID)
1277  ENCODING("i16imm_pcrel",    ENCODING_IW)
1278  ENCODING("i32imm_pcrel",    ENCODING_ID)
1279  ENCODING("brtarget",        ENCODING_Iv)
1280  ENCODING("brtarget8",       ENCODING_IB)
1281  ENCODING("i64imm",          ENCODING_IO)
1282  ENCODING("offset8",         ENCODING_Ia)
1283  ENCODING("offset16",        ENCODING_Ia)
1284  ENCODING("offset32",        ENCODING_Ia)
1285  ENCODING("offset64",        ENCODING_Ia)
1286  errs() << "Unhandled relocation encoding " << s << "\n";
1287  llvm_unreachable("Unhandled relocation encoding");
1288}
1289
1290OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1291  (const std::string &s,
1292   bool hasOpSizePrefix) {
1293  ENCODING("RST",             ENCODING_I)
1294  ENCODING("GR32",            ENCODING_Rv)
1295  ENCODING("GR64",            ENCODING_RO)
1296  ENCODING("GR16",            ENCODING_Rv)
1297  ENCODING("GR8",             ENCODING_RB)
1298  ENCODING("GR16_NOAX",       ENCODING_Rv)
1299  ENCODING("GR32_NOAX",       ENCODING_Rv)
1300  ENCODING("GR64_NOAX",       ENCODING_RO)
1301  errs() << "Unhandled opcode modifier encoding " << s << "\n";
1302  llvm_unreachable("Unhandled opcode modifier encoding");
1303}
1304#undef ENCODING
1305