X86RecognizableInstr.cpp revision c902a59f4c786a2a047f0b4c964a93108f248915 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86DisassemblerShared.h"
18#include "X86RecognizableInstr.h"
19#include "X86ModRMFilters.h"
20
21#include "llvm/Support/ErrorHandling.h"
22
23#include <string>
24
25using namespace llvm;
26
27#define MRM_MAPPING     \
28  MAP(C1, 33)           \
29  MAP(C2, 34)           \
30  MAP(C3, 35)           \
31  MAP(C4, 36)           \
32  MAP(C8, 37)           \
33  MAP(C9, 38)           \
34  MAP(E8, 39)           \
35  MAP(F0, 40)           \
36  MAP(F8, 41)		\
37  MAP(F9, 42)
38
39// A clone of X86 since we can't depend on something that is generated.
40namespace X86Local {
41  enum {
42    Pseudo      = 0,
43    RawFrm      = 1,
44    AddRegFrm   = 2,
45    MRMDestReg  = 3,
46    MRMDestMem  = 4,
47    MRMSrcReg   = 5,
48    MRMSrcMem   = 6,
49    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
53    MRMInitReg  = 32,
54
55#define MAP(from, to) MRM_##from = to,
56    MRM_MAPPING
57#undef MAP
58    lastMRM
59  };
60
61  enum {
62    TB  = 1,
63    REP = 2,
64    D8 = 3, D9 = 4, DA = 5, DB = 6,
65    DC = 7, DD = 8, DE = 9, DF = 10,
66    XD = 11,  XS = 12,
67    T8 = 13,  P_TA = 14,
68    P_0F_AE = 16, P_0F_01 = 17
69  };
70}
71
72// If rows are added to the opcode extension tables, then corresponding entries
73// must be added here.
74//
75// If the row corresponds to a single byte (i.e., 8f), then add an entry for
76// that byte to ONE_BYTE_EXTENSION_TABLES.
77//
78// If the row corresponds to two bytes where the first is 0f, add an entry for
79// the second byte to TWO_BYTE_EXTENSION_TABLES.
80//
81// If the row corresponds to some other set of bytes, you will need to modify
82// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83// to the X86 TD files, except in two cases: if the first two bytes of such a
84// new combination are 0f 38 or 0f 3a, you just have to add maps called
85// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87// in RecognizableInstr::emitDecodePath().
88
89#define ONE_BYTE_EXTENSION_TABLES \
90  EXTENSION_TABLE(80)             \
91  EXTENSION_TABLE(81)             \
92  EXTENSION_TABLE(82)             \
93  EXTENSION_TABLE(83)             \
94  EXTENSION_TABLE(8f)             \
95  EXTENSION_TABLE(c0)             \
96  EXTENSION_TABLE(c1)             \
97  EXTENSION_TABLE(c6)             \
98  EXTENSION_TABLE(c7)             \
99  EXTENSION_TABLE(d0)             \
100  EXTENSION_TABLE(d1)             \
101  EXTENSION_TABLE(d2)             \
102  EXTENSION_TABLE(d3)             \
103  EXTENSION_TABLE(f6)             \
104  EXTENSION_TABLE(f7)             \
105  EXTENSION_TABLE(fe)             \
106  EXTENSION_TABLE(ff)
107
108#define TWO_BYTE_EXTENSION_TABLES \
109  EXTENSION_TABLE(00)             \
110  EXTENSION_TABLE(01)             \
111  EXTENSION_TABLE(18)             \
112  EXTENSION_TABLE(71)             \
113  EXTENSION_TABLE(72)             \
114  EXTENSION_TABLE(73)             \
115  EXTENSION_TABLE(ae)             \
116  EXTENSION_TABLE(b9)             \
117  EXTENSION_TABLE(ba)             \
118  EXTENSION_TABLE(c7)
119
120using namespace X86Disassembler;
121
122/// needsModRMForDecode - Indicates whether a particular instruction requires a
123///   ModR/M byte for the instruction to be properly decoded.  For example, a
124///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
125///   0b11.
126///
127/// @param form - The form of the instruction.
128/// @return     - true if the form implies that a ModR/M byte is required, false
129///               otherwise.
130static bool needsModRMForDecode(uint8_t form) {
131  if (form == X86Local::MRMDestReg    ||
132     form == X86Local::MRMDestMem    ||
133     form == X86Local::MRMSrcReg     ||
134     form == X86Local::MRMSrcMem     ||
135     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
137    return true;
138  else
139    return false;
140}
141
142/// isRegFormat - Indicates whether a particular form requires the Mod field of
143///   the ModR/M byte to be 0b11.
144///
145/// @param form - The form of the instruction.
146/// @return     - true if the form implies that Mod must be 0b11, false
147///               otherwise.
148static bool isRegFormat(uint8_t form) {
149  if (form == X86Local::MRMDestReg ||
150     form == X86Local::MRMSrcReg  ||
151     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
152    return true;
153  else
154    return false;
155}
156
157/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158///   Useful for switch statements and the like.
159///
160/// @param init - A reference to the BitsInit to be decoded.
161/// @return     - The field, with the first bit in the BitsInit as the lowest
162///               order bit.
163static uint8_t byteFromBitsInit(BitsInit &init) {
164  int width = init.getNumBits();
165
166  assert(width <= 8 && "Field is too large for uint8_t!");
167
168  int     index;
169  uint8_t mask = 0x01;
170
171  uint8_t ret = 0;
172
173  for (index = 0; index < width; index++) {
174    if (static_cast<BitInit*>(init.getBit(index))->getValue())
175      ret |= mask;
176
177    mask <<= 1;
178  }
179
180  return ret;
181}
182
183/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184///   name of the field.
185///
186/// @param rec  - The record from which to extract the value.
187/// @param name - The name of the field in the record.
188/// @return     - The field, as translated by byteFromBitsInit().
189static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190  BitsInit* bits = rec->getValueAsBitsInit(name);
191  return byteFromBitsInit(*bits);
192}
193
194RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195                                     const CodeGenInstruction &insn,
196                                     InstrUID uid) {
197  UID = uid;
198
199  Rec = insn.TheDef;
200  Name = Rec->getName();
201  Spec = &tables.specForUID(UID);
202
203  if (!Rec->isSubClassOf("X86Inst")) {
204    ShouldBeEmitted = false;
205    return;
206  }
207
208  Prefix   = byteFromRec(Rec, "Prefix");
209  Opcode   = byteFromRec(Rec, "Opcode");
210  Form     = byteFromRec(Rec, "FormBits");
211  SegOvr   = byteFromRec(Rec, "SegOvrBits");
212
213  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
214  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
215  HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
216  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
217  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
218
219  Name      = Rec->getName();
220  AsmString = Rec->getValueAsString("AsmString");
221
222  Operands = &insn.OperandList;
223
224  IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
225  HasFROperands    = false;
226
227  ShouldBeEmitted  = true;
228}
229
230void RecognizableInstr::processInstr(DisassemblerTables &tables,
231                                   const CodeGenInstruction &insn,
232                                   InstrUID uid)
233{
234  // Ignore "asm parser only" instructions.
235  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
236    return;
237
238  RecognizableInstr recogInstr(tables, insn, uid);
239
240  recogInstr.emitInstructionSpecifier(tables);
241
242  if (recogInstr.shouldBeEmitted())
243    recogInstr.emitDecodePath(tables);
244}
245
246InstructionContext RecognizableInstr::insnContext() const {
247  InstructionContext insnContext;
248
249  if (Name.find("64") != Name.npos || HasREX_WPrefix) {
250    if (HasREX_WPrefix && HasOpSizePrefix)
251      insnContext = IC_64BIT_REXW_OPSIZE;
252    else if (HasOpSizePrefix)
253      insnContext = IC_64BIT_OPSIZE;
254    else if (HasREX_WPrefix && Prefix == X86Local::XS)
255      insnContext = IC_64BIT_REXW_XS;
256    else if (HasREX_WPrefix && Prefix == X86Local::XD)
257      insnContext = IC_64BIT_REXW_XD;
258    else if (Prefix == X86Local::XD)
259      insnContext = IC_64BIT_XD;
260    else if (Prefix == X86Local::XS)
261      insnContext = IC_64BIT_XS;
262    else if (HasREX_WPrefix)
263      insnContext = IC_64BIT_REXW;
264    else
265      insnContext = IC_64BIT;
266  } else {
267    if (HasOpSizePrefix)
268      insnContext = IC_OPSIZE;
269    else if (Prefix == X86Local::XD)
270      insnContext = IC_XD;
271    else if (Prefix == X86Local::XS)
272      insnContext = IC_XS;
273    else
274      insnContext = IC;
275  }
276
277  return insnContext;
278}
279
280RecognizableInstr::filter_ret RecognizableInstr::filter() const {
281  // Filter out intrinsics
282
283  if (!Rec->isSubClassOf("X86Inst"))
284    return FILTER_STRONG;
285
286  if (Form == X86Local::Pseudo ||
287      IsCodeGenOnly)
288    return FILTER_STRONG;
289
290  if (Form == X86Local::MRMInitReg)
291    return FILTER_STRONG;
292
293
294  // Filter out instructions with a LOCK prefix;
295  //   prefer forms that do not have the prefix
296  if (HasLockPrefix)
297    return FILTER_WEAK;
298
299  // Filter out artificial instructions
300
301  if (Name.find("TAILJMP") != Name.npos    ||
302     Name.find("_Int") != Name.npos       ||
303     Name.find("_int") != Name.npos       ||
304     Name.find("Int_") != Name.npos       ||
305     Name.find("_NOREX") != Name.npos     ||
306     Name.find("_TC") != Name.npos     ||
307     Name.find("EH_RETURN") != Name.npos  ||
308     Name.find("V_SET") != Name.npos      ||
309     Name.find("LOCK_") != Name.npos      ||
310     Name.find("WIN") != Name.npos)
311    return FILTER_STRONG;
312
313  // Special cases.
314
315  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
316    return FILTER_WEAK;
317  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
318    return FILTER_WEAK;
319
320  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
321    return FILTER_WEAK;
322  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
323    return FILTER_WEAK;
324  if (Name.find("Fs") != Name.npos)
325    return FILTER_WEAK;
326  if (Name == "MOVLPDrr"          ||
327      Name == "MOVLPSrr"          ||
328      Name == "PUSHFQ"            ||
329      Name == "BSF16rr"           ||
330      Name == "BSF16rm"           ||
331      Name == "BSR16rr"           ||
332      Name == "BSR16rm"           ||
333      Name == "MOVSX16rm8"        ||
334      Name == "MOVSX16rr8"        ||
335      Name == "MOVZX16rm8"        ||
336      Name == "MOVZX16rr8"        ||
337      Name == "PUSH32i16"         ||
338      Name == "PUSH64i16"         ||
339      Name == "MOVPQI2QImr"       ||
340      Name == "MOVSDmr"           ||
341      Name == "MOVSDrm"           ||
342      Name == "MOVSSmr"           ||
343      Name == "MOVSSrm"           ||
344      Name == "MMX_MOVD64rrv164"  ||
345      Name == "CRC32m16"          ||
346      Name == "MOV64ri64i32"      ||
347      Name == "CRC32r16")
348    return FILTER_WEAK;
349
350  // Filter out instructions with segment override prefixes.
351  // They're too messy to handle now and we'll special case them if needed.
352
353  if (SegOvr)
354    return FILTER_STRONG;
355
356  // Filter out instructions that can't be printed.
357
358  if (AsmString.size() == 0)
359    return FILTER_STRONG;
360
361  // Filter out instructions with subreg operands.
362
363  if (AsmString.find("subreg") != AsmString.npos)
364    return FILTER_STRONG;
365
366  if (HasFROperands && Name.find("MOV") != Name.npos &&
367     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
368      (Name.find("to") != Name.npos)))
369    return FILTER_WEAK;
370
371  return FILTER_NORMAL;
372}
373
374void RecognizableInstr::handleOperand(
375  bool optional,
376  unsigned &operandIndex,
377  unsigned &physicalOperandIndex,
378  unsigned &numPhysicalOperands,
379  unsigned *operandMapping,
380  OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
381  if (optional) {
382    if (physicalOperandIndex >= numPhysicalOperands)
383      return;
384  } else {
385    assert(physicalOperandIndex < numPhysicalOperands);
386  }
387
388  while (operandMapping[operandIndex] != operandIndex) {
389    Spec->operands[operandIndex].encoding = ENCODING_DUP;
390    Spec->operands[operandIndex].type =
391      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
392    ++operandIndex;
393  }
394
395  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
396
397  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
398                                                              HasOpSizePrefix);
399  Spec->operands[operandIndex].type = typeFromString(typeName,
400                                                      IsSSE,
401                                                      HasREX_WPrefix,
402                                                      HasOpSizePrefix);
403
404  ++operandIndex;
405  ++physicalOperandIndex;
406}
407
408void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
409  Spec->name       = Name;
410
411  if (!Rec->isSubClassOf("X86Inst"))
412    return;
413
414  switch (filter()) {
415  case FILTER_WEAK:
416    Spec->filtered = true;
417    break;
418  case FILTER_STRONG:
419    ShouldBeEmitted = false;
420    return;
421  case FILTER_NORMAL:
422    break;
423  }
424
425  Spec->insnContext = insnContext();
426
427  const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
428
429  unsigned operandIndex;
430  unsigned numOperands = OperandList.size();
431  unsigned numPhysicalOperands = 0;
432
433  // operandMapping maps from operands in OperandList to their originals.
434  // If operandMapping[i] != i, then the entry is a duplicate.
435  unsigned operandMapping[X86_MAX_OPERANDS];
436
437  bool hasFROperands = false;
438
439  assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
440
441  for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
442    if (OperandList[operandIndex].Constraints.size()) {
443      const CodeGenInstruction::ConstraintInfo &Constraint =
444        OperandList[operandIndex].Constraints[0];
445      if (Constraint.isTied()) {
446        operandMapping[operandIndex] = Constraint.getTiedOperand();
447      } else {
448        ++numPhysicalOperands;
449        operandMapping[operandIndex] = operandIndex;
450      }
451    } else {
452      ++numPhysicalOperands;
453      operandMapping[operandIndex] = operandIndex;
454    }
455
456    const std::string &recName = OperandList[operandIndex].Rec->getName();
457
458    if (recName.find("FR") != recName.npos)
459      hasFROperands = true;
460  }
461
462  if (hasFROperands && Name.find("MOV") != Name.npos &&
463     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
464      (Name.find("to") != Name.npos)))
465    ShouldBeEmitted = false;
466
467  if (!ShouldBeEmitted)
468    return;
469
470#define HANDLE_OPERAND(class)               \
471  handleOperand(false,                      \
472                operandIndex,               \
473                physicalOperandIndex,       \
474                numPhysicalOperands,        \
475                operandMapping,             \
476                class##EncodingFromString);
477
478#define HANDLE_OPTIONAL(class)              \
479  handleOperand(true,                       \
480                operandIndex,               \
481                physicalOperandIndex,       \
482                numPhysicalOperands,        \
483                operandMapping,             \
484                class##EncodingFromString);
485
486  // operandIndex should always be < numOperands
487  operandIndex = 0;
488  // physicalOperandIndex should always be < numPhysicalOperands
489  unsigned physicalOperandIndex = 0;
490
491  switch (Form) {
492  case X86Local::RawFrm:
493    // Operand 1 (optional) is an address or immediate.
494    // Operand 2 (optional) is an immediate.
495    assert(numPhysicalOperands <= 2 &&
496           "Unexpected number of operands for RawFrm");
497    HANDLE_OPTIONAL(relocation)
498    HANDLE_OPTIONAL(immediate)
499    break;
500  case X86Local::AddRegFrm:
501    // Operand 1 is added to the opcode.
502    // Operand 2 (optional) is an address.
503    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
504           "Unexpected number of operands for AddRegFrm");
505    HANDLE_OPERAND(opcodeModifier)
506    HANDLE_OPTIONAL(relocation)
507    break;
508  case X86Local::MRMDestReg:
509    // Operand 1 is a register operand in the R/M field.
510    // Operand 2 is a register operand in the Reg/Opcode field.
511    // Operand 3 (optional) is an immediate.
512    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
513           "Unexpected number of operands for MRMDestRegFrm");
514    HANDLE_OPERAND(rmRegister)
515    HANDLE_OPERAND(roRegister)
516    HANDLE_OPTIONAL(immediate)
517    break;
518  case X86Local::MRMDestMem:
519    // Operand 1 is a memory operand (possibly SIB-extended)
520    // Operand 2 is a register operand in the Reg/Opcode field.
521    // Operand 3 (optional) is an immediate.
522    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
523           "Unexpected number of operands for MRMDestMemFrm");
524    HANDLE_OPERAND(memory)
525    HANDLE_OPERAND(roRegister)
526    HANDLE_OPTIONAL(immediate)
527    break;
528  case X86Local::MRMSrcReg:
529    // Operand 1 is a register operand in the Reg/Opcode field.
530    // Operand 2 is a register operand in the R/M field.
531    // Operand 3 (optional) is an immediate.
532    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
533           "Unexpected number of operands for MRMSrcRegFrm");
534    HANDLE_OPERAND(roRegister)
535    HANDLE_OPERAND(rmRegister)
536
537    if (HasVEX_4VPrefix)
538      // FIXME: In AVX, the register below becomes the one encoded
539      // in ModRMVEX and the one above the one in the VEX.VVVV field
540      HANDLE_OPTIONAL(rmRegister)
541    else
542      HANDLE_OPTIONAL(immediate)
543    break;
544  case X86Local::MRMSrcMem:
545    // Operand 1 is a register operand in the Reg/Opcode field.
546    // Operand 2 is a memory operand (possibly SIB-extended)
547    // Operand 3 (optional) is an immediate.
548    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
549           "Unexpected number of operands for MRMSrcMemFrm");
550    HANDLE_OPERAND(roRegister)
551
552    if (HasVEX_4VPrefix)
553      // FIXME: In AVX, the register below becomes the one encoded
554      // in ModRMVEX and the one above the one in the VEX.VVVV field
555      HANDLE_OPTIONAL(rmRegister)
556
557    HANDLE_OPERAND(memory)
558    HANDLE_OPTIONAL(immediate)
559    break;
560  case X86Local::MRM0r:
561  case X86Local::MRM1r:
562  case X86Local::MRM2r:
563  case X86Local::MRM3r:
564  case X86Local::MRM4r:
565  case X86Local::MRM5r:
566  case X86Local::MRM6r:
567  case X86Local::MRM7r:
568    // Operand 1 is a register operand in the R/M field.
569    // Operand 2 (optional) is an immediate or relocation.
570    assert(numPhysicalOperands <= 2 &&
571           "Unexpected number of operands for MRMnRFrm");
572    HANDLE_OPTIONAL(rmRegister)
573    HANDLE_OPTIONAL(relocation)
574    break;
575  case X86Local::MRM0m:
576  case X86Local::MRM1m:
577  case X86Local::MRM2m:
578  case X86Local::MRM3m:
579  case X86Local::MRM4m:
580  case X86Local::MRM5m:
581  case X86Local::MRM6m:
582  case X86Local::MRM7m:
583    // Operand 1 is a memory operand (possibly SIB-extended)
584    // Operand 2 (optional) is an immediate or relocation.
585    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
586           "Unexpected number of operands for MRMnMFrm");
587    HANDLE_OPERAND(memory)
588    HANDLE_OPTIONAL(relocation)
589    break;
590  case X86Local::MRMInitReg:
591    // Ignored.
592    break;
593  }
594
595  #undef HANDLE_OPERAND
596  #undef HANDLE_OPTIONAL
597}
598
599void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
600  // Special cases where the LLVM tables are not complete
601
602#define MAP(from, to)                     \
603  case X86Local::MRM_##from:              \
604    filter = new ExactFilter(0x##from);   \
605    break;
606
607  OpcodeType    opcodeType  = (OpcodeType)-1;
608
609  ModRMFilter*  filter      = NULL;
610  uint8_t       opcodeToSet = 0;
611
612  switch (Prefix) {
613  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
614  case X86Local::XD:
615  case X86Local::XS:
616  case X86Local::TB:
617    opcodeType = TWOBYTE;
618
619    switch (Opcode) {
620    default:
621      if (needsModRMForDecode(Form))
622        filter = new ModFilter(isRegFormat(Form));
623      else
624        filter = new DumbFilter();
625      break;
626#define EXTENSION_TABLE(n) case 0x##n:
627    TWO_BYTE_EXTENSION_TABLES
628#undef EXTENSION_TABLE
629      switch (Form) {
630      default:
631        llvm_unreachable("Unhandled two-byte extended opcode");
632      case X86Local::MRM0r:
633      case X86Local::MRM1r:
634      case X86Local::MRM2r:
635      case X86Local::MRM3r:
636      case X86Local::MRM4r:
637      case X86Local::MRM5r:
638      case X86Local::MRM6r:
639      case X86Local::MRM7r:
640        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
641        break;
642      case X86Local::MRM0m:
643      case X86Local::MRM1m:
644      case X86Local::MRM2m:
645      case X86Local::MRM3m:
646      case X86Local::MRM4m:
647      case X86Local::MRM5m:
648      case X86Local::MRM6m:
649      case X86Local::MRM7m:
650        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
651        break;
652      MRM_MAPPING
653      } // switch (Form)
654      break;
655    } // switch (Opcode)
656    opcodeToSet = Opcode;
657    break;
658  case X86Local::T8:
659    opcodeType = THREEBYTE_38;
660    if (needsModRMForDecode(Form))
661      filter = new ModFilter(isRegFormat(Form));
662    else
663      filter = new DumbFilter();
664    opcodeToSet = Opcode;
665    break;
666  case X86Local::P_TA:
667    opcodeType = THREEBYTE_3A;
668    if (needsModRMForDecode(Form))
669      filter = new ModFilter(isRegFormat(Form));
670    else
671      filter = new DumbFilter();
672    opcodeToSet = Opcode;
673    break;
674  case X86Local::D8:
675  case X86Local::D9:
676  case X86Local::DA:
677  case X86Local::DB:
678  case X86Local::DC:
679  case X86Local::DD:
680  case X86Local::DE:
681  case X86Local::DF:
682    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
683    opcodeType = ONEBYTE;
684    if (Form == X86Local::AddRegFrm) {
685      Spec->modifierType = MODIFIER_MODRM;
686      Spec->modifierBase = Opcode;
687      filter = new AddRegEscapeFilter(Opcode);
688    } else {
689      filter = new EscapeFilter(true, Opcode);
690    }
691    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
692    break;
693  default:
694    opcodeType = ONEBYTE;
695    switch (Opcode) {
696#define EXTENSION_TABLE(n) case 0x##n:
697    ONE_BYTE_EXTENSION_TABLES
698#undef EXTENSION_TABLE
699      switch (Form) {
700      default:
701        llvm_unreachable("Fell through the cracks of a single-byte "
702                         "extended opcode");
703      case X86Local::MRM0r:
704      case X86Local::MRM1r:
705      case X86Local::MRM2r:
706      case X86Local::MRM3r:
707      case X86Local::MRM4r:
708      case X86Local::MRM5r:
709      case X86Local::MRM6r:
710      case X86Local::MRM7r:
711        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
712        break;
713      case X86Local::MRM0m:
714      case X86Local::MRM1m:
715      case X86Local::MRM2m:
716      case X86Local::MRM3m:
717      case X86Local::MRM4m:
718      case X86Local::MRM5m:
719      case X86Local::MRM6m:
720      case X86Local::MRM7m:
721        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
722        break;
723      MRM_MAPPING
724      } // switch (Form)
725      break;
726    case 0xd8:
727    case 0xd9:
728    case 0xda:
729    case 0xdb:
730    case 0xdc:
731    case 0xdd:
732    case 0xde:
733    case 0xdf:
734      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
735      break;
736    default:
737      if (needsModRMForDecode(Form))
738        filter = new ModFilter(isRegFormat(Form));
739      else
740        filter = new DumbFilter();
741      break;
742    } // switch (Opcode)
743    opcodeToSet = Opcode;
744  } // switch (Prefix)
745
746  assert(opcodeType != (OpcodeType)-1 &&
747         "Opcode type not set");
748  assert(filter && "Filter not set");
749
750  if (Form == X86Local::AddRegFrm) {
751    if(Spec->modifierType != MODIFIER_MODRM) {
752      assert(opcodeToSet < 0xf9 &&
753             "Not enough room for all ADDREG_FRM operands");
754
755      uint8_t currentOpcode;
756
757      for (currentOpcode = opcodeToSet;
758           currentOpcode < opcodeToSet + 8;
759           ++currentOpcode)
760        tables.setTableFields(opcodeType,
761                              insnContext(),
762                              currentOpcode,
763                              *filter,
764                              UID);
765
766      Spec->modifierType = MODIFIER_OPCODE;
767      Spec->modifierBase = opcodeToSet;
768    } else {
769      // modifierBase was set where MODIFIER_MODRM was set
770      tables.setTableFields(opcodeType,
771                            insnContext(),
772                            opcodeToSet,
773                            *filter,
774                            UID);
775    }
776  } else {
777    tables.setTableFields(opcodeType,
778                          insnContext(),
779                          opcodeToSet,
780                          *filter,
781                          UID);
782
783    Spec->modifierType = MODIFIER_NONE;
784    Spec->modifierBase = opcodeToSet;
785  }
786
787  delete filter;
788
789#undef MAP
790}
791
792#define TYPE(str, type) if (s == str) return type;
793OperandType RecognizableInstr::typeFromString(const std::string &s,
794                                              bool isSSE,
795                                              bool hasREX_WPrefix,
796                                              bool hasOpSizePrefix) {
797  if (isSSE) {
798    // For SSE instructions, we ignore the OpSize prefix and force operand
799    // sizes.
800    TYPE("GR16",              TYPE_R16)
801    TYPE("GR32",              TYPE_R32)
802    TYPE("GR64",              TYPE_R64)
803  }
804  if(hasREX_WPrefix) {
805    // For instructions with a REX_W prefix, a declared 32-bit register encoding
806    // is special.
807    TYPE("GR32",              TYPE_R32)
808  }
809  if(!hasOpSizePrefix) {
810    // For instructions without an OpSize prefix, a declared 16-bit register or
811    // immediate encoding is special.
812    TYPE("GR16",              TYPE_R16)
813    TYPE("i16imm",            TYPE_IMM16)
814  }
815  TYPE("i16mem",              TYPE_Mv)
816  TYPE("i16imm",              TYPE_IMMv)
817  TYPE("i16i8imm",            TYPE_IMMv)
818  TYPE("GR16",                TYPE_Rv)
819  TYPE("i32mem",              TYPE_Mv)
820  TYPE("i32imm",              TYPE_IMMv)
821  TYPE("i32i8imm",            TYPE_IMM32)
822  TYPE("GR32",                TYPE_Rv)
823  TYPE("i64mem",              TYPE_Mv)
824  TYPE("i64i32imm",           TYPE_IMM64)
825  TYPE("i64i8imm",            TYPE_IMM64)
826  TYPE("GR64",                TYPE_R64)
827  TYPE("i8mem",               TYPE_M8)
828  TYPE("i8imm",               TYPE_IMM8)
829  TYPE("GR8",                 TYPE_R8)
830  TYPE("VR128",               TYPE_XMM128)
831  TYPE("f128mem",             TYPE_M128)
832  TYPE("FR64",                TYPE_XMM64)
833  TYPE("f64mem",              TYPE_M64FP)
834  TYPE("FR32",                TYPE_XMM32)
835  TYPE("f32mem",              TYPE_M32FP)
836  TYPE("RST",                 TYPE_ST)
837  TYPE("i128mem",             TYPE_M128)
838  TYPE("i64i32imm_pcrel",     TYPE_REL64)
839  TYPE("i32imm_pcrel",        TYPE_REL32)
840  TYPE("SSECC",               TYPE_IMM3)
841  TYPE("brtarget",            TYPE_RELv)
842  TYPE("brtarget8",           TYPE_REL8)
843  TYPE("f80mem",              TYPE_M80FP)
844  TYPE("lea32mem",            TYPE_LEA)
845  TYPE("lea64_32mem",         TYPE_LEA)
846  TYPE("lea64mem",            TYPE_LEA)
847  TYPE("VR64",                TYPE_MM64)
848  TYPE("i64imm",              TYPE_IMMv)
849  TYPE("opaque32mem",         TYPE_M1616)
850  TYPE("opaque48mem",         TYPE_M1632)
851  TYPE("opaque80mem",         TYPE_M1664)
852  TYPE("opaque512mem",        TYPE_M512)
853  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
854  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
855  TYPE("CONTROL_REG",         TYPE_CONTROLREG)
856  TYPE("offset8",             TYPE_MOFFS8)
857  TYPE("offset16",            TYPE_MOFFS16)
858  TYPE("offset32",            TYPE_MOFFS32)
859  TYPE("offset64",            TYPE_MOFFS64)
860  errs() << "Unhandled type string " << s << "\n";
861  llvm_unreachable("Unhandled type string");
862}
863#undef TYPE
864
865#define ENCODING(str, encoding) if (s == str) return encoding;
866OperandEncoding RecognizableInstr::immediateEncodingFromString
867  (const std::string &s,
868   bool hasOpSizePrefix) {
869  if(!hasOpSizePrefix) {
870    // For instructions without an OpSize prefix, a declared 16-bit register or
871    // immediate encoding is special.
872    ENCODING("i16imm",        ENCODING_IW)
873  }
874  ENCODING("i32i8imm",        ENCODING_IB)
875  ENCODING("SSECC",           ENCODING_IB)
876  ENCODING("i16imm",          ENCODING_Iv)
877  ENCODING("i16i8imm",        ENCODING_IB)
878  ENCODING("i32imm",          ENCODING_Iv)
879  ENCODING("i64i32imm",       ENCODING_ID)
880  ENCODING("i64i8imm",        ENCODING_IB)
881  ENCODING("i8imm",           ENCODING_IB)
882  errs() << "Unhandled immediate encoding " << s << "\n";
883  llvm_unreachable("Unhandled immediate encoding");
884}
885
886OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
887  (const std::string &s,
888   bool hasOpSizePrefix) {
889  ENCODING("GR16",            ENCODING_RM)
890  ENCODING("GR32",            ENCODING_RM)
891  ENCODING("GR64",            ENCODING_RM)
892  ENCODING("GR8",             ENCODING_RM)
893  ENCODING("VR128",           ENCODING_RM)
894  ENCODING("FR64",            ENCODING_RM)
895  ENCODING("FR32",            ENCODING_RM)
896  ENCODING("VR64",            ENCODING_RM)
897  errs() << "Unhandled R/M register encoding " << s << "\n";
898  llvm_unreachable("Unhandled R/M register encoding");
899}
900
901OperandEncoding RecognizableInstr::roRegisterEncodingFromString
902  (const std::string &s,
903   bool hasOpSizePrefix) {
904  ENCODING("GR16",            ENCODING_REG)
905  ENCODING("GR32",            ENCODING_REG)
906  ENCODING("GR64",            ENCODING_REG)
907  ENCODING("GR8",             ENCODING_REG)
908  ENCODING("VR128",           ENCODING_REG)
909  ENCODING("FR64",            ENCODING_REG)
910  ENCODING("FR32",            ENCODING_REG)
911  ENCODING("VR64",            ENCODING_REG)
912  ENCODING("SEGMENT_REG",     ENCODING_REG)
913  ENCODING("DEBUG_REG",       ENCODING_REG)
914  ENCODING("CONTROL_REG",     ENCODING_REG)
915  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
916  llvm_unreachable("Unhandled reg/opcode register encoding");
917}
918
919OperandEncoding RecognizableInstr::memoryEncodingFromString
920  (const std::string &s,
921   bool hasOpSizePrefix) {
922  ENCODING("i16mem",          ENCODING_RM)
923  ENCODING("i32mem",          ENCODING_RM)
924  ENCODING("i64mem",          ENCODING_RM)
925  ENCODING("i8mem",           ENCODING_RM)
926  ENCODING("f128mem",         ENCODING_RM)
927  ENCODING("f64mem",          ENCODING_RM)
928  ENCODING("f32mem",          ENCODING_RM)
929  ENCODING("i128mem",         ENCODING_RM)
930  ENCODING("f80mem",          ENCODING_RM)
931  ENCODING("lea32mem",        ENCODING_RM)
932  ENCODING("lea64_32mem",     ENCODING_RM)
933  ENCODING("lea64mem",        ENCODING_RM)
934  ENCODING("opaque32mem",     ENCODING_RM)
935  ENCODING("opaque48mem",     ENCODING_RM)
936  ENCODING("opaque80mem",     ENCODING_RM)
937  ENCODING("opaque512mem",    ENCODING_RM)
938  errs() << "Unhandled memory encoding " << s << "\n";
939  llvm_unreachable("Unhandled memory encoding");
940}
941
942OperandEncoding RecognizableInstr::relocationEncodingFromString
943  (const std::string &s,
944   bool hasOpSizePrefix) {
945  if(!hasOpSizePrefix) {
946    // For instructions without an OpSize prefix, a declared 16-bit register or
947    // immediate encoding is special.
948    ENCODING("i16imm",        ENCODING_IW)
949  }
950  ENCODING("i16imm",          ENCODING_Iv)
951  ENCODING("i16i8imm",        ENCODING_IB)
952  ENCODING("i32imm",          ENCODING_Iv)
953  ENCODING("i32i8imm",        ENCODING_IB)
954  ENCODING("i64i32imm",       ENCODING_ID)
955  ENCODING("i64i8imm",        ENCODING_IB)
956  ENCODING("i8imm",           ENCODING_IB)
957  ENCODING("i64i32imm_pcrel", ENCODING_ID)
958  ENCODING("i32imm_pcrel",    ENCODING_ID)
959  ENCODING("brtarget",        ENCODING_Iv)
960  ENCODING("brtarget8",       ENCODING_IB)
961  ENCODING("i64imm",          ENCODING_IO)
962  ENCODING("offset8",         ENCODING_Ia)
963  ENCODING("offset16",        ENCODING_Ia)
964  ENCODING("offset32",        ENCODING_Ia)
965  ENCODING("offset64",        ENCODING_Ia)
966  errs() << "Unhandled relocation encoding " << s << "\n";
967  llvm_unreachable("Unhandled relocation encoding");
968}
969
970OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
971  (const std::string &s,
972   bool hasOpSizePrefix) {
973  ENCODING("RST",             ENCODING_I)
974  ENCODING("GR32",            ENCODING_Rv)
975  ENCODING("GR64",            ENCODING_RO)
976  ENCODING("GR16",            ENCODING_Rv)
977  ENCODING("GR8",             ENCODING_RB)
978  errs() << "Unhandled opcode modifier encoding " << s << "\n";
979  llvm_unreachable("Unhandled opcode modifier encoding");
980}
981#undef ENCODING
982