brw_eu.h revision 9f344b3e7d6e23674dd4747faec253f103563b36
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33#ifndef BRW_EU_H 34#define BRW_EU_H 35 36#include "brw_structs.h" 37#include "brw_defines.h" 38#include "shader/program.h" 39 40#define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6)) 41#define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3) 42 43#define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3) 44#define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3) 45#define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0) 46#define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1) 47 48 49#define REG_SIZE (8*4) 50 51 52/* These aren't hardware structs, just something useful for us to pass around: 53 * 54 * Align1 operation has a lot of control over input ranges. Used in 55 * WM programs to implement shaders decomposed into "channel serial" 56 * or "structure of array" form: 57 */ 58struct brw_reg 59{ 60 GLuint type:4; 61 GLuint file:2; 62 GLuint nr:8; 63 GLuint subnr:5; /* :1 in align16 */ 64 GLuint negate:1; /* source only */ 65 GLuint abs:1; /* source only */ 66 GLuint vstride:4; /* source only */ 67 GLuint width:3; /* src only, align1 only */ 68 GLuint hstride:2; /* src only, align1 only */ 69 GLuint address_mode:1; /* relative addressing, hopefully! */ 70 GLuint pad0:1; 71 72 union { 73 struct { 74 GLuint swizzle:8; /* src only, align16 only */ 75 GLuint writemask:4; /* dest only, align16 only */ 76 GLint indirect_offset:10; /* relative addressing offset */ 77 GLuint pad1:10; /* two dwords total */ 78 } bits; 79 80 GLfloat f; 81 GLint d; 82 GLuint ud; 83 } dw1; 84}; 85 86 87struct brw_indirect { 88 GLuint addr_subnr:4; 89 GLint addr_offset:10; 90 GLuint pad:18; 91}; 92 93 94#define BRW_EU_MAX_INSN_STACK 5 95#define BRW_EU_MAX_INSN 1200 96 97struct brw_compile { 98 struct brw_instruction store[BRW_EU_MAX_INSN]; 99 GLuint nr_insn; 100 101 /* Allow clients to push/pop instruction state: 102 */ 103 struct brw_instruction stack[BRW_EU_MAX_INSN_STACK]; 104 struct brw_instruction *current; 105 106 GLuint flag_value; 107}; 108 109 110 111static __inline int type_sz( GLuint type ) 112{ 113 switch( type ) { 114 case BRW_REGISTER_TYPE_UD: 115 case BRW_REGISTER_TYPE_D: 116 case BRW_REGISTER_TYPE_F: 117 return 4; 118 case BRW_REGISTER_TYPE_HF: 119 case BRW_REGISTER_TYPE_UW: 120 case BRW_REGISTER_TYPE_W: 121 return 2; 122 case BRW_REGISTER_TYPE_UB: 123 case BRW_REGISTER_TYPE_B: 124 return 1; 125 default: 126 return 0; 127 } 128} 129 130static __inline struct brw_reg brw_reg( GLuint file, 131 GLuint nr, 132 GLuint subnr, 133 GLuint type, 134 GLuint vstride, 135 GLuint width, 136 GLuint hstride, 137 GLuint swizzle, 138 GLuint writemask) 139{ 140 141 struct brw_reg reg; 142 reg.type = type; 143 reg.file = file; 144 reg.nr = nr; 145 reg.subnr = subnr * type_sz(type); 146 reg.negate = 0; 147 reg.abs = 0; 148 reg.vstride = vstride; 149 reg.width = width; 150 reg.hstride = hstride; 151 reg.address_mode = BRW_ADDRESS_DIRECT; 152 reg.pad0 = 0; 153 154 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to 155 * set swizzle and writemask to W, as the lower bits of subnr will 156 * be lost when converted to align16. This is probably too much to 157 * keep track of as you'd want it adjusted by suboffset(), etc. 158 * Perhaps fix up when converting to align16? 159 */ 160 reg.dw1.bits.swizzle = swizzle; 161 reg.dw1.bits.writemask = writemask; 162 reg.dw1.bits.indirect_offset = 0; 163 reg.dw1.bits.pad1 = 0; 164 return reg; 165} 166 167static __inline struct brw_reg brw_vec16_reg( GLuint file, 168 GLuint nr, 169 GLuint subnr ) 170{ 171 return brw_reg(file, 172 nr, 173 subnr, 174 BRW_REGISTER_TYPE_F, 175 BRW_VERTICAL_STRIDE_16, 176 BRW_WIDTH_16, 177 BRW_HORIZONTAL_STRIDE_1, 178 BRW_SWIZZLE_XYZW, 179 WRITEMASK_XYZW); 180} 181 182static __inline struct brw_reg brw_vec8_reg( GLuint file, 183 GLuint nr, 184 GLuint subnr ) 185{ 186 return brw_reg(file, 187 nr, 188 subnr, 189 BRW_REGISTER_TYPE_F, 190 BRW_VERTICAL_STRIDE_8, 191 BRW_WIDTH_8, 192 BRW_HORIZONTAL_STRIDE_1, 193 BRW_SWIZZLE_XYZW, 194 WRITEMASK_XYZW); 195} 196 197 198static __inline struct brw_reg brw_vec4_reg( GLuint file, 199 GLuint nr, 200 GLuint subnr ) 201{ 202 return brw_reg(file, 203 nr, 204 subnr, 205 BRW_REGISTER_TYPE_F, 206 BRW_VERTICAL_STRIDE_4, 207 BRW_WIDTH_4, 208 BRW_HORIZONTAL_STRIDE_1, 209 BRW_SWIZZLE_XYZW, 210 WRITEMASK_XYZW); 211} 212 213 214static __inline struct brw_reg brw_vec2_reg( GLuint file, 215 GLuint nr, 216 GLuint subnr ) 217{ 218 return brw_reg(file, 219 nr, 220 subnr, 221 BRW_REGISTER_TYPE_F, 222 BRW_VERTICAL_STRIDE_2, 223 BRW_WIDTH_2, 224 BRW_HORIZONTAL_STRIDE_1, 225 BRW_SWIZZLE_XYXY, 226 WRITEMASK_XY); 227} 228 229static __inline struct brw_reg brw_vec1_reg( GLuint file, 230 GLuint nr, 231 GLuint subnr ) 232{ 233 return brw_reg(file, 234 nr, 235 subnr, 236 BRW_REGISTER_TYPE_F, 237 BRW_VERTICAL_STRIDE_0, 238 BRW_WIDTH_1, 239 BRW_HORIZONTAL_STRIDE_0, 240 BRW_SWIZZLE_XXXX, 241 WRITEMASK_X); 242} 243 244 245static __inline struct brw_reg retype( struct brw_reg reg, 246 GLuint type ) 247{ 248 reg.type = type; 249 return reg; 250} 251 252static __inline struct brw_reg suboffset( struct brw_reg reg, 253 GLuint delta ) 254{ 255 reg.subnr += delta * type_sz(reg.type); 256 return reg; 257} 258 259 260static __inline struct brw_reg offset( struct brw_reg reg, 261 GLuint delta ) 262{ 263 reg.nr += delta; 264 return reg; 265} 266 267 268static __inline struct brw_reg byte_offset( struct brw_reg reg, 269 GLuint bytes ) 270{ 271 GLuint newoffset = reg.nr * REG_SIZE + reg.subnr + bytes; 272 reg.nr = newoffset / REG_SIZE; 273 reg.subnr = newoffset % REG_SIZE; 274 return reg; 275} 276 277 278static __inline struct brw_reg brw_uw16_reg( GLuint file, 279 GLuint nr, 280 GLuint subnr ) 281{ 282 return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); 283} 284 285static __inline struct brw_reg brw_uw8_reg( GLuint file, 286 GLuint nr, 287 GLuint subnr ) 288{ 289 return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); 290} 291 292static __inline struct brw_reg brw_uw1_reg( GLuint file, 293 GLuint nr, 294 GLuint subnr ) 295{ 296 return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); 297} 298 299static __inline struct brw_reg brw_imm_reg( GLuint type ) 300{ 301 return brw_reg( BRW_IMMEDIATE_VALUE, 302 0, 303 0, 304 type, 305 BRW_VERTICAL_STRIDE_0, 306 BRW_WIDTH_1, 307 BRW_HORIZONTAL_STRIDE_0, 308 0, 309 0); 310} 311 312static __inline struct brw_reg brw_imm_f( GLfloat f ) 313{ 314 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); 315 imm.dw1.f = f; 316 return imm; 317} 318 319static __inline struct brw_reg brw_imm_d( GLint d ) 320{ 321 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D); 322 imm.dw1.d = d; 323 return imm; 324} 325 326static __inline struct brw_reg brw_imm_ud( GLuint ud ) 327{ 328 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD); 329 imm.dw1.ud = ud; 330 return imm; 331} 332 333static __inline struct brw_reg brw_imm_uw( GLushort uw ) 334{ 335 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW); 336 imm.dw1.ud = uw; 337 return imm; 338} 339 340static __inline struct brw_reg brw_imm_w( GLshort w ) 341{ 342 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W); 343 imm.dw1.d = w; 344 return imm; 345} 346 347/* brw_imm_b and brw_imm_ub aren't supported by hardware - the type 348 * numbers alias with _V and _VF below: 349 */ 350 351/* Vector of eight signed half-byte values: 352 */ 353static __inline struct brw_reg brw_imm_v( GLuint v ) 354{ 355 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V); 356 imm.vstride = BRW_VERTICAL_STRIDE_0; 357 imm.width = BRW_WIDTH_8; 358 imm.hstride = BRW_HORIZONTAL_STRIDE_1; 359 imm.dw1.ud = v; 360 return imm; 361} 362 363/* Vector of four 8-bit float values: 364 */ 365static __inline struct brw_reg brw_imm_vf( GLuint v ) 366{ 367 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); 368 imm.vstride = BRW_VERTICAL_STRIDE_0; 369 imm.width = BRW_WIDTH_4; 370 imm.hstride = BRW_HORIZONTAL_STRIDE_1; 371 imm.dw1.ud = v; 372 return imm; 373} 374 375#define VF_ZERO 0x0 376#define VF_ONE 0x30 377#define VF_NEG (1<<7) 378 379static __inline struct brw_reg brw_imm_vf4( GLuint v0, 380 GLuint v1, 381 GLuint v2, 382 GLuint v3) 383{ 384 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); 385 imm.vstride = BRW_VERTICAL_STRIDE_0; 386 imm.width = BRW_WIDTH_4; 387 imm.hstride = BRW_HORIZONTAL_STRIDE_1; 388 imm.dw1.ud = ((v0 << 0) | 389 (v1 << 8) | 390 (v2 << 16) | 391 (v3 << 24)); 392 return imm; 393} 394 395 396static __inline struct brw_reg brw_address( struct brw_reg reg ) 397{ 398 return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr); 399} 400 401 402static __inline struct brw_reg brw_vec1_grf( GLuint nr, 403 GLuint subnr ) 404{ 405 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); 406} 407 408static __inline struct brw_reg brw_vec8_grf( GLuint nr, 409 GLuint subnr ) 410{ 411 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); 412} 413 414static __inline struct brw_reg brw_vec4_grf( GLuint nr, 415 GLuint subnr ) 416{ 417 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); 418} 419 420 421static __inline struct brw_reg brw_vec2_grf( GLuint nr, 422 GLuint subnr ) 423{ 424 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); 425} 426 427static __inline struct brw_reg brw_uw8_grf( GLuint nr, 428 GLuint subnr ) 429{ 430 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); 431} 432 433static __inline struct brw_reg brw_null_reg( void ) 434{ 435 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, 436 BRW_ARF_NULL, 437 0); 438} 439 440static __inline struct brw_reg brw_address_reg( GLuint subnr ) 441{ 442 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, 443 BRW_ARF_ADDRESS, 444 subnr); 445} 446 447/* If/else instructions break in align16 mode if writemask & swizzle 448 * aren't xyzw. This goes against the convention for other scalar 449 * regs: 450 */ 451static __inline struct brw_reg brw_ip_reg( void ) 452{ 453 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, 454 BRW_ARF_IP, 455 0, 456 BRW_REGISTER_TYPE_UD, 457 BRW_VERTICAL_STRIDE_4, /* ? */ 458 BRW_WIDTH_1, 459 BRW_HORIZONTAL_STRIDE_0, 460 BRW_SWIZZLE_XYZW, /* NOTE! */ 461 WRITEMASK_XYZW); /* NOTE! */ 462} 463 464static __inline struct brw_reg brw_acc_reg( void ) 465{ 466 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, 467 BRW_ARF_ACCUMULATOR, 468 0); 469} 470 471 472static __inline struct brw_reg brw_flag_reg( void ) 473{ 474 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, 475 BRW_ARF_FLAG, 476 0); 477} 478 479 480static __inline struct brw_reg brw_mask_reg( GLuint subnr ) 481{ 482 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, 483 BRW_ARF_MASK, 484 subnr); 485} 486 487static __inline struct brw_reg brw_message_reg( GLuint nr ) 488{ 489 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 490 nr, 491 0); 492} 493 494 495 496 497/* This is almost always called with a numeric constant argument, so 498 * make things easy to evaluate at compile time: 499 */ 500static __inline GLuint cvt( GLuint val ) 501{ 502 switch (val) { 503 case 0: return 0; 504 case 1: return 1; 505 case 2: return 2; 506 case 4: return 3; 507 case 8: return 4; 508 case 16: return 5; 509 case 32: return 6; 510 } 511 return 0; 512} 513 514static __inline struct brw_reg stride( struct brw_reg reg, 515 GLuint vstride, 516 GLuint width, 517 GLuint hstride ) 518{ 519 520 reg.vstride = cvt(vstride); 521 reg.width = cvt(width) - 1; 522 reg.hstride = cvt(hstride); 523 return reg; 524} 525 526static __inline struct brw_reg vec16( struct brw_reg reg ) 527{ 528 return stride(reg, 16,16,1); 529} 530 531static __inline struct brw_reg vec8( struct brw_reg reg ) 532{ 533 return stride(reg, 8,8,1); 534} 535 536static __inline struct brw_reg vec4( struct brw_reg reg ) 537{ 538 return stride(reg, 4,4,1); 539} 540 541static __inline struct brw_reg vec2( struct brw_reg reg ) 542{ 543 return stride(reg, 2,2,1); 544} 545 546static __inline struct brw_reg vec1( struct brw_reg reg ) 547{ 548 return stride(reg, 0,1,0); 549} 550 551static __inline struct brw_reg get_element( struct brw_reg reg, GLuint elt ) 552{ 553 return vec1(suboffset(reg, elt)); 554} 555 556static __inline struct brw_reg get_element_ud( struct brw_reg reg, GLuint elt ) 557{ 558 return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt)); 559} 560 561 562static __inline struct brw_reg brw_swizzle( struct brw_reg reg, 563 GLuint x, 564 GLuint y, 565 GLuint z, 566 GLuint w) 567{ 568 reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x), 569 BRW_GET_SWZ(reg.dw1.bits.swizzle, y), 570 BRW_GET_SWZ(reg.dw1.bits.swizzle, z), 571 BRW_GET_SWZ(reg.dw1.bits.swizzle, w)); 572 return reg; 573} 574 575 576static __inline struct brw_reg brw_swizzle1( struct brw_reg reg, 577 GLuint x ) 578{ 579 return brw_swizzle(reg, x, x, x, x); 580} 581 582static __inline struct brw_reg brw_writemask( struct brw_reg reg, 583 GLuint mask ) 584{ 585 reg.dw1.bits.writemask &= mask; 586 return reg; 587} 588 589static __inline struct brw_reg brw_set_writemask( struct brw_reg reg, 590 GLuint mask ) 591{ 592 reg.dw1.bits.writemask = mask; 593 return reg; 594} 595 596static __inline struct brw_reg negate( struct brw_reg reg ) 597{ 598 reg.negate ^= 1; 599 return reg; 600} 601 602static __inline struct brw_reg brw_abs( struct brw_reg reg ) 603{ 604 reg.abs = 1; 605 return reg; 606} 607 608/*********************************************************************** 609 */ 610static __inline struct brw_reg brw_vec4_indirect( GLuint subnr, 611 GLint offset ) 612{ 613 struct brw_reg reg = brw_vec4_grf(0, 0); 614 reg.subnr = subnr; 615 reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; 616 reg.dw1.bits.indirect_offset = offset; 617 return reg; 618} 619 620static __inline struct brw_reg brw_vec1_indirect( GLuint subnr, 621 GLint offset ) 622{ 623 struct brw_reg reg = brw_vec1_grf(0, 0); 624 reg.subnr = subnr; 625 reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; 626 reg.dw1.bits.indirect_offset = offset; 627 return reg; 628} 629 630static __inline struct brw_reg deref_4f(struct brw_indirect ptr, GLint offset) 631{ 632 return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset); 633} 634 635static __inline struct brw_reg deref_1f(struct brw_indirect ptr, GLint offset) 636{ 637 return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset); 638} 639 640static __inline struct brw_reg deref_4b(struct brw_indirect ptr, GLint offset) 641{ 642 return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B); 643} 644 645static __inline struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset) 646{ 647 return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW); 648} 649 650static __inline struct brw_reg get_addr_reg(struct brw_indirect ptr) 651{ 652 return brw_address_reg(ptr.addr_subnr); 653} 654 655static __inline struct brw_indirect brw_indirect_offset( struct brw_indirect ptr, GLint offset ) 656{ 657 ptr.addr_offset += offset; 658 return ptr; 659} 660 661static __inline struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset ) 662{ 663 struct brw_indirect ptr; 664 ptr.addr_subnr = addr_subnr; 665 ptr.addr_offset = offset; 666 ptr.pad = 0; 667 return ptr; 668} 669 670 671 672void brw_pop_insn_state( struct brw_compile *p ); 673void brw_push_insn_state( struct brw_compile *p ); 674void brw_set_mask_control( struct brw_compile *p, GLuint value ); 675void brw_set_saturate( struct brw_compile *p, GLuint value ); 676void brw_set_access_mode( struct brw_compile *p, GLuint access_mode ); 677void brw_set_compression_control( struct brw_compile *p, GLboolean control ); 678void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value ); 679void brw_set_predicate_control( struct brw_compile *p, GLuint pc ); 680void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional ); 681 682void brw_init_compile( struct brw_compile *p ); 683const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz ); 684 685 686/* Helpers for regular instructions: 687 */ 688#define ALU1(OP) \ 689struct brw_instruction *brw_##OP(struct brw_compile *p, \ 690 struct brw_reg dest, \ 691 struct brw_reg src0); 692 693#define ALU2(OP) \ 694struct brw_instruction *brw_##OP(struct brw_compile *p, \ 695 struct brw_reg dest, \ 696 struct brw_reg src0, \ 697 struct brw_reg src1); 698 699ALU1(MOV) 700ALU2(SEL) 701ALU1(NOT) 702ALU2(AND) 703ALU2(OR) 704ALU2(XOR) 705ALU2(SHR) 706ALU2(SHL) 707ALU2(RSR) 708ALU2(RSL) 709ALU2(ASR) 710ALU2(JMPI) 711ALU2(ADD) 712ALU2(MUL) 713ALU1(FRC) 714ALU1(RNDD) 715ALU2(MAC) 716ALU2(MACH) 717ALU1(LZD) 718ALU2(DP4) 719ALU2(DPH) 720ALU2(DP3) 721ALU2(DP2) 722ALU2(LINE) 723 724#undef ALU1 725#undef ALU2 726 727 728 729/* Helpers for SEND instruction: 730 */ 731void brw_urb_WRITE(struct brw_compile *p, 732 struct brw_reg dest, 733 GLuint msg_reg_nr, 734 struct brw_reg src0, 735 GLboolean allocate, 736 GLboolean used, 737 GLuint msg_length, 738 GLuint response_length, 739 GLboolean eot, 740 GLboolean writes_complete, 741 GLuint offset, 742 GLuint swizzle); 743 744void brw_fb_WRITE(struct brw_compile *p, 745 struct brw_reg dest, 746 GLuint msg_reg_nr, 747 struct brw_reg src0, 748 GLuint binding_table_index, 749 GLuint msg_length, 750 GLuint response_length, 751 GLboolean eot); 752 753void brw_SAMPLE(struct brw_compile *p, 754 struct brw_reg dest, 755 GLuint msg_reg_nr, 756 struct brw_reg src0, 757 GLuint binding_table_index, 758 GLuint sampler, 759 GLuint writemask, 760 GLuint msg_type, 761 GLuint response_length, 762 GLuint msg_length, 763 GLboolean eot); 764 765void brw_math_16( struct brw_compile *p, 766 struct brw_reg dest, 767 GLuint function, 768 GLuint saturate, 769 GLuint msg_reg_nr, 770 struct brw_reg src, 771 GLuint precision ); 772 773void brw_math( struct brw_compile *p, 774 struct brw_reg dest, 775 GLuint function, 776 GLuint saturate, 777 GLuint msg_reg_nr, 778 struct brw_reg src, 779 GLuint data_type, 780 GLuint precision ); 781 782void brw_dp_READ_16( struct brw_compile *p, 783 struct brw_reg dest, 784 GLuint msg_reg_nr, 785 GLuint scratch_offset ); 786 787void brw_dp_WRITE_16( struct brw_compile *p, 788 struct brw_reg src, 789 GLuint msg_reg_nr, 790 GLuint scratch_offset ); 791 792/* If/else/endif. Works by manipulating the execution flags on each 793 * channel. 794 */ 795struct brw_instruction *brw_IF(struct brw_compile *p, 796 GLuint execute_size); 797 798struct brw_instruction *brw_ELSE(struct brw_compile *p, 799 struct brw_instruction *if_insn); 800 801void brw_ENDIF(struct brw_compile *p, 802 struct brw_instruction *if_or_else_insn); 803 804 805/* DO/WHILE loops: 806 */ 807struct brw_instruction *brw_DO(struct brw_compile *p, 808 GLuint execute_size); 809 810void brw_WHILE(struct brw_compile *p, 811 struct brw_instruction *patch_insn); 812 813/* Forward jumps: 814 */ 815void brw_land_fwd_jump(struct brw_compile *p, 816 struct brw_instruction *jmp_insn); 817 818 819 820void brw_NOP(struct brw_compile *p); 821 822/* Special case: there is never a destination, execution size will be 823 * taken from src0: 824 */ 825void brw_CMP(struct brw_compile *p, 826 struct brw_reg dest, 827 GLuint conditional, 828 struct brw_reg src0, 829 struct brw_reg src1); 830 831void brw_print_reg( struct brw_reg reg ); 832 833 834/*********************************************************************** 835 * brw_eu_util.c: 836 */ 837 838void brw_copy_indirect_to_indirect(struct brw_compile *p, 839 struct brw_indirect dst_ptr, 840 struct brw_indirect src_ptr, 841 GLuint count); 842 843void brw_copy_from_indirect(struct brw_compile *p, 844 struct brw_reg dst, 845 struct brw_indirect ptr, 846 GLuint count); 847 848void brw_copy4(struct brw_compile *p, 849 struct brw_reg dst, 850 struct brw_reg src, 851 GLuint count); 852 853void brw_copy8(struct brw_compile *p, 854 struct brw_reg dst, 855 struct brw_reg src, 856 GLuint count); 857 858void brw_math_invert( struct brw_compile *p, 859 struct brw_reg dst, 860 struct brw_reg src); 861 862 863#endif 864