brw_structs.h revision 24ff42e7d56ac489caeca6b5ffcc3091cc8194b5
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33#ifndef BRW_STRUCTS_H 34#define BRW_STRUCTS_H 35 36 37/** Number of general purpose registers (VS, WM, etc) */ 38#define BRW_MAX_GRF 128 39 40/** Number of message register file registers */ 41#define BRW_MAX_MRF 16 42 43 44/* Command packets: 45 */ 46struct header 47{ 48 GLuint length:16; 49 GLuint opcode:16; 50}; 51 52 53union header_union 54{ 55 struct header bits; 56 GLuint dword; 57}; 58 59struct brw_3d_control 60{ 61 struct 62 { 63 GLuint length:8; 64 GLuint notify_enable:1; 65 GLuint pad:3; 66 GLuint wc_flush_enable:1; 67 GLuint depth_stall_enable:1; 68 GLuint operation:2; 69 GLuint opcode:16; 70 } header; 71 72 struct 73 { 74 GLuint pad:2; 75 GLuint dest_addr_type:1; 76 GLuint dest_addr:29; 77 } dest; 78 79 GLuint dword2; 80 GLuint dword3; 81}; 82 83 84struct brw_3d_primitive 85{ 86 struct 87 { 88 GLuint length:8; 89 GLuint pad:2; 90 GLuint topology:5; 91 GLuint indexed:1; 92 GLuint opcode:16; 93 } header; 94 95 GLuint verts_per_instance; 96 GLuint start_vert_location; 97 GLuint instance_count; 98 GLuint start_instance_location; 99 GLuint base_vert_location; 100}; 101 102/* These seem to be passed around as function args, so it works out 103 * better to keep them as #defines: 104 */ 105#define BRW_FLUSH_READ_CACHE 0x1 106#define BRW_FLUSH_STATE_CACHE 0x2 107#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 108#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 109 110struct brw_mi_flush 111{ 112 GLuint flags:4; 113 GLuint pad:12; 114 GLuint opcode:16; 115}; 116 117struct brw_vf_statistics 118{ 119 GLuint statistics_enable:1; 120 GLuint pad:15; 121 GLuint opcode:16; 122}; 123 124 125 126struct brw_binding_table_pointers 127{ 128 struct header header; 129 GLuint vs; 130 GLuint gs; 131 GLuint clp; 132 GLuint sf; 133 GLuint wm; 134}; 135 136 137struct brw_blend_constant_color 138{ 139 struct header header; 140 GLfloat blend_constant_color[4]; 141}; 142 143 144struct brw_depthbuffer 145{ 146 union header_union header; 147 148 union { 149 struct { 150 GLuint pitch:18; 151 GLuint format:3; 152 GLuint pad:2; 153 GLuint software_tiled_rendering_mode:2; 154 GLuint depth_offset_disable:1; 155 GLuint tile_walk:1; 156 GLuint tiled_surface:1; 157 GLuint pad2:1; 158 GLuint surface_type:3; 159 } bits; 160 GLuint dword; 161 } dword1; 162 163 GLuint dword2_base_addr; 164 165 union { 166 struct { 167 GLuint pad:1; 168 GLuint mipmap_layout:1; 169 GLuint lod:4; 170 GLuint width:13; 171 GLuint height:13; 172 } bits; 173 GLuint dword; 174 } dword3; 175 176 union { 177 struct { 178 GLuint pad:10; 179 GLuint min_array_element:11; 180 GLuint depth:11; 181 } bits; 182 GLuint dword; 183 } dword4; 184}; 185 186struct brw_depthbuffer_g4x 187{ 188 union header_union header; 189 190 union { 191 struct { 192 GLuint pitch:18; 193 GLuint format:3; 194 GLuint pad:2; 195 GLuint software_tiled_rendering_mode:2; 196 GLuint depth_offset_disable:1; 197 GLuint tile_walk:1; 198 GLuint tiled_surface:1; 199 GLuint pad2:1; 200 GLuint surface_type:3; 201 } bits; 202 GLuint dword; 203 } dword1; 204 205 GLuint dword2_base_addr; 206 207 union { 208 struct { 209 GLuint pad:1; 210 GLuint mipmap_layout:1; 211 GLuint lod:4; 212 GLuint width:13; 213 GLuint height:13; 214 } bits; 215 GLuint dword; 216 } dword3; 217 218 union { 219 struct { 220 GLuint pad:10; 221 GLuint min_array_element:11; 222 GLuint depth:11; 223 } bits; 224 GLuint dword; 225 } dword4; 226 227 union { 228 struct { 229 GLuint xoffset:16; 230 GLuint yoffset:16; 231 } bits; 232 GLuint dword; 233 } dword5; /* NEW in Integrated Graphics Device */ 234}; 235 236struct brw_drawrect 237{ 238 struct header header; 239 GLuint xmin:16; 240 GLuint ymin:16; 241 GLuint xmax:16; 242 GLuint ymax:16; 243 GLuint xorg:16; 244 GLuint yorg:16; 245}; 246 247 248 249 250struct brw_global_depth_offset_clamp 251{ 252 struct header header; 253 GLfloat depth_offset_clamp; 254}; 255 256struct brw_indexbuffer 257{ 258 union { 259 struct 260 { 261 GLuint length:8; 262 GLuint index_format:2; 263 GLuint cut_index_enable:1; 264 GLuint pad:5; 265 GLuint opcode:16; 266 } bits; 267 GLuint dword; 268 269 } header; 270 271 GLuint buffer_start; 272 GLuint buffer_end; 273}; 274 275/* NEW in Integrated Graphics Device */ 276struct brw_aa_line_parameters 277{ 278 struct header header; 279 280 struct { 281 GLuint aa_coverage_slope:8; 282 GLuint pad0:8; 283 GLuint aa_coverage_bias:8; 284 GLuint pad1:8; 285 } bits0; 286 287 struct { 288 GLuint aa_coverage_endcap_slope:8; 289 GLuint pad0:8; 290 GLuint aa_coverage_endcap_bias:8; 291 GLuint pad1:8; 292 } bits1; 293}; 294 295struct brw_line_stipple 296{ 297 struct header header; 298 299 struct 300 { 301 GLuint pattern:16; 302 GLuint pad:16; 303 } bits0; 304 305 struct 306 { 307 GLuint repeat_count:9; 308 GLuint pad:7; 309 GLuint inverse_repeat_count:16; 310 } bits1; 311}; 312 313 314struct brw_pipelined_state_pointers 315{ 316 struct header header; 317 318 struct { 319 GLuint pad:5; 320 GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ 321 } vs; 322 323 struct 324 { 325 GLuint enable:1; 326 GLuint pad:4; 327 GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ 328 } gs; 329 330 struct 331 { 332 GLuint enable:1; 333 GLuint pad:4; 334 GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ 335 } clp; 336 337 struct 338 { 339 GLuint pad:5; 340 GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ 341 } sf; 342 343 struct 344 { 345 GLuint pad:5; 346 GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ 347 } wm; 348 349 struct 350 { 351 GLuint pad:5; 352 GLuint offset:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */ 353 } cc; 354}; 355 356 357struct brw_polygon_stipple_offset 358{ 359 struct header header; 360 361 struct { 362 GLuint y_offset:5; 363 GLuint pad:3; 364 GLuint x_offset:5; 365 GLuint pad0:19; 366 } bits0; 367}; 368 369 370 371struct brw_polygon_stipple 372{ 373 struct header header; 374 GLuint stipple[32]; 375}; 376 377 378 379struct brw_pipeline_select 380{ 381 struct 382 { 383 GLuint pipeline_select:1; 384 GLuint pad:15; 385 GLuint opcode:16; 386 } header; 387}; 388 389 390struct brw_pipe_control 391{ 392 struct 393 { 394 GLuint length:8; 395 GLuint notify_enable:1; 396 GLuint texture_cache_flush_enable:1; 397 GLuint indirect_state_pointers_disable:1; 398 GLuint instruction_state_cache_flush_enable:1; 399 GLuint write_cache_flush_enable:1; 400 GLuint depth_stall_enable:1; 401 GLuint post_sync_operation:2; 402 403 GLuint opcode:16; 404 } header; 405 406 struct 407 { 408 GLuint pad:2; 409 GLuint dest_addr_type:1; 410 GLuint dest_addr:29; 411 } bits1; 412 413 GLuint data0; 414 GLuint data1; 415}; 416 417 418struct brw_urb_fence 419{ 420 struct 421 { 422 GLuint length:8; 423 GLuint vs_realloc:1; 424 GLuint gs_realloc:1; 425 GLuint clp_realloc:1; 426 GLuint sf_realloc:1; 427 GLuint vfe_realloc:1; 428 GLuint cs_realloc:1; 429 GLuint pad:2; 430 GLuint opcode:16; 431 } header; 432 433 struct 434 { 435 GLuint vs_fence:10; 436 GLuint gs_fence:10; 437 GLuint clp_fence:10; 438 GLuint pad:2; 439 } bits0; 440 441 struct 442 { 443 GLuint sf_fence:10; 444 GLuint vf_fence:10; 445 GLuint cs_fence:11; 446 GLuint pad:1; 447 } bits1; 448}; 449 450struct brw_cs_urb_state 451{ 452 struct header header; 453 454 struct 455 { 456 GLuint nr_urb_entries:3; 457 GLuint pad:1; 458 GLuint urb_entry_size:5; 459 GLuint pad0:23; 460 } bits0; 461}; 462 463struct brw_constant_buffer 464{ 465 struct 466 { 467 GLuint length:8; 468 GLuint valid:1; 469 GLuint pad:7; 470 GLuint opcode:16; 471 } header; 472 473 struct 474 { 475 GLuint buffer_length:6; 476 GLuint buffer_address:26; 477 } bits0; 478}; 479 480struct brw_state_base_address 481{ 482 struct header header; 483 484 struct 485 { 486 GLuint modify_enable:1; 487 GLuint pad:4; 488 GLuint general_state_address:27; 489 } bits0; 490 491 struct 492 { 493 GLuint modify_enable:1; 494 GLuint pad:4; 495 GLuint surface_state_address:27; 496 } bits1; 497 498 struct 499 { 500 GLuint modify_enable:1; 501 GLuint pad:4; 502 GLuint indirect_object_state_address:27; 503 } bits2; 504 505 struct 506 { 507 GLuint modify_enable:1; 508 GLuint pad:11; 509 GLuint general_state_upper_bound:20; 510 } bits3; 511 512 struct 513 { 514 GLuint modify_enable:1; 515 GLuint pad:11; 516 GLuint indirect_object_state_upper_bound:20; 517 } bits4; 518}; 519 520struct brw_state_prefetch 521{ 522 struct header header; 523 524 struct 525 { 526 GLuint prefetch_count:3; 527 GLuint pad:3; 528 GLuint prefetch_pointer:26; 529 } bits0; 530}; 531 532struct brw_system_instruction_pointer 533{ 534 struct header header; 535 536 struct 537 { 538 GLuint pad:4; 539 GLuint system_instruction_pointer:28; 540 } bits0; 541}; 542 543 544 545 546/* State structs for the various fixed function units: 547 */ 548 549 550struct thread0 551{ 552 GLuint pad0:1; 553 GLuint grf_reg_count:3; 554 GLuint pad1:2; 555 GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */ 556}; 557 558struct thread1 559{ 560 GLuint ext_halt_exception_enable:1; 561 GLuint sw_exception_enable:1; 562 GLuint mask_stack_exception_enable:1; 563 GLuint timeout_exception_enable:1; 564 GLuint illegal_op_exception_enable:1; 565 GLuint pad0:3; 566 GLuint depth_coef_urb_read_offset:6; /* WM only */ 567 GLuint pad1:2; 568 GLuint floating_point_mode:1; 569 GLuint thread_priority:1; 570 GLuint binding_table_entry_count:8; 571 GLuint pad3:5; 572 GLuint single_program_flow:1; 573}; 574 575struct thread2 576{ 577 GLuint per_thread_scratch_space:4; 578 GLuint pad0:6; 579 GLuint scratch_space_base_pointer:22; 580}; 581 582 583struct thread3 584{ 585 GLuint dispatch_grf_start_reg:4; 586 GLuint urb_entry_read_offset:6; 587 GLuint pad0:1; 588 GLuint urb_entry_read_length:6; 589 GLuint pad1:1; 590 GLuint const_urb_entry_read_offset:6; 591 GLuint pad2:1; 592 GLuint const_urb_entry_read_length:6; 593 GLuint pad3:1; 594}; 595 596 597 598struct brw_clip_unit_state 599{ 600 struct thread0 thread0; 601 struct 602 { 603 GLuint pad0:7; 604 GLuint sw_exception_enable:1; 605 GLuint pad1:3; 606 GLuint mask_stack_exception_enable:1; 607 GLuint pad2:1; 608 GLuint illegal_op_exception_enable:1; 609 GLuint pad3:2; 610 GLuint floating_point_mode:1; 611 GLuint thread_priority:1; 612 GLuint binding_table_entry_count:8; 613 GLuint pad4:5; 614 GLuint single_program_flow:1; 615 } thread1; 616 617 struct thread2 thread2; 618 struct thread3 thread3; 619 620 struct 621 { 622 GLuint pad0:9; 623 GLuint gs_output_stats:1; /* not always */ 624 GLuint stats_enable:1; 625 GLuint nr_urb_entries:7; 626 GLuint pad1:1; 627 GLuint urb_entry_allocation_size:5; 628 GLuint pad2:1; 629 GLuint max_threads:5; /* may be less */ 630 GLuint pad3:2; 631 } thread4; 632 633 struct 634 { 635 GLuint pad0:13; 636 GLuint clip_mode:3; 637 GLuint userclip_enable_flags:8; 638 GLuint userclip_must_clip:1; 639 GLuint negative_w_clip_test:1; 640 GLuint guard_band_enable:1; 641 GLuint viewport_z_clip_enable:1; 642 GLuint viewport_xy_clip_enable:1; 643 GLuint vertex_position_space:1; 644 GLuint api_mode:1; 645 GLuint pad2:1; 646 } clip5; 647 648 struct 649 { 650 GLuint pad0:5; 651 GLuint clipper_viewport_state_ptr:27; 652 } clip6; 653 654 655 GLfloat viewport_xmin; 656 GLfloat viewport_xmax; 657 GLfloat viewport_ymin; 658 GLfloat viewport_ymax; 659}; 660 661struct gen6_blend_state 662{ 663 struct { 664 GLuint dest_blend_factor:5; 665 GLuint source_blend_factor:5; 666 GLuint pad3:1; 667 GLuint blend_func:3; 668 GLuint pad2:1; 669 GLuint ia_dest_blend_factor:5; 670 GLuint ia_source_blend_factor:5; 671 GLuint pad1:1; 672 GLuint ia_blend_func:3; 673 GLuint pad0:1; 674 GLuint ia_blend_enable:1; 675 GLuint blend_enable:1; 676 } blend0; 677 678 struct { 679 GLuint post_blend_clamp_enable:1; 680 GLuint pre_blend_clamp_enable:1; 681 GLuint clamp_range:2; 682 GLuint pad0:4; 683 GLuint x_dither_offset:2; 684 GLuint y_dither_offset:2; 685 GLuint dither_enable:1; 686 GLuint alpha_test_func:3; 687 GLuint alpha_test_enable:1; 688 GLuint pad1:1; 689 GLuint logic_op_func:4; 690 GLuint logic_op_enable:1; 691 GLuint pad2:1; 692 GLuint write_disable_b:1; 693 GLuint write_disable_g:1; 694 GLuint write_disable_r:1; 695 GLuint write_disable_a:1; 696 GLuint pad3:1; 697 GLuint alpha_to_coverage_dither:1; 698 GLuint alpha_to_one:1; 699 GLuint alpha_to_coverage:1; 700 } blend1; 701}; 702 703struct gen6_color_calc_state 704{ 705 struct { 706 GLuint alpha_test_format:1; 707 GLuint pad0:14; 708 GLuint round_disable:1; 709 GLuint bf_stencil_ref:8; 710 GLuint stencil_ref:8; 711 } cc0; 712 713 union { 714 GLfloat alpha_ref_f; 715 struct { 716 GLuint ui:8; 717 GLuint pad0:24; 718 } alpha_ref_fi; 719 } cc1; 720 721 GLfloat constant_r; 722 GLfloat constant_g; 723 GLfloat constant_b; 724 GLfloat constant_a; 725}; 726 727struct gen6_depth_stencil_state 728{ 729 struct { 730 GLuint pad0:3; 731 GLuint bf_stencil_pass_depth_pass_op:3; 732 GLuint bf_stencil_pass_depth_fail_op:3; 733 GLuint bf_stencil_fail_op:3; 734 GLuint bf_stencil_func:3; 735 GLuint bf_stencil_enable:1; 736 GLuint pad1:2; 737 GLuint stencil_write_enable:1; 738 GLuint stencil_pass_depth_pass_op:3; 739 GLuint stencil_pass_depth_fail_op:3; 740 GLuint stencil_fail_op:3; 741 GLuint stencil_func:3; 742 GLuint stencil_enable:1; 743 } ds0; 744 745 struct { 746 GLuint bf_stencil_write_mask:8; 747 GLuint bf_stencil_test_mask:8; 748 GLuint stencil_write_mask:8; 749 GLuint stencil_test_mask:8; 750 } ds1; 751 752 struct { 753 GLuint pad0:26; 754 GLuint depth_write_enable:1; 755 GLuint depth_test_func:3; 756 GLuint pad1:1; 757 GLuint depth_test_enable:1; 758 } ds2; 759}; 760 761struct brw_cc_unit_state 762{ 763 struct 764 { 765 GLuint pad0:3; 766 GLuint bf_stencil_pass_depth_pass_op:3; 767 GLuint bf_stencil_pass_depth_fail_op:3; 768 GLuint bf_stencil_fail_op:3; 769 GLuint bf_stencil_func:3; 770 GLuint bf_stencil_enable:1; 771 GLuint pad1:2; 772 GLuint stencil_write_enable:1; 773 GLuint stencil_pass_depth_pass_op:3; 774 GLuint stencil_pass_depth_fail_op:3; 775 GLuint stencil_fail_op:3; 776 GLuint stencil_func:3; 777 GLuint stencil_enable:1; 778 } cc0; 779 780 781 struct 782 { 783 GLuint bf_stencil_ref:8; 784 GLuint stencil_write_mask:8; 785 GLuint stencil_test_mask:8; 786 GLuint stencil_ref:8; 787 } cc1; 788 789 790 struct 791 { 792 GLuint logicop_enable:1; 793 GLuint pad0:10; 794 GLuint depth_write_enable:1; 795 GLuint depth_test_function:3; 796 GLuint depth_test:1; 797 GLuint bf_stencil_write_mask:8; 798 GLuint bf_stencil_test_mask:8; 799 } cc2; 800 801 802 struct 803 { 804 GLuint pad0:8; 805 GLuint alpha_test_func:3; 806 GLuint alpha_test:1; 807 GLuint blend_enable:1; 808 GLuint ia_blend_enable:1; 809 GLuint pad1:1; 810 GLuint alpha_test_format:1; 811 GLuint pad2:16; 812 } cc3; 813 814 struct 815 { 816 GLuint pad0:5; 817 GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ 818 } cc4; 819 820 struct 821 { 822 GLuint pad0:2; 823 GLuint ia_dest_blend_factor:5; 824 GLuint ia_src_blend_factor:5; 825 GLuint ia_blend_function:3; 826 GLuint statistics_enable:1; 827 GLuint logicop_func:4; 828 GLuint pad1:11; 829 GLuint dither_enable:1; 830 } cc5; 831 832 struct 833 { 834 GLuint clamp_post_alpha_blend:1; 835 GLuint clamp_pre_alpha_blend:1; 836 GLuint clamp_range:2; 837 GLuint pad0:11; 838 GLuint y_dither_offset:2; 839 GLuint x_dither_offset:2; 840 GLuint dest_blend_factor:5; 841 GLuint src_blend_factor:5; 842 GLuint blend_function:3; 843 } cc6; 844 845 struct { 846 union { 847 GLfloat f; 848 GLubyte ub[4]; 849 } alpha_ref; 850 } cc7; 851}; 852 853struct brw_sf_unit_state 854{ 855 struct thread0 thread0; 856 struct thread1 thread1; 857 struct thread2 thread2; 858 struct thread3 thread3; 859 860 struct 861 { 862 GLuint pad0:10; 863 GLuint stats_enable:1; 864 GLuint nr_urb_entries:7; 865 GLuint pad1:1; 866 GLuint urb_entry_allocation_size:5; 867 GLuint pad2:1; 868 GLuint max_threads:6; 869 GLuint pad3:1; 870 } thread4; 871 872 struct 873 { 874 GLuint front_winding:1; 875 GLuint viewport_transform:1; 876 GLuint pad0:3; 877 GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ 878 } sf5; 879 880 struct 881 { 882 GLuint pad0:9; 883 GLuint dest_org_vbias:4; 884 GLuint dest_org_hbias:4; 885 GLuint scissor:1; 886 GLuint disable_2x2_trifilter:1; 887 GLuint disable_zero_pix_trifilter:1; 888 GLuint point_rast_rule:2; 889 GLuint line_endcap_aa_region_width:2; 890 GLuint line_width:4; 891 GLuint fast_scissor_disable:1; 892 GLuint cull_mode:2; 893 GLuint aa_enable:1; 894 } sf6; 895 896 struct 897 { 898 GLuint point_size:11; 899 GLuint use_point_size_state:1; 900 GLuint subpixel_precision:1; 901 GLuint sprite_point:1; 902 GLuint pad0:10; 903 GLuint aa_line_distance_mode:1; 904 GLuint trifan_pv:2; 905 GLuint linestrip_pv:2; 906 GLuint tristrip_pv:2; 907 GLuint line_last_pixel_enable:1; 908 } sf7; 909 910}; 911 912struct gen6_scissor_state 913{ 914 GLuint ymin, xmin; 915 GLuint ymax, xmax; 916}; 917 918struct brw_gs_unit_state 919{ 920 struct thread0 thread0; 921 struct thread1 thread1; 922 struct thread2 thread2; 923 struct thread3 thread3; 924 925 struct 926 { 927 GLuint pad0:8; 928 GLuint rendering_enable:1; /* for Ironlake */ 929 GLuint pad4:1; 930 GLuint stats_enable:1; 931 GLuint nr_urb_entries:7; 932 GLuint pad1:1; 933 GLuint urb_entry_allocation_size:5; 934 GLuint pad2:1; 935 GLuint max_threads:5; 936 GLuint pad3:2; 937 } thread4; 938 939 struct 940 { 941 GLuint sampler_count:3; 942 GLuint pad0:2; 943 GLuint sampler_state_pointer:27; 944 } gs5; 945 946 947 struct 948 { 949 GLuint max_vp_index:4; 950 GLuint pad0:12; 951 GLuint svbi_post_inc_value:10; 952 GLuint pad1:1; 953 GLuint svbi_post_inc_enable:1; 954 GLuint svbi_payload:1; 955 GLuint discard_adjaceny:1; 956 GLuint reorder_enable:1; 957 GLuint pad2:1; 958 } gs6; 959}; 960 961 962struct brw_vs_unit_state 963{ 964 struct thread0 thread0; 965 struct thread1 thread1; 966 struct thread2 thread2; 967 struct thread3 thread3; 968 969 struct 970 { 971 GLuint pad0:10; 972 GLuint stats_enable:1; 973 GLuint nr_urb_entries:7; 974 GLuint pad1:1; 975 GLuint urb_entry_allocation_size:5; 976 GLuint pad2:1; 977 GLuint max_threads:6; 978 GLuint pad3:1; 979 } thread4; 980 981 struct 982 { 983 GLuint sampler_count:3; 984 GLuint pad0:2; 985 GLuint sampler_state_pointer:27; 986 } vs5; 987 988 struct 989 { 990 GLuint vs_enable:1; 991 GLuint vert_cache_disable:1; 992 GLuint pad0:30; 993 } vs6; 994}; 995 996 997struct brw_wm_unit_state 998{ 999 struct thread0 thread0; 1000 struct thread1 thread1; 1001 struct thread2 thread2; 1002 struct thread3 thread3; 1003 1004 struct { 1005 GLuint stats_enable:1; 1006 GLuint depth_buffer_clear:1; 1007 GLuint sampler_count:3; 1008 GLuint sampler_state_pointer:27; 1009 } wm4; 1010 1011 struct 1012 { 1013 GLuint enable_8_pix:1; 1014 GLuint enable_16_pix:1; 1015 GLuint enable_32_pix:1; 1016 GLuint enable_con_32_pix:1; 1017 GLuint enable_con_64_pix:1; 1018 GLuint pad0:5; 1019 GLuint legacy_global_depth_bias:1; 1020 GLuint line_stipple:1; 1021 GLuint depth_offset:1; 1022 GLuint polygon_stipple:1; 1023 GLuint line_aa_region_width:2; 1024 GLuint line_endcap_aa_region_width:2; 1025 GLuint early_depth_test:1; 1026 GLuint thread_dispatch_enable:1; 1027 GLuint program_uses_depth:1; 1028 GLuint program_computes_depth:1; 1029 GLuint program_uses_killpixel:1; 1030 GLuint legacy_line_rast: 1; 1031 GLuint transposed_urb_read_enable:1; 1032 GLuint max_threads:7; 1033 } wm5; 1034 1035 GLfloat global_depth_offset_constant; 1036 GLfloat global_depth_offset_scale; 1037 1038 /* for Ironlake only */ 1039 struct { 1040 GLuint pad0:1; 1041 GLuint grf_reg_count_1:3; 1042 GLuint pad1:2; 1043 GLuint kernel_start_pointer_1:26; 1044 } wm8; 1045 1046 struct { 1047 GLuint pad0:1; 1048 GLuint grf_reg_count_2:3; 1049 GLuint pad1:2; 1050 GLuint kernel_start_pointer_2:26; 1051 } wm9; 1052 1053 struct { 1054 GLuint pad0:1; 1055 GLuint grf_reg_count_3:3; 1056 GLuint pad1:2; 1057 GLuint kernel_start_pointer_3:26; 1058 } wm10; 1059}; 1060 1061struct brw_sampler_default_color { 1062 GLfloat color[4]; 1063}; 1064 1065struct brw_sampler_state 1066{ 1067 1068 struct 1069 { 1070 GLuint shadow_function:3; 1071 GLuint lod_bias:11; 1072 GLuint min_filter:3; 1073 GLuint mag_filter:3; 1074 GLuint mip_filter:2; 1075 GLuint base_level:5; 1076 GLuint pad:1; 1077 GLuint lod_preclamp:1; 1078 GLuint default_color_mode:1; 1079 GLuint pad0:1; 1080 GLuint disable:1; 1081 } ss0; 1082 1083 struct 1084 { 1085 GLuint r_wrap_mode:3; 1086 GLuint t_wrap_mode:3; 1087 GLuint s_wrap_mode:3; 1088 GLuint pad:3; 1089 GLuint max_lod:10; 1090 GLuint min_lod:10; 1091 } ss1; 1092 1093 1094 struct 1095 { 1096 GLuint pad:5; 1097 GLuint default_color_pointer:27; 1098 } ss2; 1099 1100 struct 1101 { 1102 GLuint pad:19; 1103 GLuint max_aniso:3; 1104 GLuint chroma_key_mode:1; 1105 GLuint chroma_key_index:2; 1106 GLuint chroma_key_enable:1; 1107 GLuint monochrome_filter_width:3; 1108 GLuint monochrome_filter_height:3; 1109 } ss3; 1110}; 1111 1112 1113struct brw_clipper_viewport 1114{ 1115 GLfloat xmin; 1116 GLfloat xmax; 1117 GLfloat ymin; 1118 GLfloat ymax; 1119}; 1120 1121struct brw_cc_viewport 1122{ 1123 GLfloat min_depth; 1124 GLfloat max_depth; 1125}; 1126 1127struct brw_sf_viewport 1128{ 1129 struct { 1130 GLfloat m00; 1131 GLfloat m11; 1132 GLfloat m22; 1133 GLfloat m30; 1134 GLfloat m31; 1135 GLfloat m32; 1136 } viewport; 1137 1138 /* scissor coordinates are inclusive */ 1139 struct { 1140 GLshort xmin; 1141 GLshort ymin; 1142 GLshort xmax; 1143 GLshort ymax; 1144 } scissor; 1145}; 1146 1147struct gen6_sf_viewport { 1148 GLfloat m00; 1149 GLfloat m11; 1150 GLfloat m22; 1151 GLfloat m30; 1152 GLfloat m31; 1153 GLfloat m32; 1154}; 1155 1156/* Documented in the subsystem/shared-functions/sampler chapter... 1157 */ 1158struct brw_surface_state 1159{ 1160 struct { 1161 GLuint cube_pos_z:1; 1162 GLuint cube_neg_z:1; 1163 GLuint cube_pos_y:1; 1164 GLuint cube_neg_y:1; 1165 GLuint cube_pos_x:1; 1166 GLuint cube_neg_x:1; 1167 GLuint pad:4; 1168 GLuint mipmap_layout_mode:1; 1169 GLuint vert_line_stride_ofs:1; 1170 GLuint vert_line_stride:1; 1171 GLuint color_blend:1; 1172 GLuint writedisable_blue:1; 1173 GLuint writedisable_green:1; 1174 GLuint writedisable_red:1; 1175 GLuint writedisable_alpha:1; 1176 GLuint surface_format:9; /**< BRW_SURFACEFORMAT_x */ 1177 GLuint data_return_format:1; 1178 GLuint pad0:1; 1179 GLuint surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ 1180 } ss0; 1181 1182 struct { 1183 GLuint base_addr; 1184 } ss1; 1185 1186 struct { 1187 GLuint pad:2; 1188 GLuint mip_count:4; 1189 GLuint width:13; 1190 GLuint height:13; 1191 } ss2; 1192 1193 struct { 1194 GLuint tile_walk:1; 1195 GLuint tiled_surface:1; 1196 GLuint pad:1; 1197 GLuint pitch:18; 1198 GLuint depth:11; 1199 } ss3; 1200 1201 struct { 1202 GLuint multisample_position_palette_index:3; 1203 GLuint pad1:1; 1204 GLuint num_multisamples:3; 1205 GLuint pad0:1; 1206 GLuint render_target_view_extent:9; 1207 GLuint min_array_elt:11; 1208 GLuint min_lod:4; 1209 } ss4; 1210 1211 struct { 1212 GLuint pad1:16; 1213 GLuint llc_mapping:1; 1214 GLuint mlc_mapping:1; 1215 GLuint gfdt:1; 1216 GLuint gfdt_src:1; 1217 GLuint y_offset:4; 1218 GLuint pad0:1; 1219 GLuint x_offset:7; 1220 } ss5; /* New in G4X */ 1221 1222}; 1223 1224 1225 1226struct brw_vertex_buffer_state 1227{ 1228 struct { 1229 GLuint pitch:11; 1230 GLuint pad:15; 1231 GLuint access_type:1; 1232 GLuint vb_index:5; 1233 } vb0; 1234 1235 GLuint start_addr; 1236 GLuint max_index; 1237#if 1 1238 GLuint instance_data_step_rate; /* not included for sequential/random vertices? */ 1239#endif 1240}; 1241 1242#define BRW_VBP_MAX 17 1243 1244struct brw_vb_array_state { 1245 struct header header; 1246 struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; 1247}; 1248 1249 1250struct brw_vertex_element_state 1251{ 1252 struct 1253 { 1254 GLuint src_offset:11; 1255 GLuint pad:5; 1256 GLuint src_format:9; 1257 GLuint pad0:1; 1258 GLuint valid:1; 1259 GLuint vertex_buffer_index:5; 1260 } ve0; 1261 1262 struct 1263 { 1264 GLuint dst_offset:8; 1265 GLuint pad:8; 1266 GLuint vfcomponent3:4; 1267 GLuint vfcomponent2:4; 1268 GLuint vfcomponent1:4; 1269 GLuint vfcomponent0:4; 1270 } ve1; 1271}; 1272 1273#define BRW_VEP_MAX 18 1274 1275struct brw_vertex_element_packet { 1276 struct header header; 1277 struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ 1278}; 1279 1280 1281struct brw_urb_immediate { 1282 GLuint opcode:4; 1283 GLuint offset:6; 1284 GLuint swizzle_control:2; 1285 GLuint pad:1; 1286 GLuint allocate:1; 1287 GLuint used:1; 1288 GLuint complete:1; 1289 GLuint response_length:4; 1290 GLuint msg_length:4; 1291 GLuint msg_target:4; 1292 GLuint pad1:3; 1293 GLuint end_of_thread:1; 1294}; 1295 1296/* Instruction format for the execution units: 1297 */ 1298 1299struct brw_instruction 1300{ 1301 struct 1302 { 1303 GLuint opcode:7; 1304 GLuint pad:1; 1305 GLuint access_mode:1; 1306 GLuint mask_control:1; 1307 GLuint dependency_control:2; 1308 GLuint compression_control:2; /* gen6: quater control */ 1309 GLuint thread_control:2; 1310 GLuint predicate_control:4; 1311 GLuint predicate_inverse:1; 1312 GLuint execution_size:3; 1313 GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */ 1314 GLuint acc_wr_control:1; 1315 GLuint cmpt_control:1; 1316 GLuint debug_control:1; 1317 GLuint saturate:1; 1318 } header; 1319 1320 union { 1321 struct 1322 { 1323 GLuint dest_reg_file:2; 1324 GLuint dest_reg_type:3; 1325 GLuint src0_reg_file:2; 1326 GLuint src0_reg_type:3; 1327 GLuint src1_reg_file:2; 1328 GLuint src1_reg_type:3; 1329 GLuint pad:1; 1330 GLuint dest_subreg_nr:5; 1331 GLuint dest_reg_nr:8; 1332 GLuint dest_horiz_stride:2; 1333 GLuint dest_address_mode:1; 1334 } da1; 1335 1336 struct 1337 { 1338 GLuint dest_reg_file:2; 1339 GLuint dest_reg_type:3; 1340 GLuint src0_reg_file:2; 1341 GLuint src0_reg_type:3; 1342 GLuint src1_reg_file:2; /* 0x00000c00 */ 1343 GLuint src1_reg_type:3; /* 0x00007000 */ 1344 GLuint pad:1; 1345 GLint dest_indirect_offset:10; /* offset against the deref'd address reg */ 1346 GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */ 1347 GLuint dest_horiz_stride:2; 1348 GLuint dest_address_mode:1; 1349 } ia1; 1350 1351 struct 1352 { 1353 GLuint dest_reg_file:2; 1354 GLuint dest_reg_type:3; 1355 GLuint src0_reg_file:2; 1356 GLuint src0_reg_type:3; 1357 GLuint src1_reg_file:2; 1358 GLuint src1_reg_type:3; 1359 GLuint pad:1; 1360 GLuint dest_writemask:4; 1361 GLuint dest_subreg_nr:1; 1362 GLuint dest_reg_nr:8; 1363 GLuint dest_horiz_stride:2; 1364 GLuint dest_address_mode:1; 1365 } da16; 1366 1367 struct 1368 { 1369 GLuint dest_reg_file:2; 1370 GLuint dest_reg_type:3; 1371 GLuint src0_reg_file:2; 1372 GLuint src0_reg_type:3; 1373 GLuint pad0:6; 1374 GLuint dest_writemask:4; 1375 GLint dest_indirect_offset:6; 1376 GLuint dest_subreg_nr:3; 1377 GLuint dest_horiz_stride:2; 1378 GLuint dest_address_mode:1; 1379 } ia16; 1380 } bits1; 1381 1382 1383 union { 1384 struct 1385 { 1386 GLuint src0_subreg_nr:5; 1387 GLuint src0_reg_nr:8; 1388 GLuint src0_abs:1; 1389 GLuint src0_negate:1; 1390 GLuint src0_address_mode:1; 1391 GLuint src0_horiz_stride:2; 1392 GLuint src0_width:3; 1393 GLuint src0_vert_stride:4; 1394 GLuint flag_reg_nr:1; 1395 GLuint pad:6; 1396 } da1; 1397 1398 struct 1399 { 1400 GLint src0_indirect_offset:10; 1401 GLuint src0_subreg_nr:3; 1402 GLuint src0_abs:1; 1403 GLuint src0_negate:1; 1404 GLuint src0_address_mode:1; 1405 GLuint src0_horiz_stride:2; 1406 GLuint src0_width:3; 1407 GLuint src0_vert_stride:4; 1408 GLuint flag_reg_nr:1; 1409 GLuint pad:6; 1410 } ia1; 1411 1412 struct 1413 { 1414 GLuint src0_swz_x:2; 1415 GLuint src0_swz_y:2; 1416 GLuint src0_subreg_nr:1; 1417 GLuint src0_reg_nr:8; 1418 GLuint src0_abs:1; 1419 GLuint src0_negate:1; 1420 GLuint src0_address_mode:1; 1421 GLuint src0_swz_z:2; 1422 GLuint src0_swz_w:2; 1423 GLuint pad0:1; 1424 GLuint src0_vert_stride:4; 1425 GLuint flag_reg_nr:1; 1426 GLuint pad1:6; 1427 } da16; 1428 1429 struct 1430 { 1431 GLuint src0_swz_x:2; 1432 GLuint src0_swz_y:2; 1433 GLint src0_indirect_offset:6; 1434 GLuint src0_subreg_nr:3; 1435 GLuint src0_abs:1; 1436 GLuint src0_negate:1; 1437 GLuint src0_address_mode:1; 1438 GLuint src0_swz_z:2; 1439 GLuint src0_swz_w:2; 1440 GLuint pad0:1; 1441 GLuint src0_vert_stride:4; 1442 GLuint flag_reg_nr:1; 1443 GLuint pad1:6; 1444 } ia16; 1445 1446 struct 1447 { 1448 GLuint pad:26; 1449 GLuint end_of_thread:1; 1450 GLuint pad1:1; 1451 GLuint sfid:4; 1452 } send_gen5; /* for Ironlake only */ 1453 1454 } bits2; 1455 1456 union 1457 { 1458 struct 1459 { 1460 GLuint src1_subreg_nr:5; 1461 GLuint src1_reg_nr:8; 1462 GLuint src1_abs:1; 1463 GLuint src1_negate:1; 1464 GLuint src1_address_mode:1; 1465 GLuint src1_horiz_stride:2; 1466 GLuint src1_width:3; 1467 GLuint src1_vert_stride:4; 1468 GLuint pad0:7; 1469 } da1; 1470 1471 struct 1472 { 1473 GLuint src1_swz_x:2; 1474 GLuint src1_swz_y:2; 1475 GLuint src1_subreg_nr:1; 1476 GLuint src1_reg_nr:8; 1477 GLuint src1_abs:1; 1478 GLuint src1_negate:1; 1479 GLuint src1_address_mode:1; 1480 GLuint src1_swz_z:2; 1481 GLuint src1_swz_w:2; 1482 GLuint pad1:1; 1483 GLuint src1_vert_stride:4; 1484 GLuint pad2:7; 1485 } da16; 1486 1487 struct 1488 { 1489 GLint src1_indirect_offset:10; 1490 GLuint src1_subreg_nr:3; 1491 GLuint src1_abs:1; 1492 GLuint src1_negate:1; 1493 GLuint src1_address_mode:1; 1494 GLuint src1_horiz_stride:2; 1495 GLuint src1_width:3; 1496 GLuint src1_vert_stride:4; 1497 GLuint flag_reg_nr:1; 1498 GLuint pad1:6; 1499 } ia1; 1500 1501 struct 1502 { 1503 GLuint src1_swz_x:2; 1504 GLuint src1_swz_y:2; 1505 GLint src1_indirect_offset:6; 1506 GLuint src1_subreg_nr:3; 1507 GLuint src1_abs:1; 1508 GLuint src1_negate:1; 1509 GLuint pad0:1; 1510 GLuint src1_swz_z:2; 1511 GLuint src1_swz_w:2; 1512 GLuint pad1:1; 1513 GLuint src1_vert_stride:4; 1514 GLuint flag_reg_nr:1; 1515 GLuint pad2:6; 1516 } ia16; 1517 1518 1519 struct 1520 { 1521 GLint jump_count:16; /* note: signed */ 1522 GLuint pop_count:4; 1523 GLuint pad0:12; 1524 } if_else; 1525 1526 struct { 1527 GLuint function:4; 1528 GLuint int_type:1; 1529 GLuint precision:1; 1530 GLuint saturate:1; 1531 GLuint data_type:1; 1532 GLuint pad0:8; 1533 GLuint response_length:4; 1534 GLuint msg_length:4; 1535 GLuint msg_target:4; 1536 GLuint pad1:3; 1537 GLuint end_of_thread:1; 1538 } math; 1539 1540 struct { 1541 GLuint function:4; 1542 GLuint int_type:1; 1543 GLuint precision:1; 1544 GLuint saturate:1; 1545 GLuint data_type:1; 1546 GLuint snapshot:1; 1547 GLuint pad0:10; 1548 GLuint header_present:1; 1549 GLuint response_length:5; 1550 GLuint msg_length:4; 1551 GLuint pad1:2; 1552 GLuint end_of_thread:1; 1553 } math_gen5; 1554 1555 struct { 1556 GLuint binding_table_index:8; 1557 GLuint sampler:4; 1558 GLuint return_format:2; 1559 GLuint msg_type:2; 1560 GLuint response_length:4; 1561 GLuint msg_length:4; 1562 GLuint msg_target:4; 1563 GLuint pad1:3; 1564 GLuint end_of_thread:1; 1565 } sampler; 1566 1567 struct { 1568 GLuint binding_table_index:8; 1569 GLuint sampler:4; 1570 GLuint msg_type:4; 1571 GLuint response_length:4; 1572 GLuint msg_length:4; 1573 GLuint msg_target:4; 1574 GLuint pad1:3; 1575 GLuint end_of_thread:1; 1576 } sampler_g4x; 1577 1578 struct { 1579 GLuint binding_table_index:8; 1580 GLuint sampler:4; 1581 GLuint msg_type:4; 1582 GLuint simd_mode:2; 1583 GLuint pad0:1; 1584 GLuint header_present:1; 1585 GLuint response_length:5; 1586 GLuint msg_length:4; 1587 GLuint pad1:2; 1588 GLuint end_of_thread:1; 1589 } sampler_gen5; 1590 1591 struct brw_urb_immediate urb; 1592 1593 struct { 1594 GLuint opcode:4; 1595 GLuint offset:6; 1596 GLuint swizzle_control:2; 1597 GLuint pad:1; 1598 GLuint allocate:1; 1599 GLuint used:1; 1600 GLuint complete:1; 1601 GLuint pad0:3; 1602 GLuint header_present:1; 1603 GLuint response_length:5; 1604 GLuint msg_length:4; 1605 GLuint pad1:2; 1606 GLuint end_of_thread:1; 1607 } urb_gen5; 1608 1609 struct { 1610 GLuint binding_table_index:8; 1611 GLuint msg_control:4; 1612 GLuint msg_type:2; 1613 GLuint target_cache:2; 1614 GLuint response_length:4; 1615 GLuint msg_length:4; 1616 GLuint msg_target:4; 1617 GLuint pad1:3; 1618 GLuint end_of_thread:1; 1619 } dp_read; 1620 1621 struct { 1622 GLuint binding_table_index:8; 1623 GLuint msg_control:3; 1624 GLuint msg_type:3; 1625 GLuint target_cache:2; 1626 GLuint pad0:3; 1627 GLuint header_present:1; 1628 GLuint response_length:5; 1629 GLuint msg_length:4; 1630 GLuint pad1:2; 1631 GLuint end_of_thread:1; 1632 } dp_read_gen5; 1633 1634 struct { 1635 GLuint binding_table_index:8; 1636 GLuint msg_control:3; 1637 GLuint pixel_scoreboard_clear:1; 1638 GLuint msg_type:3; 1639 GLuint send_commit_msg:1; 1640 GLuint response_length:4; 1641 GLuint msg_length:4; 1642 GLuint msg_target:4; 1643 GLuint pad1:3; 1644 GLuint end_of_thread:1; 1645 } dp_write; 1646 1647 struct { 1648 GLuint binding_table_index:8; 1649 GLuint msg_control:3; 1650 GLuint pixel_scoreboard_clear:1; 1651 GLuint msg_type:3; 1652 GLuint send_commit_msg:1; 1653 GLuint pad0:3; 1654 GLuint header_present:1; 1655 GLuint response_length:5; 1656 GLuint msg_length:4; 1657 GLuint pad1:2; 1658 GLuint end_of_thread:1; 1659 } dp_write_gen5; 1660 1661 /* Sandybridge DP for sample cache, constant cache, render cache */ 1662 struct { 1663 GLuint binding_table_index:8; 1664 GLuint msg_control:5; 1665 GLuint msg_type:3; 1666 GLuint pad0:3; 1667 GLuint header_present:1; 1668 GLuint response_length:5; 1669 GLuint msg_length:4; 1670 GLuint pad1:2; 1671 GLuint end_of_thread:1; 1672 } dp_sampler_const_cache; 1673 1674 struct { 1675 GLuint binding_table_index:8; 1676 GLuint msg_control:3; 1677 GLuint slot_group_select:1; 1678 GLuint pixel_scoreboard_clear:1; 1679 GLuint msg_type:4; 1680 GLuint send_commit_msg:1; 1681 GLuint pad0:1; 1682 GLuint header_present:1; 1683 GLuint response_length:5; 1684 GLuint msg_length:4; 1685 GLuint pad1:2; 1686 GLuint end_of_thread:1; 1687 } dp_render_cache; 1688 1689 struct { 1690 GLuint function_control:16; 1691 GLuint response_length:4; 1692 GLuint msg_length:4; 1693 GLuint msg_target:4; 1694 GLuint pad1:3; 1695 GLuint end_of_thread:1; 1696 } generic; 1697 1698 /* Of this struct, only end_of_thread is not present for gen6. */ 1699 struct { 1700 GLuint function_control:19; 1701 GLuint header_present:1; 1702 GLuint response_length:5; 1703 GLuint msg_length:4; 1704 GLuint pad1:2; 1705 GLuint end_of_thread:1; 1706 } generic_gen5; 1707 1708 GLint d; 1709 GLuint ud; 1710 float f; 1711 } bits3; 1712}; 1713 1714 1715#endif 1716