| cbcf750d5f2c4695c39766938b4cd9d8942d850b |
|
27-Jul-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix typo in shader channel select field name.
"chanel" isn't very searchable. I can type, honest!
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 0ba813506d770ead7eb181fb2bf48d5a408fe0ea |
|
03-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add CMS MSAA settings to brw_structs.h.
Previously the DWORD used to control the CMS MSAA layout was just a
pad value, because we didn't use it.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 4848122a96a46d6725cbfe92041459d11aea70fc |
|
20-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set "Shader Channel Select" fields in Haswell's SURFACE_STATE.
These can be used to implement EXT_texture_swizzle without baking
state-dependent swizzle instructions into the shader and forcing
recompiles.
For now, just set them to pass-through mode, so everything continues to
work as it did on Ivybridge. We can optimize this later.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 2b28fd6ca603df40a5d02aac4035eced3a1d079a |
|
22-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the MAD opcode on gen6+.
v2: Fix MRF handling on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| e910241e9754b6e673ed0fc3133c8b1de56e76c7 |
|
27-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix rendering corruption in unigine tropics.
We were allocating registers into the MRF hack region, resulting in
sparkly renering in a few of the scenes. We could do better
allocation by making an MRF class, having MRFs conflict with the
corresponding GRFs, and tracking the live intervals of the "MRF"s and
setting up the conflicts. But this is way easier for the moment.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 9472f6677672ac89d6addba025b33287670da9e9 |
|
09-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace a should-never-happen fallback with asserts where it matters.
We only allow 16 vec4s of attributes in our GLSL/ARB_vp programs, and
1 more element will get used for gl_VertexID/gl_InstanceID. So it
should never have been possible to hit this fallback, unless there was
another bug. If you do hit this, you're probably using gl_VertexID
and falling back to swrast won't work for you anyway.
This also updates the limits for gen6+.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| dcf03e7c09378dfcc744e28f198eaf713d3a21fb |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Document most of the brw_instruction message structs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 53798f90e818e9bf213c3ae4298751362a5ecd50 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Finding this bit in the documentation proved challenging. It wasn't in
the SEND instruction's message descriptor section, nor the data port
message descriptor section. It turns out to be part of the Render
Target Write message's control bits, and in the documentation is named
"Last Render Target Select".
Shaders that use Multiple Render Targets should set this bit on the last
RT write, but not on any prior ones.
The GPU does update the Pixel Scoreboard appropriately, but doesn't
document this bit as directly causing a scoreboard clear.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 0ec04c5a33731991f80eead39c6ee46535e3d4b2 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Document the brw_instruction Message Descriptor structures.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 3de9405763ad4b9e78577699ec206be7dda03374 |
|
30-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove unused structures for command packets.
We simply emit these using OUT_BATCH and bitshifting, as it results in
better compiled code than packed structures. Since our documentation
is public, it's not terribly useful to keep these around for reference.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 473a519d20c97b54504ff61aaedc0665529c14b7 |
|
30-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit 3DSTATE_VF_STATISTICS in OUT_BATCH style.
This is a little different from most because it's a single DWord;
there's no length field.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| a68c5e6b71ac9abf70eb443637d4e79ffba66595 |
|
30-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP to OUT_BATCH style.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| f04765922c02f2b522b0de17c7c7ce67beca1efe |
|
24-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw_surface_state struct that is now unused.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 64ce592679a5b08d66e3cbbf964f9e695e14aee1 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge.
Ivybridge's IF instruction doesn't support conditional modifiers.
It also introduces UIP, which must point to the ENDIF instruction.
ELSE and ENDIF remain the same except that JIP moves from dst to src1.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 36f8de02e71ee5c2ca55d86c486eb00d043ae1f5 |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix sampler message descriptor on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 3f44043da37bcd0c481ceddf4f878ddb3419b763 |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix SAMPLER_STATE on Ivybridge.
Most of this code copied from brw_wm_sampler_state.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| b2b6cc662271d611462532222ef2fcc30042bd0f |
|
28-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update SURFACE_STATE for Ivybridge.
I'm still not happy with the amount of code duplication here, but it
will have to do for now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 97d4d6f77e885d2c343697f26a5ecf821caaf13b |
|
19-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix the URB write message descriptor on Ivybridge.
The message header is still incorrect, but this is a start.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| ce526a7452abf552af38b86bd3546d6ff9a83194 |
|
19-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix render target writes on Ivybridge.
Ivybridge shifts the data port messages by one bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 18402fbf79e96d7afb6b690906a7656f01a92b9d |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge Viewport state setup.
SF and CLIP viewport state has been combined into SF_CLIP_VIEWPORT;
SF_CLIP and CC state pointers can now be uploaded independently.
Some portions of the hardware documentation refer to separate upload
commands for SF and CLIP; these are outdated and incorrect.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| c77855d64eae45786d2d637bd065c8a700b788e5 |
|
13-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename dp_render_target struct to gen6_dp.
This is actually just the message descriptor for Gen6+ dataport access;
it has nothing to do with the render cache. Access to the sampler cache
and constant cache also would use this struct; rename for clarity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| dfaaf7c5e8d05ebf544f758be79f12c824c5cdd7 |
|
20-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove dead vertex buffer structs.
We do this OUT_BATCH-style in brw_draw_upload.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| ff5dd55e264d8f0282aa3ae3dc4f6ab26d98731d |
|
14-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.
Most of the newer portions of the code use OUT_BATCH style. I prefer
this style because it offers a clear distinction between a) hardware
messages/structures with a mandatory format, and b) data structures for
our own internal use that we can format however we want.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 4b929c75e2d868cbfb21b5dbeb1f6c689a903be6 |
|
22-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add new HiZ related bits to WM_STATE.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 5dc53444c8323c1787dddbe6b67048828df9c684 |
|
23-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Correct the dp_read message descriptor setup on g4x.
It's mostly like gen4 message descriptor setup, except that the sizes
of type/control changed to be like gen5. Fixes 21 piglit cases on
gm45, including the regressions in bug #32311 from increased VS
constant buffer usage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 834cc8e501c2632fd8f9fc78502a1a99803e6fb9 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: remove unused variable since brw_wm_glsl.c removal.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| cfcc2ef587fad91ad1dff1abbd42886dbe9cc095 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set render_cache_read_write surface state bit on gen6 constant surfs.
This is said to be required in the spec, even when you aren't doing writes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 30f25a10190632a971e2b214c443e54afa463ead |
|
16-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set up the correct texture border color state struct for Ironlake.
This doesn't actually fix border color on Ironlake, but it appears to
be a requirement, and gen6 needs it too.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 00e5a743e2ee3981a34b95067a97fa73c0f5d779 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 BREAK ISA emit.
There are now two targets: the hop-to-end-of-block target, and the
target for where to resume execution for active channels.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| feca6609390d4642418cf7aab878e654964510c4 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up IF/ELSE/ENDIF for gen6.
The jump delta is now in the part of the instruction where the
destination fields used to be, and the src args are ignored (or not,
for the new non-predicated IF that we don't use yet).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 4b6b0bf24a043035d7ada0c966e01df6327dc529 |
|
28-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix scissor state on sandybridge
Fix incorrect scissor rect struct and missed scissor state pointer
setting for sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 956f866030f7bea5fc4a2de28c72e60bdc3a5b3d |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Fix sampler on sandybridge
Sandybridge has not much change on texture sampler with Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 24ff42e7d56ac489caeca6b5ffcc3091cc8194b5 |
|
31-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix depth test on sandybridge
This includes several corrections for fixing depth test on sandybridge.
Fix wrong bits definition in depth stencil state. Fix wrong order of
state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use
buffer width parameter in depth buffer setting.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 3ce2eccbfb925a3af0b91a89a9f7a3603fa45d2d |
|
21-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Set the destination horiz stride even for da16, as SNB seems to need it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 93ba0055c325007656c14ba38302e21be3dc599f |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add AccWrCtl support on Sandybridge.
Whenever the accumulator results are needed, this bit must be set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 8a3f2eb9e6c830ff953751221961f2a6c8f76661 |
|
08-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for SEND mlen/rlen on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 04466795511bc93e4301e71b9e0c7a9154ecf042 |
|
29-Jun-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add definitions for Sandybridge DP write/read messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 1ea7a6a44db7ef8199b7fe78956e158727092479 |
|
15-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the name of aa_coverage_slope in the improved AA line params.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 1ae0cb5f286bbba10e99c8e3bc1c55d2aeb38b59 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add Sandybridge viewport setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 64e0c586a74553b2941f18feb199d8cddb192102 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add Sandybridge scissor state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 7ee590424c974cb10882e9c4664a6024595fc9de |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start adding support for the Sandybridge CC unit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 98a8744e02c5c1aa0c97c0265680f09f92a68818 |
|
02-Sep-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: CS FENCE in URB_FENCE is 11-bits wide
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| b010814e9c7ed30cbdd60a49d81a6ea774c8c3a3 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Spell "conditional" correctly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 1d4bace9fca64c61ccd9f4205262417fa0ae3883 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out,
and running intel-gen4disasm on it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 0fe19bc91d89dd83b9a7bab28a6009a30e1bc856 |
|
01-Jul-2009 |
Brian Paul <brianp@vmware.com> |
i965: move BRW_MAX_GRF, define BRW_MAX_MRF
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 0f328c90dbc893e15005f2ab441d309c1c176245 |
|
06-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fall back or appropriately adjust offsets of drawing to tiled regions.
3D rendering to tiled textures was being done with non-tile-aligned offsets.
The G4X hardware has fields to let us support it easily and correctly, while
the pre-G4X hardware requires a path full of suffering, so we just fall back.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| d0415a5a01c1a8c2c2a389d977401a7f6cee031b |
|
25-Feb-2009 |
Eric Anholt <eric@anholt.net> |
i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 3147d7785d5cd8c898b19040cb1d30265fba2350 |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor comments
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 34b1776e8d965605d12807884c9c447214d57281 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Merge GM45 into the G4X chipset define.
The mobile and desktop chipsets are the same, and having them separate is
more typing and more chances to screw up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 92c075eeb7c330ea420400d1c2bae57356b19f03 |
|
08-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: official name for GM45 chipset
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
|
| 447facfcd6d807128ebf6ba3efc894180b447494 |
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17-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Simplify scissor handling by using DrawBuffer values.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
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| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
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14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
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| 1b9f78195f62959601d440475a6cbba5e8046813 |
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18-Oct-2006 |
Eric Anholt <eric@anholt.net> |
i965: Avoid branch instructions while in single program flow mode.
There is an errata for Broadwater that threads don't have the instruction/loop
mask stacks initialized on thread spawn. In single program flow mode, those
stacks are not writable, so we can't initialize them. However, they do get
read during ELSE and ENDIF instructions. So, instead, replace branch
instructions in single program flow mode with predicated jumps (ADD to the ip
register), avoiding use of the more complicated branch instructions that may
fail. This is also a minor optimization as no ENDIF equivalent is necessary.
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
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09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_structs.h
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