brw_structs.h revision 97d4d6f77e885d2c343697f26a5ecf821caaf13b
1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28  * Authors:
29  *   Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32
33#ifndef BRW_STRUCTS_H
34#define BRW_STRUCTS_H
35
36
37/** Number of general purpose registers (VS, WM, etc) */
38#define BRW_MAX_GRF 128
39
40/** Number of message register file registers */
41#define BRW_MAX_MRF 16
42
43
44/* Command packets:
45 */
46struct header
47{
48   GLuint length:16;
49   GLuint opcode:16;
50};
51
52
53union header_union
54{
55   struct header bits;
56   GLuint dword;
57};
58
59struct brw_3d_control
60{
61   struct
62   {
63      GLuint length:8;
64      GLuint notify_enable:1;
65      GLuint pad:3;
66      GLuint wc_flush_enable:1;
67      GLuint depth_stall_enable:1;
68      GLuint operation:2;
69      GLuint opcode:16;
70   } header;
71
72   struct
73   {
74      GLuint pad:2;
75      GLuint dest_addr_type:1;
76      GLuint dest_addr:29;
77   } dest;
78
79   GLuint dword2;
80   GLuint dword3;
81};
82
83/* These seem to be passed around as function args, so it works out
84 * better to keep them as #defines:
85 */
86#define BRW_FLUSH_READ_CACHE           0x1
87#define BRW_FLUSH_STATE_CACHE          0x2
88#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
89#define BRW_FLUSH_SNAPSHOT_COUNTERS    0x8
90
91struct brw_mi_flush
92{
93   GLuint flags:4;
94   GLuint pad:12;
95   GLuint opcode:16;
96};
97
98struct brw_vf_statistics
99{
100   GLuint statistics_enable:1;
101   GLuint pad:15;
102   GLuint opcode:16;
103};
104
105
106
107struct brw_binding_table_pointers
108{
109   struct header header;
110   GLuint vs;
111   GLuint gs;
112   GLuint clp;
113   GLuint sf;
114   GLuint wm;
115};
116
117
118struct brw_blend_constant_color
119{
120   struct header header;
121   GLfloat blend_constant_color[4];
122};
123
124
125struct brw_depthbuffer
126{
127   union header_union header;
128
129   union {
130      struct {
131	 GLuint pitch:18;
132	 GLuint format:3;
133	 GLuint pad:2;
134	 GLuint software_tiled_rendering_mode:2;
135	 GLuint depth_offset_disable:1;
136	 GLuint tile_walk:1;
137	 GLuint tiled_surface:1;
138	 GLuint pad2:1;
139	 GLuint surface_type:3;
140      } bits;
141      GLuint dword;
142   } dword1;
143
144   GLuint dword2_base_addr;
145
146   union {
147      struct {
148	 GLuint pad:1;
149	 GLuint mipmap_layout:1;
150	 GLuint lod:4;
151	 GLuint width:13;
152	 GLuint height:13;
153      } bits;
154      GLuint dword;
155   } dword3;
156
157   union {
158      struct {
159	 GLuint pad:10;
160	 GLuint min_array_element:11;
161	 GLuint depth:11;
162      } bits;
163      GLuint dword;
164   } dword4;
165};
166
167struct brw_depthbuffer_g4x
168{
169   union header_union header;
170
171   union {
172      struct {
173	 GLuint pitch:18;
174	 GLuint format:3;
175	 GLuint pad:2;
176	 GLuint software_tiled_rendering_mode:2;
177	 GLuint depth_offset_disable:1;
178	 GLuint tile_walk:1;
179	 GLuint tiled_surface:1;
180	 GLuint pad2:1;
181	 GLuint surface_type:3;
182      } bits;
183      GLuint dword;
184   } dword1;
185
186   GLuint dword2_base_addr;
187
188   union {
189      struct {
190	 GLuint pad:1;
191	 GLuint mipmap_layout:1;
192	 GLuint lod:4;
193	 GLuint width:13;
194	 GLuint height:13;
195      } bits;
196      GLuint dword;
197   } dword3;
198
199   union {
200      struct {
201	 GLuint pad:10;
202	 GLuint min_array_element:11;
203	 GLuint depth:11;
204      } bits;
205      GLuint dword;
206   } dword4;
207
208   union {
209      struct {
210         GLuint xoffset:16;
211         GLuint yoffset:16;
212      } bits;
213      GLuint dword;
214   } dword5;   /* NEW in Integrated Graphics Device */
215};
216
217struct brw_drawrect
218{
219   struct header header;
220   GLuint xmin:16;
221   GLuint ymin:16;
222   GLuint xmax:16;
223   GLuint ymax:16;
224   GLuint xorg:16;
225   GLuint yorg:16;
226};
227
228
229
230
231struct brw_global_depth_offset_clamp
232{
233   struct header header;
234   GLfloat depth_offset_clamp;
235};
236
237struct brw_indexbuffer
238{
239   union {
240      struct
241      {
242	 GLuint length:8;
243	 GLuint index_format:2;
244	 GLuint cut_index_enable:1;
245	 GLuint pad:5;
246	 GLuint opcode:16;
247      } bits;
248      GLuint dword;
249
250   } header;
251
252   GLuint buffer_start;
253   GLuint buffer_end;
254};
255
256/* NEW in Integrated Graphics Device */
257struct brw_aa_line_parameters
258{
259   struct header header;
260
261   struct {
262      GLuint aa_coverage_slope:8;
263      GLuint pad0:8;
264      GLuint aa_coverage_bias:8;
265      GLuint pad1:8;
266   } bits0;
267
268   struct {
269      GLuint aa_coverage_endcap_slope:8;
270      GLuint pad0:8;
271      GLuint aa_coverage_endcap_bias:8;
272      GLuint pad1:8;
273   } bits1;
274};
275
276struct brw_line_stipple
277{
278   struct header header;
279
280   struct
281   {
282      GLuint pattern:16;
283      GLuint pad:16;
284   } bits0;
285
286   struct
287   {
288      GLuint repeat_count:9;
289      GLuint pad:7;
290      GLuint inverse_repeat_count:16;
291   } bits1;
292};
293
294
295struct brw_pipelined_state_pointers
296{
297   struct header header;
298
299   struct {
300      GLuint pad:5;
301      GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
302   } vs;
303
304   struct
305   {
306      GLuint enable:1;
307      GLuint pad:4;
308      GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
309   } gs;
310
311   struct
312   {
313      GLuint enable:1;
314      GLuint pad:4;
315      GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
316   } clp;
317
318   struct
319   {
320      GLuint pad:5;
321      GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
322   } sf;
323
324   struct
325   {
326      GLuint pad:5;
327      GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
328   } wm;
329
330   struct
331   {
332      GLuint pad:5;
333      GLuint offset:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */
334   } cc;
335};
336
337
338struct brw_polygon_stipple_offset
339{
340   struct header header;
341
342   struct {
343      GLuint y_offset:5;
344      GLuint pad:3;
345      GLuint x_offset:5;
346      GLuint pad0:19;
347   } bits0;
348};
349
350
351
352struct brw_polygon_stipple
353{
354   struct header header;
355   GLuint stipple[32];
356};
357
358
359
360struct brw_pipeline_select
361{
362   struct
363   {
364      GLuint pipeline_select:1;
365      GLuint pad:15;
366      GLuint opcode:16;
367   } header;
368};
369
370
371struct brw_pipe_control
372{
373   struct
374   {
375      GLuint length:8;
376      GLuint notify_enable:1;
377      GLuint texture_cache_flush_enable:1;
378      GLuint indirect_state_pointers_disable:1;
379      GLuint instruction_state_cache_flush_enable:1;
380      GLuint write_cache_flush_enable:1;
381      GLuint depth_stall_enable:1;
382      GLuint post_sync_operation:2;
383
384      GLuint opcode:16;
385   } header;
386
387   struct
388   {
389      GLuint pad:2;
390      GLuint dest_addr_type:1;
391      GLuint dest_addr:29;
392   } bits1;
393
394   GLuint data0;
395   GLuint data1;
396};
397
398
399struct brw_urb_fence
400{
401   struct
402   {
403      GLuint length:8;
404      GLuint vs_realloc:1;
405      GLuint gs_realloc:1;
406      GLuint clp_realloc:1;
407      GLuint sf_realloc:1;
408      GLuint vfe_realloc:1;
409      GLuint cs_realloc:1;
410      GLuint pad:2;
411      GLuint opcode:16;
412   } header;
413
414   struct
415   {
416      GLuint vs_fence:10;
417      GLuint gs_fence:10;
418      GLuint clp_fence:10;
419      GLuint pad:2;
420   } bits0;
421
422   struct
423   {
424      GLuint sf_fence:10;
425      GLuint vf_fence:10;
426      GLuint cs_fence:11;
427      GLuint pad:1;
428   } bits1;
429};
430
431struct brw_cs_urb_state
432{
433   struct header header;
434
435   struct
436   {
437      GLuint nr_urb_entries:3;
438      GLuint pad:1;
439      GLuint urb_entry_size:5;
440      GLuint pad0:23;
441   } bits0;
442};
443
444struct brw_constant_buffer
445{
446   struct
447   {
448      GLuint length:8;
449      GLuint valid:1;
450      GLuint pad:7;
451      GLuint opcode:16;
452   } header;
453
454   struct
455   {
456      GLuint buffer_length:6;
457      GLuint buffer_address:26;
458   } bits0;
459};
460
461struct brw_state_base_address
462{
463   struct header header;
464
465   struct
466   {
467      GLuint modify_enable:1;
468      GLuint pad:4;
469      GLuint general_state_address:27;
470   } bits0;
471
472   struct
473   {
474      GLuint modify_enable:1;
475      GLuint pad:4;
476      GLuint surface_state_address:27;
477   } bits1;
478
479   struct
480   {
481      GLuint modify_enable:1;
482      GLuint pad:4;
483      GLuint indirect_object_state_address:27;
484   } bits2;
485
486   struct
487   {
488      GLuint modify_enable:1;
489      GLuint pad:11;
490      GLuint general_state_upper_bound:20;
491   } bits3;
492
493   struct
494   {
495      GLuint modify_enable:1;
496      GLuint pad:11;
497      GLuint indirect_object_state_upper_bound:20;
498   } bits4;
499};
500
501struct brw_state_prefetch
502{
503   struct header header;
504
505   struct
506   {
507      GLuint prefetch_count:3;
508      GLuint pad:3;
509      GLuint prefetch_pointer:26;
510   } bits0;
511};
512
513struct brw_system_instruction_pointer
514{
515   struct header header;
516
517   struct
518   {
519      GLuint pad:4;
520      GLuint system_instruction_pointer:28;
521   } bits0;
522};
523
524
525
526
527/* State structs for the various fixed function units:
528 */
529
530
531struct thread0
532{
533   GLuint pad0:1;
534   GLuint grf_reg_count:3;
535   GLuint pad1:2;
536   GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
537};
538
539struct thread1
540{
541   GLuint ext_halt_exception_enable:1;
542   GLuint sw_exception_enable:1;
543   GLuint mask_stack_exception_enable:1;
544   GLuint timeout_exception_enable:1;
545   GLuint illegal_op_exception_enable:1;
546   GLuint pad0:3;
547   GLuint depth_coef_urb_read_offset:6;	/* WM only */
548   GLuint pad1:2;
549   GLuint floating_point_mode:1;
550   GLuint thread_priority:1;
551   GLuint binding_table_entry_count:8;
552   GLuint pad3:5;
553   GLuint single_program_flow:1;
554};
555
556struct thread2
557{
558   GLuint per_thread_scratch_space:4;
559   GLuint pad0:6;
560   GLuint scratch_space_base_pointer:22;
561};
562
563
564struct thread3
565{
566   GLuint dispatch_grf_start_reg:4;
567   GLuint urb_entry_read_offset:6;
568   GLuint pad0:1;
569   GLuint urb_entry_read_length:6;
570   GLuint pad1:1;
571   GLuint const_urb_entry_read_offset:6;
572   GLuint pad2:1;
573   GLuint const_urb_entry_read_length:6;
574   GLuint pad3:1;
575};
576
577
578
579struct brw_clip_unit_state
580{
581   struct thread0 thread0;
582   struct
583   {
584      GLuint pad0:7;
585      GLuint sw_exception_enable:1;
586      GLuint pad1:3;
587      GLuint mask_stack_exception_enable:1;
588      GLuint pad2:1;
589      GLuint illegal_op_exception_enable:1;
590      GLuint pad3:2;
591      GLuint floating_point_mode:1;
592      GLuint thread_priority:1;
593      GLuint binding_table_entry_count:8;
594      GLuint pad4:5;
595      GLuint single_program_flow:1;
596   } thread1;
597
598   struct thread2 thread2;
599   struct thread3 thread3;
600
601   struct
602   {
603      GLuint pad0:9;
604      GLuint gs_output_stats:1; /* not always */
605      GLuint stats_enable:1;
606      GLuint nr_urb_entries:7;
607      GLuint pad1:1;
608      GLuint urb_entry_allocation_size:5;
609      GLuint pad2:1;
610      GLuint max_threads:5; 	/* may be less */
611      GLuint pad3:2;
612   } thread4;
613
614   struct
615   {
616      GLuint pad0:13;
617      GLuint clip_mode:3;
618      GLuint userclip_enable_flags:8;
619      GLuint userclip_must_clip:1;
620      GLuint negative_w_clip_test:1;
621      GLuint guard_band_enable:1;
622      GLuint viewport_z_clip_enable:1;
623      GLuint viewport_xy_clip_enable:1;
624      GLuint vertex_position_space:1;
625      GLuint api_mode:1;
626      GLuint pad2:1;
627   } clip5;
628
629   struct
630   {
631      GLuint pad0:5;
632      GLuint clipper_viewport_state_ptr:27;
633   } clip6;
634
635
636   GLfloat viewport_xmin;
637   GLfloat viewport_xmax;
638   GLfloat viewport_ymin;
639   GLfloat viewport_ymax;
640};
641
642struct gen6_blend_state
643{
644   struct {
645      GLuint dest_blend_factor:5;
646      GLuint source_blend_factor:5;
647      GLuint pad3:1;
648      GLuint blend_func:3;
649      GLuint pad2:1;
650      GLuint ia_dest_blend_factor:5;
651      GLuint ia_source_blend_factor:5;
652      GLuint pad1:1;
653      GLuint ia_blend_func:3;
654      GLuint pad0:1;
655      GLuint ia_blend_enable:1;
656      GLuint blend_enable:1;
657   } blend0;
658
659   struct {
660      GLuint post_blend_clamp_enable:1;
661      GLuint pre_blend_clamp_enable:1;
662      GLuint clamp_range:2;
663      GLuint pad0:4;
664      GLuint x_dither_offset:2;
665      GLuint y_dither_offset:2;
666      GLuint dither_enable:1;
667      GLuint alpha_test_func:3;
668      GLuint alpha_test_enable:1;
669      GLuint pad1:1;
670      GLuint logic_op_func:4;
671      GLuint logic_op_enable:1;
672      GLuint pad2:1;
673      GLuint write_disable_b:1;
674      GLuint write_disable_g:1;
675      GLuint write_disable_r:1;
676      GLuint write_disable_a:1;
677      GLuint pad3:1;
678      GLuint alpha_to_coverage_dither:1;
679      GLuint alpha_to_one:1;
680      GLuint alpha_to_coverage:1;
681   } blend1;
682};
683
684struct gen6_color_calc_state
685{
686   struct {
687      GLuint alpha_test_format:1;
688      GLuint pad0:14;
689      GLuint round_disable:1;
690      GLuint bf_stencil_ref:8;
691      GLuint stencil_ref:8;
692   } cc0;
693
694   union {
695      GLfloat alpha_ref_f;
696      struct {
697	 GLuint ui:8;
698	 GLuint pad0:24;
699      } alpha_ref_fi;
700   } cc1;
701
702   GLfloat constant_r;
703   GLfloat constant_g;
704   GLfloat constant_b;
705   GLfloat constant_a;
706};
707
708struct gen6_depth_stencil_state
709{
710   struct {
711      GLuint pad0:3;
712      GLuint bf_stencil_pass_depth_pass_op:3;
713      GLuint bf_stencil_pass_depth_fail_op:3;
714      GLuint bf_stencil_fail_op:3;
715      GLuint bf_stencil_func:3;
716      GLuint bf_stencil_enable:1;
717      GLuint pad1:2;
718      GLuint stencil_write_enable:1;
719      GLuint stencil_pass_depth_pass_op:3;
720      GLuint stencil_pass_depth_fail_op:3;
721      GLuint stencil_fail_op:3;
722      GLuint stencil_func:3;
723      GLuint stencil_enable:1;
724   } ds0;
725
726   struct {
727      GLuint bf_stencil_write_mask:8;
728      GLuint bf_stencil_test_mask:8;
729      GLuint stencil_write_mask:8;
730      GLuint stencil_test_mask:8;
731   } ds1;
732
733   struct {
734      GLuint pad0:26;
735      GLuint depth_write_enable:1;
736      GLuint depth_test_func:3;
737      GLuint pad1:1;
738      GLuint depth_test_enable:1;
739   } ds2;
740};
741
742struct brw_cc_unit_state
743{
744   struct
745   {
746      GLuint pad0:3;
747      GLuint bf_stencil_pass_depth_pass_op:3;
748      GLuint bf_stencil_pass_depth_fail_op:3;
749      GLuint bf_stencil_fail_op:3;
750      GLuint bf_stencil_func:3;
751      GLuint bf_stencil_enable:1;
752      GLuint pad1:2;
753      GLuint stencil_write_enable:1;
754      GLuint stencil_pass_depth_pass_op:3;
755      GLuint stencil_pass_depth_fail_op:3;
756      GLuint stencil_fail_op:3;
757      GLuint stencil_func:3;
758      GLuint stencil_enable:1;
759   } cc0;
760
761
762   struct
763   {
764      GLuint bf_stencil_ref:8;
765      GLuint stencil_write_mask:8;
766      GLuint stencil_test_mask:8;
767      GLuint stencil_ref:8;
768   } cc1;
769
770
771   struct
772   {
773      GLuint logicop_enable:1;
774      GLuint pad0:10;
775      GLuint depth_write_enable:1;
776      GLuint depth_test_function:3;
777      GLuint depth_test:1;
778      GLuint bf_stencil_write_mask:8;
779      GLuint bf_stencil_test_mask:8;
780   } cc2;
781
782
783   struct
784   {
785      GLuint pad0:8;
786      GLuint alpha_test_func:3;
787      GLuint alpha_test:1;
788      GLuint blend_enable:1;
789      GLuint ia_blend_enable:1;
790      GLuint pad1:1;
791      GLuint alpha_test_format:1;
792      GLuint pad2:16;
793   } cc3;
794
795   struct
796   {
797      GLuint pad0:5;
798      GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
799   } cc4;
800
801   struct
802   {
803      GLuint pad0:2;
804      GLuint ia_dest_blend_factor:5;
805      GLuint ia_src_blend_factor:5;
806      GLuint ia_blend_function:3;
807      GLuint statistics_enable:1;
808      GLuint logicop_func:4;
809      GLuint pad1:11;
810      GLuint dither_enable:1;
811   } cc5;
812
813   struct
814   {
815      GLuint clamp_post_alpha_blend:1;
816      GLuint clamp_pre_alpha_blend:1;
817      GLuint clamp_range:2;
818      GLuint pad0:11;
819      GLuint y_dither_offset:2;
820      GLuint x_dither_offset:2;
821      GLuint dest_blend_factor:5;
822      GLuint src_blend_factor:5;
823      GLuint blend_function:3;
824   } cc6;
825
826   struct {
827      union {
828	 GLfloat f;
829	 GLubyte ub[4];
830      } alpha_ref;
831   } cc7;
832};
833
834struct brw_sf_unit_state
835{
836   struct thread0 thread0;
837   struct thread1 thread1;
838   struct thread2 thread2;
839   struct thread3 thread3;
840
841   struct
842   {
843      GLuint pad0:10;
844      GLuint stats_enable:1;
845      GLuint nr_urb_entries:7;
846      GLuint pad1:1;
847      GLuint urb_entry_allocation_size:5;
848      GLuint pad2:1;
849      GLuint max_threads:6;
850      GLuint pad3:1;
851   } thread4;
852
853   struct
854   {
855      GLuint front_winding:1;
856      GLuint viewport_transform:1;
857      GLuint pad0:3;
858      GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
859   } sf5;
860
861   struct
862   {
863      GLuint pad0:9;
864      GLuint dest_org_vbias:4;
865      GLuint dest_org_hbias:4;
866      GLuint scissor:1;
867      GLuint disable_2x2_trifilter:1;
868      GLuint disable_zero_pix_trifilter:1;
869      GLuint point_rast_rule:2;
870      GLuint line_endcap_aa_region_width:2;
871      GLuint line_width:4;
872      GLuint fast_scissor_disable:1;
873      GLuint cull_mode:2;
874      GLuint aa_enable:1;
875   } sf6;
876
877   struct
878   {
879      GLuint point_size:11;
880      GLuint use_point_size_state:1;
881      GLuint subpixel_precision:1;
882      GLuint sprite_point:1;
883      GLuint pad0:10;
884      GLuint aa_line_distance_mode:1;
885      GLuint trifan_pv:2;
886      GLuint linestrip_pv:2;
887      GLuint tristrip_pv:2;
888      GLuint line_last_pixel_enable:1;
889   } sf7;
890
891};
892
893struct gen6_scissor_rect
894{
895   GLuint xmin:16;
896   GLuint ymin:16;
897   GLuint xmax:16;
898   GLuint ymax:16;
899};
900
901struct brw_gs_unit_state
902{
903   struct thread0 thread0;
904   struct thread1 thread1;
905   struct thread2 thread2;
906   struct thread3 thread3;
907
908   struct
909   {
910      GLuint pad0:8;
911      GLuint rendering_enable:1; /* for Ironlake */
912      GLuint pad4:1;
913      GLuint stats_enable:1;
914      GLuint nr_urb_entries:7;
915      GLuint pad1:1;
916      GLuint urb_entry_allocation_size:5;
917      GLuint pad2:1;
918      GLuint max_threads:5;
919      GLuint pad3:2;
920   } thread4;
921
922   struct
923   {
924      GLuint sampler_count:3;
925      GLuint pad0:2;
926      GLuint sampler_state_pointer:27;
927   } gs5;
928
929
930   struct
931   {
932      GLuint max_vp_index:4;
933      GLuint pad0:12;
934      GLuint svbi_post_inc_value:10;
935      GLuint pad1:1;
936      GLuint svbi_post_inc_enable:1;
937      GLuint svbi_payload:1;
938      GLuint discard_adjaceny:1;
939      GLuint reorder_enable:1;
940      GLuint pad2:1;
941   } gs6;
942};
943
944
945struct brw_vs_unit_state
946{
947   struct thread0 thread0;
948   struct thread1 thread1;
949   struct thread2 thread2;
950   struct thread3 thread3;
951
952   struct
953   {
954      GLuint pad0:10;
955      GLuint stats_enable:1;
956      GLuint nr_urb_entries:7;
957      GLuint pad1:1;
958      GLuint urb_entry_allocation_size:5;
959      GLuint pad2:1;
960      GLuint max_threads:6;
961      GLuint pad3:1;
962   } thread4;
963
964   struct
965   {
966      GLuint sampler_count:3;
967      GLuint pad0:2;
968      GLuint sampler_state_pointer:27;
969   } vs5;
970
971   struct
972   {
973      GLuint vs_enable:1;
974      GLuint vert_cache_disable:1;
975      GLuint pad0:30;
976   } vs6;
977};
978
979
980struct brw_wm_unit_state
981{
982   struct thread0 thread0;
983   struct thread1 thread1;
984   struct thread2 thread2;
985   struct thread3 thread3;
986
987   struct {
988      GLuint stats_enable:1;
989      GLuint depth_buffer_clear:1;
990      GLuint sampler_count:3;
991      GLuint sampler_state_pointer:27;
992   } wm4;
993
994   struct
995   {
996      GLuint enable_8_pix:1;
997      GLuint enable_16_pix:1;
998      GLuint enable_32_pix:1;
999      GLuint enable_con_32_pix:1;
1000      GLuint enable_con_64_pix:1;
1001      GLuint pad0:1;
1002
1003      /* These next four bits are for Ironlake+ */
1004      GLuint fast_span_coverage_enable:1;
1005      GLuint depth_buffer_clear:1;
1006      GLuint depth_buffer_resolve_enable:1;
1007      GLuint hierarchical_depth_buffer_resolve_enable:1;
1008
1009      GLuint legacy_global_depth_bias:1;
1010      GLuint line_stipple:1;
1011      GLuint depth_offset:1;
1012      GLuint polygon_stipple:1;
1013      GLuint line_aa_region_width:2;
1014      GLuint line_endcap_aa_region_width:2;
1015      GLuint early_depth_test:1;
1016      GLuint thread_dispatch_enable:1;
1017      GLuint program_uses_depth:1;
1018      GLuint program_computes_depth:1;
1019      GLuint program_uses_killpixel:1;
1020      GLuint legacy_line_rast: 1;
1021      GLuint transposed_urb_read_enable:1;
1022      GLuint max_threads:7;
1023   } wm5;
1024
1025   GLfloat global_depth_offset_constant;
1026   GLfloat global_depth_offset_scale;
1027
1028   /* for Ironlake only */
1029   struct {
1030      GLuint pad0:1;
1031      GLuint grf_reg_count_1:3;
1032      GLuint pad1:2;
1033      GLuint kernel_start_pointer_1:26;
1034   } wm8;
1035
1036   struct {
1037      GLuint pad0:1;
1038      GLuint grf_reg_count_2:3;
1039      GLuint pad1:2;
1040      GLuint kernel_start_pointer_2:26;
1041   } wm9;
1042
1043   struct {
1044      GLuint pad0:1;
1045      GLuint grf_reg_count_3:3;
1046      GLuint pad1:2;
1047      GLuint kernel_start_pointer_3:26;
1048   } wm10;
1049};
1050
1051struct brw_sampler_default_color {
1052   GLfloat color[4];
1053};
1054
1055struct gen5_sampler_default_color {
1056   uint8_t ub[4];
1057   float f[4];
1058   uint16_t hf[4];
1059   uint16_t us[4];
1060   int16_t s[4];
1061   uint8_t b[4];
1062};
1063
1064struct brw_sampler_state
1065{
1066
1067   struct
1068   {
1069      GLuint shadow_function:3;
1070      GLuint lod_bias:11;
1071      GLuint min_filter:3;
1072      GLuint mag_filter:3;
1073      GLuint mip_filter:2;
1074      GLuint base_level:5;
1075      GLuint min_mag_neq:1;
1076      GLuint lod_preclamp:1;
1077      GLuint default_color_mode:1;
1078      GLuint pad0:1;
1079      GLuint disable:1;
1080   } ss0;
1081
1082   struct
1083   {
1084      GLuint r_wrap_mode:3;
1085      GLuint t_wrap_mode:3;
1086      GLuint s_wrap_mode:3;
1087      GLuint cube_control_mode:1;
1088      GLuint pad:2;
1089      GLuint max_lod:10;
1090      GLuint min_lod:10;
1091   } ss1;
1092
1093
1094   struct
1095   {
1096      GLuint pad:5;
1097      GLuint default_color_pointer:27;
1098   } ss2;
1099
1100   struct
1101   {
1102      GLuint non_normalized_coord:1;
1103      GLuint pad:12;
1104      GLuint address_round:6;
1105      GLuint max_aniso:3;
1106      GLuint chroma_key_mode:1;
1107      GLuint chroma_key_index:2;
1108      GLuint chroma_key_enable:1;
1109      GLuint monochrome_filter_width:3;
1110      GLuint monochrome_filter_height:3;
1111   } ss3;
1112};
1113
1114
1115struct brw_clipper_viewport
1116{
1117   GLfloat xmin;
1118   GLfloat xmax;
1119   GLfloat ymin;
1120   GLfloat ymax;
1121};
1122
1123struct brw_cc_viewport
1124{
1125   GLfloat min_depth;
1126   GLfloat max_depth;
1127};
1128
1129struct brw_sf_viewport
1130{
1131   struct {
1132      GLfloat m00;
1133      GLfloat m11;
1134      GLfloat m22;
1135      GLfloat m30;
1136      GLfloat m31;
1137      GLfloat m32;
1138   } viewport;
1139
1140   /* scissor coordinates are inclusive */
1141   struct {
1142      GLshort xmin;
1143      GLshort ymin;
1144      GLshort xmax;
1145      GLshort ymax;
1146   } scissor;
1147};
1148
1149struct gen6_sf_viewport {
1150   GLfloat m00;
1151   GLfloat m11;
1152   GLfloat m22;
1153   GLfloat m30;
1154   GLfloat m31;
1155   GLfloat m32;
1156};
1157
1158struct gen7_sf_clip_viewport {
1159   struct {
1160      GLfloat m00;
1161      GLfloat m11;
1162      GLfloat m22;
1163      GLfloat m30;
1164      GLfloat m31;
1165      GLfloat m32;
1166   } viewport;
1167
1168   GLuint pad0[2];
1169
1170   struct {
1171      GLfloat xmin;
1172      GLfloat xmax;
1173      GLfloat ymin;
1174      GLfloat ymax;
1175   } guardband;
1176
1177   GLfloat pad1[4];
1178};
1179
1180/* Documented in the subsystem/shared-functions/sampler chapter...
1181 */
1182struct brw_surface_state
1183{
1184   struct {
1185      GLuint cube_pos_z:1;
1186      GLuint cube_neg_z:1;
1187      GLuint cube_pos_y:1;
1188      GLuint cube_neg_y:1;
1189      GLuint cube_pos_x:1;
1190      GLuint cube_neg_x:1;
1191      GLuint pad:2;
1192      /* Required on gen6 for surfaces accessed through render cache messages.
1193       */
1194      GLuint render_cache_read_write:1;
1195      /* Ironlake and newer: instead of replicating one of the texels */
1196      GLuint cube_corner_average:1;
1197      GLuint mipmap_layout_mode:1;
1198      GLuint vert_line_stride_ofs:1;
1199      GLuint vert_line_stride:1;
1200      GLuint color_blend:1;
1201      GLuint writedisable_blue:1;
1202      GLuint writedisable_green:1;
1203      GLuint writedisable_red:1;
1204      GLuint writedisable_alpha:1;
1205      GLuint surface_format:9;     /**< BRW_SURFACEFORMAT_x */
1206      GLuint data_return_format:1;
1207      GLuint pad0:1;
1208      GLuint surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
1209   } ss0;
1210
1211   struct {
1212      GLuint base_addr;
1213   } ss1;
1214
1215   struct {
1216      GLuint pad:2;
1217      GLuint mip_count:4;
1218      GLuint width:13;
1219      GLuint height:13;
1220   } ss2;
1221
1222   struct {
1223      GLuint tile_walk:1;
1224      GLuint tiled_surface:1;
1225      GLuint pad:1;
1226      GLuint pitch:18;
1227      GLuint depth:11;
1228   } ss3;
1229
1230   struct {
1231      GLuint multisample_position_palette_index:3;
1232      GLuint pad1:1;
1233      GLuint num_multisamples:3;
1234      GLuint pad0:1;
1235      GLuint render_target_view_extent:9;
1236      GLuint min_array_elt:11;
1237      GLuint min_lod:4;
1238   } ss4;
1239
1240   struct {
1241      GLuint pad1:16;
1242      GLuint cache_control:2;
1243      GLuint gfdt:1;
1244      GLuint encrypt:1;
1245      GLuint y_offset:4;
1246      GLuint pad0:1;
1247      GLuint x_offset:7;
1248   } ss5;   /* New in G4X */
1249
1250};
1251
1252
1253struct brw_vertex_element_state
1254{
1255   struct
1256   {
1257      GLuint src_offset:11;
1258      GLuint pad:5;
1259      GLuint src_format:9;
1260      GLuint pad0:1;
1261      GLuint valid:1;
1262      GLuint vertex_buffer_index:5;
1263   } ve0;
1264
1265   struct
1266   {
1267      GLuint dst_offset:8;
1268      GLuint pad:8;
1269      GLuint vfcomponent3:4;
1270      GLuint vfcomponent2:4;
1271      GLuint vfcomponent1:4;
1272      GLuint vfcomponent0:4;
1273   } ve1;
1274};
1275
1276#define BRW_VEP_MAX 18
1277
1278struct brw_vertex_element_packet {
1279   struct header header;
1280   struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */
1281};
1282
1283
1284struct brw_urb_immediate {
1285   GLuint opcode:4;
1286   GLuint offset:6;
1287   GLuint swizzle_control:2;
1288   GLuint pad:1;
1289   GLuint allocate:1;
1290   GLuint used:1;
1291   GLuint complete:1;
1292   GLuint response_length:4;
1293   GLuint msg_length:4;
1294   GLuint msg_target:4;
1295   GLuint pad1:3;
1296   GLuint end_of_thread:1;
1297};
1298
1299/* Instruction format for the execution units:
1300 */
1301
1302struct brw_instruction
1303{
1304   struct
1305   {
1306      GLuint opcode:7;
1307      GLuint pad:1;
1308      GLuint access_mode:1;
1309      GLuint mask_control:1;
1310      GLuint dependency_control:2;
1311      GLuint compression_control:2; /* gen6: quater control */
1312      GLuint thread_control:2;
1313      GLuint predicate_control:4;
1314      GLuint predicate_inverse:1;
1315      GLuint execution_size:3;
1316      GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
1317      GLuint acc_wr_control:1;
1318      GLuint cmpt_control:1;
1319      GLuint debug_control:1;
1320      GLuint saturate:1;
1321   } header;
1322
1323   union {
1324      struct
1325      {
1326	 GLuint dest_reg_file:2;
1327	 GLuint dest_reg_type:3;
1328	 GLuint src0_reg_file:2;
1329	 GLuint src0_reg_type:3;
1330	 GLuint src1_reg_file:2;
1331	 GLuint src1_reg_type:3;
1332	 GLuint pad:1;
1333	 GLuint dest_subreg_nr:5;
1334	 GLuint dest_reg_nr:8;
1335	 GLuint dest_horiz_stride:2;
1336	 GLuint dest_address_mode:1;
1337      } da1;
1338
1339      struct
1340      {
1341	 GLuint dest_reg_file:2;
1342	 GLuint dest_reg_type:3;
1343	 GLuint src0_reg_file:2;
1344	 GLuint src0_reg_type:3;
1345	 GLuint src1_reg_file:2;        /* 0x00000c00 */
1346	 GLuint src1_reg_type:3;        /* 0x00007000 */
1347	 GLuint pad:1;
1348	 GLint dest_indirect_offset:10;	/* offset against the deref'd address reg */
1349	 GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
1350	 GLuint dest_horiz_stride:2;
1351	 GLuint dest_address_mode:1;
1352      } ia1;
1353
1354      struct
1355      {
1356	 GLuint dest_reg_file:2;
1357	 GLuint dest_reg_type:3;
1358	 GLuint src0_reg_file:2;
1359	 GLuint src0_reg_type:3;
1360	 GLuint src1_reg_file:2;
1361	 GLuint src1_reg_type:3;
1362	 GLuint pad:1;
1363	 GLuint dest_writemask:4;
1364	 GLuint dest_subreg_nr:1;
1365	 GLuint dest_reg_nr:8;
1366	 GLuint dest_horiz_stride:2;
1367	 GLuint dest_address_mode:1;
1368      } da16;
1369
1370      struct
1371      {
1372	 GLuint dest_reg_file:2;
1373	 GLuint dest_reg_type:3;
1374	 GLuint src0_reg_file:2;
1375	 GLuint src0_reg_type:3;
1376	 GLuint pad0:6;
1377	 GLuint dest_writemask:4;
1378	 GLint dest_indirect_offset:6;
1379	 GLuint dest_subreg_nr:3;
1380	 GLuint dest_horiz_stride:2;
1381	 GLuint dest_address_mode:1;
1382      } ia16;
1383
1384      struct {
1385	 GLuint dest_reg_file:2;
1386	 GLuint dest_reg_type:3;
1387	 GLuint src0_reg_file:2;
1388	 GLuint src0_reg_type:3;
1389	 GLuint src1_reg_file:2;
1390	 GLuint src1_reg_type:3;
1391	 GLuint pad:1;
1392
1393	 GLint jump_count:16;
1394      } branch_gen6;
1395   } bits1;
1396
1397
1398   union {
1399      struct
1400      {
1401	 GLuint src0_subreg_nr:5;
1402	 GLuint src0_reg_nr:8;
1403	 GLuint src0_abs:1;
1404	 GLuint src0_negate:1;
1405	 GLuint src0_address_mode:1;
1406	 GLuint src0_horiz_stride:2;
1407	 GLuint src0_width:3;
1408	 GLuint src0_vert_stride:4;
1409	 GLuint flag_reg_nr:1;
1410	 GLuint pad:6;
1411      } da1;
1412
1413      struct
1414      {
1415	 GLint src0_indirect_offset:10;
1416	 GLuint src0_subreg_nr:3;
1417	 GLuint src0_abs:1;
1418	 GLuint src0_negate:1;
1419	 GLuint src0_address_mode:1;
1420	 GLuint src0_horiz_stride:2;
1421	 GLuint src0_width:3;
1422	 GLuint src0_vert_stride:4;
1423	 GLuint flag_reg_nr:1;
1424	 GLuint pad:6;
1425      } ia1;
1426
1427      struct
1428      {
1429	 GLuint src0_swz_x:2;
1430	 GLuint src0_swz_y:2;
1431	 GLuint src0_subreg_nr:1;
1432	 GLuint src0_reg_nr:8;
1433	 GLuint src0_abs:1;
1434	 GLuint src0_negate:1;
1435	 GLuint src0_address_mode:1;
1436	 GLuint src0_swz_z:2;
1437	 GLuint src0_swz_w:2;
1438	 GLuint pad0:1;
1439	 GLuint src0_vert_stride:4;
1440	 GLuint flag_reg_nr:1;
1441	 GLuint pad1:6;
1442      } da16;
1443
1444      struct
1445      {
1446	 GLuint src0_swz_x:2;
1447	 GLuint src0_swz_y:2;
1448	 GLint src0_indirect_offset:6;
1449	 GLuint src0_subreg_nr:3;
1450	 GLuint src0_abs:1;
1451	 GLuint src0_negate:1;
1452	 GLuint src0_address_mode:1;
1453	 GLuint src0_swz_z:2;
1454	 GLuint src0_swz_w:2;
1455	 GLuint pad0:1;
1456	 GLuint src0_vert_stride:4;
1457	 GLuint flag_reg_nr:1;
1458	 GLuint pad1:6;
1459      } ia16;
1460
1461       struct
1462       {
1463           GLuint pad:26;
1464           GLuint end_of_thread:1;
1465           GLuint pad1:1;
1466           GLuint sfid:4;
1467       } send_gen5;  /* for Ironlake only */
1468
1469   } bits2;
1470
1471   union
1472   {
1473      struct
1474      {
1475	 GLuint src1_subreg_nr:5;
1476	 GLuint src1_reg_nr:8;
1477	 GLuint src1_abs:1;
1478	 GLuint src1_negate:1;
1479	 GLuint src1_address_mode:1;
1480	 GLuint src1_horiz_stride:2;
1481	 GLuint src1_width:3;
1482	 GLuint src1_vert_stride:4;
1483	 GLuint pad0:7;
1484      } da1;
1485
1486      struct
1487      {
1488	 GLuint src1_swz_x:2;
1489	 GLuint src1_swz_y:2;
1490	 GLuint src1_subreg_nr:1;
1491	 GLuint src1_reg_nr:8;
1492	 GLuint src1_abs:1;
1493	 GLuint src1_negate:1;
1494	 GLuint src1_address_mode:1;
1495	 GLuint src1_swz_z:2;
1496	 GLuint src1_swz_w:2;
1497	 GLuint pad1:1;
1498	 GLuint src1_vert_stride:4;
1499	 GLuint pad2:7;
1500      } da16;
1501
1502      struct
1503      {
1504	 GLint  src1_indirect_offset:10;
1505	 GLuint src1_subreg_nr:3;
1506	 GLuint src1_abs:1;
1507	 GLuint src1_negate:1;
1508	 GLuint src1_address_mode:1;
1509	 GLuint src1_horiz_stride:2;
1510	 GLuint src1_width:3;
1511	 GLuint src1_vert_stride:4;
1512	 GLuint flag_reg_nr:1;
1513	 GLuint pad1:6;
1514      } ia1;
1515
1516      struct
1517      {
1518	 GLuint src1_swz_x:2;
1519	 GLuint src1_swz_y:2;
1520	 GLint  src1_indirect_offset:6;
1521	 GLuint src1_subreg_nr:3;
1522	 GLuint src1_abs:1;
1523	 GLuint src1_negate:1;
1524	 GLuint pad0:1;
1525	 GLuint src1_swz_z:2;
1526	 GLuint src1_swz_w:2;
1527	 GLuint pad1:1;
1528	 GLuint src1_vert_stride:4;
1529	 GLuint flag_reg_nr:1;
1530	 GLuint pad2:6;
1531      } ia16;
1532
1533
1534      struct
1535      {
1536	 GLint  jump_count:16;	/* note: signed */
1537	 GLuint  pop_count:4;
1538	 GLuint  pad0:12;
1539      } if_else;
1540
1541      struct
1542      {
1543	 /* Signed jump distance to the ip to jump to if all channels
1544	  * are disabled after the break or continue.  It should point
1545	  * to the end of the innermost control flow block, as that's
1546	  * where some channel could get re-enabled.
1547	  */
1548	 int jip:16;
1549
1550	 /* Signed jump distance to the location to resume execution
1551	  * of this channel if it's enabled for the break or continue.
1552	  */
1553	 int uip:16;
1554      } break_cont;
1555
1556      struct {
1557	 GLuint function:4;
1558	 GLuint int_type:1;
1559	 GLuint precision:1;
1560	 GLuint saturate:1;
1561	 GLuint data_type:1;
1562	 GLuint pad0:8;
1563	 GLuint response_length:4;
1564	 GLuint msg_length:4;
1565	 GLuint msg_target:4;
1566	 GLuint pad1:3;
1567	 GLuint end_of_thread:1;
1568      } math;
1569
1570      struct {
1571	 GLuint function:4;
1572	 GLuint int_type:1;
1573	 GLuint precision:1;
1574	 GLuint saturate:1;
1575	 GLuint data_type:1;
1576	 GLuint snapshot:1;
1577	 GLuint pad0:10;
1578	 GLuint header_present:1;
1579	 GLuint response_length:5;
1580	 GLuint msg_length:4;
1581	 GLuint pad1:2;
1582	 GLuint end_of_thread:1;
1583      } math_gen5;
1584
1585      struct {
1586	 GLuint binding_table_index:8;
1587	 GLuint sampler:4;
1588	 GLuint return_format:2;
1589	 GLuint msg_type:2;
1590	 GLuint response_length:4;
1591	 GLuint msg_length:4;
1592	 GLuint msg_target:4;
1593	 GLuint pad1:3;
1594	 GLuint end_of_thread:1;
1595      } sampler;
1596
1597      struct {
1598         GLuint binding_table_index:8;
1599         GLuint sampler:4;
1600         GLuint msg_type:4;
1601         GLuint response_length:4;
1602         GLuint msg_length:4;
1603         GLuint msg_target:4;
1604         GLuint pad1:3;
1605         GLuint end_of_thread:1;
1606      } sampler_g4x;
1607
1608      struct {
1609	 GLuint binding_table_index:8;
1610	 GLuint sampler:4;
1611	 GLuint msg_type:4;
1612	 GLuint simd_mode:2;
1613	 GLuint pad0:1;
1614	 GLuint header_present:1;
1615	 GLuint response_length:5;
1616	 GLuint msg_length:4;
1617	 GLuint pad1:2;
1618	 GLuint end_of_thread:1;
1619      } sampler_gen5;
1620
1621      struct brw_urb_immediate urb;
1622
1623      struct {
1624	 GLuint opcode:4;
1625	 GLuint offset:6;
1626	 GLuint swizzle_control:2;
1627	 GLuint pad:1;
1628	 GLuint allocate:1;
1629	 GLuint used:1;
1630	 GLuint complete:1;
1631	 GLuint pad0:3;
1632	 GLuint header_present:1;
1633	 GLuint response_length:5;
1634	 GLuint msg_length:4;
1635	 GLuint pad1:2;
1636	 GLuint end_of_thread:1;
1637      } urb_gen5;
1638
1639      struct {
1640	 GLuint opcode:3;
1641	 GLuint offset:11;
1642	 GLuint swizzle_control:1;
1643	 GLuint complete:1;
1644	 GLuint per_slot_offset:1;
1645	 GLuint pad0:2;
1646	 GLuint header_present:1;
1647	 GLuint response_length:5;
1648	 GLuint msg_length:4;
1649	 GLuint pad1:2;
1650	 GLuint end_of_thread:1;
1651      } urb_gen7;
1652
1653      struct {
1654	 GLuint binding_table_index:8;
1655	 GLuint msg_control:4;
1656	 GLuint msg_type:2;
1657	 GLuint target_cache:2;
1658	 GLuint response_length:4;
1659	 GLuint msg_length:4;
1660	 GLuint msg_target:4;
1661	 GLuint pad1:3;
1662	 GLuint end_of_thread:1;
1663      } dp_read;
1664
1665      struct {
1666	 GLuint binding_table_index:8;
1667	 GLuint msg_control:3;
1668	 GLuint msg_type:3;
1669	 GLuint target_cache:2;
1670	 GLuint response_length:4;
1671	 GLuint msg_length:4;
1672	 GLuint msg_target:4;
1673	 GLuint pad1:3;
1674	 GLuint end_of_thread:1;
1675      } dp_read_g4x;
1676
1677      struct {
1678	 GLuint binding_table_index:8;
1679	 GLuint msg_control:3;
1680	 GLuint msg_type:3;
1681	 GLuint target_cache:2;
1682	 GLuint pad0:3;
1683	 GLuint header_present:1;
1684	 GLuint response_length:5;
1685	 GLuint msg_length:4;
1686	 GLuint pad1:2;
1687	 GLuint end_of_thread:1;
1688      } dp_read_gen5;
1689
1690      struct {
1691	 GLuint binding_table_index:8;
1692	 GLuint msg_control:3;
1693	 GLuint pixel_scoreboard_clear:1;
1694	 GLuint msg_type:3;
1695	 GLuint send_commit_msg:1;
1696	 GLuint response_length:4;
1697	 GLuint msg_length:4;
1698	 GLuint msg_target:4;
1699	 GLuint pad1:3;
1700	 GLuint end_of_thread:1;
1701      } dp_write;
1702
1703      struct {
1704	 GLuint binding_table_index:8;
1705	 GLuint msg_control:3;
1706	 GLuint pixel_scoreboard_clear:1;
1707	 GLuint msg_type:3;
1708	 GLuint send_commit_msg:1;
1709	 GLuint pad0:3;
1710	 GLuint header_present:1;
1711	 GLuint response_length:5;
1712	 GLuint msg_length:4;
1713	 GLuint pad1:2;
1714	 GLuint end_of_thread:1;
1715      } dp_write_gen5;
1716
1717      /* Sandybridge DP for sample cache, constant cache, render cache */
1718      struct {
1719	 GLuint binding_table_index:8;
1720	 GLuint msg_control:5;
1721	 GLuint msg_type:3;
1722	 GLuint pad0:3;
1723	 GLuint header_present:1;
1724	 GLuint response_length:5;
1725	 GLuint msg_length:4;
1726	 GLuint pad1:2;
1727	 GLuint end_of_thread:1;
1728      } dp_sampler_const_cache;
1729
1730      struct {
1731	 GLuint binding_table_index:8;
1732	 GLuint msg_control:3;
1733	 GLuint slot_group_select:1;
1734	 GLuint pixel_scoreboard_clear:1;
1735	 GLuint msg_type:4;
1736	 GLuint send_commit_msg:1;
1737	 GLuint pad0:1;
1738	 GLuint header_present:1;
1739	 GLuint response_length:5;
1740	 GLuint msg_length:4;
1741	 GLuint pad1:2;
1742	 GLuint end_of_thread:1;
1743      } gen6_dp;
1744
1745      /* See volume vol5c.2 sections 2.11.2.1.5 and 2.11.21.2.2. */
1746      struct {
1747	 GLuint binding_table_index:8;
1748	 GLuint msg_control:3;
1749	 GLuint slot_group_select:1;
1750	 GLuint pixel_scoreboard_clear:1;
1751	 GLuint pad0:1;
1752	 GLuint msg_type:4;
1753	 GLuint pad1:1;
1754	 GLuint header_present:1;
1755	 GLuint response_length:5;
1756	 GLuint msg_length:4;
1757	 GLuint pad2:2;
1758	 GLuint end_of_thread:1;
1759      } gen7_dp;
1760
1761      struct {
1762	 GLuint function_control:16;
1763	 GLuint response_length:4;
1764	 GLuint msg_length:4;
1765	 GLuint msg_target:4;
1766	 GLuint pad1:3;
1767	 GLuint end_of_thread:1;
1768      } generic;
1769
1770      /* Of this struct, only end_of_thread is not present for gen6. */
1771      struct {
1772	 GLuint function_control:19;
1773	 GLuint header_present:1;
1774	 GLuint response_length:5;
1775	 GLuint msg_length:4;
1776	 GLuint pad1:2;
1777	 GLuint end_of_thread:1;
1778      } generic_gen5;
1779
1780      GLint d;
1781      GLuint ud;
1782      float f;
1783   } bits3;
1784};
1785
1786
1787#endif
1788