brw_vec4_emit.cpp revision 259b65e2e7938de4aab323033cfe2b33369ddb07
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28#include "main/macros.h" 29}; 30 31using namespace brw; 32 33namespace brw { 34 35int 36vec4_visitor::setup_attributes(int payload_reg) 37{ 38 int nr_attributes; 39 int attribute_map[VERT_ATTRIB_MAX + 1]; 40 41 nr_attributes = 0; 42 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 43 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 44 attribute_map[i] = payload_reg + nr_attributes; 45 nr_attributes++; 46 } 47 } 48 49 /* VertexID is stored by the VF as the last vertex element, but we 50 * don't represent it with a flag in inputs_read, so we call it 51 * VERT_ATTRIB_MAX. 52 */ 53 if (prog_data->uses_vertexid) { 54 attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes; 55 nr_attributes++; 56 } 57 58 foreach_list(node, &this->instructions) { 59 vec4_instruction *inst = (vec4_instruction *)node; 60 61 /* We have to support ATTR as a destination for GL_FIXED fixup. */ 62 if (inst->dst.file == ATTR) { 63 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; 64 65 struct brw_reg reg = brw_vec8_grf(grf, 0); 66 reg.dw1.bits.writemask = inst->dst.writemask; 67 68 inst->dst.file = HW_REG; 69 inst->dst.fixed_hw_reg = reg; 70 } 71 72 for (int i = 0; i < 3; i++) { 73 if (inst->src[i].file != ATTR) 74 continue; 75 76 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 77 78 struct brw_reg reg = brw_vec8_grf(grf, 0); 79 reg.dw1.bits.swizzle = inst->src[i].swizzle; 80 reg.type = inst->src[i].type; 81 if (inst->src[i].abs) 82 reg = brw_abs(reg); 83 if (inst->src[i].negate) 84 reg = negate(reg); 85 86 inst->src[i].file = HW_REG; 87 inst->src[i].fixed_hw_reg = reg; 88 } 89 } 90 91 /* The BSpec says we always have to read at least one thing from 92 * the VF, and it appears that the hardware wedges otherwise. 93 */ 94 if (nr_attributes == 0) 95 nr_attributes = 1; 96 97 prog_data->urb_read_length = (nr_attributes + 1) / 2; 98 99 unsigned vue_entries = MAX2(nr_attributes, c->vue_map.num_slots); 100 101 if (intel->gen == 6) 102 c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8; 103 else 104 c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4; 105 106 return payload_reg + nr_attributes; 107} 108 109int 110vec4_visitor::setup_uniforms(int reg) 111{ 112 /* The pre-gen6 VS requires that some push constants get loaded no 113 * matter what, or the GPU would hang. 114 */ 115 if (intel->gen < 6 && this->uniforms == 0) { 116 this->uniform_vector_size[this->uniforms] = 1; 117 118 for (unsigned int i = 0; i < 4; i++) { 119 unsigned int slot = this->uniforms * 4 + i; 120 static float zero = 0.0; 121 c->prog_data.param[slot] = &zero; 122 } 123 124 this->uniforms++; 125 reg++; 126 } else { 127 reg += ALIGN(uniforms, 2) / 2; 128 } 129 130 c->prog_data.nr_params = this->uniforms * 4; 131 132 c->prog_data.curb_read_length = reg - 1; 133 c->prog_data.uses_new_param_layout = true; 134 135 return reg; 136} 137 138void 139vec4_visitor::setup_payload(void) 140{ 141 int reg = 0; 142 143 /* The payload always contains important data in g0, which contains 144 * the URB handles that are passed on to the URB write at the end 145 * of the thread. So, we always start push constants at g1. 146 */ 147 reg++; 148 149 reg = setup_uniforms(reg); 150 151 reg = setup_attributes(reg); 152 153 this->first_non_payload_grf = reg; 154} 155 156struct brw_reg 157vec4_instruction::get_dst(void) 158{ 159 struct brw_reg brw_reg; 160 161 switch (dst.file) { 162 case GRF: 163 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 164 brw_reg = retype(brw_reg, dst.type); 165 brw_reg.dw1.bits.writemask = dst.writemask; 166 break; 167 168 case MRF: 169 brw_reg = brw_message_reg(dst.reg + dst.reg_offset); 170 brw_reg = retype(brw_reg, dst.type); 171 brw_reg.dw1.bits.writemask = dst.writemask; 172 break; 173 174 case HW_REG: 175 brw_reg = dst.fixed_hw_reg; 176 break; 177 178 case BAD_FILE: 179 brw_reg = brw_null_reg(); 180 break; 181 182 default: 183 assert(!"not reached"); 184 brw_reg = brw_null_reg(); 185 break; 186 } 187 return brw_reg; 188} 189 190struct brw_reg 191vec4_instruction::get_src(int i) 192{ 193 struct brw_reg brw_reg; 194 195 switch (src[i].file) { 196 case GRF: 197 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 198 brw_reg = retype(brw_reg, src[i].type); 199 brw_reg.dw1.bits.swizzle = src[i].swizzle; 200 if (src[i].abs) 201 brw_reg = brw_abs(brw_reg); 202 if (src[i].negate) 203 brw_reg = negate(brw_reg); 204 break; 205 206 case IMM: 207 switch (src[i].type) { 208 case BRW_REGISTER_TYPE_F: 209 brw_reg = brw_imm_f(src[i].imm.f); 210 break; 211 case BRW_REGISTER_TYPE_D: 212 brw_reg = brw_imm_d(src[i].imm.i); 213 break; 214 case BRW_REGISTER_TYPE_UD: 215 brw_reg = brw_imm_ud(src[i].imm.u); 216 break; 217 default: 218 assert(!"not reached"); 219 brw_reg = brw_null_reg(); 220 break; 221 } 222 break; 223 224 case UNIFORM: 225 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 226 ((src[i].reg + src[i].reg_offset) % 2) * 4), 227 0, 4, 1); 228 brw_reg = retype(brw_reg, src[i].type); 229 brw_reg.dw1.bits.swizzle = src[i].swizzle; 230 if (src[i].abs) 231 brw_reg = brw_abs(brw_reg); 232 if (src[i].negate) 233 brw_reg = negate(brw_reg); 234 235 /* This should have been moved to pull constants. */ 236 assert(!src[i].reladdr); 237 break; 238 239 case HW_REG: 240 brw_reg = src[i].fixed_hw_reg; 241 break; 242 243 case BAD_FILE: 244 /* Probably unused. */ 245 brw_reg = brw_null_reg(); 246 break; 247 case ATTR: 248 default: 249 assert(!"not reached"); 250 brw_reg = brw_null_reg(); 251 break; 252 } 253 254 return brw_reg; 255} 256 257void 258vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 259 struct brw_reg dst, 260 struct brw_reg src) 261{ 262 brw_math(p, 263 dst, 264 brw_math_function(inst->opcode), 265 BRW_MATH_SATURATE_NONE, 266 inst->base_mrf, 267 src, 268 BRW_MATH_DATA_VECTOR, 269 BRW_MATH_PRECISION_FULL); 270} 271 272static void 273check_gen6_math_src_arg(struct brw_reg src) 274{ 275 /* Source swizzles are ignored. */ 276 assert(!src.abs); 277 assert(!src.negate); 278 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW); 279} 280 281void 282vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 283 struct brw_reg dst, 284 struct brw_reg src) 285{ 286 /* Can't do writemask because math can't be align16. */ 287 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 288 check_gen6_math_src_arg(src); 289 290 brw_set_access_mode(p, BRW_ALIGN_1); 291 brw_math(p, 292 dst, 293 brw_math_function(inst->opcode), 294 BRW_MATH_SATURATE_NONE, 295 inst->base_mrf, 296 src, 297 BRW_MATH_DATA_SCALAR, 298 BRW_MATH_PRECISION_FULL); 299 brw_set_access_mode(p, BRW_ALIGN_16); 300} 301 302void 303vec4_visitor::generate_math2_gen7(vec4_instruction *inst, 304 struct brw_reg dst, 305 struct brw_reg src0, 306 struct brw_reg src1) 307{ 308 brw_math2(p, 309 dst, 310 brw_math_function(inst->opcode), 311 src0, src1); 312} 313 314void 315vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 316 struct brw_reg dst, 317 struct brw_reg src0, 318 struct brw_reg src1) 319{ 320 /* Can't do writemask because math can't be align16. */ 321 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 322 /* Source swizzles are ignored. */ 323 check_gen6_math_src_arg(src0); 324 check_gen6_math_src_arg(src1); 325 326 brw_set_access_mode(p, BRW_ALIGN_1); 327 brw_math2(p, 328 dst, 329 brw_math_function(inst->opcode), 330 src0, src1); 331 brw_set_access_mode(p, BRW_ALIGN_16); 332} 333 334void 335vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 336 struct brw_reg dst, 337 struct brw_reg src0, 338 struct brw_reg src1) 339{ 340 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13 341 * "Message Payload": 342 * 343 * "Operand0[7]. For the INT DIV functions, this operand is the 344 * denominator." 345 * ... 346 * "Operand1[7]. For the INT DIV functions, this operand is the 347 * numerator." 348 */ 349 bool is_int_div = inst->opcode != SHADER_OPCODE_POW; 350 struct brw_reg &op0 = is_int_div ? src1 : src0; 351 struct brw_reg &op1 = is_int_div ? src0 : src1; 352 353 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); 354 355 brw_math(p, 356 dst, 357 brw_math_function(inst->opcode), 358 BRW_MATH_SATURATE_NONE, 359 inst->base_mrf, 360 op0, 361 BRW_MATH_DATA_VECTOR, 362 BRW_MATH_PRECISION_FULL); 363} 364 365void 366vec4_visitor::generate_tex(vec4_instruction *inst, 367 struct brw_reg dst, 368 struct brw_reg src) 369{ 370 int msg_type = -1; 371 372 if (intel->gen >= 5) { 373 switch (inst->opcode) { 374 case SHADER_OPCODE_TEX: 375 case SHADER_OPCODE_TXL: 376 if (inst->shadow_compare) { 377 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; 378 } else { 379 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; 380 } 381 break; 382 case SHADER_OPCODE_TXD: 383 /* There is no sample_d_c message; comparisons are done manually. */ 384 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; 385 break; 386 case SHADER_OPCODE_TXF: 387 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; 388 break; 389 case SHADER_OPCODE_TXS: 390 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; 391 break; 392 default: 393 assert(!"should not get here: invalid VS texture opcode"); 394 break; 395 } 396 } else { 397 switch (inst->opcode) { 398 case SHADER_OPCODE_TEX: 399 case SHADER_OPCODE_TXL: 400 if (inst->shadow_compare) { 401 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE; 402 assert(inst->mlen == 3); 403 } else { 404 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD; 405 assert(inst->mlen == 2); 406 } 407 break; 408 case SHADER_OPCODE_TXD: 409 /* There is no sample_d_c message; comparisons are done manually. */ 410 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS; 411 assert(inst->mlen == 4); 412 break; 413 case SHADER_OPCODE_TXF: 414 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD; 415 assert(inst->mlen == 2); 416 break; 417 case SHADER_OPCODE_TXS: 418 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO; 419 assert(inst->mlen == 2); 420 break; 421 default: 422 assert(!"should not get here: invalid VS texture opcode"); 423 break; 424 } 425 } 426 427 assert(msg_type != -1); 428 429 /* Load the message header if present. If there's a texture offset, we need 430 * to set it up explicitly and load the offset bitfield. Otherwise, we can 431 * use an implied move from g0 to the first message register. 432 */ 433 if (inst->texture_offset) { 434 /* Explicitly set up the message header by copying g0 to the MRF. */ 435 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD), 436 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); 437 438 /* Then set the offset bits in DWord 2. */ 439 brw_set_access_mode(p, BRW_ALIGN_1); 440 brw_MOV(p, 441 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2), 442 BRW_REGISTER_TYPE_UD), 443 brw_imm_uw(inst->texture_offset)); 444 brw_set_access_mode(p, BRW_ALIGN_16); 445 } else if (inst->header_present) { 446 /* Set up an implied move from g0 to the MRF. */ 447 src = brw_vec8_grf(0, 0); 448 } 449 450 uint32_t return_format; 451 452 switch (dst.type) { 453 case BRW_REGISTER_TYPE_D: 454 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32; 455 break; 456 case BRW_REGISTER_TYPE_UD: 457 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; 458 break; 459 default: 460 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; 461 break; 462 } 463 464 brw_SAMPLE(p, 465 dst, 466 inst->base_mrf, 467 src, 468 SURF_INDEX_TEXTURE(inst->sampler), 469 inst->sampler, 470 WRITEMASK_XYZW, 471 msg_type, 472 1, /* response length */ 473 inst->mlen, 474 inst->header_present, 475 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 476 return_format); 477} 478 479void 480vec4_visitor::generate_urb_write(vec4_instruction *inst) 481{ 482 brw_urb_WRITE(p, 483 brw_null_reg(), /* dest */ 484 inst->base_mrf, /* starting mrf reg nr */ 485 brw_vec8_grf(0, 0), /* src */ 486 false, /* allocate */ 487 true, /* used */ 488 inst->mlen, 489 0, /* response len */ 490 inst->eot, /* eot */ 491 inst->eot, /* writes complete */ 492 inst->offset, /* urb destination offset */ 493 BRW_URB_SWIZZLE_INTERLEAVE); 494} 495 496void 497vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 498 struct brw_reg index) 499{ 500 int second_vertex_offset; 501 502 if (intel->gen >= 6) 503 second_vertex_offset = 1; 504 else 505 second_vertex_offset = 16; 506 507 m1 = retype(m1, BRW_REGISTER_TYPE_D); 508 509 /* Set up M1 (message payload). Only the block offsets in M1.0 and 510 * M1.4 are used, and the rest are ignored. 511 */ 512 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 513 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 514 struct brw_reg index_0 = suboffset(vec1(index), 0); 515 struct brw_reg index_4 = suboffset(vec1(index), 4); 516 517 brw_push_insn_state(p); 518 brw_set_mask_control(p, BRW_MASK_DISABLE); 519 brw_set_access_mode(p, BRW_ALIGN_1); 520 521 brw_MOV(p, m1_0, index_0); 522 523 brw_set_predicate_inverse(p, true); 524 if (index.file == BRW_IMMEDIATE_VALUE) { 525 index_4.dw1.ud += second_vertex_offset; 526 brw_MOV(p, m1_4, index_4); 527 } else { 528 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 529 } 530 531 brw_pop_insn_state(p); 532} 533 534void 535vec4_visitor::generate_scratch_read(vec4_instruction *inst, 536 struct brw_reg dst, 537 struct brw_reg index) 538{ 539 struct brw_reg header = brw_vec8_grf(0, 0); 540 541 gen6_resolve_implied_move(p, &header, inst->base_mrf); 542 543 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 544 index); 545 546 uint32_t msg_type; 547 548 if (intel->gen >= 6) 549 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 550 else if (intel->gen == 5 || intel->is_g4x) 551 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 552 else 553 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 554 555 /* Each of the 8 channel enables is considered for whether each 556 * dword is written. 557 */ 558 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 559 brw_set_dest(p, send, dst); 560 brw_set_src0(p, send, header); 561 if (intel->gen < 6) 562 send->header.destreg__conditionalmod = inst->base_mrf; 563 brw_set_dp_read_message(p, send, 564 255, /* binding table index: stateless access */ 565 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 566 msg_type, 567 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 568 2, /* mlen */ 569 1 /* rlen */); 570} 571 572void 573vec4_visitor::generate_scratch_write(vec4_instruction *inst, 574 struct brw_reg dst, 575 struct brw_reg src, 576 struct brw_reg index) 577{ 578 struct brw_reg header = brw_vec8_grf(0, 0); 579 bool write_commit; 580 581 /* If the instruction is predicated, we'll predicate the send, not 582 * the header setup. 583 */ 584 brw_set_predicate_control(p, false); 585 586 gen6_resolve_implied_move(p, &header, inst->base_mrf); 587 588 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 589 index); 590 591 brw_MOV(p, 592 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 593 retype(src, BRW_REGISTER_TYPE_D)); 594 595 uint32_t msg_type; 596 597 if (intel->gen >= 7) 598 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 599 else if (intel->gen == 6) 600 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 601 else 602 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 603 604 brw_set_predicate_control(p, inst->predicate); 605 606 /* Pre-gen6, we have to specify write commits to ensure ordering 607 * between reads and writes within a thread. Afterwards, that's 608 * guaranteed and write commits only matter for inter-thread 609 * synchronization. 610 */ 611 if (intel->gen >= 6) { 612 write_commit = false; 613 } else { 614 /* The visitor set up our destination register to be g0. This 615 * means that when the next read comes along, we will end up 616 * reading from g0 and causing a block on the write commit. For 617 * write-after-read, we are relying on the value of the previous 618 * read being used (and thus blocking on completion) before our 619 * write is executed. This means we have to be careful in 620 * instruction scheduling to not violate this assumption. 621 */ 622 write_commit = true; 623 } 624 625 /* Each of the 8 channel enables is considered for whether each 626 * dword is written. 627 */ 628 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 629 brw_set_dest(p, send, dst); 630 brw_set_src0(p, send, header); 631 if (intel->gen < 6) 632 send->header.destreg__conditionalmod = inst->base_mrf; 633 brw_set_dp_write_message(p, send, 634 255, /* binding table index: stateless access */ 635 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 636 msg_type, 637 3, /* mlen */ 638 true, /* header present */ 639 false, /* not a render target write */ 640 write_commit, /* rlen */ 641 false, /* eot */ 642 write_commit); 643} 644 645void 646vec4_visitor::generate_pull_constant_load(vec4_instruction *inst, 647 struct brw_reg dst, 648 struct brw_reg index) 649{ 650 if (intel->gen == 7) { 651 gen6_resolve_implied_move(p, &index, inst->base_mrf); 652 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); 653 brw_set_dest(p, insn, dst); 654 brw_set_src0(p, insn, index); 655 brw_set_sampler_message(p, insn, 656 SURF_INDEX_VERT_CONST_BUFFER, 657 0, /* LD message ignores sampler unit */ 658 GEN5_SAMPLER_MESSAGE_SAMPLE_LD, 659 1, /* rlen */ 660 1, /* mlen */ 661 false, /* no header */ 662 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 663 0); 664 return; 665 } 666 667 struct brw_reg header = brw_vec8_grf(0, 0); 668 669 gen6_resolve_implied_move(p, &header, inst->base_mrf); 670 671 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D), 672 index); 673 674 uint32_t msg_type; 675 676 if (intel->gen >= 6) 677 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 678 else if (intel->gen == 5 || intel->is_g4x) 679 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 680 else 681 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 682 683 /* Each of the 8 channel enables is considered for whether each 684 * dword is written. 685 */ 686 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 687 brw_set_dest(p, send, dst); 688 brw_set_src0(p, send, header); 689 if (intel->gen < 6) 690 send->header.destreg__conditionalmod = inst->base_mrf; 691 brw_set_dp_read_message(p, send, 692 SURF_INDEX_VERT_CONST_BUFFER, 693 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 694 msg_type, 695 BRW_DATAPORT_READ_TARGET_DATA_CACHE, 696 2, /* mlen */ 697 1 /* rlen */); 698} 699 700void 701vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 702 struct brw_reg dst, 703 struct brw_reg *src) 704{ 705 vec4_instruction *inst = (vec4_instruction *)instruction; 706 707 switch (inst->opcode) { 708 case SHADER_OPCODE_RCP: 709 case SHADER_OPCODE_RSQ: 710 case SHADER_OPCODE_SQRT: 711 case SHADER_OPCODE_EXP2: 712 case SHADER_OPCODE_LOG2: 713 case SHADER_OPCODE_SIN: 714 case SHADER_OPCODE_COS: 715 if (intel->gen == 6) { 716 generate_math1_gen6(inst, dst, src[0]); 717 } else { 718 /* Also works for Gen7. */ 719 generate_math1_gen4(inst, dst, src[0]); 720 } 721 break; 722 723 case SHADER_OPCODE_POW: 724 case SHADER_OPCODE_INT_QUOTIENT: 725 case SHADER_OPCODE_INT_REMAINDER: 726 if (intel->gen >= 7) { 727 generate_math2_gen7(inst, dst, src[0], src[1]); 728 } else if (intel->gen == 6) { 729 generate_math2_gen6(inst, dst, src[0], src[1]); 730 } else { 731 generate_math2_gen4(inst, dst, src[0], src[1]); 732 } 733 break; 734 735 case SHADER_OPCODE_TEX: 736 case SHADER_OPCODE_TXD: 737 case SHADER_OPCODE_TXF: 738 case SHADER_OPCODE_TXL: 739 case SHADER_OPCODE_TXS: 740 generate_tex(inst, dst, src[0]); 741 break; 742 743 case VS_OPCODE_URB_WRITE: 744 generate_urb_write(inst); 745 break; 746 747 case VS_OPCODE_SCRATCH_READ: 748 generate_scratch_read(inst, dst, src[0]); 749 break; 750 751 case VS_OPCODE_SCRATCH_WRITE: 752 generate_scratch_write(inst, dst, src[0], src[1]); 753 break; 754 755 case VS_OPCODE_PULL_CONSTANT_LOAD: 756 generate_pull_constant_load(inst, dst, src[0]); 757 break; 758 759 default: 760 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 761 fail("unsupported opcode in `%s' in VS\n", 762 brw_opcodes[inst->opcode].name); 763 } else { 764 fail("Unsupported opcode %d in VS", inst->opcode); 765 } 766 } 767} 768 769bool 770vec4_visitor::run() 771{ 772 if (c->key.userclip_active && !c->key.uses_clip_distance) 773 setup_uniform_clipplane_values(); 774 775 /* Generate VS IR for main(). (the visitor only descends into 776 * functions called "main"). 777 */ 778 visit_instructions(shader->ir); 779 780 emit_urb_writes(); 781 782 /* Before any optimization, push array accesses out to scratch 783 * space where we need them to be. This pass may allocate new 784 * virtual GRFs, so we want to do it early. It also makes sure 785 * that we have reladdr computations available for CSE, since we'll 786 * often do repeated subexpressions for those. 787 */ 788 move_grf_array_access_to_scratch(); 789 move_uniform_array_access_to_pull_constants(); 790 pack_uniform_registers(); 791 move_push_constants_to_pull_constants(); 792 793 bool progress; 794 do { 795 progress = false; 796 progress = dead_code_eliminate() || progress; 797 progress = opt_copy_propagation() || progress; 798 progress = opt_algebraic() || progress; 799 progress = opt_compute_to_mrf() || progress; 800 } while (progress); 801 802 803 if (failed) 804 return false; 805 806 setup_payload(); 807 reg_allocate(); 808 809 if (failed) 810 return false; 811 812 brw_set_access_mode(p, BRW_ALIGN_16); 813 814 generate_code(); 815 816 return !failed; 817} 818 819void 820vec4_visitor::generate_code() 821{ 822 int last_native_inst = 0; 823 const char *last_annotation_string = NULL; 824 ir_instruction *last_annotation_ir = NULL; 825 826 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 827 printf("Native code for vertex shader %d:\n", prog->Name); 828 } 829 830 foreach_list(node, &this->instructions) { 831 vec4_instruction *inst = (vec4_instruction *)node; 832 struct brw_reg src[3], dst; 833 834 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 835 if (last_annotation_ir != inst->ir) { 836 last_annotation_ir = inst->ir; 837 if (last_annotation_ir) { 838 printf(" "); 839 last_annotation_ir->print(); 840 printf("\n"); 841 } 842 } 843 if (last_annotation_string != inst->annotation) { 844 last_annotation_string = inst->annotation; 845 if (last_annotation_string) 846 printf(" %s\n", last_annotation_string); 847 } 848 } 849 850 for (unsigned int i = 0; i < 3; i++) { 851 src[i] = inst->get_src(i); 852 } 853 dst = inst->get_dst(); 854 855 brw_set_conditionalmod(p, inst->conditional_mod); 856 brw_set_predicate_control(p, inst->predicate); 857 brw_set_predicate_inverse(p, inst->predicate_inverse); 858 brw_set_saturate(p, inst->saturate); 859 860 switch (inst->opcode) { 861 case BRW_OPCODE_MOV: 862 brw_MOV(p, dst, src[0]); 863 break; 864 case BRW_OPCODE_ADD: 865 brw_ADD(p, dst, src[0], src[1]); 866 break; 867 case BRW_OPCODE_MUL: 868 brw_MUL(p, dst, src[0], src[1]); 869 break; 870 case BRW_OPCODE_MACH: 871 brw_set_acc_write_control(p, 1); 872 brw_MACH(p, dst, src[0], src[1]); 873 brw_set_acc_write_control(p, 0); 874 break; 875 876 case BRW_OPCODE_FRC: 877 brw_FRC(p, dst, src[0]); 878 break; 879 case BRW_OPCODE_RNDD: 880 brw_RNDD(p, dst, src[0]); 881 break; 882 case BRW_OPCODE_RNDE: 883 brw_RNDE(p, dst, src[0]); 884 break; 885 case BRW_OPCODE_RNDZ: 886 brw_RNDZ(p, dst, src[0]); 887 break; 888 889 case BRW_OPCODE_AND: 890 brw_AND(p, dst, src[0], src[1]); 891 break; 892 case BRW_OPCODE_OR: 893 brw_OR(p, dst, src[0], src[1]); 894 break; 895 case BRW_OPCODE_XOR: 896 brw_XOR(p, dst, src[0], src[1]); 897 break; 898 case BRW_OPCODE_NOT: 899 brw_NOT(p, dst, src[0]); 900 break; 901 case BRW_OPCODE_ASR: 902 brw_ASR(p, dst, src[0], src[1]); 903 break; 904 case BRW_OPCODE_SHR: 905 brw_SHR(p, dst, src[0], src[1]); 906 break; 907 case BRW_OPCODE_SHL: 908 brw_SHL(p, dst, src[0], src[1]); 909 break; 910 911 case BRW_OPCODE_CMP: 912 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 913 break; 914 case BRW_OPCODE_SEL: 915 brw_SEL(p, dst, src[0], src[1]); 916 break; 917 918 case BRW_OPCODE_DP4: 919 brw_DP4(p, dst, src[0], src[1]); 920 break; 921 922 case BRW_OPCODE_DP3: 923 brw_DP3(p, dst, src[0], src[1]); 924 break; 925 926 case BRW_OPCODE_DP2: 927 brw_DP2(p, dst, src[0], src[1]); 928 break; 929 930 case BRW_OPCODE_IF: 931 if (inst->src[0].file != BAD_FILE) { 932 /* The instruction has an embedded compare (only allowed on gen6) */ 933 assert(intel->gen == 6); 934 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 935 } else { 936 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 937 brw_inst->header.predicate_control = inst->predicate; 938 } 939 break; 940 941 case BRW_OPCODE_ELSE: 942 brw_ELSE(p); 943 break; 944 case BRW_OPCODE_ENDIF: 945 brw_ENDIF(p); 946 break; 947 948 case BRW_OPCODE_DO: 949 brw_DO(p, BRW_EXECUTE_8); 950 break; 951 952 case BRW_OPCODE_BREAK: 953 brw_BREAK(p); 954 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 955 break; 956 case BRW_OPCODE_CONTINUE: 957 /* FINISHME: We need to write the loop instruction support still. */ 958 if (intel->gen >= 6) 959 gen6_CONT(p); 960 else 961 brw_CONT(p); 962 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 963 break; 964 965 case BRW_OPCODE_WHILE: 966 brw_WHILE(p); 967 break; 968 969 default: 970 generate_vs_instruction(inst, dst, src); 971 break; 972 } 973 974 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 975 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 976 if (0) { 977 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 978 ((uint32_t *)&p->store[i])[3], 979 ((uint32_t *)&p->store[i])[2], 980 ((uint32_t *)&p->store[i])[1], 981 ((uint32_t *)&p->store[i])[0]); 982 } 983 brw_disasm(stdout, &p->store[i], intel->gen); 984 } 985 } 986 987 last_native_inst = p->nr_insn; 988 } 989 990 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 991 printf("\n"); 992 } 993 994 brw_set_uip_jip(p); 995 996 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 997 * emit issues, it doesn't get the jump distances into the output, 998 * which is often something we want to debug. So this is here in 999 * case you're doing that. 1000 */ 1001 if (0) { 1002 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 1003 for (unsigned int i = 0; i < p->nr_insn; i++) { 1004 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 1005 ((uint32_t *)&p->store[i])[3], 1006 ((uint32_t *)&p->store[i])[2], 1007 ((uint32_t *)&p->store[i])[1], 1008 ((uint32_t *)&p->store[i])[0]); 1009 brw_disasm(stdout, &p->store[i], intel->gen); 1010 } 1011 } 1012 } 1013} 1014 1015extern "C" { 1016 1017bool 1018brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 1019{ 1020 if (!prog) 1021 return false; 1022 1023 struct brw_shader *shader = 1024 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 1025 if (!shader) 1026 return false; 1027 1028 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 1029 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 1030 _mesa_print_ir(shader->ir, NULL); 1031 printf("\n\n"); 1032 } 1033 1034 vec4_visitor v(c, prog, shader); 1035 if (!v.run()) { 1036 prog->LinkStatus = false; 1037 ralloc_strcat(&prog->InfoLog, v.fail_msg); 1038 return false; 1039 } 1040 1041 return true; 1042} 1043 1044} /* extern "C" */ 1045 1046} /* namespace brw */ 1047