| 4e35ffa762d763820b7defc14af564b2a02c61c8 |
|
03-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Try again when we've successfully spilled a reg.
Before, we'd spill one reg, then continue on without actually register
allocating, then assertion fail when we tried to use a vgrf number as a
register number.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit d4bcc6591812ebe72a363cf98371de5e5016f481)
This should have been picked when 9237f0e was picked.
Bugzill: https://bugs.freedesktop.org/show_bug.cgi?id=59700
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| d02343e5016a5795451af3e0315b658b39463a30 |
|
04-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use Haswell's sample_d_c for textureGrad with shadow samplers.
The new hardware actually just supports this now.
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 899017fc54c40c969b5239b33f3a17b311878b0d)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| b22de71c1bc2530e139d75d934e203f4eee89f41 |
|
02-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement register spilling.
To validate this code, I ran piglit -t vs quick.tests with the "go spill
everything" debugging code enabled. There was only one regression:
glsl-vs-unroll-explosion simply ran out of registers. This should be
fine in the real world, since no one actually spills every single
register.
NOTE: This is a candidate for the 9.0 branch. Even if it proves to have
bugs, it's likely better than simply failing to compile.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 9237f0ea8d176fb5dcd41868dcc723fe34f6b1f3)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| c20cb8d1f6cac0b98950828e69376bb9406761ff |
|
26-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Add VS program key dumping to INTEL_DEBUG=perf.
Eric added support for WM key debugging. This adds it for the VS.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 43e3a7533d5537e48cef23588131dd25d938ee4b |
|
14-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Fix the scaling of seconds to ms in perf debug.
*headdesk*
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 006c1a3c652803e2ff8d5f7ea55c9cb5d8353279 |
|
07-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add perf debug for stalls during shader compiles.
v2: fix bad comment from before I gave up and decided to just use doubles.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| fc3b7c9b56701f23b002543de33a8d8c43f9bdc2 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add performance debug for shader recompiles.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| b0adbda75a092a92211bb519a395494532ddb17e |
|
07-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Protect pow(x,y) MOV of y on gen4 from other instruction flags.
I don't know if it was possible to trigger this bug -- we don't merge
saturates into the math instruction because we're bad at coalescing currently,
and there's nothing generating these with predicates. Still, let's avoid
future bugs when we do smarter codegen.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 9b4053cabd8bda180b352d2d2047209f6ca5f6e8 |
|
06-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop the confusing saturate argument to math instruction setup.
This was ridiculous. We were ignoring the inst->header.saturate flag in the
case of math and only math. On gen4, we would leave inst->header.saturate in
place if it happened to be set, which would end up being applied to the
implicit mov and thus trash the first argument. On gen6, we would overwrite
inst->header.saturate with the saturate flag from the argument, which was not
set appropriately in brw_vec4_emit.cpp, and was only not a bug due to our
incompetence at coalescing saturate moves.
By ripping the argument out and making saturate work just like all the other
brw_eu_emit.c code generation, we can avoid both these classes of bugs.
Fixes piglit fog-modes, and the new specific fs-saturate-exp2 case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| bb020d09c382285210a5aebe412ddabfad19e4a0 |
|
25-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add a surface index to VS_OPCODE_PULL_CONSTANT instructions.
Similar to the previous commit for the fragment shader, now we have a buffer
index and an offset.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 07e00b3040d6da381595c65db5afe597f20d99fc |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the VS binding table to a separate table.
This is a step toward making the samplers/binding tables reflect
sampler uniform mappings instead of embedding those in the programs.
No significant performance difference on the microbenchmark (n=10).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| f0cecd43d6b6d3f5def3fd43b9c95baaf3be9b16 |
|
13-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Move VUE map computation to once at VS compile time.
With this and the previous patch, 640x480 nexuiz is running 0.169118%
+/- 0.0863696% faster (n=121). On a VS state change microbenchmark,
performance is increased 8.28645% +/- 0.460478% (n=52).
v2: Fix CACHE_NEW_VS comment.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 259b65e2e7938de4aab323033cfe2b33369ddb07 |
|
26-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Use the sampler for VS pull constant loading on Ivybridge.
Substantially increases performance in GLBenchmark PRO:
- 320x240 => 3.28x
- 1920x1080 => 1.47x
- 2560x1440 => 1.27x
The LD message ignores the sampler unit index and SAMPLER_STATE pointer,
instead relying on hard-wired default state. Thus, there's no need to
worry about running out of sampler units or providing SAMPLER_STATE;
this small patch should be all that's required.
NOTE: This is a candidate for release branches.
(It requires the preceding commit to compile.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 2e712e41db0c0676e9f30fc73172c0e8de8d84d4 |
|
18-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Take attributes into account when deciding urb_entry_size.
Both the VF and VS share space in the URB. First, the VF stores
attributes (shader inputs) there. The VS then reads the attributes,
executes, and reuses the space to store varyings (shader outputs).
Thus, we need to calculate the amount of URB space necessary for inputs,
outputs, and pick whichever is greater.
The old VS backend correctly did this (brw_vs_emit.c:408), but the new
VS backend only considered outputs.
Fixes vertex scrambling in GLBenchmark PRO on Ivybridge.
NOTE: This is a candidate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41318
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| f1d89638c02afafbf82ef657cd6ba9965dad6738 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop.
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| ce6be334bbf7f44c71ad5d190f9fb075d2f9a38c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching.
The EU code itself can just do this work, since all the consumers were
duplicating it.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 32118cfe37495738ed5931c6b1a71b8ee2ad189c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 9f8814752f306cb9a26d283f0b7cf876639e10f7 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop unused do_insn argument from gen6_CONT().
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 328b693a199a67ce3a17d258f34d7bfd26790871 |
|
12-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Add support for texel offsets.
The visit() half computes the values to put in the header based on the
IR and simply stuffs that in the vec4_instruction; the emit() half uses
this to set up the message header. This works out well since emit() can
use brw_reg directly and access individual DWords without kludgery.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| ca182cd0fa338ad39d531cb1be6a5a1bbf455771 |
|
26-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement vec4_visitor::generate_tex().
This is the part that takes the vec4_instruction IR and turns it into
actual Gen ISA.
v2: Add Gen4 messages, don't retype m0 to UW.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 1c65abb211e6a3df8c46180ae3242486ee97dc8d |
|
09-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gl_VertexID and gl_InstanceID.
The compiler setup for these VF-uploaded attributes looks a little
cheesy with mixing system values and real VBO-sourced attributes. It
would be nice if we could just compute the ATTR[] map to GRF index up
front and use it at visit time instead of using ir->location in the
ATTR file. However, we don't know the reg_offset at
visit(ir_variable *) time, so we can't do the mapping that early.
Fixes piglit vertexid test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| a73c65c5342bf41fa0dfefe7daa9197ce6a11db4 |
|
18-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable faster workaround-free math on Ivybridge.
According to the documentation, Ivybridge's math instruction works in
SIMD16 mode for the fragment shader, and no longer forbids align16 mode
for the vertex shader.
The documentation claims that SIMD16 mode isn't supported for INT DIV,
but empirical evidence shows that it works fine. Presumably the note
is trying to warn us that the variant that returns both quotient and
remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1
would be sechalf(dst), trashing half your results. Since we don't use
that variant, we don't care and can just enable SIMD16 everywhere.
The documentation also still claims that source modifiers and
conditional modifiers aren't supported, but empirical evidence and
study of the simulator both show that they work just fine.
Goodbye workarounds. Math just works now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 29e2bc8b13be0f7ec48f8514e47322353e041365 |
|
01-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for integral vertex attributes.
When a vertex shader input attribute is declared with an integral type
(e.g. ivec4), we need to ensure that the generated vertex shader code
addresses the vertex attribute register using the proper register
type. (Previously, we assumed all vertex shader input attributes were
floating-point).
In addition, when uploading vertex data that was specified with
VertexAttribIPointer, we need to instruct the vertex fetch unit to
convert the data to signed or unsigned int, rather than float. And
when filling in the implied w=1 on a vector with less than 4
components, we need to fill it in with the integer representation of 1
rather than the floating-point representation of 1.
Fixes piglit tests vs-attrib-{ivec4,uvec4}-precision.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 53798f90e818e9bf213c3ae4298751362a5ecd50 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Finding this bit in the documentation proved challenging. It wasn't in
the SEND instruction's message descriptor section, nor the data port
message descriptor section. It turns out to be part of the Render
Target Write message's control bits, and in the documentation is named
"Last Render Target Select".
Shaders that use Multiple Render Targets should set this bit on the last
RT write, but not on any prior ones.
The GPU does update the Pixel Scoreboard appropriately, but doesn't
document this bit as directly causing a scoreboard clear.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 0d4a9ba9b247664bc5662b3db774064778f9aa17 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use Ivybridge's "Legacy Data Port" for reads/writes.
Using the constant cache for reads isn't going to work for scratch
reads (variably-indexed arrays or register spills), as these aren't
constant at all.
Also, in the new VS backend, use the proper message number for OWord
Dual Block Write messages. It's now 10, instead of 9.
+205 piglits.
NOTE: This is a candidate for the 7.11 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 18e2e19b07b312c978dfbb6d336f69fa84b3ffe2 |
|
27-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Make brw_compute_vue_map's userclip dependency a boolean.
Previously, brw_compute_vue_map required an argument indicating the
number of clip planes in use, but all it did with it was check if it
was nonzero.
This patch changes brw_compute_vue_map to take a boolean instead.
This allows us to avoid some unnecessary recompilation of the Gen4/5
GS and SF threads.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| b9af592dfa8f8d0fe9f29c2d48bf6846cbd5c50f |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Reverse the operands for INT DIV prior to Gen6.
Apparently on Gen4 and 5, the denominator comes first.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 1d4f3ca8f0442821c914b758b323e6e5124149a3 |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement integer quotient and remainder math operations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 8ccbcda5c64a8bea47f6b41d46bf015ba8e515fc |
|
30-Sep-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965/gen6: Fix assign instead of compare in assert
This is from a Coverity defect report.
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
268 static void
269 check_gen6_math_src_arg(struct brw_reg src)
270 {
271 /* Source swizzles are ignored. */
272 assert(!src.abs);
273 assert(!src.negate);
-> 274 assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
275 }
Reported-by: Vinson Lee <vlee@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40214
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| e7da40afe84349a640fe15e3af408a0dfe880e85 |
|
24-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 new VS: don't share clip plane constants in pre-GEN6
In pre-GEN6, when using clip planes, both the vertex shader and the
clipper need access to the client-supplied clip planes, since the
vertex shader needs them to set the clip flags, and the clipper needs
them to determine where to insert new vertices.
With the old VS backend, we used a clever optimization to avoid
placing duplicate copies of these planes in the CURBE: we used the
same block of memory for both the clipper and vertex shader constants,
with the clip planes at the front of it, and then we instructed the
clipper to read just the initial part of this block containing the
clip planes.
This optimization was tricky, of dubious value, and not completely
working in the new VS backend, so I've removed it. Now, when using
the new VS backend, separate parts of the CURBE are used for the
clipper and the vertex shader. Note that this doesn't affect the
number of push constants available to the vertex shader, it simply
causes the CURBE to occupy a few more bytes of URB memory.
The old VS backend is unaffected. GEN6+, which does clipping entirely
in hardware, is also unaffected.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| d9cb683f81b5daefda2f8599b4ba0365cc6f009a |
|
02-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Don't upload clip planes when gl_ClipDistance is in use.
When the vertex shader writes to gl_ClipDistance, we do clipping based
on clip distances rather than user clip planes, so don't waste push
constant space storing user clip planes that won't be used.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| c662764f4f9d9d0303fb2685dfdc93824fa15dca |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for compute-to-MRF.
Removes 1.8% of the instructions from 97% of the vertex shaders in
shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 65d46c96c2540f8181293c318b412446a953faef |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Handle destinations in the MRF file.
We've been referencing MRFs through the HW_REG file so far, but that
makes it harder to handle compute-to-MRF and similar optimizations.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| f0c04e6c22babf2aee2ad1ee85dbd6f996be3712 |
|
03-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for simple algebraic optimizations.
We generate silly code for array access, and it's easier to generally
support the cleanup than to specifically avoid the bad code in each
place we might generate it.
Removes 4.6% of instructions from 41.6% of shaders in shader-db,
particularly savage2/hon and unigine.
v2: Fixes by Ken: Make is_zero/one member functions, and fix a
progress flag.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 42ce13195b94d0d51ca8e7fa5eed07fde8f37988 |
|
30-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add constant propagation to a few opcodes.
This differs from the FS in that we track constants in each
destination channel, and we we have to look at all the swizzled source
channels. Also, the instruction stream walk is done in an O(n) manner
instead of O(n^2).
Across shader-db, this reduces 8.0% of the instructions from 60.0% of
the vertex shaders, leaving us now behind the old backend by 11.1%
overall.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| df35d691807656d3627b6fa6f51a08674bdc043e |
|
07-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for overflowing the number of available push constants.
Fixes glsl-vs-uniform-array-4.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33742
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| f3ed973f53d2a621d915de2cdc8e09c0755db016 |
|
07-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Pack uniform registers before optimization
We don't expect uniform accesses to generally go away from being dead
code at this point, and we will want to have uniforms packed before
spilling them out to pull constants when we are forced to do that.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 9367960ea64a087895caaadbd0353080c14b4bab |
|
31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Use write commits on scratch writes in pre-gen6.
This is required to ensure ordering between reads and writes within a
thread.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| ddf8e602a774ecfd1b660e398dd9bf763d86a074 |
|
31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix message setup for array read/writes on pre-gen6.
We were passing an MRF as the source argument, instead of using the
implied move and putting the MRF number in the proper place in the
instruction encoding.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 88612e2c1b1580b92d229ec6d2236fe07b32e060 |
|
31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix constant-indexed array read/write addresses on pre-gen6.
The second vertex was getting a garbage index.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 9f842886077258ddda5d5a32b1f5d9fe2e5818bc |
|
31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Make pre-gen6 math operate in vector mode instead of scalar.
On the old backend, we used scalar mode because Mesa IR math is
result.xyzw = math(op0.xxxx), which matched up well. However, in GLSL
IR we do things like result.xy = math(op0.xy), so we want vector mode.
For the common case of result.x = math(op0.x), performance will be the
same (no cost for un-executed channels), though result.xyzw =
math(op0.xxxx) would be worse.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 87be0ac96ce5aaea2a08f1ed63871c0dd3a3f9d5 |
|
03-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix copy-and-paste disaster in pre-gen6 POW support.
Fixes vs-pow-float-float and friends.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| ee41383ab31f6ef5f1d18961de78371d4f52065b |
|
30-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Fix NULL pointer dereference in pre-Gen6 push constant loading.
According to the comment, we need to load /some/ push constants on
pre-Gen6 hardware or the GPU will hang. The existing code set these
bogus parameters to NULL pointers; unfortunately, the code in
brw_curbe.c that loads them dereferences those pointers. So, change
them to be pointers to an actual floating point value of 0.0.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 81a0b2166991a3015f8336e184c34cf6a92adfe0 |
|
23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix GL_FIXED setup when a writemask is present.
By emitting code before generate_code(), we ended up in align1 mode
where writemasks don't exist, so we rescaled gl_Vertex.w and things
went badly. By moving GL_FIXED support to the visitor, we end up with
normal codegen, and as a bonus the GL_FIXED setup ends up getting
printed appropriately in debug output.
Fixes gtf/GL2Tests/fixed_data_type
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 72cfc6f3778d8297e52c254a5861a88eb62e4d67 |
|
23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Pack live uniform vectors together in the push constant upload.
At some point we need to also move uniform accesses out to pull
constants when there are just too many in use, but we lack tests for
that at the moment.
Fixes glsl-vs-large-uniform-array.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 483f5b348b0f3c0ca7082fd2047c354e8af285e7 |
|
22-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for pull constant loads for uniform arrays.
v2: reworked the instruction emit and made use of gen6_resolve_implied_move,
from Ken's review
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 55b7fbb70ffc1f4def5c3ded63c3ef569e693731 |
|
19-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use native integer uniforms when the new VS backend is in use.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 8174945d3346dc049ae56dcb4bf1eab39f5c88aa |
|
17-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add simple dead code elimination.
This is copied right from the fragment shader. It is needed for real
register allocation to work correctly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 0ddf0f1c3451eef8a7c7f46afca623dc4f7c5af6 |
|
16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix multiplies to actually do 32-bit multiplies.
Fixes vs-op-mult-int-int and friends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 905f3d03090c7b86e410959c5640054f5f6894ef |
|
12-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Remove remaining use of foreach_iter.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 54e66a0a6327b55f15a7c641ec68da505ff19a35 |
|
12-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix abs/negate handling on attributes.
Fixes glsl-vs-neg-attribute and glsl-vs-abs-attribute.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 7fbe7fe13359d3f349664410ec73d7bd48824ed6 |
|
11-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Run the shader backend at link time and return compile failures.
Link failure is something that shouldn't happen, but we sometimes want
it during development. The precompile also allows analysis of shader
codegen with shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| e8980c61b2932cd4c8791fcc5afdb54fa033c224 |
|
11-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix the trivial register allocator's failure path.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 072d64121e13ad6bcb9b703090de1ee4a59f7096 |
|
10-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for GL_FIXED attributes.
Fixes arb_es2_compatibility-fixed-type
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| a55fbbc1a2b579aed1e80036367b521ef6928f66 |
|
10-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix access of attribute arrays.
By leaving out the column index, we were reading an unallocated
attribute on glsl-mat-attribute.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| abf843a797876b5e3c5c91dbec25b6553d2cc281 |
|
09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for ir_binop_pow.
Fixes vs-pow-float-float.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 250770b74d33bb8625c780a74a89477af033d13a |
|
09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Respect the gen6 limitation that math opcodes can't be align16.
Fixes vs-acos-vec3 and friends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 584ff407482fd3baf5ce081dbbf9653eb76c40f1 |
|
07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for scratch read/write codegen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| d0e4d71070cd7fa197ed98612782484ec1f27123 |
|
07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 2b7632aeaa5f8b4ab3da7d33a3c71c71023a072a |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6.
Fixes vs-temp-array-mat2-col-rd.shader_test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| c3752b399ab376aa53392afb8f2d4b526054f0a8 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for dot product opcodes.
Fixes glsl-vs-dot-vec2.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| 814a9bef30beda427e8fbf6f3b8abb6a45f0e2e4 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Drop the assertion about dst.reg_offset == 0.
Adding the offset is the right thing to do here, and fixes
glsl-vs-mat-add-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| eca762d831e099b549dafa0be896eac82b3fceb9 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix support for zero uniforms in use.
We were looking for attributes in the wrong place, and pointlessly
doing the work on gen6 at all.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| a070d5f363e99b0f846d555e9ca3a74ec807fdc0 |
|
04-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Start adding support for uniforms
There's no clever packing here, no pull constants, and no array support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|
| af3c9803d818fd33139f1247a387d64b967b8992 |
|
02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
|