brw_vec4_emit.cpp revision e7da40afe84349a640fe15e3af408a0dfe880e85
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28}; 29 30using namespace brw; 31 32namespace brw { 33 34int 35vec4_visitor::setup_attributes(int payload_reg) 36{ 37 int nr_attributes; 38 int attribute_map[VERT_ATTRIB_MAX]; 39 40 nr_attributes = 0; 41 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 42 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 43 attribute_map[i] = payload_reg + nr_attributes; 44 nr_attributes++; 45 } 46 } 47 48 foreach_list(node, &this->instructions) { 49 vec4_instruction *inst = (vec4_instruction *)node; 50 51 /* We have to support ATTR as a destination for GL_FIXED fixup. */ 52 if (inst->dst.file == ATTR) { 53 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; 54 55 struct brw_reg reg = brw_vec8_grf(grf, 0); 56 reg.dw1.bits.writemask = inst->dst.writemask; 57 58 inst->dst.file = HW_REG; 59 inst->dst.fixed_hw_reg = reg; 60 } 61 62 for (int i = 0; i < 3; i++) { 63 if (inst->src[i].file != ATTR) 64 continue; 65 66 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 67 68 struct brw_reg reg = brw_vec8_grf(grf, 0); 69 reg.dw1.bits.swizzle = inst->src[i].swizzle; 70 if (inst->src[i].abs) 71 reg = brw_abs(reg); 72 if (inst->src[i].negate) 73 reg = negate(reg); 74 75 inst->src[i].file = HW_REG; 76 inst->src[i].fixed_hw_reg = reg; 77 } 78 } 79 80 /* The BSpec says we always have to read at least one thing from 81 * the VF, and it appears that the hardware wedges otherwise. 82 */ 83 if (nr_attributes == 0) 84 nr_attributes = 1; 85 86 prog_data->urb_read_length = (nr_attributes + 1) / 2; 87 88 return payload_reg + nr_attributes; 89} 90 91int 92vec4_visitor::setup_uniforms(int reg) 93{ 94 /* The pre-gen6 VS requires that some push constants get loaded no 95 * matter what, or the GPU would hang. 96 */ 97 if (intel->gen < 6 && this->uniforms == 0) { 98 this->uniform_vector_size[this->uniforms] = 1; 99 100 for (unsigned int i = 0; i < 4; i++) { 101 unsigned int slot = this->uniforms * 4 + i; 102 static float zero = 0.0; 103 c->prog_data.param[slot] = &zero; 104 } 105 106 this->uniforms++; 107 reg++; 108 } else { 109 reg += ALIGN(uniforms, 2) / 2; 110 } 111 112 c->prog_data.nr_params = this->uniforms * 4; 113 114 c->prog_data.curb_read_length = reg - 1; 115 c->prog_data.uses_new_param_layout = true; 116 117 return reg; 118} 119 120void 121vec4_visitor::setup_payload(void) 122{ 123 int reg = 0; 124 125 /* The payload always contains important data in g0, which contains 126 * the URB handles that are passed on to the URB write at the end 127 * of the thread. So, we always start push constants at g1. 128 */ 129 reg++; 130 131 reg = setup_uniforms(reg); 132 133 reg = setup_attributes(reg); 134 135 this->first_non_payload_grf = reg; 136} 137 138struct brw_reg 139vec4_instruction::get_dst(void) 140{ 141 struct brw_reg brw_reg; 142 143 switch (dst.file) { 144 case GRF: 145 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 146 brw_reg = retype(brw_reg, dst.type); 147 brw_reg.dw1.bits.writemask = dst.writemask; 148 break; 149 150 case MRF: 151 brw_reg = brw_message_reg(dst.reg + dst.reg_offset); 152 brw_reg = retype(brw_reg, dst.type); 153 brw_reg.dw1.bits.writemask = dst.writemask; 154 break; 155 156 case HW_REG: 157 brw_reg = dst.fixed_hw_reg; 158 break; 159 160 case BAD_FILE: 161 brw_reg = brw_null_reg(); 162 break; 163 164 default: 165 assert(!"not reached"); 166 brw_reg = brw_null_reg(); 167 break; 168 } 169 return brw_reg; 170} 171 172struct brw_reg 173vec4_instruction::get_src(int i) 174{ 175 struct brw_reg brw_reg; 176 177 switch (src[i].file) { 178 case GRF: 179 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 180 brw_reg = retype(brw_reg, src[i].type); 181 brw_reg.dw1.bits.swizzle = src[i].swizzle; 182 if (src[i].abs) 183 brw_reg = brw_abs(brw_reg); 184 if (src[i].negate) 185 brw_reg = negate(brw_reg); 186 break; 187 188 case IMM: 189 switch (src[i].type) { 190 case BRW_REGISTER_TYPE_F: 191 brw_reg = brw_imm_f(src[i].imm.f); 192 break; 193 case BRW_REGISTER_TYPE_D: 194 brw_reg = brw_imm_d(src[i].imm.i); 195 break; 196 case BRW_REGISTER_TYPE_UD: 197 brw_reg = brw_imm_ud(src[i].imm.u); 198 break; 199 default: 200 assert(!"not reached"); 201 brw_reg = brw_null_reg(); 202 break; 203 } 204 break; 205 206 case UNIFORM: 207 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 208 ((src[i].reg + src[i].reg_offset) % 2) * 4), 209 0, 4, 1); 210 brw_reg = retype(brw_reg, src[i].type); 211 brw_reg.dw1.bits.swizzle = src[i].swizzle; 212 if (src[i].abs) 213 brw_reg = brw_abs(brw_reg); 214 if (src[i].negate) 215 brw_reg = negate(brw_reg); 216 217 /* This should have been moved to pull constants. */ 218 assert(!src[i].reladdr); 219 break; 220 221 case HW_REG: 222 brw_reg = src[i].fixed_hw_reg; 223 break; 224 225 case BAD_FILE: 226 /* Probably unused. */ 227 brw_reg = brw_null_reg(); 228 break; 229 case ATTR: 230 default: 231 assert(!"not reached"); 232 brw_reg = brw_null_reg(); 233 break; 234 } 235 236 return brw_reg; 237} 238 239void 240vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 241 struct brw_reg dst, 242 struct brw_reg src) 243{ 244 brw_math(p, 245 dst, 246 brw_math_function(inst->opcode), 247 BRW_MATH_SATURATE_NONE, 248 inst->base_mrf, 249 src, 250 BRW_MATH_DATA_VECTOR, 251 BRW_MATH_PRECISION_FULL); 252} 253 254static void 255check_gen6_math_src_arg(struct brw_reg src) 256{ 257 /* Source swizzles are ignored. */ 258 assert(!src.abs); 259 assert(!src.negate); 260 assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); 261} 262 263void 264vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 265 struct brw_reg dst, 266 struct brw_reg src) 267{ 268 /* Can't do writemask because math can't be align16. */ 269 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 270 check_gen6_math_src_arg(src); 271 272 brw_set_access_mode(p, BRW_ALIGN_1); 273 brw_math(p, 274 dst, 275 brw_math_function(inst->opcode), 276 BRW_MATH_SATURATE_NONE, 277 inst->base_mrf, 278 src, 279 BRW_MATH_DATA_SCALAR, 280 BRW_MATH_PRECISION_FULL); 281 brw_set_access_mode(p, BRW_ALIGN_16); 282} 283 284void 285vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 286 struct brw_reg dst, 287 struct brw_reg src0, 288 struct brw_reg src1) 289{ 290 /* Can't do writemask because math can't be align16. */ 291 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 292 /* Source swizzles are ignored. */ 293 check_gen6_math_src_arg(src0); 294 check_gen6_math_src_arg(src1); 295 296 brw_set_access_mode(p, BRW_ALIGN_1); 297 brw_math2(p, 298 dst, 299 brw_math_function(inst->opcode), 300 src0, src1); 301 brw_set_access_mode(p, BRW_ALIGN_16); 302} 303 304void 305vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 306 struct brw_reg dst, 307 struct brw_reg src0, 308 struct brw_reg src1) 309{ 310 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1); 311 312 brw_math(p, 313 dst, 314 brw_math_function(inst->opcode), 315 BRW_MATH_SATURATE_NONE, 316 inst->base_mrf, 317 src0, 318 BRW_MATH_DATA_VECTOR, 319 BRW_MATH_PRECISION_FULL); 320} 321 322void 323vec4_visitor::generate_urb_write(vec4_instruction *inst) 324{ 325 brw_urb_WRITE(p, 326 brw_null_reg(), /* dest */ 327 inst->base_mrf, /* starting mrf reg nr */ 328 brw_vec8_grf(0, 0), /* src */ 329 false, /* allocate */ 330 true, /* used */ 331 inst->mlen, 332 0, /* response len */ 333 inst->eot, /* eot */ 334 inst->eot, /* writes complete */ 335 inst->offset, /* urb destination offset */ 336 BRW_URB_SWIZZLE_INTERLEAVE); 337} 338 339void 340vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 341 struct brw_reg index) 342{ 343 int second_vertex_offset; 344 345 if (intel->gen >= 6) 346 second_vertex_offset = 1; 347 else 348 second_vertex_offset = 16; 349 350 m1 = retype(m1, BRW_REGISTER_TYPE_D); 351 352 /* Set up M1 (message payload). Only the block offsets in M1.0 and 353 * M1.4 are used, and the rest are ignored. 354 */ 355 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 356 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 357 struct brw_reg index_0 = suboffset(vec1(index), 0); 358 struct brw_reg index_4 = suboffset(vec1(index), 4); 359 360 brw_push_insn_state(p); 361 brw_set_mask_control(p, BRW_MASK_DISABLE); 362 brw_set_access_mode(p, BRW_ALIGN_1); 363 364 brw_MOV(p, m1_0, index_0); 365 366 brw_set_predicate_inverse(p, true); 367 if (index.file == BRW_IMMEDIATE_VALUE) { 368 index_4.dw1.ud += second_vertex_offset; 369 brw_MOV(p, m1_4, index_4); 370 } else { 371 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 372 } 373 374 brw_pop_insn_state(p); 375} 376 377void 378vec4_visitor::generate_scratch_read(vec4_instruction *inst, 379 struct brw_reg dst, 380 struct brw_reg index) 381{ 382 struct brw_reg header = brw_vec8_grf(0, 0); 383 384 gen6_resolve_implied_move(p, &header, inst->base_mrf); 385 386 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 387 index); 388 389 uint32_t msg_type; 390 391 if (intel->gen >= 6) 392 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 393 else if (intel->gen == 5 || intel->is_g4x) 394 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 395 else 396 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 397 398 /* Each of the 8 channel enables is considered for whether each 399 * dword is written. 400 */ 401 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 402 brw_set_dest(p, send, dst); 403 brw_set_src0(p, send, header); 404 if (intel->gen < 6) 405 send->header.destreg__conditionalmod = inst->base_mrf; 406 brw_set_dp_read_message(p, send, 407 255, /* binding table index: stateless access */ 408 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 409 msg_type, 410 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 411 2, /* mlen */ 412 1 /* rlen */); 413} 414 415void 416vec4_visitor::generate_scratch_write(vec4_instruction *inst, 417 struct brw_reg dst, 418 struct brw_reg src, 419 struct brw_reg index) 420{ 421 struct brw_reg header = brw_vec8_grf(0, 0); 422 bool write_commit; 423 424 /* If the instruction is predicated, we'll predicate the send, not 425 * the header setup. 426 */ 427 brw_set_predicate_control(p, false); 428 429 gen6_resolve_implied_move(p, &header, inst->base_mrf); 430 431 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 432 index); 433 434 brw_MOV(p, 435 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 436 retype(src, BRW_REGISTER_TYPE_D)); 437 438 uint32_t msg_type; 439 440 if (intel->gen >= 6) 441 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 442 else 443 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 444 445 brw_set_predicate_control(p, inst->predicate); 446 447 /* Pre-gen6, we have to specify write commits to ensure ordering 448 * between reads and writes within a thread. Afterwards, that's 449 * guaranteed and write commits only matter for inter-thread 450 * synchronization. 451 */ 452 if (intel->gen >= 6) { 453 write_commit = false; 454 } else { 455 /* The visitor set up our destination register to be g0. This 456 * means that when the next read comes along, we will end up 457 * reading from g0 and causing a block on the write commit. For 458 * write-after-read, we are relying on the value of the previous 459 * read being used (and thus blocking on completion) before our 460 * write is executed. This means we have to be careful in 461 * instruction scheduling to not violate this assumption. 462 */ 463 write_commit = true; 464 } 465 466 /* Each of the 8 channel enables is considered for whether each 467 * dword is written. 468 */ 469 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 470 brw_set_dest(p, send, dst); 471 brw_set_src0(p, send, header); 472 if (intel->gen < 6) 473 send->header.destreg__conditionalmod = inst->base_mrf; 474 brw_set_dp_write_message(p, send, 475 255, /* binding table index: stateless access */ 476 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 477 msg_type, 478 3, /* mlen */ 479 true, /* header present */ 480 false, /* pixel scoreboard */ 481 write_commit, /* rlen */ 482 false, /* eot */ 483 write_commit); 484} 485 486void 487vec4_visitor::generate_pull_constant_load(vec4_instruction *inst, 488 struct brw_reg dst, 489 struct brw_reg index) 490{ 491 struct brw_reg header = brw_vec8_grf(0, 0); 492 493 gen6_resolve_implied_move(p, &header, inst->base_mrf); 494 495 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D), 496 index); 497 498 uint32_t msg_type; 499 500 if (intel->gen >= 6) 501 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 502 else if (intel->gen == 5 || intel->is_g4x) 503 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 504 else 505 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 506 507 /* Each of the 8 channel enables is considered for whether each 508 * dword is written. 509 */ 510 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 511 brw_set_dest(p, send, dst); 512 brw_set_src0(p, send, header); 513 if (intel->gen < 6) 514 send->header.destreg__conditionalmod = inst->base_mrf; 515 brw_set_dp_read_message(p, send, 516 SURF_INDEX_VERT_CONST_BUFFER, 517 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 518 msg_type, 519 BRW_DATAPORT_READ_TARGET_DATA_CACHE, 520 2, /* mlen */ 521 1 /* rlen */); 522} 523 524void 525vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 526 struct brw_reg dst, 527 struct brw_reg *src) 528{ 529 vec4_instruction *inst = (vec4_instruction *)instruction; 530 531 switch (inst->opcode) { 532 case SHADER_OPCODE_RCP: 533 case SHADER_OPCODE_RSQ: 534 case SHADER_OPCODE_SQRT: 535 case SHADER_OPCODE_EXP2: 536 case SHADER_OPCODE_LOG2: 537 case SHADER_OPCODE_SIN: 538 case SHADER_OPCODE_COS: 539 if (intel->gen >= 6) { 540 generate_math1_gen6(inst, dst, src[0]); 541 } else { 542 generate_math1_gen4(inst, dst, src[0]); 543 } 544 break; 545 546 case SHADER_OPCODE_POW: 547 if (intel->gen >= 6) { 548 generate_math2_gen6(inst, dst, src[0], src[1]); 549 } else { 550 generate_math2_gen4(inst, dst, src[0], src[1]); 551 } 552 break; 553 554 case VS_OPCODE_URB_WRITE: 555 generate_urb_write(inst); 556 break; 557 558 case VS_OPCODE_SCRATCH_READ: 559 generate_scratch_read(inst, dst, src[0]); 560 break; 561 562 case VS_OPCODE_SCRATCH_WRITE: 563 generate_scratch_write(inst, dst, src[0], src[1]); 564 break; 565 566 case VS_OPCODE_PULL_CONSTANT_LOAD: 567 generate_pull_constant_load(inst, dst, src[0]); 568 break; 569 570 default: 571 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 572 fail("unsupported opcode in `%s' in VS\n", 573 brw_opcodes[inst->opcode].name); 574 } else { 575 fail("Unsupported opcode %d in VS", inst->opcode); 576 } 577 } 578} 579 580bool 581vec4_visitor::run() 582{ 583 if (c->key.nr_userclip && !c->key.uses_clip_distance) 584 setup_uniform_clipplane_values(); 585 586 /* Generate VS IR for main(). (the visitor only descends into 587 * functions called "main"). 588 */ 589 visit_instructions(shader->ir); 590 591 emit_urb_writes(); 592 593 /* Before any optimization, push array accesses out to scratch 594 * space where we need them to be. This pass may allocate new 595 * virtual GRFs, so we want to do it early. It also makes sure 596 * that we have reladdr computations available for CSE, since we'll 597 * often do repeated subexpressions for those. 598 */ 599 move_grf_array_access_to_scratch(); 600 move_uniform_array_access_to_pull_constants(); 601 pack_uniform_registers(); 602 move_push_constants_to_pull_constants(); 603 604 bool progress; 605 do { 606 progress = false; 607 progress = dead_code_eliminate() || progress; 608 progress = opt_copy_propagation() || progress; 609 progress = opt_algebraic() || progress; 610 progress = opt_compute_to_mrf() || progress; 611 } while (progress); 612 613 614 if (failed) 615 return false; 616 617 setup_payload(); 618 reg_allocate(); 619 620 if (failed) 621 return false; 622 623 brw_set_access_mode(p, BRW_ALIGN_16); 624 625 generate_code(); 626 627 return !failed; 628} 629 630void 631vec4_visitor::generate_code() 632{ 633 int last_native_inst = 0; 634 const char *last_annotation_string = NULL; 635 ir_instruction *last_annotation_ir = NULL; 636 637 int loop_stack_array_size = 16; 638 int loop_stack_depth = 0; 639 brw_instruction **loop_stack = 640 rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size); 641 int *if_depth_in_loop = 642 rzalloc_array(this->mem_ctx, int, loop_stack_array_size); 643 644 645 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 646 printf("Native code for vertex shader %d:\n", prog->Name); 647 } 648 649 foreach_list(node, &this->instructions) { 650 vec4_instruction *inst = (vec4_instruction *)node; 651 struct brw_reg src[3], dst; 652 653 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 654 if (last_annotation_ir != inst->ir) { 655 last_annotation_ir = inst->ir; 656 if (last_annotation_ir) { 657 printf(" "); 658 last_annotation_ir->print(); 659 printf("\n"); 660 } 661 } 662 if (last_annotation_string != inst->annotation) { 663 last_annotation_string = inst->annotation; 664 if (last_annotation_string) 665 printf(" %s\n", last_annotation_string); 666 } 667 } 668 669 for (unsigned int i = 0; i < 3; i++) { 670 src[i] = inst->get_src(i); 671 } 672 dst = inst->get_dst(); 673 674 brw_set_conditionalmod(p, inst->conditional_mod); 675 brw_set_predicate_control(p, inst->predicate); 676 brw_set_predicate_inverse(p, inst->predicate_inverse); 677 brw_set_saturate(p, inst->saturate); 678 679 switch (inst->opcode) { 680 case BRW_OPCODE_MOV: 681 brw_MOV(p, dst, src[0]); 682 break; 683 case BRW_OPCODE_ADD: 684 brw_ADD(p, dst, src[0], src[1]); 685 break; 686 case BRW_OPCODE_MUL: 687 brw_MUL(p, dst, src[0], src[1]); 688 break; 689 case BRW_OPCODE_MACH: 690 brw_set_acc_write_control(p, 1); 691 brw_MACH(p, dst, src[0], src[1]); 692 brw_set_acc_write_control(p, 0); 693 break; 694 695 case BRW_OPCODE_FRC: 696 brw_FRC(p, dst, src[0]); 697 break; 698 case BRW_OPCODE_RNDD: 699 brw_RNDD(p, dst, src[0]); 700 break; 701 case BRW_OPCODE_RNDE: 702 brw_RNDE(p, dst, src[0]); 703 break; 704 case BRW_OPCODE_RNDZ: 705 brw_RNDZ(p, dst, src[0]); 706 break; 707 708 case BRW_OPCODE_AND: 709 brw_AND(p, dst, src[0], src[1]); 710 break; 711 case BRW_OPCODE_OR: 712 brw_OR(p, dst, src[0], src[1]); 713 break; 714 case BRW_OPCODE_XOR: 715 brw_XOR(p, dst, src[0], src[1]); 716 break; 717 case BRW_OPCODE_NOT: 718 brw_NOT(p, dst, src[0]); 719 break; 720 case BRW_OPCODE_ASR: 721 brw_ASR(p, dst, src[0], src[1]); 722 break; 723 case BRW_OPCODE_SHR: 724 brw_SHR(p, dst, src[0], src[1]); 725 break; 726 case BRW_OPCODE_SHL: 727 brw_SHL(p, dst, src[0], src[1]); 728 break; 729 730 case BRW_OPCODE_CMP: 731 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 732 break; 733 case BRW_OPCODE_SEL: 734 brw_SEL(p, dst, src[0], src[1]); 735 break; 736 737 case BRW_OPCODE_DP4: 738 brw_DP4(p, dst, src[0], src[1]); 739 break; 740 741 case BRW_OPCODE_DP3: 742 brw_DP3(p, dst, src[0], src[1]); 743 break; 744 745 case BRW_OPCODE_DP2: 746 brw_DP2(p, dst, src[0], src[1]); 747 break; 748 749 case BRW_OPCODE_IF: 750 if (inst->src[0].file != BAD_FILE) { 751 /* The instruction has an embedded compare (only allowed on gen6) */ 752 assert(intel->gen == 6); 753 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 754 } else { 755 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 756 brw_inst->header.predicate_control = inst->predicate; 757 } 758 if_depth_in_loop[loop_stack_depth]++; 759 break; 760 761 case BRW_OPCODE_ELSE: 762 brw_ELSE(p); 763 break; 764 case BRW_OPCODE_ENDIF: 765 brw_ENDIF(p); 766 if_depth_in_loop[loop_stack_depth]--; 767 break; 768 769 case BRW_OPCODE_DO: 770 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 771 if (loop_stack_array_size <= loop_stack_depth) { 772 loop_stack_array_size *= 2; 773 loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *, 774 loop_stack_array_size); 775 if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int, 776 loop_stack_array_size); 777 } 778 if_depth_in_loop[loop_stack_depth] = 0; 779 break; 780 781 case BRW_OPCODE_BREAK: 782 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 783 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 784 break; 785 case BRW_OPCODE_CONTINUE: 786 /* FINISHME: We need to write the loop instruction support still. */ 787 if (intel->gen >= 6) 788 gen6_CONT(p, loop_stack[loop_stack_depth - 1]); 789 else 790 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 791 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 792 break; 793 794 case BRW_OPCODE_WHILE: { 795 struct brw_instruction *inst0, *inst1; 796 GLuint br = 1; 797 798 if (intel->gen >= 5) 799 br = 2; 800 801 assert(loop_stack_depth > 0); 802 loop_stack_depth--; 803 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 804 if (intel->gen < 6) { 805 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 806 while (inst0 > loop_stack[loop_stack_depth]) { 807 inst0--; 808 if (inst0->header.opcode == BRW_OPCODE_BREAK && 809 inst0->bits3.if_else.jump_count == 0) { 810 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 811 } 812 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 813 inst0->bits3.if_else.jump_count == 0) { 814 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 815 } 816 } 817 } 818 } 819 break; 820 821 default: 822 generate_vs_instruction(inst, dst, src); 823 break; 824 } 825 826 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 827 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 828 if (0) { 829 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 830 ((uint32_t *)&p->store[i])[3], 831 ((uint32_t *)&p->store[i])[2], 832 ((uint32_t *)&p->store[i])[1], 833 ((uint32_t *)&p->store[i])[0]); 834 } 835 brw_disasm(stdout, &p->store[i], intel->gen); 836 } 837 } 838 839 last_native_inst = p->nr_insn; 840 } 841 842 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 843 printf("\n"); 844 } 845 846 ralloc_free(loop_stack); 847 ralloc_free(if_depth_in_loop); 848 849 brw_set_uip_jip(p); 850 851 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 852 * emit issues, it doesn't get the jump distances into the output, 853 * which is often something we want to debug. So this is here in 854 * case you're doing that. 855 */ 856 if (0) { 857 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 858 for (unsigned int i = 0; i < p->nr_insn; i++) { 859 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 860 ((uint32_t *)&p->store[i])[3], 861 ((uint32_t *)&p->store[i])[2], 862 ((uint32_t *)&p->store[i])[1], 863 ((uint32_t *)&p->store[i])[0]); 864 brw_disasm(stdout, &p->store[i], intel->gen); 865 } 866 } 867 } 868} 869 870extern "C" { 871 872bool 873brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 874{ 875 if (!prog) 876 return false; 877 878 struct brw_shader *shader = 879 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 880 if (!shader) 881 return false; 882 883 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 884 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 885 _mesa_print_ir(shader->ir, NULL); 886 printf("\n\n"); 887 } 888 889 vec4_visitor v(c, prog, shader); 890 if (!v.run()) { 891 prog->LinkStatus = GL_FALSE; 892 ralloc_strcat(&prog->InfoLog, v.fail_msg); 893 return false; 894 } 895 896 return true; 897} 898 899} /* extern "C" */ 900 901} /* namespace brw */ 902