brw_vec4_emit.cpp revision b9af592dfa8f8d0fe9f29c2d48bf6846cbd5c50f
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28}; 29 30using namespace brw; 31 32namespace brw { 33 34int 35vec4_visitor::setup_attributes(int payload_reg) 36{ 37 int nr_attributes; 38 int attribute_map[VERT_ATTRIB_MAX]; 39 40 nr_attributes = 0; 41 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 42 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 43 attribute_map[i] = payload_reg + nr_attributes; 44 nr_attributes++; 45 } 46 } 47 48 foreach_list(node, &this->instructions) { 49 vec4_instruction *inst = (vec4_instruction *)node; 50 51 /* We have to support ATTR as a destination for GL_FIXED fixup. */ 52 if (inst->dst.file == ATTR) { 53 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; 54 55 struct brw_reg reg = brw_vec8_grf(grf, 0); 56 reg.dw1.bits.writemask = inst->dst.writemask; 57 58 inst->dst.file = HW_REG; 59 inst->dst.fixed_hw_reg = reg; 60 } 61 62 for (int i = 0; i < 3; i++) { 63 if (inst->src[i].file != ATTR) 64 continue; 65 66 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 67 68 struct brw_reg reg = brw_vec8_grf(grf, 0); 69 reg.dw1.bits.swizzle = inst->src[i].swizzle; 70 if (inst->src[i].abs) 71 reg = brw_abs(reg); 72 if (inst->src[i].negate) 73 reg = negate(reg); 74 75 inst->src[i].file = HW_REG; 76 inst->src[i].fixed_hw_reg = reg; 77 } 78 } 79 80 /* The BSpec says we always have to read at least one thing from 81 * the VF, and it appears that the hardware wedges otherwise. 82 */ 83 if (nr_attributes == 0) 84 nr_attributes = 1; 85 86 prog_data->urb_read_length = (nr_attributes + 1) / 2; 87 88 return payload_reg + nr_attributes; 89} 90 91int 92vec4_visitor::setup_uniforms(int reg) 93{ 94 /* The pre-gen6 VS requires that some push constants get loaded no 95 * matter what, or the GPU would hang. 96 */ 97 if (intel->gen < 6 && this->uniforms == 0) { 98 this->uniform_vector_size[this->uniforms] = 1; 99 100 for (unsigned int i = 0; i < 4; i++) { 101 unsigned int slot = this->uniforms * 4 + i; 102 static float zero = 0.0; 103 c->prog_data.param[slot] = &zero; 104 } 105 106 this->uniforms++; 107 reg++; 108 } else { 109 reg += ALIGN(uniforms, 2) / 2; 110 } 111 112 c->prog_data.nr_params = this->uniforms * 4; 113 114 c->prog_data.curb_read_length = reg - 1; 115 c->prog_data.uses_new_param_layout = true; 116 117 return reg; 118} 119 120void 121vec4_visitor::setup_payload(void) 122{ 123 int reg = 0; 124 125 /* The payload always contains important data in g0, which contains 126 * the URB handles that are passed on to the URB write at the end 127 * of the thread. So, we always start push constants at g1. 128 */ 129 reg++; 130 131 reg = setup_uniforms(reg); 132 133 reg = setup_attributes(reg); 134 135 this->first_non_payload_grf = reg; 136} 137 138struct brw_reg 139vec4_instruction::get_dst(void) 140{ 141 struct brw_reg brw_reg; 142 143 switch (dst.file) { 144 case GRF: 145 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 146 brw_reg = retype(brw_reg, dst.type); 147 brw_reg.dw1.bits.writemask = dst.writemask; 148 break; 149 150 case MRF: 151 brw_reg = brw_message_reg(dst.reg + dst.reg_offset); 152 brw_reg = retype(brw_reg, dst.type); 153 brw_reg.dw1.bits.writemask = dst.writemask; 154 break; 155 156 case HW_REG: 157 brw_reg = dst.fixed_hw_reg; 158 break; 159 160 case BAD_FILE: 161 brw_reg = brw_null_reg(); 162 break; 163 164 default: 165 assert(!"not reached"); 166 brw_reg = brw_null_reg(); 167 break; 168 } 169 return brw_reg; 170} 171 172struct brw_reg 173vec4_instruction::get_src(int i) 174{ 175 struct brw_reg brw_reg; 176 177 switch (src[i].file) { 178 case GRF: 179 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 180 brw_reg = retype(brw_reg, src[i].type); 181 brw_reg.dw1.bits.swizzle = src[i].swizzle; 182 if (src[i].abs) 183 brw_reg = brw_abs(brw_reg); 184 if (src[i].negate) 185 brw_reg = negate(brw_reg); 186 break; 187 188 case IMM: 189 switch (src[i].type) { 190 case BRW_REGISTER_TYPE_F: 191 brw_reg = brw_imm_f(src[i].imm.f); 192 break; 193 case BRW_REGISTER_TYPE_D: 194 brw_reg = brw_imm_d(src[i].imm.i); 195 break; 196 case BRW_REGISTER_TYPE_UD: 197 brw_reg = brw_imm_ud(src[i].imm.u); 198 break; 199 default: 200 assert(!"not reached"); 201 brw_reg = brw_null_reg(); 202 break; 203 } 204 break; 205 206 case UNIFORM: 207 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 208 ((src[i].reg + src[i].reg_offset) % 2) * 4), 209 0, 4, 1); 210 brw_reg = retype(brw_reg, src[i].type); 211 brw_reg.dw1.bits.swizzle = src[i].swizzle; 212 if (src[i].abs) 213 brw_reg = brw_abs(brw_reg); 214 if (src[i].negate) 215 brw_reg = negate(brw_reg); 216 217 /* This should have been moved to pull constants. */ 218 assert(!src[i].reladdr); 219 break; 220 221 case HW_REG: 222 brw_reg = src[i].fixed_hw_reg; 223 break; 224 225 case BAD_FILE: 226 /* Probably unused. */ 227 brw_reg = brw_null_reg(); 228 break; 229 case ATTR: 230 default: 231 assert(!"not reached"); 232 brw_reg = brw_null_reg(); 233 break; 234 } 235 236 return brw_reg; 237} 238 239void 240vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 241 struct brw_reg dst, 242 struct brw_reg src) 243{ 244 brw_math(p, 245 dst, 246 brw_math_function(inst->opcode), 247 BRW_MATH_SATURATE_NONE, 248 inst->base_mrf, 249 src, 250 BRW_MATH_DATA_VECTOR, 251 BRW_MATH_PRECISION_FULL); 252} 253 254static void 255check_gen6_math_src_arg(struct brw_reg src) 256{ 257 /* Source swizzles are ignored. */ 258 assert(!src.abs); 259 assert(!src.negate); 260 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW); 261} 262 263void 264vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 265 struct brw_reg dst, 266 struct brw_reg src) 267{ 268 /* Can't do writemask because math can't be align16. */ 269 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 270 check_gen6_math_src_arg(src); 271 272 brw_set_access_mode(p, BRW_ALIGN_1); 273 brw_math(p, 274 dst, 275 brw_math_function(inst->opcode), 276 BRW_MATH_SATURATE_NONE, 277 inst->base_mrf, 278 src, 279 BRW_MATH_DATA_SCALAR, 280 BRW_MATH_PRECISION_FULL); 281 brw_set_access_mode(p, BRW_ALIGN_16); 282} 283 284void 285vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 286 struct brw_reg dst, 287 struct brw_reg src0, 288 struct brw_reg src1) 289{ 290 /* Can't do writemask because math can't be align16. */ 291 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 292 /* Source swizzles are ignored. */ 293 check_gen6_math_src_arg(src0); 294 check_gen6_math_src_arg(src1); 295 296 brw_set_access_mode(p, BRW_ALIGN_1); 297 brw_math2(p, 298 dst, 299 brw_math_function(inst->opcode), 300 src0, src1); 301 brw_set_access_mode(p, BRW_ALIGN_16); 302} 303 304void 305vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 306 struct brw_reg dst, 307 struct brw_reg src0, 308 struct brw_reg src1) 309{ 310 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13 311 * "Message Payload": 312 * 313 * "Operand0[7]. For the INT DIV functions, this operand is the 314 * denominator." 315 * ... 316 * "Operand1[7]. For the INT DIV functions, this operand is the 317 * numerator." 318 */ 319 bool is_int_div = inst->opcode != SHADER_OPCODE_POW; 320 struct brw_reg &op0 = is_int_div ? src1 : src0; 321 struct brw_reg &op1 = is_int_div ? src0 : src1; 322 323 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); 324 325 brw_math(p, 326 dst, 327 brw_math_function(inst->opcode), 328 BRW_MATH_SATURATE_NONE, 329 inst->base_mrf, 330 op0, 331 BRW_MATH_DATA_VECTOR, 332 BRW_MATH_PRECISION_FULL); 333} 334 335void 336vec4_visitor::generate_urb_write(vec4_instruction *inst) 337{ 338 brw_urb_WRITE(p, 339 brw_null_reg(), /* dest */ 340 inst->base_mrf, /* starting mrf reg nr */ 341 brw_vec8_grf(0, 0), /* src */ 342 false, /* allocate */ 343 true, /* used */ 344 inst->mlen, 345 0, /* response len */ 346 inst->eot, /* eot */ 347 inst->eot, /* writes complete */ 348 inst->offset, /* urb destination offset */ 349 BRW_URB_SWIZZLE_INTERLEAVE); 350} 351 352void 353vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 354 struct brw_reg index) 355{ 356 int second_vertex_offset; 357 358 if (intel->gen >= 6) 359 second_vertex_offset = 1; 360 else 361 second_vertex_offset = 16; 362 363 m1 = retype(m1, BRW_REGISTER_TYPE_D); 364 365 /* Set up M1 (message payload). Only the block offsets in M1.0 and 366 * M1.4 are used, and the rest are ignored. 367 */ 368 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 369 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 370 struct brw_reg index_0 = suboffset(vec1(index), 0); 371 struct brw_reg index_4 = suboffset(vec1(index), 4); 372 373 brw_push_insn_state(p); 374 brw_set_mask_control(p, BRW_MASK_DISABLE); 375 brw_set_access_mode(p, BRW_ALIGN_1); 376 377 brw_MOV(p, m1_0, index_0); 378 379 brw_set_predicate_inverse(p, true); 380 if (index.file == BRW_IMMEDIATE_VALUE) { 381 index_4.dw1.ud += second_vertex_offset; 382 brw_MOV(p, m1_4, index_4); 383 } else { 384 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 385 } 386 387 brw_pop_insn_state(p); 388} 389 390void 391vec4_visitor::generate_scratch_read(vec4_instruction *inst, 392 struct brw_reg dst, 393 struct brw_reg index) 394{ 395 struct brw_reg header = brw_vec8_grf(0, 0); 396 397 gen6_resolve_implied_move(p, &header, inst->base_mrf); 398 399 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 400 index); 401 402 uint32_t msg_type; 403 404 if (intel->gen >= 6) 405 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 406 else if (intel->gen == 5 || intel->is_g4x) 407 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 408 else 409 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 410 411 /* Each of the 8 channel enables is considered for whether each 412 * dword is written. 413 */ 414 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 415 brw_set_dest(p, send, dst); 416 brw_set_src0(p, send, header); 417 if (intel->gen < 6) 418 send->header.destreg__conditionalmod = inst->base_mrf; 419 brw_set_dp_read_message(p, send, 420 255, /* binding table index: stateless access */ 421 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 422 msg_type, 423 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 424 2, /* mlen */ 425 1 /* rlen */); 426} 427 428void 429vec4_visitor::generate_scratch_write(vec4_instruction *inst, 430 struct brw_reg dst, 431 struct brw_reg src, 432 struct brw_reg index) 433{ 434 struct brw_reg header = brw_vec8_grf(0, 0); 435 bool write_commit; 436 437 /* If the instruction is predicated, we'll predicate the send, not 438 * the header setup. 439 */ 440 brw_set_predicate_control(p, false); 441 442 gen6_resolve_implied_move(p, &header, inst->base_mrf); 443 444 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 445 index); 446 447 brw_MOV(p, 448 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 449 retype(src, BRW_REGISTER_TYPE_D)); 450 451 uint32_t msg_type; 452 453 if (intel->gen >= 6) 454 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 455 else 456 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 457 458 brw_set_predicate_control(p, inst->predicate); 459 460 /* Pre-gen6, we have to specify write commits to ensure ordering 461 * between reads and writes within a thread. Afterwards, that's 462 * guaranteed and write commits only matter for inter-thread 463 * synchronization. 464 */ 465 if (intel->gen >= 6) { 466 write_commit = false; 467 } else { 468 /* The visitor set up our destination register to be g0. This 469 * means that when the next read comes along, we will end up 470 * reading from g0 and causing a block on the write commit. For 471 * write-after-read, we are relying on the value of the previous 472 * read being used (and thus blocking on completion) before our 473 * write is executed. This means we have to be careful in 474 * instruction scheduling to not violate this assumption. 475 */ 476 write_commit = true; 477 } 478 479 /* Each of the 8 channel enables is considered for whether each 480 * dword is written. 481 */ 482 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 483 brw_set_dest(p, send, dst); 484 brw_set_src0(p, send, header); 485 if (intel->gen < 6) 486 send->header.destreg__conditionalmod = inst->base_mrf; 487 brw_set_dp_write_message(p, send, 488 255, /* binding table index: stateless access */ 489 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 490 msg_type, 491 3, /* mlen */ 492 true, /* header present */ 493 false, /* pixel scoreboard */ 494 write_commit, /* rlen */ 495 false, /* eot */ 496 write_commit); 497} 498 499void 500vec4_visitor::generate_pull_constant_load(vec4_instruction *inst, 501 struct brw_reg dst, 502 struct brw_reg index) 503{ 504 struct brw_reg header = brw_vec8_grf(0, 0); 505 506 gen6_resolve_implied_move(p, &header, inst->base_mrf); 507 508 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D), 509 index); 510 511 uint32_t msg_type; 512 513 if (intel->gen >= 6) 514 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 515 else if (intel->gen == 5 || intel->is_g4x) 516 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 517 else 518 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 519 520 /* Each of the 8 channel enables is considered for whether each 521 * dword is written. 522 */ 523 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 524 brw_set_dest(p, send, dst); 525 brw_set_src0(p, send, header); 526 if (intel->gen < 6) 527 send->header.destreg__conditionalmod = inst->base_mrf; 528 brw_set_dp_read_message(p, send, 529 SURF_INDEX_VERT_CONST_BUFFER, 530 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 531 msg_type, 532 BRW_DATAPORT_READ_TARGET_DATA_CACHE, 533 2, /* mlen */ 534 1 /* rlen */); 535} 536 537void 538vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 539 struct brw_reg dst, 540 struct brw_reg *src) 541{ 542 vec4_instruction *inst = (vec4_instruction *)instruction; 543 544 switch (inst->opcode) { 545 case SHADER_OPCODE_RCP: 546 case SHADER_OPCODE_RSQ: 547 case SHADER_OPCODE_SQRT: 548 case SHADER_OPCODE_EXP2: 549 case SHADER_OPCODE_LOG2: 550 case SHADER_OPCODE_SIN: 551 case SHADER_OPCODE_COS: 552 if (intel->gen >= 6) { 553 generate_math1_gen6(inst, dst, src[0]); 554 } else { 555 generate_math1_gen4(inst, dst, src[0]); 556 } 557 break; 558 559 case SHADER_OPCODE_POW: 560 case SHADER_OPCODE_INT_QUOTIENT: 561 case SHADER_OPCODE_INT_REMAINDER: 562 if (intel->gen >= 6) { 563 generate_math2_gen6(inst, dst, src[0], src[1]); 564 } else { 565 generate_math2_gen4(inst, dst, src[0], src[1]); 566 } 567 break; 568 569 case VS_OPCODE_URB_WRITE: 570 generate_urb_write(inst); 571 break; 572 573 case VS_OPCODE_SCRATCH_READ: 574 generate_scratch_read(inst, dst, src[0]); 575 break; 576 577 case VS_OPCODE_SCRATCH_WRITE: 578 generate_scratch_write(inst, dst, src[0], src[1]); 579 break; 580 581 case VS_OPCODE_PULL_CONSTANT_LOAD: 582 generate_pull_constant_load(inst, dst, src[0]); 583 break; 584 585 default: 586 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 587 fail("unsupported opcode in `%s' in VS\n", 588 brw_opcodes[inst->opcode].name); 589 } else { 590 fail("Unsupported opcode %d in VS", inst->opcode); 591 } 592 } 593} 594 595bool 596vec4_visitor::run() 597{ 598 if (c->key.nr_userclip && !c->key.uses_clip_distance) 599 setup_uniform_clipplane_values(); 600 601 /* Generate VS IR for main(). (the visitor only descends into 602 * functions called "main"). 603 */ 604 visit_instructions(shader->ir); 605 606 emit_urb_writes(); 607 608 /* Before any optimization, push array accesses out to scratch 609 * space where we need them to be. This pass may allocate new 610 * virtual GRFs, so we want to do it early. It also makes sure 611 * that we have reladdr computations available for CSE, since we'll 612 * often do repeated subexpressions for those. 613 */ 614 move_grf_array_access_to_scratch(); 615 move_uniform_array_access_to_pull_constants(); 616 pack_uniform_registers(); 617 move_push_constants_to_pull_constants(); 618 619 bool progress; 620 do { 621 progress = false; 622 progress = dead_code_eliminate() || progress; 623 progress = opt_copy_propagation() || progress; 624 progress = opt_algebraic() || progress; 625 progress = opt_compute_to_mrf() || progress; 626 } while (progress); 627 628 629 if (failed) 630 return false; 631 632 setup_payload(); 633 reg_allocate(); 634 635 if (failed) 636 return false; 637 638 brw_set_access_mode(p, BRW_ALIGN_16); 639 640 generate_code(); 641 642 return !failed; 643} 644 645void 646vec4_visitor::generate_code() 647{ 648 int last_native_inst = 0; 649 const char *last_annotation_string = NULL; 650 ir_instruction *last_annotation_ir = NULL; 651 652 int loop_stack_array_size = 16; 653 int loop_stack_depth = 0; 654 brw_instruction **loop_stack = 655 rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size); 656 int *if_depth_in_loop = 657 rzalloc_array(this->mem_ctx, int, loop_stack_array_size); 658 659 660 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 661 printf("Native code for vertex shader %d:\n", prog->Name); 662 } 663 664 foreach_list(node, &this->instructions) { 665 vec4_instruction *inst = (vec4_instruction *)node; 666 struct brw_reg src[3], dst; 667 668 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 669 if (last_annotation_ir != inst->ir) { 670 last_annotation_ir = inst->ir; 671 if (last_annotation_ir) { 672 printf(" "); 673 last_annotation_ir->print(); 674 printf("\n"); 675 } 676 } 677 if (last_annotation_string != inst->annotation) { 678 last_annotation_string = inst->annotation; 679 if (last_annotation_string) 680 printf(" %s\n", last_annotation_string); 681 } 682 } 683 684 for (unsigned int i = 0; i < 3; i++) { 685 src[i] = inst->get_src(i); 686 } 687 dst = inst->get_dst(); 688 689 brw_set_conditionalmod(p, inst->conditional_mod); 690 brw_set_predicate_control(p, inst->predicate); 691 brw_set_predicate_inverse(p, inst->predicate_inverse); 692 brw_set_saturate(p, inst->saturate); 693 694 switch (inst->opcode) { 695 case BRW_OPCODE_MOV: 696 brw_MOV(p, dst, src[0]); 697 break; 698 case BRW_OPCODE_ADD: 699 brw_ADD(p, dst, src[0], src[1]); 700 break; 701 case BRW_OPCODE_MUL: 702 brw_MUL(p, dst, src[0], src[1]); 703 break; 704 case BRW_OPCODE_MACH: 705 brw_set_acc_write_control(p, 1); 706 brw_MACH(p, dst, src[0], src[1]); 707 brw_set_acc_write_control(p, 0); 708 break; 709 710 case BRW_OPCODE_FRC: 711 brw_FRC(p, dst, src[0]); 712 break; 713 case BRW_OPCODE_RNDD: 714 brw_RNDD(p, dst, src[0]); 715 break; 716 case BRW_OPCODE_RNDE: 717 brw_RNDE(p, dst, src[0]); 718 break; 719 case BRW_OPCODE_RNDZ: 720 brw_RNDZ(p, dst, src[0]); 721 break; 722 723 case BRW_OPCODE_AND: 724 brw_AND(p, dst, src[0], src[1]); 725 break; 726 case BRW_OPCODE_OR: 727 brw_OR(p, dst, src[0], src[1]); 728 break; 729 case BRW_OPCODE_XOR: 730 brw_XOR(p, dst, src[0], src[1]); 731 break; 732 case BRW_OPCODE_NOT: 733 brw_NOT(p, dst, src[0]); 734 break; 735 case BRW_OPCODE_ASR: 736 brw_ASR(p, dst, src[0], src[1]); 737 break; 738 case BRW_OPCODE_SHR: 739 brw_SHR(p, dst, src[0], src[1]); 740 break; 741 case BRW_OPCODE_SHL: 742 brw_SHL(p, dst, src[0], src[1]); 743 break; 744 745 case BRW_OPCODE_CMP: 746 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 747 break; 748 case BRW_OPCODE_SEL: 749 brw_SEL(p, dst, src[0], src[1]); 750 break; 751 752 case BRW_OPCODE_DP4: 753 brw_DP4(p, dst, src[0], src[1]); 754 break; 755 756 case BRW_OPCODE_DP3: 757 brw_DP3(p, dst, src[0], src[1]); 758 break; 759 760 case BRW_OPCODE_DP2: 761 brw_DP2(p, dst, src[0], src[1]); 762 break; 763 764 case BRW_OPCODE_IF: 765 if (inst->src[0].file != BAD_FILE) { 766 /* The instruction has an embedded compare (only allowed on gen6) */ 767 assert(intel->gen == 6); 768 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 769 } else { 770 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 771 brw_inst->header.predicate_control = inst->predicate; 772 } 773 if_depth_in_loop[loop_stack_depth]++; 774 break; 775 776 case BRW_OPCODE_ELSE: 777 brw_ELSE(p); 778 break; 779 case BRW_OPCODE_ENDIF: 780 brw_ENDIF(p); 781 if_depth_in_loop[loop_stack_depth]--; 782 break; 783 784 case BRW_OPCODE_DO: 785 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 786 if (loop_stack_array_size <= loop_stack_depth) { 787 loop_stack_array_size *= 2; 788 loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *, 789 loop_stack_array_size); 790 if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int, 791 loop_stack_array_size); 792 } 793 if_depth_in_loop[loop_stack_depth] = 0; 794 break; 795 796 case BRW_OPCODE_BREAK: 797 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 798 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 799 break; 800 case BRW_OPCODE_CONTINUE: 801 /* FINISHME: We need to write the loop instruction support still. */ 802 if (intel->gen >= 6) 803 gen6_CONT(p, loop_stack[loop_stack_depth - 1]); 804 else 805 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 806 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 807 break; 808 809 case BRW_OPCODE_WHILE: { 810 struct brw_instruction *inst0, *inst1; 811 GLuint br = 1; 812 813 if (intel->gen >= 5) 814 br = 2; 815 816 assert(loop_stack_depth > 0); 817 loop_stack_depth--; 818 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 819 if (intel->gen < 6) { 820 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 821 while (inst0 > loop_stack[loop_stack_depth]) { 822 inst0--; 823 if (inst0->header.opcode == BRW_OPCODE_BREAK && 824 inst0->bits3.if_else.jump_count == 0) { 825 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 826 } 827 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 828 inst0->bits3.if_else.jump_count == 0) { 829 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 830 } 831 } 832 } 833 } 834 break; 835 836 default: 837 generate_vs_instruction(inst, dst, src); 838 break; 839 } 840 841 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 842 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 843 if (0) { 844 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 845 ((uint32_t *)&p->store[i])[3], 846 ((uint32_t *)&p->store[i])[2], 847 ((uint32_t *)&p->store[i])[1], 848 ((uint32_t *)&p->store[i])[0]); 849 } 850 brw_disasm(stdout, &p->store[i], intel->gen); 851 } 852 } 853 854 last_native_inst = p->nr_insn; 855 } 856 857 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 858 printf("\n"); 859 } 860 861 ralloc_free(loop_stack); 862 ralloc_free(if_depth_in_loop); 863 864 brw_set_uip_jip(p); 865 866 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 867 * emit issues, it doesn't get the jump distances into the output, 868 * which is often something we want to debug. So this is here in 869 * case you're doing that. 870 */ 871 if (0) { 872 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 873 for (unsigned int i = 0; i < p->nr_insn; i++) { 874 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 875 ((uint32_t *)&p->store[i])[3], 876 ((uint32_t *)&p->store[i])[2], 877 ((uint32_t *)&p->store[i])[1], 878 ((uint32_t *)&p->store[i])[0]); 879 brw_disasm(stdout, &p->store[i], intel->gen); 880 } 881 } 882 } 883} 884 885extern "C" { 886 887bool 888brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 889{ 890 if (!prog) 891 return false; 892 893 struct brw_shader *shader = 894 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 895 if (!shader) 896 return false; 897 898 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 899 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 900 _mesa_print_ir(shader->ir, NULL); 901 printf("\n\n"); 902 } 903 904 vec4_visitor v(c, prog, shader); 905 if (!v.run()) { 906 prog->LinkStatus = GL_FALSE; 907 ralloc_strcat(&prog->InfoLog, v.fail_msg); 908 return false; 909 } 910 911 return true; 912} 913 914} /* extern "C" */ 915 916} /* namespace brw */ 917