brw_vec4_emit.cpp revision 81a0b2166991a3015f8336e184c34cf6a92adfe0
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28}; 29 30using namespace brw; 31 32namespace brw { 33 34int 35vec4_visitor::setup_attributes(int payload_reg) 36{ 37 int nr_attributes; 38 int attribute_map[VERT_ATTRIB_MAX]; 39 40 nr_attributes = 0; 41 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 42 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 43 attribute_map[i] = payload_reg + nr_attributes; 44 nr_attributes++; 45 } 46 } 47 48 foreach_list(node, &this->instructions) { 49 vec4_instruction *inst = (vec4_instruction *)node; 50 51 /* We have to support ATTR as a destination for GL_FIXED fixup. */ 52 if (inst->dst.file == ATTR) { 53 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; 54 55 struct brw_reg reg = brw_vec8_grf(grf, 0); 56 reg.dw1.bits.writemask = inst->dst.writemask; 57 58 inst->dst.file = HW_REG; 59 inst->dst.fixed_hw_reg = reg; 60 } 61 62 for (int i = 0; i < 3; i++) { 63 if (inst->src[i].file != ATTR) 64 continue; 65 66 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 67 68 struct brw_reg reg = brw_vec8_grf(grf, 0); 69 reg.dw1.bits.swizzle = inst->src[i].swizzle; 70 if (inst->src[i].abs) 71 reg = brw_abs(reg); 72 if (inst->src[i].negate) 73 reg = negate(reg); 74 75 inst->src[i].file = HW_REG; 76 inst->src[i].fixed_hw_reg = reg; 77 } 78 } 79 80 /* The BSpec says we always have to read at least one thing from 81 * the VF, and it appears that the hardware wedges otherwise. 82 */ 83 if (nr_attributes == 0) 84 nr_attributes = 1; 85 86 prog_data->urb_read_length = (nr_attributes + 1) / 2; 87 88 return payload_reg + nr_attributes; 89} 90 91int 92vec4_visitor::setup_uniforms(int reg) 93{ 94 /* User clip planes from curbe: 95 */ 96 if (c->key.nr_userclip) { 97 if (intel->gen >= 6) { 98 for (int i = 0; i < c->key.nr_userclip; i++) { 99 c->userplane[i] = stride(brw_vec4_grf(reg + i / 2, 100 (i % 2) * 4), 0, 4, 1); 101 } 102 reg += ALIGN(c->key.nr_userclip, 2) / 2; 103 } else { 104 for (int i = 0; i < c->key.nr_userclip; i++) { 105 c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2, 106 (i % 2) * 4), 0, 4, 1); 107 } 108 reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2; 109 } 110 } 111 112 /* The pre-gen6 VS requires that some push constants get loaded no 113 * matter what, or the GPU would hang. 114 */ 115 if (intel->gen < 6 && this->uniforms == 0) { 116 this->uniform_vector_size[this->uniforms] = 1; 117 118 for (unsigned int i = 0; i < 4; i++) { 119 unsigned int slot = this->uniforms * 4 + i; 120 121 c->prog_data.param[slot] = NULL; 122 } 123 124 this->uniforms++; 125 reg++; 126 } else { 127 reg += ALIGN(uniforms, 2) / 2; 128 } 129 130 c->prog_data.nr_params = this->uniforms * 4; 131 132 c->prog_data.curb_read_length = reg - 1; 133 c->prog_data.uses_new_param_layout = true; 134 135 return reg; 136} 137 138void 139vec4_visitor::setup_payload(void) 140{ 141 int reg = 0; 142 143 /* The payload always contains important data in g0, which contains 144 * the URB handles that are passed on to the URB write at the end 145 * of the thread. So, we always start push constants at g1. 146 */ 147 reg++; 148 149 reg = setup_uniforms(reg); 150 151 reg = setup_attributes(reg); 152 153 this->first_non_payload_grf = reg; 154} 155 156struct brw_reg 157vec4_instruction::get_dst(void) 158{ 159 struct brw_reg brw_reg; 160 161 switch (dst.file) { 162 case GRF: 163 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 164 brw_reg = retype(brw_reg, dst.type); 165 brw_reg.dw1.bits.writemask = dst.writemask; 166 break; 167 168 case HW_REG: 169 brw_reg = dst.fixed_hw_reg; 170 break; 171 172 case BAD_FILE: 173 brw_reg = brw_null_reg(); 174 break; 175 176 default: 177 assert(!"not reached"); 178 brw_reg = brw_null_reg(); 179 break; 180 } 181 return brw_reg; 182} 183 184struct brw_reg 185vec4_instruction::get_src(int i) 186{ 187 struct brw_reg brw_reg; 188 189 switch (src[i].file) { 190 case GRF: 191 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 192 brw_reg = retype(brw_reg, src[i].type); 193 brw_reg.dw1.bits.swizzle = src[i].swizzle; 194 if (src[i].abs) 195 brw_reg = brw_abs(brw_reg); 196 if (src[i].negate) 197 brw_reg = negate(brw_reg); 198 break; 199 200 case IMM: 201 switch (src[i].type) { 202 case BRW_REGISTER_TYPE_F: 203 brw_reg = brw_imm_f(src[i].imm.f); 204 break; 205 case BRW_REGISTER_TYPE_D: 206 brw_reg = brw_imm_d(src[i].imm.i); 207 break; 208 case BRW_REGISTER_TYPE_UD: 209 brw_reg = brw_imm_ud(src[i].imm.u); 210 break; 211 default: 212 assert(!"not reached"); 213 brw_reg = brw_null_reg(); 214 break; 215 } 216 break; 217 218 case UNIFORM: 219 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 220 ((src[i].reg + src[i].reg_offset) % 2) * 4), 221 0, 4, 1); 222 brw_reg = retype(brw_reg, src[i].type); 223 brw_reg.dw1.bits.swizzle = src[i].swizzle; 224 if (src[i].abs) 225 brw_reg = brw_abs(brw_reg); 226 if (src[i].negate) 227 brw_reg = negate(brw_reg); 228 229 /* This should have been moved to pull constants. */ 230 assert(!src[i].reladdr); 231 break; 232 233 case HW_REG: 234 brw_reg = src[i].fixed_hw_reg; 235 break; 236 237 case BAD_FILE: 238 /* Probably unused. */ 239 brw_reg = brw_null_reg(); 240 break; 241 case ATTR: 242 default: 243 assert(!"not reached"); 244 brw_reg = brw_null_reg(); 245 break; 246 } 247 248 return brw_reg; 249} 250 251void 252vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 253 struct brw_reg dst, 254 struct brw_reg src) 255{ 256 brw_math(p, 257 dst, 258 brw_math_function(inst->opcode), 259 BRW_MATH_SATURATE_NONE, 260 inst->base_mrf, 261 src, 262 BRW_MATH_DATA_SCALAR, 263 BRW_MATH_PRECISION_FULL); 264} 265 266static void 267check_gen6_math_src_arg(struct brw_reg src) 268{ 269 /* Source swizzles are ignored. */ 270 assert(!src.abs); 271 assert(!src.negate); 272 assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); 273} 274 275void 276vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 277 struct brw_reg dst, 278 struct brw_reg src) 279{ 280 /* Can't do writemask because math can't be align16. */ 281 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 282 check_gen6_math_src_arg(src); 283 284 brw_set_access_mode(p, BRW_ALIGN_1); 285 brw_math(p, 286 dst, 287 brw_math_function(inst->opcode), 288 BRW_MATH_SATURATE_NONE, 289 inst->base_mrf, 290 src, 291 BRW_MATH_DATA_SCALAR, 292 BRW_MATH_PRECISION_FULL); 293 brw_set_access_mode(p, BRW_ALIGN_16); 294} 295 296void 297vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 298 struct brw_reg dst, 299 struct brw_reg src0, 300 struct brw_reg src1) 301{ 302 /* Can't do writemask because math can't be align16. */ 303 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 304 /* Source swizzles are ignored. */ 305 check_gen6_math_src_arg(src0); 306 check_gen6_math_src_arg(src1); 307 308 brw_set_access_mode(p, BRW_ALIGN_1); 309 brw_math2(p, 310 dst, 311 brw_math_function(inst->opcode), 312 src0, src1); 313 brw_set_access_mode(p, BRW_ALIGN_16); 314} 315 316void 317vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 318 struct brw_reg dst, 319 struct brw_reg src0, 320 struct brw_reg src1) 321{ 322 /* Can't do writemask because math can't be align16. */ 323 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 324 325 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1); 326 327 brw_set_access_mode(p, BRW_ALIGN_1); 328 brw_math(p, 329 dst, 330 brw_math_function(inst->opcode), 331 BRW_MATH_SATURATE_NONE, 332 inst->base_mrf, 333 src0, 334 BRW_MATH_DATA_VECTOR, 335 BRW_MATH_PRECISION_FULL); 336 brw_set_access_mode(p, BRW_ALIGN_16); 337} 338 339void 340vec4_visitor::generate_urb_write(vec4_instruction *inst) 341{ 342 brw_urb_WRITE(p, 343 brw_null_reg(), /* dest */ 344 inst->base_mrf, /* starting mrf reg nr */ 345 brw_vec8_grf(0, 0), /* src */ 346 false, /* allocate */ 347 true, /* used */ 348 inst->mlen, 349 0, /* response len */ 350 inst->eot, /* eot */ 351 inst->eot, /* writes complete */ 352 inst->offset, /* urb destination offset */ 353 BRW_URB_SWIZZLE_INTERLEAVE); 354} 355 356void 357vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 358 struct brw_reg index) 359{ 360 int second_vertex_offset; 361 362 if (intel->gen >= 6) 363 second_vertex_offset = 1; 364 else 365 second_vertex_offset = 16; 366 367 m1 = retype(m1, BRW_REGISTER_TYPE_D); 368 369 /* Set up M1 (message payload). Only the block offsets in M1.0 and 370 * M1.4 are used, and the rest are ignored. 371 */ 372 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 373 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 374 struct brw_reg index_0 = suboffset(vec1(index), 0); 375 struct brw_reg index_4 = suboffset(vec1(index), 4); 376 377 brw_push_insn_state(p); 378 brw_set_mask_control(p, BRW_MASK_DISABLE); 379 brw_set_access_mode(p, BRW_ALIGN_1); 380 381 brw_MOV(p, m1_0, index_0); 382 383 brw_set_predicate_inverse(p, true); 384 if (index.file == BRW_IMMEDIATE_VALUE) { 385 index_4.dw1.ud++; 386 brw_MOV(p, m1_4, index_4); 387 } else { 388 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 389 } 390 391 brw_pop_insn_state(p); 392} 393 394void 395vec4_visitor::generate_scratch_read(vec4_instruction *inst, 396 struct brw_reg dst, 397 struct brw_reg index) 398{ 399 if (intel->gen >= 6) { 400 brw_push_insn_state(p); 401 brw_set_mask_control(p, BRW_MASK_DISABLE); 402 brw_MOV(p, 403 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D), 404 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D)); 405 brw_pop_insn_state(p); 406 } 407 408 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 409 index); 410 411 uint32_t msg_type; 412 413 if (intel->gen >= 6) 414 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 415 else if (intel->gen == 5 || intel->is_g4x) 416 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 417 else 418 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 419 420 /* Each of the 8 channel enables is considered for whether each 421 * dword is written. 422 */ 423 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 424 brw_set_dest(p, send, dst); 425 brw_set_src0(p, send, brw_message_reg(inst->base_mrf)); 426 brw_set_dp_read_message(p, send, 427 255, /* binding table index: stateless access */ 428 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 429 msg_type, 430 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 431 2, /* mlen */ 432 1 /* rlen */); 433} 434 435void 436vec4_visitor::generate_scratch_write(vec4_instruction *inst, 437 struct brw_reg dst, 438 struct brw_reg src, 439 struct brw_reg index) 440{ 441 /* If the instruction is predicated, we'll predicate the send, not 442 * the header setup. 443 */ 444 brw_set_predicate_control(p, false); 445 446 if (intel->gen >= 6) { 447 brw_push_insn_state(p); 448 brw_set_mask_control(p, BRW_MASK_DISABLE); 449 brw_MOV(p, 450 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D), 451 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D)); 452 brw_pop_insn_state(p); 453 } 454 455 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 456 index); 457 458 brw_MOV(p, 459 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 460 retype(src, BRW_REGISTER_TYPE_D)); 461 462 uint32_t msg_type; 463 464 if (intel->gen >= 6) 465 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 466 else 467 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 468 469 brw_set_predicate_control(p, inst->predicate); 470 471 /* Each of the 8 channel enables is considered for whether each 472 * dword is written. 473 */ 474 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 475 brw_set_dest(p, send, dst); 476 brw_set_src0(p, send, brw_message_reg(inst->base_mrf)); 477 brw_set_dp_write_message(p, send, 478 255, /* binding table index: stateless access */ 479 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 480 msg_type, 481 3, /* mlen */ 482 true, /* header present */ 483 false, /* pixel scoreboard */ 484 0, /* rlen */ 485 false, /* eot */ 486 false /* commit */); 487} 488 489void 490vec4_visitor::generate_pull_constant_load(vec4_instruction *inst, 491 struct brw_reg dst, 492 struct brw_reg index) 493{ 494 struct brw_reg header = brw_vec8_grf(0, 0); 495 496 gen6_resolve_implied_move(p, &header, inst->base_mrf); 497 498 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D), 499 index); 500 501 uint32_t msg_type; 502 503 if (intel->gen >= 6) 504 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 505 else if (intel->gen == 5 || intel->is_g4x) 506 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 507 else 508 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 509 510 /* Each of the 8 channel enables is considered for whether each 511 * dword is written. 512 */ 513 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 514 brw_set_dest(p, send, dst); 515 brw_set_src0(p, send, header); 516 brw_set_dp_read_message(p, send, 517 SURF_INDEX_VERT_CONST_BUFFER, 518 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 519 msg_type, 520 BRW_DATAPORT_READ_TARGET_DATA_CACHE, 521 2, /* mlen */ 522 1 /* rlen */); 523} 524 525void 526vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 527 struct brw_reg dst, 528 struct brw_reg *src) 529{ 530 vec4_instruction *inst = (vec4_instruction *)instruction; 531 532 switch (inst->opcode) { 533 case SHADER_OPCODE_RCP: 534 case SHADER_OPCODE_RSQ: 535 case SHADER_OPCODE_SQRT: 536 case SHADER_OPCODE_EXP2: 537 case SHADER_OPCODE_LOG2: 538 case SHADER_OPCODE_SIN: 539 case SHADER_OPCODE_COS: 540 if (intel->gen >= 6) { 541 generate_math1_gen6(inst, dst, src[0]); 542 } else { 543 generate_math1_gen4(inst, dst, src[0]); 544 } 545 break; 546 547 case SHADER_OPCODE_POW: 548 if (intel->gen >= 6) { 549 generate_math2_gen6(inst, dst, src[0], src[1]); 550 } else { 551 generate_math2_gen4(inst, dst, src[0], src[1]); 552 } 553 break; 554 555 case VS_OPCODE_URB_WRITE: 556 generate_urb_write(inst); 557 break; 558 559 case VS_OPCODE_SCRATCH_READ: 560 generate_scratch_read(inst, dst, src[0]); 561 break; 562 563 case VS_OPCODE_SCRATCH_WRITE: 564 generate_scratch_write(inst, dst, src[0], src[1]); 565 break; 566 567 case VS_OPCODE_PULL_CONSTANT_LOAD: 568 generate_pull_constant_load(inst, dst, src[0]); 569 break; 570 571 default: 572 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 573 fail("unsupported opcode in `%s' in VS\n", 574 brw_opcodes[inst->opcode].name); 575 } else { 576 fail("Unsupported opcode %d in VS", inst->opcode); 577 } 578 } 579} 580 581bool 582vec4_visitor::run() 583{ 584 /* Generate VS IR for main(). (the visitor only descends into 585 * functions called "main"). 586 */ 587 visit_instructions(shader->ir); 588 589 emit_urb_writes(); 590 591 /* Before any optimization, push array accesses out to scratch 592 * space where we need them to be. This pass may allocate new 593 * virtual GRFs, so we want to do it early. It also makes sure 594 * that we have reladdr computations available for CSE, since we'll 595 * often do repeated subexpressions for those. 596 */ 597 move_grf_array_access_to_scratch(); 598 move_uniform_array_access_to_pull_constants(); 599 600 bool progress; 601 do { 602 progress = false; 603 progress = dead_code_eliminate() || progress; 604 } while (progress); 605 606 pack_uniform_registers(); 607 608 if (failed) 609 return false; 610 611 setup_payload(); 612 reg_allocate(); 613 614 if (failed) 615 return false; 616 617 brw_set_access_mode(p, BRW_ALIGN_16); 618 619 generate_code(); 620 621 return !failed; 622} 623 624void 625vec4_visitor::generate_code() 626{ 627 int last_native_inst = 0; 628 const char *last_annotation_string = NULL; 629 ir_instruction *last_annotation_ir = NULL; 630 631 int loop_stack_array_size = 16; 632 int loop_stack_depth = 0; 633 brw_instruction **loop_stack = 634 rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size); 635 int *if_depth_in_loop = 636 rzalloc_array(this->mem_ctx, int, loop_stack_array_size); 637 638 639 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 640 printf("Native code for vertex shader %d:\n", prog->Name); 641 } 642 643 foreach_list(node, &this->instructions) { 644 vec4_instruction *inst = (vec4_instruction *)node; 645 struct brw_reg src[3], dst; 646 647 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 648 if (last_annotation_ir != inst->ir) { 649 last_annotation_ir = inst->ir; 650 if (last_annotation_ir) { 651 printf(" "); 652 last_annotation_ir->print(); 653 printf("\n"); 654 } 655 } 656 if (last_annotation_string != inst->annotation) { 657 last_annotation_string = inst->annotation; 658 if (last_annotation_string) 659 printf(" %s\n", last_annotation_string); 660 } 661 } 662 663 for (unsigned int i = 0; i < 3; i++) { 664 src[i] = inst->get_src(i); 665 } 666 dst = inst->get_dst(); 667 668 brw_set_conditionalmod(p, inst->conditional_mod); 669 brw_set_predicate_control(p, inst->predicate); 670 brw_set_predicate_inverse(p, inst->predicate_inverse); 671 brw_set_saturate(p, inst->saturate); 672 673 switch (inst->opcode) { 674 case BRW_OPCODE_MOV: 675 brw_MOV(p, dst, src[0]); 676 break; 677 case BRW_OPCODE_ADD: 678 brw_ADD(p, dst, src[0], src[1]); 679 break; 680 case BRW_OPCODE_MUL: 681 brw_MUL(p, dst, src[0], src[1]); 682 break; 683 case BRW_OPCODE_MACH: 684 brw_set_acc_write_control(p, 1); 685 brw_MACH(p, dst, src[0], src[1]); 686 brw_set_acc_write_control(p, 0); 687 break; 688 689 case BRW_OPCODE_FRC: 690 brw_FRC(p, dst, src[0]); 691 break; 692 case BRW_OPCODE_RNDD: 693 brw_RNDD(p, dst, src[0]); 694 break; 695 case BRW_OPCODE_RNDE: 696 brw_RNDE(p, dst, src[0]); 697 break; 698 case BRW_OPCODE_RNDZ: 699 brw_RNDZ(p, dst, src[0]); 700 break; 701 702 case BRW_OPCODE_AND: 703 brw_AND(p, dst, src[0], src[1]); 704 break; 705 case BRW_OPCODE_OR: 706 brw_OR(p, dst, src[0], src[1]); 707 break; 708 case BRW_OPCODE_XOR: 709 brw_XOR(p, dst, src[0], src[1]); 710 break; 711 case BRW_OPCODE_NOT: 712 brw_NOT(p, dst, src[0]); 713 break; 714 case BRW_OPCODE_ASR: 715 brw_ASR(p, dst, src[0], src[1]); 716 break; 717 case BRW_OPCODE_SHR: 718 brw_SHR(p, dst, src[0], src[1]); 719 break; 720 case BRW_OPCODE_SHL: 721 brw_SHL(p, dst, src[0], src[1]); 722 break; 723 724 case BRW_OPCODE_CMP: 725 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 726 break; 727 case BRW_OPCODE_SEL: 728 brw_SEL(p, dst, src[0], src[1]); 729 break; 730 731 case BRW_OPCODE_DP4: 732 brw_DP4(p, dst, src[0], src[1]); 733 break; 734 735 case BRW_OPCODE_DP3: 736 brw_DP3(p, dst, src[0], src[1]); 737 break; 738 739 case BRW_OPCODE_DP2: 740 brw_DP2(p, dst, src[0], src[1]); 741 break; 742 743 case BRW_OPCODE_IF: 744 if (inst->src[0].file != BAD_FILE) { 745 /* The instruction has an embedded compare (only allowed on gen6) */ 746 assert(intel->gen == 6); 747 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 748 } else { 749 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 750 brw_inst->header.predicate_control = inst->predicate; 751 } 752 if_depth_in_loop[loop_stack_depth]++; 753 break; 754 755 case BRW_OPCODE_ELSE: 756 brw_ELSE(p); 757 break; 758 case BRW_OPCODE_ENDIF: 759 brw_ENDIF(p); 760 if_depth_in_loop[loop_stack_depth]--; 761 break; 762 763 case BRW_OPCODE_DO: 764 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 765 if (loop_stack_array_size <= loop_stack_depth) { 766 loop_stack_array_size *= 2; 767 loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *, 768 loop_stack_array_size); 769 if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int, 770 loop_stack_array_size); 771 } 772 if_depth_in_loop[loop_stack_depth] = 0; 773 break; 774 775 case BRW_OPCODE_BREAK: 776 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 777 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 778 break; 779 case BRW_OPCODE_CONTINUE: 780 /* FINISHME: We need to write the loop instruction support still. */ 781 if (intel->gen >= 6) 782 gen6_CONT(p, loop_stack[loop_stack_depth - 1]); 783 else 784 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 785 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 786 break; 787 788 case BRW_OPCODE_WHILE: { 789 struct brw_instruction *inst0, *inst1; 790 GLuint br = 1; 791 792 if (intel->gen >= 5) 793 br = 2; 794 795 assert(loop_stack_depth > 0); 796 loop_stack_depth--; 797 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 798 if (intel->gen < 6) { 799 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 800 while (inst0 > loop_stack[loop_stack_depth]) { 801 inst0--; 802 if (inst0->header.opcode == BRW_OPCODE_BREAK && 803 inst0->bits3.if_else.jump_count == 0) { 804 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 805 } 806 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 807 inst0->bits3.if_else.jump_count == 0) { 808 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 809 } 810 } 811 } 812 } 813 break; 814 815 default: 816 generate_vs_instruction(inst, dst, src); 817 break; 818 } 819 820 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 821 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 822 if (0) { 823 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 824 ((uint32_t *)&p->store[i])[3], 825 ((uint32_t *)&p->store[i])[2], 826 ((uint32_t *)&p->store[i])[1], 827 ((uint32_t *)&p->store[i])[0]); 828 } 829 brw_disasm(stdout, &p->store[i], intel->gen); 830 } 831 } 832 833 last_native_inst = p->nr_insn; 834 } 835 836 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 837 printf("\n"); 838 } 839 840 ralloc_free(loop_stack); 841 ralloc_free(if_depth_in_loop); 842 843 brw_set_uip_jip(p); 844 845 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 846 * emit issues, it doesn't get the jump distances into the output, 847 * which is often something we want to debug. So this is here in 848 * case you're doing that. 849 */ 850 if (0) { 851 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 852 for (unsigned int i = 0; i < p->nr_insn; i++) { 853 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 854 ((uint32_t *)&p->store[i])[3], 855 ((uint32_t *)&p->store[i])[2], 856 ((uint32_t *)&p->store[i])[1], 857 ((uint32_t *)&p->store[i])[0]); 858 brw_disasm(stdout, &p->store[i], intel->gen); 859 } 860 } 861 } 862} 863 864extern "C" { 865 866bool 867brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 868{ 869 if (!prog) 870 return false; 871 872 struct brw_shader *shader = 873 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 874 if (!shader) 875 return false; 876 877 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 878 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 879 _mesa_print_ir(shader->ir, NULL); 880 printf("\n\n"); 881 } 882 883 vec4_visitor v(c, prog, shader); 884 if (!v.run()) { 885 prog->LinkStatus = GL_FALSE; 886 ralloc_strcat(&prog->InfoLog, v.fail_msg); 887 return false; 888 } 889 890 return true; 891} 892 893} /* extern "C" */ 894 895} /* namespace brw */ 896