brw_vec4_emit.cpp revision 88612e2c1b1580b92d229ec6d2236fe07b32e060
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28}; 29 30using namespace brw; 31 32namespace brw { 33 34int 35vec4_visitor::setup_attributes(int payload_reg) 36{ 37 int nr_attributes; 38 int attribute_map[VERT_ATTRIB_MAX]; 39 40 nr_attributes = 0; 41 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 42 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 43 attribute_map[i] = payload_reg + nr_attributes; 44 nr_attributes++; 45 } 46 } 47 48 foreach_list(node, &this->instructions) { 49 vec4_instruction *inst = (vec4_instruction *)node; 50 51 /* We have to support ATTR as a destination for GL_FIXED fixup. */ 52 if (inst->dst.file == ATTR) { 53 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; 54 55 struct brw_reg reg = brw_vec8_grf(grf, 0); 56 reg.dw1.bits.writemask = inst->dst.writemask; 57 58 inst->dst.file = HW_REG; 59 inst->dst.fixed_hw_reg = reg; 60 } 61 62 for (int i = 0; i < 3; i++) { 63 if (inst->src[i].file != ATTR) 64 continue; 65 66 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 67 68 struct brw_reg reg = brw_vec8_grf(grf, 0); 69 reg.dw1.bits.swizzle = inst->src[i].swizzle; 70 if (inst->src[i].abs) 71 reg = brw_abs(reg); 72 if (inst->src[i].negate) 73 reg = negate(reg); 74 75 inst->src[i].file = HW_REG; 76 inst->src[i].fixed_hw_reg = reg; 77 } 78 } 79 80 /* The BSpec says we always have to read at least one thing from 81 * the VF, and it appears that the hardware wedges otherwise. 82 */ 83 if (nr_attributes == 0) 84 nr_attributes = 1; 85 86 prog_data->urb_read_length = (nr_attributes + 1) / 2; 87 88 return payload_reg + nr_attributes; 89} 90 91int 92vec4_visitor::setup_uniforms(int reg) 93{ 94 /* User clip planes from curbe: 95 */ 96 if (c->key.nr_userclip) { 97 if (intel->gen >= 6) { 98 for (int i = 0; i < c->key.nr_userclip; i++) { 99 c->userplane[i] = stride(brw_vec4_grf(reg + i / 2, 100 (i % 2) * 4), 0, 4, 1); 101 } 102 reg += ALIGN(c->key.nr_userclip, 2) / 2; 103 } else { 104 for (int i = 0; i < c->key.nr_userclip; i++) { 105 c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2, 106 (i % 2) * 4), 0, 4, 1); 107 } 108 reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2; 109 } 110 } 111 112 /* The pre-gen6 VS requires that some push constants get loaded no 113 * matter what, or the GPU would hang. 114 */ 115 if (intel->gen < 6 && this->uniforms == 0) { 116 this->uniform_vector_size[this->uniforms] = 1; 117 118 for (unsigned int i = 0; i < 4; i++) { 119 unsigned int slot = this->uniforms * 4 + i; 120 static float zero = 0.0; 121 c->prog_data.param[slot] = &zero; 122 } 123 124 this->uniforms++; 125 reg++; 126 } else { 127 reg += ALIGN(uniforms, 2) / 2; 128 } 129 130 c->prog_data.nr_params = this->uniforms * 4; 131 132 c->prog_data.curb_read_length = reg - 1; 133 c->prog_data.uses_new_param_layout = true; 134 135 return reg; 136} 137 138void 139vec4_visitor::setup_payload(void) 140{ 141 int reg = 0; 142 143 /* The payload always contains important data in g0, which contains 144 * the URB handles that are passed on to the URB write at the end 145 * of the thread. So, we always start push constants at g1. 146 */ 147 reg++; 148 149 reg = setup_uniforms(reg); 150 151 reg = setup_attributes(reg); 152 153 this->first_non_payload_grf = reg; 154} 155 156struct brw_reg 157vec4_instruction::get_dst(void) 158{ 159 struct brw_reg brw_reg; 160 161 switch (dst.file) { 162 case GRF: 163 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 164 brw_reg = retype(brw_reg, dst.type); 165 brw_reg.dw1.bits.writemask = dst.writemask; 166 break; 167 168 case HW_REG: 169 brw_reg = dst.fixed_hw_reg; 170 break; 171 172 case BAD_FILE: 173 brw_reg = brw_null_reg(); 174 break; 175 176 default: 177 assert(!"not reached"); 178 brw_reg = brw_null_reg(); 179 break; 180 } 181 return brw_reg; 182} 183 184struct brw_reg 185vec4_instruction::get_src(int i) 186{ 187 struct brw_reg brw_reg; 188 189 switch (src[i].file) { 190 case GRF: 191 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 192 brw_reg = retype(brw_reg, src[i].type); 193 brw_reg.dw1.bits.swizzle = src[i].swizzle; 194 if (src[i].abs) 195 brw_reg = brw_abs(brw_reg); 196 if (src[i].negate) 197 brw_reg = negate(brw_reg); 198 break; 199 200 case IMM: 201 switch (src[i].type) { 202 case BRW_REGISTER_TYPE_F: 203 brw_reg = brw_imm_f(src[i].imm.f); 204 break; 205 case BRW_REGISTER_TYPE_D: 206 brw_reg = brw_imm_d(src[i].imm.i); 207 break; 208 case BRW_REGISTER_TYPE_UD: 209 brw_reg = brw_imm_ud(src[i].imm.u); 210 break; 211 default: 212 assert(!"not reached"); 213 brw_reg = brw_null_reg(); 214 break; 215 } 216 break; 217 218 case UNIFORM: 219 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 220 ((src[i].reg + src[i].reg_offset) % 2) * 4), 221 0, 4, 1); 222 brw_reg = retype(brw_reg, src[i].type); 223 brw_reg.dw1.bits.swizzle = src[i].swizzle; 224 if (src[i].abs) 225 brw_reg = brw_abs(brw_reg); 226 if (src[i].negate) 227 brw_reg = negate(brw_reg); 228 229 /* This should have been moved to pull constants. */ 230 assert(!src[i].reladdr); 231 break; 232 233 case HW_REG: 234 brw_reg = src[i].fixed_hw_reg; 235 break; 236 237 case BAD_FILE: 238 /* Probably unused. */ 239 brw_reg = brw_null_reg(); 240 break; 241 case ATTR: 242 default: 243 assert(!"not reached"); 244 brw_reg = brw_null_reg(); 245 break; 246 } 247 248 return brw_reg; 249} 250 251void 252vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 253 struct brw_reg dst, 254 struct brw_reg src) 255{ 256 brw_math(p, 257 dst, 258 brw_math_function(inst->opcode), 259 BRW_MATH_SATURATE_NONE, 260 inst->base_mrf, 261 src, 262 BRW_MATH_DATA_VECTOR, 263 BRW_MATH_PRECISION_FULL); 264} 265 266static void 267check_gen6_math_src_arg(struct brw_reg src) 268{ 269 /* Source swizzles are ignored. */ 270 assert(!src.abs); 271 assert(!src.negate); 272 assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); 273} 274 275void 276vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 277 struct brw_reg dst, 278 struct brw_reg src) 279{ 280 /* Can't do writemask because math can't be align16. */ 281 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 282 check_gen6_math_src_arg(src); 283 284 brw_set_access_mode(p, BRW_ALIGN_1); 285 brw_math(p, 286 dst, 287 brw_math_function(inst->opcode), 288 BRW_MATH_SATURATE_NONE, 289 inst->base_mrf, 290 src, 291 BRW_MATH_DATA_SCALAR, 292 BRW_MATH_PRECISION_FULL); 293 brw_set_access_mode(p, BRW_ALIGN_16); 294} 295 296void 297vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 298 struct brw_reg dst, 299 struct brw_reg src0, 300 struct brw_reg src1) 301{ 302 /* Can't do writemask because math can't be align16. */ 303 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 304 /* Source swizzles are ignored. */ 305 check_gen6_math_src_arg(src0); 306 check_gen6_math_src_arg(src1); 307 308 brw_set_access_mode(p, BRW_ALIGN_1); 309 brw_math2(p, 310 dst, 311 brw_math_function(inst->opcode), 312 src0, src1); 313 brw_set_access_mode(p, BRW_ALIGN_16); 314} 315 316void 317vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 318 struct brw_reg dst, 319 struct brw_reg src0, 320 struct brw_reg src1) 321{ 322 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1); 323 324 brw_math(p, 325 dst, 326 brw_math_function(inst->opcode), 327 BRW_MATH_SATURATE_NONE, 328 inst->base_mrf, 329 src0, 330 BRW_MATH_DATA_VECTOR, 331 BRW_MATH_PRECISION_FULL); 332} 333 334void 335vec4_visitor::generate_urb_write(vec4_instruction *inst) 336{ 337 brw_urb_WRITE(p, 338 brw_null_reg(), /* dest */ 339 inst->base_mrf, /* starting mrf reg nr */ 340 brw_vec8_grf(0, 0), /* src */ 341 false, /* allocate */ 342 true, /* used */ 343 inst->mlen, 344 0, /* response len */ 345 inst->eot, /* eot */ 346 inst->eot, /* writes complete */ 347 inst->offset, /* urb destination offset */ 348 BRW_URB_SWIZZLE_INTERLEAVE); 349} 350 351void 352vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 353 struct brw_reg index) 354{ 355 int second_vertex_offset; 356 357 if (intel->gen >= 6) 358 second_vertex_offset = 1; 359 else 360 second_vertex_offset = 16; 361 362 m1 = retype(m1, BRW_REGISTER_TYPE_D); 363 364 /* Set up M1 (message payload). Only the block offsets in M1.0 and 365 * M1.4 are used, and the rest are ignored. 366 */ 367 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 368 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 369 struct brw_reg index_0 = suboffset(vec1(index), 0); 370 struct brw_reg index_4 = suboffset(vec1(index), 4); 371 372 brw_push_insn_state(p); 373 brw_set_mask_control(p, BRW_MASK_DISABLE); 374 brw_set_access_mode(p, BRW_ALIGN_1); 375 376 brw_MOV(p, m1_0, index_0); 377 378 brw_set_predicate_inverse(p, true); 379 if (index.file == BRW_IMMEDIATE_VALUE) { 380 index_4.dw1.ud += second_vertex_offset; 381 brw_MOV(p, m1_4, index_4); 382 } else { 383 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 384 } 385 386 brw_pop_insn_state(p); 387} 388 389void 390vec4_visitor::generate_scratch_read(vec4_instruction *inst, 391 struct brw_reg dst, 392 struct brw_reg index) 393{ 394 if (intel->gen >= 6) { 395 brw_push_insn_state(p); 396 brw_set_mask_control(p, BRW_MASK_DISABLE); 397 brw_MOV(p, 398 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D), 399 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D)); 400 brw_pop_insn_state(p); 401 } 402 403 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 404 index); 405 406 uint32_t msg_type; 407 408 if (intel->gen >= 6) 409 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 410 else if (intel->gen == 5 || intel->is_g4x) 411 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 412 else 413 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 414 415 /* Each of the 8 channel enables is considered for whether each 416 * dword is written. 417 */ 418 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 419 brw_set_dest(p, send, dst); 420 brw_set_src0(p, send, brw_message_reg(inst->base_mrf)); 421 brw_set_dp_read_message(p, send, 422 255, /* binding table index: stateless access */ 423 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 424 msg_type, 425 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 426 2, /* mlen */ 427 1 /* rlen */); 428} 429 430void 431vec4_visitor::generate_scratch_write(vec4_instruction *inst, 432 struct brw_reg dst, 433 struct brw_reg src, 434 struct brw_reg index) 435{ 436 /* If the instruction is predicated, we'll predicate the send, not 437 * the header setup. 438 */ 439 brw_set_predicate_control(p, false); 440 441 if (intel->gen >= 6) { 442 brw_push_insn_state(p); 443 brw_set_mask_control(p, BRW_MASK_DISABLE); 444 brw_MOV(p, 445 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D), 446 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D)); 447 brw_pop_insn_state(p); 448 } 449 450 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 451 index); 452 453 brw_MOV(p, 454 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 455 retype(src, BRW_REGISTER_TYPE_D)); 456 457 uint32_t msg_type; 458 459 if (intel->gen >= 6) 460 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 461 else 462 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 463 464 brw_set_predicate_control(p, inst->predicate); 465 466 /* Each of the 8 channel enables is considered for whether each 467 * dword is written. 468 */ 469 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 470 brw_set_dest(p, send, dst); 471 brw_set_src0(p, send, brw_message_reg(inst->base_mrf)); 472 brw_set_dp_write_message(p, send, 473 255, /* binding table index: stateless access */ 474 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 475 msg_type, 476 3, /* mlen */ 477 true, /* header present */ 478 false, /* pixel scoreboard */ 479 0, /* rlen */ 480 false, /* eot */ 481 false /* commit */); 482} 483 484void 485vec4_visitor::generate_pull_constant_load(vec4_instruction *inst, 486 struct brw_reg dst, 487 struct brw_reg index) 488{ 489 struct brw_reg header = brw_vec8_grf(0, 0); 490 491 gen6_resolve_implied_move(p, &header, inst->base_mrf); 492 493 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D), 494 index); 495 496 uint32_t msg_type; 497 498 if (intel->gen >= 6) 499 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 500 else if (intel->gen == 5 || intel->is_g4x) 501 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 502 else 503 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 504 505 /* Each of the 8 channel enables is considered for whether each 506 * dword is written. 507 */ 508 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 509 brw_set_dest(p, send, dst); 510 brw_set_src0(p, send, header); 511 brw_set_dp_read_message(p, send, 512 SURF_INDEX_VERT_CONST_BUFFER, 513 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 514 msg_type, 515 BRW_DATAPORT_READ_TARGET_DATA_CACHE, 516 2, /* mlen */ 517 1 /* rlen */); 518} 519 520void 521vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 522 struct brw_reg dst, 523 struct brw_reg *src) 524{ 525 vec4_instruction *inst = (vec4_instruction *)instruction; 526 527 switch (inst->opcode) { 528 case SHADER_OPCODE_RCP: 529 case SHADER_OPCODE_RSQ: 530 case SHADER_OPCODE_SQRT: 531 case SHADER_OPCODE_EXP2: 532 case SHADER_OPCODE_LOG2: 533 case SHADER_OPCODE_SIN: 534 case SHADER_OPCODE_COS: 535 if (intel->gen >= 6) { 536 generate_math1_gen6(inst, dst, src[0]); 537 } else { 538 generate_math1_gen4(inst, dst, src[0]); 539 } 540 break; 541 542 case SHADER_OPCODE_POW: 543 if (intel->gen >= 6) { 544 generate_math2_gen6(inst, dst, src[0], src[1]); 545 } else { 546 generate_math2_gen4(inst, dst, src[0], src[1]); 547 } 548 break; 549 550 case VS_OPCODE_URB_WRITE: 551 generate_urb_write(inst); 552 break; 553 554 case VS_OPCODE_SCRATCH_READ: 555 generate_scratch_read(inst, dst, src[0]); 556 break; 557 558 case VS_OPCODE_SCRATCH_WRITE: 559 generate_scratch_write(inst, dst, src[0], src[1]); 560 break; 561 562 case VS_OPCODE_PULL_CONSTANT_LOAD: 563 generate_pull_constant_load(inst, dst, src[0]); 564 break; 565 566 default: 567 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 568 fail("unsupported opcode in `%s' in VS\n", 569 brw_opcodes[inst->opcode].name); 570 } else { 571 fail("Unsupported opcode %d in VS", inst->opcode); 572 } 573 } 574} 575 576bool 577vec4_visitor::run() 578{ 579 /* Generate VS IR for main(). (the visitor only descends into 580 * functions called "main"). 581 */ 582 visit_instructions(shader->ir); 583 584 emit_urb_writes(); 585 586 /* Before any optimization, push array accesses out to scratch 587 * space where we need them to be. This pass may allocate new 588 * virtual GRFs, so we want to do it early. It also makes sure 589 * that we have reladdr computations available for CSE, since we'll 590 * often do repeated subexpressions for those. 591 */ 592 move_grf_array_access_to_scratch(); 593 move_uniform_array_access_to_pull_constants(); 594 595 bool progress; 596 do { 597 progress = false; 598 progress = dead_code_eliminate() || progress; 599 } while (progress); 600 601 pack_uniform_registers(); 602 603 if (failed) 604 return false; 605 606 setup_payload(); 607 reg_allocate(); 608 609 if (failed) 610 return false; 611 612 brw_set_access_mode(p, BRW_ALIGN_16); 613 614 generate_code(); 615 616 return !failed; 617} 618 619void 620vec4_visitor::generate_code() 621{ 622 int last_native_inst = 0; 623 const char *last_annotation_string = NULL; 624 ir_instruction *last_annotation_ir = NULL; 625 626 int loop_stack_array_size = 16; 627 int loop_stack_depth = 0; 628 brw_instruction **loop_stack = 629 rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size); 630 int *if_depth_in_loop = 631 rzalloc_array(this->mem_ctx, int, loop_stack_array_size); 632 633 634 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 635 printf("Native code for vertex shader %d:\n", prog->Name); 636 } 637 638 foreach_list(node, &this->instructions) { 639 vec4_instruction *inst = (vec4_instruction *)node; 640 struct brw_reg src[3], dst; 641 642 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 643 if (last_annotation_ir != inst->ir) { 644 last_annotation_ir = inst->ir; 645 if (last_annotation_ir) { 646 printf(" "); 647 last_annotation_ir->print(); 648 printf("\n"); 649 } 650 } 651 if (last_annotation_string != inst->annotation) { 652 last_annotation_string = inst->annotation; 653 if (last_annotation_string) 654 printf(" %s\n", last_annotation_string); 655 } 656 } 657 658 for (unsigned int i = 0; i < 3; i++) { 659 src[i] = inst->get_src(i); 660 } 661 dst = inst->get_dst(); 662 663 brw_set_conditionalmod(p, inst->conditional_mod); 664 brw_set_predicate_control(p, inst->predicate); 665 brw_set_predicate_inverse(p, inst->predicate_inverse); 666 brw_set_saturate(p, inst->saturate); 667 668 switch (inst->opcode) { 669 case BRW_OPCODE_MOV: 670 brw_MOV(p, dst, src[0]); 671 break; 672 case BRW_OPCODE_ADD: 673 brw_ADD(p, dst, src[0], src[1]); 674 break; 675 case BRW_OPCODE_MUL: 676 brw_MUL(p, dst, src[0], src[1]); 677 break; 678 case BRW_OPCODE_MACH: 679 brw_set_acc_write_control(p, 1); 680 brw_MACH(p, dst, src[0], src[1]); 681 brw_set_acc_write_control(p, 0); 682 break; 683 684 case BRW_OPCODE_FRC: 685 brw_FRC(p, dst, src[0]); 686 break; 687 case BRW_OPCODE_RNDD: 688 brw_RNDD(p, dst, src[0]); 689 break; 690 case BRW_OPCODE_RNDE: 691 brw_RNDE(p, dst, src[0]); 692 break; 693 case BRW_OPCODE_RNDZ: 694 brw_RNDZ(p, dst, src[0]); 695 break; 696 697 case BRW_OPCODE_AND: 698 brw_AND(p, dst, src[0], src[1]); 699 break; 700 case BRW_OPCODE_OR: 701 brw_OR(p, dst, src[0], src[1]); 702 break; 703 case BRW_OPCODE_XOR: 704 brw_XOR(p, dst, src[0], src[1]); 705 break; 706 case BRW_OPCODE_NOT: 707 brw_NOT(p, dst, src[0]); 708 break; 709 case BRW_OPCODE_ASR: 710 brw_ASR(p, dst, src[0], src[1]); 711 break; 712 case BRW_OPCODE_SHR: 713 brw_SHR(p, dst, src[0], src[1]); 714 break; 715 case BRW_OPCODE_SHL: 716 brw_SHL(p, dst, src[0], src[1]); 717 break; 718 719 case BRW_OPCODE_CMP: 720 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 721 break; 722 case BRW_OPCODE_SEL: 723 brw_SEL(p, dst, src[0], src[1]); 724 break; 725 726 case BRW_OPCODE_DP4: 727 brw_DP4(p, dst, src[0], src[1]); 728 break; 729 730 case BRW_OPCODE_DP3: 731 brw_DP3(p, dst, src[0], src[1]); 732 break; 733 734 case BRW_OPCODE_DP2: 735 brw_DP2(p, dst, src[0], src[1]); 736 break; 737 738 case BRW_OPCODE_IF: 739 if (inst->src[0].file != BAD_FILE) { 740 /* The instruction has an embedded compare (only allowed on gen6) */ 741 assert(intel->gen == 6); 742 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 743 } else { 744 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 745 brw_inst->header.predicate_control = inst->predicate; 746 } 747 if_depth_in_loop[loop_stack_depth]++; 748 break; 749 750 case BRW_OPCODE_ELSE: 751 brw_ELSE(p); 752 break; 753 case BRW_OPCODE_ENDIF: 754 brw_ENDIF(p); 755 if_depth_in_loop[loop_stack_depth]--; 756 break; 757 758 case BRW_OPCODE_DO: 759 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 760 if (loop_stack_array_size <= loop_stack_depth) { 761 loop_stack_array_size *= 2; 762 loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *, 763 loop_stack_array_size); 764 if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int, 765 loop_stack_array_size); 766 } 767 if_depth_in_loop[loop_stack_depth] = 0; 768 break; 769 770 case BRW_OPCODE_BREAK: 771 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 772 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 773 break; 774 case BRW_OPCODE_CONTINUE: 775 /* FINISHME: We need to write the loop instruction support still. */ 776 if (intel->gen >= 6) 777 gen6_CONT(p, loop_stack[loop_stack_depth - 1]); 778 else 779 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 780 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 781 break; 782 783 case BRW_OPCODE_WHILE: { 784 struct brw_instruction *inst0, *inst1; 785 GLuint br = 1; 786 787 if (intel->gen >= 5) 788 br = 2; 789 790 assert(loop_stack_depth > 0); 791 loop_stack_depth--; 792 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 793 if (intel->gen < 6) { 794 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 795 while (inst0 > loop_stack[loop_stack_depth]) { 796 inst0--; 797 if (inst0->header.opcode == BRW_OPCODE_BREAK && 798 inst0->bits3.if_else.jump_count == 0) { 799 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 800 } 801 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 802 inst0->bits3.if_else.jump_count == 0) { 803 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 804 } 805 } 806 } 807 } 808 break; 809 810 default: 811 generate_vs_instruction(inst, dst, src); 812 break; 813 } 814 815 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 816 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 817 if (0) { 818 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 819 ((uint32_t *)&p->store[i])[3], 820 ((uint32_t *)&p->store[i])[2], 821 ((uint32_t *)&p->store[i])[1], 822 ((uint32_t *)&p->store[i])[0]); 823 } 824 brw_disasm(stdout, &p->store[i], intel->gen); 825 } 826 } 827 828 last_native_inst = p->nr_insn; 829 } 830 831 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 832 printf("\n"); 833 } 834 835 ralloc_free(loop_stack); 836 ralloc_free(if_depth_in_loop); 837 838 brw_set_uip_jip(p); 839 840 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 841 * emit issues, it doesn't get the jump distances into the output, 842 * which is often something we want to debug. So this is here in 843 * case you're doing that. 844 */ 845 if (0) { 846 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 847 for (unsigned int i = 0; i < p->nr_insn; i++) { 848 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 849 ((uint32_t *)&p->store[i])[3], 850 ((uint32_t *)&p->store[i])[2], 851 ((uint32_t *)&p->store[i])[1], 852 ((uint32_t *)&p->store[i])[0]); 853 brw_disasm(stdout, &p->store[i], intel->gen); 854 } 855 } 856 } 857} 858 859extern "C" { 860 861bool 862brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 863{ 864 if (!prog) 865 return false; 866 867 struct brw_shader *shader = 868 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 869 if (!shader) 870 return false; 871 872 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 873 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 874 _mesa_print_ir(shader->ir, NULL); 875 printf("\n\n"); 876 } 877 878 vec4_visitor v(c, prog, shader); 879 if (!v.run()) { 880 prog->LinkStatus = GL_FALSE; 881 ralloc_strcat(&prog->InfoLog, v.fail_msg); 882 return false; 883 } 884 885 return true; 886} 887 888} /* extern "C" */ 889 890} /* namespace brw */ 891