brw_vec4_emit.cpp revision 54e66a0a6327b55f15a7c641ec68da505ff19a35
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "../glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28}; 29 30using namespace brw; 31 32namespace brw { 33 34int 35vec4_visitor::setup_attributes(int payload_reg) 36{ 37 int nr_attributes; 38 int attribute_map[VERT_ATTRIB_MAX]; 39 40 nr_attributes = 0; 41 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 42 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 43 attribute_map[i] = payload_reg + nr_attributes; 44 nr_attributes++; 45 46 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED 47 * attributes come in as floating point conversions of the 48 * integer values. 49 */ 50 if (c->key.gl_fixed_input_size[i] != 0) { 51 struct brw_reg reg = brw_vec8_grf(attribute_map[i], 0); 52 53 brw_MUL(p, 54 brw_writemask(reg, (1 << c->key.gl_fixed_input_size[i]) - 1), 55 reg, brw_imm_f(1.0 / 65536.0)); 56 } 57 } 58 } 59 60 foreach_iter(exec_list_iterator, iter, this->instructions) { 61 vec4_instruction *inst = (vec4_instruction *)iter.get(); 62 63 for (int i = 0; i < 3; i++) { 64 if (inst->src[i].file != ATTR) 65 continue; 66 67 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 68 69 struct brw_reg reg = brw_vec8_grf(grf, 0); 70 reg.dw1.bits.swizzle = inst->src[i].swizzle; 71 if (inst->src[i].abs) 72 reg = brw_abs(reg); 73 if (inst->src[i].negate) 74 reg = negate(reg); 75 76 inst->src[i].file = HW_REG; 77 inst->src[i].fixed_hw_reg = reg; 78 } 79 } 80 81 /* The BSpec says we always have to read at least one thing from 82 * the VF, and it appears that the hardware wedges otherwise. 83 */ 84 if (nr_attributes == 0) 85 nr_attributes = 1; 86 87 prog_data->urb_read_length = (nr_attributes + 1) / 2; 88 89 return payload_reg + nr_attributes; 90} 91 92int 93vec4_visitor::setup_uniforms(int reg) 94{ 95 /* User clip planes from curbe: 96 */ 97 if (c->key.nr_userclip) { 98 if (intel->gen >= 6) { 99 for (int i = 0; i < c->key.nr_userclip; i++) { 100 c->userplane[i] = stride(brw_vec4_grf(reg + i / 2, 101 (i % 2) * 4), 0, 4, 1); 102 } 103 reg += ALIGN(c->key.nr_userclip, 2) / 2; 104 } else { 105 for (int i = 0; i < c->key.nr_userclip; i++) { 106 c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2, 107 (i % 2) * 4), 0, 4, 1); 108 } 109 reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2; 110 } 111 } 112 113 /* The pre-gen6 VS requires that some push constants get loaded no 114 * matter what, or the GPU would hang. 115 */ 116 if (intel->gen < 6 && this->uniforms == 0) { 117 this->uniform_size[this->uniforms] = 1; 118 119 for (unsigned int i = 0; i < 4; i++) { 120 unsigned int slot = this->uniforms * 4 + i; 121 122 c->prog_data.param[slot] = NULL; 123 c->prog_data.param_convert[slot] = PARAM_CONVERT_ZERO; 124 } 125 126 this->uniforms++; 127 reg++; 128 } else { 129 reg += ALIGN(uniforms, 2) / 2; 130 } 131 132 /* for now, we are not doing any elimination of unused slots, nor 133 * are we packing our uniforms. 134 */ 135 c->prog_data.nr_params = this->uniforms * 4; 136 137 c->prog_data.curb_read_length = reg - 1; 138 c->prog_data.uses_new_param_layout = true; 139 140 return reg; 141} 142 143void 144vec4_visitor::setup_payload(void) 145{ 146 int reg = 0; 147 148 /* The payload always contains important data in g0, which contains 149 * the URB handles that are passed on to the URB write at the end 150 * of the thread. So, we always start push constants at g1. 151 */ 152 reg++; 153 154 reg = setup_uniforms(reg); 155 156 reg = setup_attributes(reg); 157 158 this->first_non_payload_grf = reg; 159} 160 161struct brw_reg 162vec4_instruction::get_dst(void) 163{ 164 struct brw_reg brw_reg; 165 166 switch (dst.file) { 167 case GRF: 168 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 169 brw_reg = retype(brw_reg, dst.type); 170 brw_reg.dw1.bits.writemask = dst.writemask; 171 break; 172 173 case HW_REG: 174 brw_reg = dst.fixed_hw_reg; 175 break; 176 177 case BAD_FILE: 178 brw_reg = brw_null_reg(); 179 break; 180 181 default: 182 assert(!"not reached"); 183 brw_reg = brw_null_reg(); 184 break; 185 } 186 return brw_reg; 187} 188 189struct brw_reg 190vec4_instruction::get_src(int i) 191{ 192 struct brw_reg brw_reg; 193 194 switch (src[i].file) { 195 case GRF: 196 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 197 brw_reg = retype(brw_reg, src[i].type); 198 brw_reg.dw1.bits.swizzle = src[i].swizzle; 199 if (src[i].abs) 200 brw_reg = brw_abs(brw_reg); 201 if (src[i].negate) 202 brw_reg = negate(brw_reg); 203 break; 204 205 case IMM: 206 switch (src[i].type) { 207 case BRW_REGISTER_TYPE_F: 208 brw_reg = brw_imm_f(src[i].imm.f); 209 break; 210 case BRW_REGISTER_TYPE_D: 211 brw_reg = brw_imm_d(src[i].imm.i); 212 break; 213 case BRW_REGISTER_TYPE_UD: 214 brw_reg = brw_imm_ud(src[i].imm.u); 215 break; 216 default: 217 assert(!"not reached"); 218 brw_reg = brw_null_reg(); 219 break; 220 } 221 break; 222 223 case UNIFORM: 224 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 225 ((src[i].reg + src[i].reg_offset) % 2) * 4), 226 0, 4, 1); 227 brw_reg = retype(brw_reg, src[i].type); 228 brw_reg.dw1.bits.swizzle = src[i].swizzle; 229 if (src[i].abs) 230 brw_reg = brw_abs(brw_reg); 231 if (src[i].negate) 232 brw_reg = negate(brw_reg); 233 break; 234 235 case HW_REG: 236 brw_reg = src[i].fixed_hw_reg; 237 break; 238 239 case BAD_FILE: 240 /* Probably unused. */ 241 brw_reg = brw_null_reg(); 242 break; 243 case ATTR: 244 default: 245 assert(!"not reached"); 246 brw_reg = brw_null_reg(); 247 break; 248 } 249 250 return brw_reg; 251} 252 253void 254vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 255 struct brw_reg dst, 256 struct brw_reg src) 257{ 258 brw_math(p, 259 dst, 260 brw_math_function(inst->opcode), 261 BRW_MATH_SATURATE_NONE, 262 inst->base_mrf, 263 src, 264 BRW_MATH_DATA_SCALAR, 265 BRW_MATH_PRECISION_FULL); 266} 267 268static void 269check_gen6_math_src_arg(struct brw_reg src) 270{ 271 /* Source swizzles are ignored. */ 272 assert(!src.abs); 273 assert(!src.negate); 274 assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); 275} 276 277void 278vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 279 struct brw_reg dst, 280 struct brw_reg src) 281{ 282 /* Can't do writemask because math can't be align16. */ 283 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 284 check_gen6_math_src_arg(src); 285 286 brw_set_access_mode(p, BRW_ALIGN_1); 287 brw_math(p, 288 dst, 289 brw_math_function(inst->opcode), 290 BRW_MATH_SATURATE_NONE, 291 inst->base_mrf, 292 src, 293 BRW_MATH_DATA_SCALAR, 294 BRW_MATH_PRECISION_FULL); 295 brw_set_access_mode(p, BRW_ALIGN_16); 296} 297 298void 299vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 300 struct brw_reg dst, 301 struct brw_reg src0, 302 struct brw_reg src1) 303{ 304 /* Can't do writemask because math can't be align16. */ 305 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 306 /* Source swizzles are ignored. */ 307 check_gen6_math_src_arg(src0); 308 check_gen6_math_src_arg(src1); 309 310 brw_set_access_mode(p, BRW_ALIGN_1); 311 brw_math2(p, 312 dst, 313 brw_math_function(inst->opcode), 314 src0, src1); 315 brw_set_access_mode(p, BRW_ALIGN_16); 316} 317 318void 319vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 320 struct brw_reg dst, 321 struct brw_reg src0, 322 struct brw_reg src1) 323{ 324 /* Can't do writemask because math can't be align16. */ 325 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 326 327 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1); 328 329 brw_set_access_mode(p, BRW_ALIGN_1); 330 brw_math(p, 331 dst, 332 brw_math_function(inst->opcode), 333 BRW_MATH_SATURATE_NONE, 334 inst->base_mrf, 335 src0, 336 BRW_MATH_DATA_VECTOR, 337 BRW_MATH_PRECISION_FULL); 338 brw_set_access_mode(p, BRW_ALIGN_16); 339} 340 341void 342vec4_visitor::generate_urb_write(vec4_instruction *inst) 343{ 344 brw_urb_WRITE(p, 345 brw_null_reg(), /* dest */ 346 inst->base_mrf, /* starting mrf reg nr */ 347 brw_vec8_grf(0, 0), /* src */ 348 false, /* allocate */ 349 true, /* used */ 350 inst->mlen, 351 0, /* response len */ 352 inst->eot, /* eot */ 353 inst->eot, /* writes complete */ 354 inst->offset, /* urb destination offset */ 355 BRW_URB_SWIZZLE_INTERLEAVE); 356} 357 358void 359vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 360 struct brw_reg index) 361{ 362 int second_vertex_offset; 363 364 if (intel->gen >= 6) 365 second_vertex_offset = 1; 366 else 367 second_vertex_offset = 16; 368 369 m1 = retype(m1, BRW_REGISTER_TYPE_D); 370 371 /* Set up M1 (message payload). Only the block offsets in M1.0 and 372 * M1.4 are used, and the rest are ignored. 373 */ 374 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 375 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 376 struct brw_reg index_0 = suboffset(vec1(index), 0); 377 struct brw_reg index_4 = suboffset(vec1(index), 4); 378 379 brw_push_insn_state(p); 380 brw_set_mask_control(p, BRW_MASK_DISABLE); 381 brw_set_access_mode(p, BRW_ALIGN_1); 382 383 brw_MOV(p, m1_0, index_0); 384 385 brw_set_predicate_inverse(p, true); 386 if (index.file == BRW_IMMEDIATE_VALUE) { 387 index_4.dw1.ud++; 388 brw_MOV(p, m1_4, index_4); 389 } else { 390 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 391 } 392 393 brw_pop_insn_state(p); 394} 395 396void 397vec4_visitor::generate_scratch_read(vec4_instruction *inst, 398 struct brw_reg dst, 399 struct brw_reg index) 400{ 401 if (intel->gen >= 6) { 402 brw_push_insn_state(p); 403 brw_set_mask_control(p, BRW_MASK_DISABLE); 404 brw_MOV(p, 405 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D), 406 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D)); 407 brw_pop_insn_state(p); 408 } 409 410 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 411 index); 412 413 uint32_t msg_type; 414 415 if (intel->gen >= 6) 416 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 417 else if (intel->gen == 5 || intel->is_g4x) 418 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 419 else 420 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 421 422 /* Each of the 8 channel enables is considered for whether each 423 * dword is written. 424 */ 425 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 426 brw_set_dest(p, send, dst); 427 brw_set_src0(p, send, brw_message_reg(inst->base_mrf)); 428 brw_set_dp_read_message(p, send, 429 255, /* binding table index: stateless access */ 430 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 431 msg_type, 432 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 433 2, /* mlen */ 434 1 /* rlen */); 435} 436 437void 438vec4_visitor::generate_scratch_write(vec4_instruction *inst, 439 struct brw_reg dst, 440 struct brw_reg src, 441 struct brw_reg index) 442{ 443 /* If the instruction is predicated, we'll predicate the send, not 444 * the header setup. 445 */ 446 brw_set_predicate_control(p, false); 447 448 if (intel->gen >= 6) { 449 brw_push_insn_state(p); 450 brw_set_mask_control(p, BRW_MASK_DISABLE); 451 brw_MOV(p, 452 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D), 453 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D)); 454 brw_pop_insn_state(p); 455 } 456 457 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 458 index); 459 460 brw_MOV(p, 461 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 462 retype(src, BRW_REGISTER_TYPE_D)); 463 464 uint32_t msg_type; 465 466 if (intel->gen >= 6) 467 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 468 else 469 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 470 471 brw_set_predicate_control(p, inst->predicate); 472 473 /* Each of the 8 channel enables is considered for whether each 474 * dword is written. 475 */ 476 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 477 brw_set_dest(p, send, dst); 478 brw_set_src0(p, send, brw_message_reg(inst->base_mrf)); 479 brw_set_dp_write_message(p, send, 480 255, /* binding table index: stateless access */ 481 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 482 msg_type, 483 3, /* mlen */ 484 true, /* header present */ 485 false, /* pixel scoreboard */ 486 0, /* rlen */ 487 false, /* eot */ 488 false /* commit */); 489} 490 491void 492vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 493 struct brw_reg dst, 494 struct brw_reg *src) 495{ 496 vec4_instruction *inst = (vec4_instruction *)instruction; 497 498 switch (inst->opcode) { 499 case SHADER_OPCODE_RCP: 500 case SHADER_OPCODE_RSQ: 501 case SHADER_OPCODE_SQRT: 502 case SHADER_OPCODE_EXP2: 503 case SHADER_OPCODE_LOG2: 504 case SHADER_OPCODE_SIN: 505 case SHADER_OPCODE_COS: 506 if (intel->gen >= 6) { 507 generate_math1_gen6(inst, dst, src[0]); 508 } else { 509 generate_math1_gen4(inst, dst, src[0]); 510 } 511 break; 512 513 case SHADER_OPCODE_POW: 514 if (intel->gen >= 6) { 515 generate_math2_gen6(inst, dst, src[0], src[1]); 516 } else { 517 generate_math2_gen4(inst, dst, src[0], src[1]); 518 } 519 break; 520 521 case VS_OPCODE_URB_WRITE: 522 generate_urb_write(inst); 523 break; 524 525 case VS_OPCODE_SCRATCH_READ: 526 generate_scratch_read(inst, dst, src[0]); 527 break; 528 529 case VS_OPCODE_SCRATCH_WRITE: 530 generate_scratch_write(inst, dst, src[0], src[1]); 531 break; 532 533 default: 534 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 535 fail("unsupported opcode in `%s' in VS\n", 536 brw_opcodes[inst->opcode].name); 537 } else { 538 fail("Unsupported opcode %d in VS", inst->opcode); 539 } 540 } 541} 542 543bool 544vec4_visitor::run() 545{ 546 /* Generate VS IR for main(). (the visitor only descends into 547 * functions called "main"). 548 */ 549 foreach_iter(exec_list_iterator, iter, *shader->ir) { 550 ir_instruction *ir = (ir_instruction *)iter.get(); 551 base_ir = ir; 552 ir->accept(this); 553 } 554 555 emit_urb_writes(); 556 557 /* Before any optimization, push array accesses out to scratch 558 * space where we need them to be. This pass may allocate new 559 * virtual GRFs, so we want to do it early. It also makes sure 560 * that we have reladdr computations available for CSE, since we'll 561 * often do repeated subexpressions for those. 562 */ 563 move_grf_array_access_to_scratch(); 564 565 if (failed) 566 return false; 567 568 setup_payload(); 569 reg_allocate(); 570 571 if (failed) 572 return false; 573 574 brw_set_access_mode(p, BRW_ALIGN_16); 575 576 generate_code(); 577 578 return !failed; 579} 580 581void 582vec4_visitor::generate_code() 583{ 584 int last_native_inst = p->nr_insn; 585 const char *last_annotation_string = NULL; 586 ir_instruction *last_annotation_ir = NULL; 587 588 int loop_stack_array_size = 16; 589 int loop_stack_depth = 0; 590 brw_instruction **loop_stack = 591 rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size); 592 int *if_depth_in_loop = 593 rzalloc_array(this->mem_ctx, int, loop_stack_array_size); 594 595 596 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 597 printf("Native code for vertex shader %d:\n", prog->Name); 598 } 599 600 foreach_list(node, &this->instructions) { 601 vec4_instruction *inst = (vec4_instruction *)node; 602 struct brw_reg src[3], dst; 603 604 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 605 if (last_annotation_ir != inst->ir) { 606 last_annotation_ir = inst->ir; 607 if (last_annotation_ir) { 608 printf(" "); 609 last_annotation_ir->print(); 610 printf("\n"); 611 } 612 } 613 if (last_annotation_string != inst->annotation) { 614 last_annotation_string = inst->annotation; 615 if (last_annotation_string) 616 printf(" %s\n", last_annotation_string); 617 } 618 } 619 620 for (unsigned int i = 0; i < 3; i++) { 621 src[i] = inst->get_src(i); 622 } 623 dst = inst->get_dst(); 624 625 brw_set_conditionalmod(p, inst->conditional_mod); 626 brw_set_predicate_control(p, inst->predicate); 627 brw_set_predicate_inverse(p, inst->predicate_inverse); 628 brw_set_saturate(p, inst->saturate); 629 630 switch (inst->opcode) { 631 case BRW_OPCODE_MOV: 632 brw_MOV(p, dst, src[0]); 633 break; 634 case BRW_OPCODE_ADD: 635 brw_ADD(p, dst, src[0], src[1]); 636 break; 637 case BRW_OPCODE_MUL: 638 brw_MUL(p, dst, src[0], src[1]); 639 break; 640 641 case BRW_OPCODE_FRC: 642 brw_FRC(p, dst, src[0]); 643 break; 644 case BRW_OPCODE_RNDD: 645 brw_RNDD(p, dst, src[0]); 646 break; 647 case BRW_OPCODE_RNDE: 648 brw_RNDE(p, dst, src[0]); 649 break; 650 case BRW_OPCODE_RNDZ: 651 brw_RNDZ(p, dst, src[0]); 652 break; 653 654 case BRW_OPCODE_AND: 655 brw_AND(p, dst, src[0], src[1]); 656 break; 657 case BRW_OPCODE_OR: 658 brw_OR(p, dst, src[0], src[1]); 659 break; 660 case BRW_OPCODE_XOR: 661 brw_XOR(p, dst, src[0], src[1]); 662 break; 663 case BRW_OPCODE_NOT: 664 brw_NOT(p, dst, src[0]); 665 break; 666 case BRW_OPCODE_ASR: 667 brw_ASR(p, dst, src[0], src[1]); 668 break; 669 case BRW_OPCODE_SHR: 670 brw_SHR(p, dst, src[0], src[1]); 671 break; 672 case BRW_OPCODE_SHL: 673 brw_SHL(p, dst, src[0], src[1]); 674 break; 675 676 case BRW_OPCODE_CMP: 677 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 678 break; 679 case BRW_OPCODE_SEL: 680 brw_SEL(p, dst, src[0], src[1]); 681 break; 682 683 case BRW_OPCODE_DP4: 684 brw_DP4(p, dst, src[0], src[1]); 685 break; 686 687 case BRW_OPCODE_DP3: 688 brw_DP3(p, dst, src[0], src[1]); 689 break; 690 691 case BRW_OPCODE_DP2: 692 brw_DP2(p, dst, src[0], src[1]); 693 break; 694 695 case BRW_OPCODE_IF: 696 if (inst->src[0].file != BAD_FILE) { 697 /* The instruction has an embedded compare (only allowed on gen6) */ 698 assert(intel->gen == 6); 699 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 700 } else { 701 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 702 brw_inst->header.predicate_control = inst->predicate; 703 } 704 if_depth_in_loop[loop_stack_depth]++; 705 break; 706 707 case BRW_OPCODE_ELSE: 708 brw_ELSE(p); 709 break; 710 case BRW_OPCODE_ENDIF: 711 brw_ENDIF(p); 712 if_depth_in_loop[loop_stack_depth]--; 713 break; 714 715 case BRW_OPCODE_DO: 716 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 717 if (loop_stack_array_size <= loop_stack_depth) { 718 loop_stack_array_size *= 2; 719 loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *, 720 loop_stack_array_size); 721 if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int, 722 loop_stack_array_size); 723 } 724 if_depth_in_loop[loop_stack_depth] = 0; 725 break; 726 727 case BRW_OPCODE_BREAK: 728 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 729 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 730 break; 731 case BRW_OPCODE_CONTINUE: 732 /* FINISHME: We need to write the loop instruction support still. */ 733 if (intel->gen >= 6) 734 gen6_CONT(p, loop_stack[loop_stack_depth - 1]); 735 else 736 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 737 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 738 break; 739 740 case BRW_OPCODE_WHILE: { 741 struct brw_instruction *inst0, *inst1; 742 GLuint br = 1; 743 744 if (intel->gen >= 5) 745 br = 2; 746 747 assert(loop_stack_depth > 0); 748 loop_stack_depth--; 749 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 750 if (intel->gen < 6) { 751 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 752 while (inst0 > loop_stack[loop_stack_depth]) { 753 inst0--; 754 if (inst0->header.opcode == BRW_OPCODE_BREAK && 755 inst0->bits3.if_else.jump_count == 0) { 756 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 757 } 758 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 759 inst0->bits3.if_else.jump_count == 0) { 760 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 761 } 762 } 763 } 764 } 765 break; 766 767 default: 768 generate_vs_instruction(inst, dst, src); 769 break; 770 } 771 772 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 773 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 774 if (0) { 775 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 776 ((uint32_t *)&p->store[i])[3], 777 ((uint32_t *)&p->store[i])[2], 778 ((uint32_t *)&p->store[i])[1], 779 ((uint32_t *)&p->store[i])[0]); 780 } 781 brw_disasm(stdout, &p->store[i], intel->gen); 782 } 783 } 784 785 last_native_inst = p->nr_insn; 786 } 787 788 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 789 printf("\n"); 790 } 791 792 ralloc_free(loop_stack); 793 ralloc_free(if_depth_in_loop); 794 795 brw_set_uip_jip(p); 796 797 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 798 * emit issues, it doesn't get the jump distances into the output, 799 * which is often something we want to debug. So this is here in 800 * case you're doing that. 801 */ 802 if (0) { 803 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 804 for (unsigned int i = 0; i < p->nr_insn; i++) { 805 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 806 ((uint32_t *)&p->store[i])[3], 807 ((uint32_t *)&p->store[i])[2], 808 ((uint32_t *)&p->store[i])[1], 809 ((uint32_t *)&p->store[i])[0]); 810 brw_disasm(stdout, &p->store[i], intel->gen); 811 } 812 } 813 } 814} 815 816extern "C" { 817 818bool 819brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 820{ 821 if (!prog) 822 return false; 823 824 struct brw_shader *shader = 825 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 826 if (!shader) 827 return false; 828 829 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 830 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 831 _mesa_print_ir(shader->ir, NULL); 832 printf("\n\n"); 833 } 834 835 vec4_visitor v(c, prog, shader); 836 if (!v.run()) { 837 prog->LinkStatus = GL_FALSE; 838 ralloc_strcat(&prog->InfoLog, v.fail_msg); 839 return false; 840 } 841 842 return true; 843} 844 845} /* extern "C" */ 846 847} /* namespace brw */ 848