brw_vec4_emit.cpp revision 9367960ea64a087895caaadbd0353080c14b4bab
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28}; 29 30using namespace brw; 31 32namespace brw { 33 34int 35vec4_visitor::setup_attributes(int payload_reg) 36{ 37 int nr_attributes; 38 int attribute_map[VERT_ATTRIB_MAX]; 39 40 nr_attributes = 0; 41 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 42 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 43 attribute_map[i] = payload_reg + nr_attributes; 44 nr_attributes++; 45 } 46 } 47 48 foreach_list(node, &this->instructions) { 49 vec4_instruction *inst = (vec4_instruction *)node; 50 51 /* We have to support ATTR as a destination for GL_FIXED fixup. */ 52 if (inst->dst.file == ATTR) { 53 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; 54 55 struct brw_reg reg = brw_vec8_grf(grf, 0); 56 reg.dw1.bits.writemask = inst->dst.writemask; 57 58 inst->dst.file = HW_REG; 59 inst->dst.fixed_hw_reg = reg; 60 } 61 62 for (int i = 0; i < 3; i++) { 63 if (inst->src[i].file != ATTR) 64 continue; 65 66 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 67 68 struct brw_reg reg = brw_vec8_grf(grf, 0); 69 reg.dw1.bits.swizzle = inst->src[i].swizzle; 70 if (inst->src[i].abs) 71 reg = brw_abs(reg); 72 if (inst->src[i].negate) 73 reg = negate(reg); 74 75 inst->src[i].file = HW_REG; 76 inst->src[i].fixed_hw_reg = reg; 77 } 78 } 79 80 /* The BSpec says we always have to read at least one thing from 81 * the VF, and it appears that the hardware wedges otherwise. 82 */ 83 if (nr_attributes == 0) 84 nr_attributes = 1; 85 86 prog_data->urb_read_length = (nr_attributes + 1) / 2; 87 88 return payload_reg + nr_attributes; 89} 90 91int 92vec4_visitor::setup_uniforms(int reg) 93{ 94 /* User clip planes from curbe: 95 */ 96 if (c->key.nr_userclip) { 97 if (intel->gen >= 6) { 98 for (int i = 0; i < c->key.nr_userclip; i++) { 99 c->userplane[i] = stride(brw_vec4_grf(reg + i / 2, 100 (i % 2) * 4), 0, 4, 1); 101 } 102 reg += ALIGN(c->key.nr_userclip, 2) / 2; 103 } else { 104 for (int i = 0; i < c->key.nr_userclip; i++) { 105 c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2, 106 (i % 2) * 4), 0, 4, 1); 107 } 108 reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2; 109 } 110 } 111 112 /* The pre-gen6 VS requires that some push constants get loaded no 113 * matter what, or the GPU would hang. 114 */ 115 if (intel->gen < 6 && this->uniforms == 0) { 116 this->uniform_vector_size[this->uniforms] = 1; 117 118 for (unsigned int i = 0; i < 4; i++) { 119 unsigned int slot = this->uniforms * 4 + i; 120 static float zero = 0.0; 121 c->prog_data.param[slot] = &zero; 122 } 123 124 this->uniforms++; 125 reg++; 126 } else { 127 reg += ALIGN(uniforms, 2) / 2; 128 } 129 130 c->prog_data.nr_params = this->uniforms * 4; 131 132 c->prog_data.curb_read_length = reg - 1; 133 c->prog_data.uses_new_param_layout = true; 134 135 return reg; 136} 137 138void 139vec4_visitor::setup_payload(void) 140{ 141 int reg = 0; 142 143 /* The payload always contains important data in g0, which contains 144 * the URB handles that are passed on to the URB write at the end 145 * of the thread. So, we always start push constants at g1. 146 */ 147 reg++; 148 149 reg = setup_uniforms(reg); 150 151 reg = setup_attributes(reg); 152 153 this->first_non_payload_grf = reg; 154} 155 156struct brw_reg 157vec4_instruction::get_dst(void) 158{ 159 struct brw_reg brw_reg; 160 161 switch (dst.file) { 162 case GRF: 163 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 164 brw_reg = retype(brw_reg, dst.type); 165 brw_reg.dw1.bits.writemask = dst.writemask; 166 break; 167 168 case HW_REG: 169 brw_reg = dst.fixed_hw_reg; 170 break; 171 172 case BAD_FILE: 173 brw_reg = brw_null_reg(); 174 break; 175 176 default: 177 assert(!"not reached"); 178 brw_reg = brw_null_reg(); 179 break; 180 } 181 return brw_reg; 182} 183 184struct brw_reg 185vec4_instruction::get_src(int i) 186{ 187 struct brw_reg brw_reg; 188 189 switch (src[i].file) { 190 case GRF: 191 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 192 brw_reg = retype(brw_reg, src[i].type); 193 brw_reg.dw1.bits.swizzle = src[i].swizzle; 194 if (src[i].abs) 195 brw_reg = brw_abs(brw_reg); 196 if (src[i].negate) 197 brw_reg = negate(brw_reg); 198 break; 199 200 case IMM: 201 switch (src[i].type) { 202 case BRW_REGISTER_TYPE_F: 203 brw_reg = brw_imm_f(src[i].imm.f); 204 break; 205 case BRW_REGISTER_TYPE_D: 206 brw_reg = brw_imm_d(src[i].imm.i); 207 break; 208 case BRW_REGISTER_TYPE_UD: 209 brw_reg = brw_imm_ud(src[i].imm.u); 210 break; 211 default: 212 assert(!"not reached"); 213 brw_reg = brw_null_reg(); 214 break; 215 } 216 break; 217 218 case UNIFORM: 219 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 220 ((src[i].reg + src[i].reg_offset) % 2) * 4), 221 0, 4, 1); 222 brw_reg = retype(brw_reg, src[i].type); 223 brw_reg.dw1.bits.swizzle = src[i].swizzle; 224 if (src[i].abs) 225 brw_reg = brw_abs(brw_reg); 226 if (src[i].negate) 227 brw_reg = negate(brw_reg); 228 229 /* This should have been moved to pull constants. */ 230 assert(!src[i].reladdr); 231 break; 232 233 case HW_REG: 234 brw_reg = src[i].fixed_hw_reg; 235 break; 236 237 case BAD_FILE: 238 /* Probably unused. */ 239 brw_reg = brw_null_reg(); 240 break; 241 case ATTR: 242 default: 243 assert(!"not reached"); 244 brw_reg = brw_null_reg(); 245 break; 246 } 247 248 return brw_reg; 249} 250 251void 252vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 253 struct brw_reg dst, 254 struct brw_reg src) 255{ 256 brw_math(p, 257 dst, 258 brw_math_function(inst->opcode), 259 BRW_MATH_SATURATE_NONE, 260 inst->base_mrf, 261 src, 262 BRW_MATH_DATA_VECTOR, 263 BRW_MATH_PRECISION_FULL); 264} 265 266static void 267check_gen6_math_src_arg(struct brw_reg src) 268{ 269 /* Source swizzles are ignored. */ 270 assert(!src.abs); 271 assert(!src.negate); 272 assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); 273} 274 275void 276vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 277 struct brw_reg dst, 278 struct brw_reg src) 279{ 280 /* Can't do writemask because math can't be align16. */ 281 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 282 check_gen6_math_src_arg(src); 283 284 brw_set_access_mode(p, BRW_ALIGN_1); 285 brw_math(p, 286 dst, 287 brw_math_function(inst->opcode), 288 BRW_MATH_SATURATE_NONE, 289 inst->base_mrf, 290 src, 291 BRW_MATH_DATA_SCALAR, 292 BRW_MATH_PRECISION_FULL); 293 brw_set_access_mode(p, BRW_ALIGN_16); 294} 295 296void 297vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 298 struct brw_reg dst, 299 struct brw_reg src0, 300 struct brw_reg src1) 301{ 302 /* Can't do writemask because math can't be align16. */ 303 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 304 /* Source swizzles are ignored. */ 305 check_gen6_math_src_arg(src0); 306 check_gen6_math_src_arg(src1); 307 308 brw_set_access_mode(p, BRW_ALIGN_1); 309 brw_math2(p, 310 dst, 311 brw_math_function(inst->opcode), 312 src0, src1); 313 brw_set_access_mode(p, BRW_ALIGN_16); 314} 315 316void 317vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 318 struct brw_reg dst, 319 struct brw_reg src0, 320 struct brw_reg src1) 321{ 322 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1); 323 324 brw_math(p, 325 dst, 326 brw_math_function(inst->opcode), 327 BRW_MATH_SATURATE_NONE, 328 inst->base_mrf, 329 src0, 330 BRW_MATH_DATA_VECTOR, 331 BRW_MATH_PRECISION_FULL); 332} 333 334void 335vec4_visitor::generate_urb_write(vec4_instruction *inst) 336{ 337 brw_urb_WRITE(p, 338 brw_null_reg(), /* dest */ 339 inst->base_mrf, /* starting mrf reg nr */ 340 brw_vec8_grf(0, 0), /* src */ 341 false, /* allocate */ 342 true, /* used */ 343 inst->mlen, 344 0, /* response len */ 345 inst->eot, /* eot */ 346 inst->eot, /* writes complete */ 347 inst->offset, /* urb destination offset */ 348 BRW_URB_SWIZZLE_INTERLEAVE); 349} 350 351void 352vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 353 struct brw_reg index) 354{ 355 int second_vertex_offset; 356 357 if (intel->gen >= 6) 358 second_vertex_offset = 1; 359 else 360 second_vertex_offset = 16; 361 362 m1 = retype(m1, BRW_REGISTER_TYPE_D); 363 364 /* Set up M1 (message payload). Only the block offsets in M1.0 and 365 * M1.4 are used, and the rest are ignored. 366 */ 367 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 368 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 369 struct brw_reg index_0 = suboffset(vec1(index), 0); 370 struct brw_reg index_4 = suboffset(vec1(index), 4); 371 372 brw_push_insn_state(p); 373 brw_set_mask_control(p, BRW_MASK_DISABLE); 374 brw_set_access_mode(p, BRW_ALIGN_1); 375 376 brw_MOV(p, m1_0, index_0); 377 378 brw_set_predicate_inverse(p, true); 379 if (index.file == BRW_IMMEDIATE_VALUE) { 380 index_4.dw1.ud += second_vertex_offset; 381 brw_MOV(p, m1_4, index_4); 382 } else { 383 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 384 } 385 386 brw_pop_insn_state(p); 387} 388 389void 390vec4_visitor::generate_scratch_read(vec4_instruction *inst, 391 struct brw_reg dst, 392 struct brw_reg index) 393{ 394 struct brw_reg header = brw_vec8_grf(0, 0); 395 396 gen6_resolve_implied_move(p, &header, inst->base_mrf); 397 398 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 399 index); 400 401 uint32_t msg_type; 402 403 if (intel->gen >= 6) 404 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 405 else if (intel->gen == 5 || intel->is_g4x) 406 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 407 else 408 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 409 410 /* Each of the 8 channel enables is considered for whether each 411 * dword is written. 412 */ 413 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 414 brw_set_dest(p, send, dst); 415 brw_set_src0(p, send, header); 416 if (intel->gen < 6) 417 send->header.destreg__conditionalmod = inst->base_mrf; 418 brw_set_dp_read_message(p, send, 419 255, /* binding table index: stateless access */ 420 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 421 msg_type, 422 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 423 2, /* mlen */ 424 1 /* rlen */); 425} 426 427void 428vec4_visitor::generate_scratch_write(vec4_instruction *inst, 429 struct brw_reg dst, 430 struct brw_reg src, 431 struct brw_reg index) 432{ 433 struct brw_reg header = brw_vec8_grf(0, 0); 434 bool write_commit; 435 436 /* If the instruction is predicated, we'll predicate the send, not 437 * the header setup. 438 */ 439 brw_set_predicate_control(p, false); 440 441 gen6_resolve_implied_move(p, &header, inst->base_mrf); 442 443 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 444 index); 445 446 brw_MOV(p, 447 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 448 retype(src, BRW_REGISTER_TYPE_D)); 449 450 uint32_t msg_type; 451 452 if (intel->gen >= 6) 453 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 454 else 455 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 456 457 brw_set_predicate_control(p, inst->predicate); 458 459 /* Pre-gen6, we have to specify write commits to ensure ordering 460 * between reads and writes within a thread. Afterwards, that's 461 * guaranteed and write commits only matter for inter-thread 462 * synchronization. 463 */ 464 if (intel->gen >= 6) { 465 write_commit = false; 466 } else { 467 /* The visitor set up our destination register to be g0. This 468 * means that when the next read comes along, we will end up 469 * reading from g0 and causing a block on the write commit. For 470 * write-after-read, we are relying on the value of the previous 471 * read being used (and thus blocking on completion) before our 472 * write is executed. This means we have to be careful in 473 * instruction scheduling to not violate this assumption. 474 */ 475 write_commit = true; 476 } 477 478 /* Each of the 8 channel enables is considered for whether each 479 * dword is written. 480 */ 481 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 482 brw_set_dest(p, send, dst); 483 brw_set_src0(p, send, header); 484 if (intel->gen < 6) 485 send->header.destreg__conditionalmod = inst->base_mrf; 486 brw_set_dp_write_message(p, send, 487 255, /* binding table index: stateless access */ 488 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 489 msg_type, 490 3, /* mlen */ 491 true, /* header present */ 492 false, /* pixel scoreboard */ 493 write_commit, /* rlen */ 494 false, /* eot */ 495 write_commit); 496} 497 498void 499vec4_visitor::generate_pull_constant_load(vec4_instruction *inst, 500 struct brw_reg dst, 501 struct brw_reg index) 502{ 503 struct brw_reg header = brw_vec8_grf(0, 0); 504 505 gen6_resolve_implied_move(p, &header, inst->base_mrf); 506 507 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D), 508 index); 509 510 uint32_t msg_type; 511 512 if (intel->gen >= 6) 513 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 514 else if (intel->gen == 5 || intel->is_g4x) 515 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 516 else 517 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 518 519 /* Each of the 8 channel enables is considered for whether each 520 * dword is written. 521 */ 522 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 523 brw_set_dest(p, send, dst); 524 brw_set_src0(p, send, header); 525 if (intel->gen < 6) 526 send->header.destreg__conditionalmod = inst->base_mrf; 527 brw_set_dp_read_message(p, send, 528 SURF_INDEX_VERT_CONST_BUFFER, 529 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 530 msg_type, 531 BRW_DATAPORT_READ_TARGET_DATA_CACHE, 532 2, /* mlen */ 533 1 /* rlen */); 534} 535 536void 537vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 538 struct brw_reg dst, 539 struct brw_reg *src) 540{ 541 vec4_instruction *inst = (vec4_instruction *)instruction; 542 543 switch (inst->opcode) { 544 case SHADER_OPCODE_RCP: 545 case SHADER_OPCODE_RSQ: 546 case SHADER_OPCODE_SQRT: 547 case SHADER_OPCODE_EXP2: 548 case SHADER_OPCODE_LOG2: 549 case SHADER_OPCODE_SIN: 550 case SHADER_OPCODE_COS: 551 if (intel->gen >= 6) { 552 generate_math1_gen6(inst, dst, src[0]); 553 } else { 554 generate_math1_gen4(inst, dst, src[0]); 555 } 556 break; 557 558 case SHADER_OPCODE_POW: 559 if (intel->gen >= 6) { 560 generate_math2_gen6(inst, dst, src[0], src[1]); 561 } else { 562 generate_math2_gen4(inst, dst, src[0], src[1]); 563 } 564 break; 565 566 case VS_OPCODE_URB_WRITE: 567 generate_urb_write(inst); 568 break; 569 570 case VS_OPCODE_SCRATCH_READ: 571 generate_scratch_read(inst, dst, src[0]); 572 break; 573 574 case VS_OPCODE_SCRATCH_WRITE: 575 generate_scratch_write(inst, dst, src[0], src[1]); 576 break; 577 578 case VS_OPCODE_PULL_CONSTANT_LOAD: 579 generate_pull_constant_load(inst, dst, src[0]); 580 break; 581 582 default: 583 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 584 fail("unsupported opcode in `%s' in VS\n", 585 brw_opcodes[inst->opcode].name); 586 } else { 587 fail("Unsupported opcode %d in VS", inst->opcode); 588 } 589 } 590} 591 592bool 593vec4_visitor::run() 594{ 595 /* Generate VS IR for main(). (the visitor only descends into 596 * functions called "main"). 597 */ 598 visit_instructions(shader->ir); 599 600 emit_urb_writes(); 601 602 /* Before any optimization, push array accesses out to scratch 603 * space where we need them to be. This pass may allocate new 604 * virtual GRFs, so we want to do it early. It also makes sure 605 * that we have reladdr computations available for CSE, since we'll 606 * often do repeated subexpressions for those. 607 */ 608 move_grf_array_access_to_scratch(); 609 move_uniform_array_access_to_pull_constants(); 610 611 bool progress; 612 do { 613 progress = false; 614 progress = dead_code_eliminate() || progress; 615 } while (progress); 616 617 pack_uniform_registers(); 618 619 if (failed) 620 return false; 621 622 setup_payload(); 623 reg_allocate(); 624 625 if (failed) 626 return false; 627 628 brw_set_access_mode(p, BRW_ALIGN_16); 629 630 generate_code(); 631 632 return !failed; 633} 634 635void 636vec4_visitor::generate_code() 637{ 638 int last_native_inst = 0; 639 const char *last_annotation_string = NULL; 640 ir_instruction *last_annotation_ir = NULL; 641 642 int loop_stack_array_size = 16; 643 int loop_stack_depth = 0; 644 brw_instruction **loop_stack = 645 rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size); 646 int *if_depth_in_loop = 647 rzalloc_array(this->mem_ctx, int, loop_stack_array_size); 648 649 650 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 651 printf("Native code for vertex shader %d:\n", prog->Name); 652 } 653 654 foreach_list(node, &this->instructions) { 655 vec4_instruction *inst = (vec4_instruction *)node; 656 struct brw_reg src[3], dst; 657 658 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 659 if (last_annotation_ir != inst->ir) { 660 last_annotation_ir = inst->ir; 661 if (last_annotation_ir) { 662 printf(" "); 663 last_annotation_ir->print(); 664 printf("\n"); 665 } 666 } 667 if (last_annotation_string != inst->annotation) { 668 last_annotation_string = inst->annotation; 669 if (last_annotation_string) 670 printf(" %s\n", last_annotation_string); 671 } 672 } 673 674 for (unsigned int i = 0; i < 3; i++) { 675 src[i] = inst->get_src(i); 676 } 677 dst = inst->get_dst(); 678 679 brw_set_conditionalmod(p, inst->conditional_mod); 680 brw_set_predicate_control(p, inst->predicate); 681 brw_set_predicate_inverse(p, inst->predicate_inverse); 682 brw_set_saturate(p, inst->saturate); 683 684 switch (inst->opcode) { 685 case BRW_OPCODE_MOV: 686 brw_MOV(p, dst, src[0]); 687 break; 688 case BRW_OPCODE_ADD: 689 brw_ADD(p, dst, src[0], src[1]); 690 break; 691 case BRW_OPCODE_MUL: 692 brw_MUL(p, dst, src[0], src[1]); 693 break; 694 case BRW_OPCODE_MACH: 695 brw_set_acc_write_control(p, 1); 696 brw_MACH(p, dst, src[0], src[1]); 697 brw_set_acc_write_control(p, 0); 698 break; 699 700 case BRW_OPCODE_FRC: 701 brw_FRC(p, dst, src[0]); 702 break; 703 case BRW_OPCODE_RNDD: 704 brw_RNDD(p, dst, src[0]); 705 break; 706 case BRW_OPCODE_RNDE: 707 brw_RNDE(p, dst, src[0]); 708 break; 709 case BRW_OPCODE_RNDZ: 710 brw_RNDZ(p, dst, src[0]); 711 break; 712 713 case BRW_OPCODE_AND: 714 brw_AND(p, dst, src[0], src[1]); 715 break; 716 case BRW_OPCODE_OR: 717 brw_OR(p, dst, src[0], src[1]); 718 break; 719 case BRW_OPCODE_XOR: 720 brw_XOR(p, dst, src[0], src[1]); 721 break; 722 case BRW_OPCODE_NOT: 723 brw_NOT(p, dst, src[0]); 724 break; 725 case BRW_OPCODE_ASR: 726 brw_ASR(p, dst, src[0], src[1]); 727 break; 728 case BRW_OPCODE_SHR: 729 brw_SHR(p, dst, src[0], src[1]); 730 break; 731 case BRW_OPCODE_SHL: 732 brw_SHL(p, dst, src[0], src[1]); 733 break; 734 735 case BRW_OPCODE_CMP: 736 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 737 break; 738 case BRW_OPCODE_SEL: 739 brw_SEL(p, dst, src[0], src[1]); 740 break; 741 742 case BRW_OPCODE_DP4: 743 brw_DP4(p, dst, src[0], src[1]); 744 break; 745 746 case BRW_OPCODE_DP3: 747 brw_DP3(p, dst, src[0], src[1]); 748 break; 749 750 case BRW_OPCODE_DP2: 751 brw_DP2(p, dst, src[0], src[1]); 752 break; 753 754 case BRW_OPCODE_IF: 755 if (inst->src[0].file != BAD_FILE) { 756 /* The instruction has an embedded compare (only allowed on gen6) */ 757 assert(intel->gen == 6); 758 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 759 } else { 760 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 761 brw_inst->header.predicate_control = inst->predicate; 762 } 763 if_depth_in_loop[loop_stack_depth]++; 764 break; 765 766 case BRW_OPCODE_ELSE: 767 brw_ELSE(p); 768 break; 769 case BRW_OPCODE_ENDIF: 770 brw_ENDIF(p); 771 if_depth_in_loop[loop_stack_depth]--; 772 break; 773 774 case BRW_OPCODE_DO: 775 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 776 if (loop_stack_array_size <= loop_stack_depth) { 777 loop_stack_array_size *= 2; 778 loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *, 779 loop_stack_array_size); 780 if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int, 781 loop_stack_array_size); 782 } 783 if_depth_in_loop[loop_stack_depth] = 0; 784 break; 785 786 case BRW_OPCODE_BREAK: 787 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 788 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 789 break; 790 case BRW_OPCODE_CONTINUE: 791 /* FINISHME: We need to write the loop instruction support still. */ 792 if (intel->gen >= 6) 793 gen6_CONT(p, loop_stack[loop_stack_depth - 1]); 794 else 795 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 796 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 797 break; 798 799 case BRW_OPCODE_WHILE: { 800 struct brw_instruction *inst0, *inst1; 801 GLuint br = 1; 802 803 if (intel->gen >= 5) 804 br = 2; 805 806 assert(loop_stack_depth > 0); 807 loop_stack_depth--; 808 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 809 if (intel->gen < 6) { 810 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 811 while (inst0 > loop_stack[loop_stack_depth]) { 812 inst0--; 813 if (inst0->header.opcode == BRW_OPCODE_BREAK && 814 inst0->bits3.if_else.jump_count == 0) { 815 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 816 } 817 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 818 inst0->bits3.if_else.jump_count == 0) { 819 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 820 } 821 } 822 } 823 } 824 break; 825 826 default: 827 generate_vs_instruction(inst, dst, src); 828 break; 829 } 830 831 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 832 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 833 if (0) { 834 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 835 ((uint32_t *)&p->store[i])[3], 836 ((uint32_t *)&p->store[i])[2], 837 ((uint32_t *)&p->store[i])[1], 838 ((uint32_t *)&p->store[i])[0]); 839 } 840 brw_disasm(stdout, &p->store[i], intel->gen); 841 } 842 } 843 844 last_native_inst = p->nr_insn; 845 } 846 847 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 848 printf("\n"); 849 } 850 851 ralloc_free(loop_stack); 852 ralloc_free(if_depth_in_loop); 853 854 brw_set_uip_jip(p); 855 856 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 857 * emit issues, it doesn't get the jump distances into the output, 858 * which is often something we want to debug. So this is here in 859 * case you're doing that. 860 */ 861 if (0) { 862 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 863 for (unsigned int i = 0; i < p->nr_insn; i++) { 864 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 865 ((uint32_t *)&p->store[i])[3], 866 ((uint32_t *)&p->store[i])[2], 867 ((uint32_t *)&p->store[i])[1], 868 ((uint32_t *)&p->store[i])[0]); 869 brw_disasm(stdout, &p->store[i], intel->gen); 870 } 871 } 872 } 873} 874 875extern "C" { 876 877bool 878brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 879{ 880 if (!prog) 881 return false; 882 883 struct brw_shader *shader = 884 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 885 if (!shader) 886 return false; 887 888 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 889 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 890 _mesa_print_ir(shader->ir, NULL); 891 printf("\n\n"); 892 } 893 894 vec4_visitor v(c, prog, shader); 895 if (!v.run()) { 896 prog->LinkStatus = GL_FALSE; 897 ralloc_strcat(&prog->InfoLog, v.fail_msg); 898 return false; 899 } 900 901 return true; 902} 903 904} /* extern "C" */ 905 906} /* namespace brw */ 907