1/* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). 6 7This file is part of GDB, GAS, and the GNU binutils. 8 9This program is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 2 of the License, or 12(at your option) any later version. 13 14This program is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with this program; if not, see <http://www.gnu.org/licenses/>. */ 21 22#include "disas/bfd.h" 23 24/* mips.h. Mips opcode list for GDB, the GNU debugger. 25 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 26 Free Software Foundation, Inc. 27 Contributed by Ralph Campbell and OSF 28 Commented and modified by Ian Lance Taylor, Cygnus Support 29 30This file is part of GDB, GAS, and the GNU binutils. 31 32GDB, GAS, and the GNU binutils are free software; you can redistribute 33them and/or modify them under the terms of the GNU General Public 34License as published by the Free Software Foundation; either version 351, or (at your option) any later version. 36 37GDB, GAS, and the GNU binutils are distributed in the hope that they 38will be useful, but WITHOUT ANY WARRANTY; without even the implied 39warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 40the GNU General Public License for more details. 41 42You should have received a copy of the GNU General Public License 43along with this file; see the file COPYING. If not, 44see <http://www.gnu.org/licenses/>. */ 45 46/* These are bit masks and shift counts to use to access the various 47 fields of an instruction. To retrieve the X field of an 48 instruction, use the expression 49 (i >> OP_SH_X) & OP_MASK_X 50 To set the same field (to j), use 51 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 52 53 Make sure you use fields that are appropriate for the instruction, 54 of course. 55 56 The 'i' format uses OP, RS, RT and IMMEDIATE. 57 58 The 'j' format uses OP and TARGET. 59 60 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 61 62 The 'b' format uses OP, RS, RT and DELTA. 63 64 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 65 66 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 67 68 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 69 breakpoint instruction are not defined; Kane says the breakpoint 70 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 71 only use ten bits). An optional two-operand form of break/sdbbp 72 allows the lower ten bits to be set too, and MIPS32 and later 73 architectures allow 20 bits to be set with a signal operand 74 (using CODE20). 75 76 The syscall instruction uses CODE20. 77 78 The general coprocessor instructions use COPZ. */ 79 80#define OP_MASK_OP 0x3f 81#define OP_SH_OP 26 82#define OP_MASK_RS 0x1f 83#define OP_SH_RS 21 84#define OP_MASK_FR 0x1f 85#define OP_SH_FR 21 86#define OP_MASK_FMT 0x1f 87#define OP_SH_FMT 21 88#define OP_MASK_BCC 0x7 89#define OP_SH_BCC 18 90#define OP_MASK_CODE 0x3ff 91#define OP_SH_CODE 16 92#define OP_MASK_CODE2 0x3ff 93#define OP_SH_CODE2 6 94#define OP_MASK_RT 0x1f 95#define OP_SH_RT 16 96#define OP_MASK_FT 0x1f 97#define OP_SH_FT 16 98#define OP_MASK_CACHE 0x1f 99#define OP_SH_CACHE 16 100#define OP_MASK_RD 0x1f 101#define OP_SH_RD 11 102#define OP_MASK_FS 0x1f 103#define OP_SH_FS 11 104#define OP_MASK_PREFX 0x1f 105#define OP_SH_PREFX 11 106#define OP_MASK_CCC 0x7 107#define OP_SH_CCC 8 108#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 109#define OP_SH_CODE20 6 110#define OP_MASK_SHAMT 0x1f 111#define OP_SH_SHAMT 6 112#define OP_MASK_FD 0x1f 113#define OP_SH_FD 6 114#define OP_MASK_TARGET 0x3ffffff 115#define OP_SH_TARGET 0 116#define OP_MASK_COPZ 0x1ffffff 117#define OP_SH_COPZ 0 118#define OP_MASK_IMMEDIATE 0xffff 119#define OP_SH_IMMEDIATE 0 120#define OP_MASK_DELTA 0xffff 121#define OP_SH_DELTA 0 122#define OP_MASK_FUNCT 0x3f 123#define OP_SH_FUNCT 0 124#define OP_MASK_SPEC 0x3f 125#define OP_SH_SPEC 0 126#define OP_SH_LOCC 8 /* FP condition code. */ 127#define OP_SH_HICC 18 /* FP condition code. */ 128#define OP_MASK_CC 0x7 129#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 130#define OP_MASK_COP1NORM 0x1 /* a single bit. */ 131#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 132#define OP_MASK_COP1SPEC 0xf 133#define OP_MASK_COP1SCLR 0x4 134#define OP_MASK_COP1CMP 0x3 135#define OP_SH_COP1CMP 4 136#define OP_SH_FORMAT 21 /* FP short format field. */ 137#define OP_MASK_FORMAT 0x7 138#define OP_SH_TRUE 16 139#define OP_MASK_TRUE 0x1 140#define OP_SH_GE 17 141#define OP_MASK_GE 0x01 142#define OP_SH_UNSIGNED 16 143#define OP_MASK_UNSIGNED 0x1 144#define OP_SH_HINT 16 145#define OP_MASK_HINT 0x1f 146#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 147#define OP_MASK_MMI 0x3f 148#define OP_SH_MMISUB 6 149#define OP_MASK_MMISUB 0x1f 150#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 151#define OP_SH_PERFREG 1 152#define OP_SH_SEL 0 /* Coprocessor select field. */ 153#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 154#define OP_SH_CODE19 6 /* 19 bit wait code. */ 155#define OP_MASK_CODE19 0x7ffff 156#define OP_SH_ALN 21 157#define OP_MASK_ALN 0x7 158#define OP_SH_VSEL 21 159#define OP_MASK_VSEL 0x1f 160#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 161 but 0x8-0xf don't select bytes. */ 162#define OP_SH_VECBYTE 22 163#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 164#define OP_SH_VECALIGN 21 165#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 166#define OP_SH_INSMSB 11 167#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 168#define OP_SH_EXTMSBD 11 169 170#define OP_OP_COP0 0x10 171#define OP_OP_COP1 0x11 172#define OP_OP_COP2 0x12 173#define OP_OP_COP3 0x13 174#define OP_OP_LWC1 0x31 175#define OP_OP_LWC2 0x32 176#define OP_OP_LWC3 0x33 /* a.k.a. pref */ 177#define OP_OP_LDC1 0x35 178#define OP_OP_LDC2 0x36 179#define OP_OP_LDC3 0x37 /* a.k.a. ld */ 180#define OP_OP_SWC1 0x39 181#define OP_OP_SWC2 0x3a 182#define OP_OP_SWC3 0x3b 183#define OP_OP_SDC1 0x3d 184#define OP_OP_SDC2 0x3e 185#define OP_OP_SDC3 0x3f /* a.k.a. sd */ 186 187/* MIPS DSP ASE */ 188#define OP_SH_DSPACC 11 189#define OP_MASK_DSPACC 0x3 190#define OP_SH_DSPACC_S 21 191#define OP_MASK_DSPACC_S 0x3 192#define OP_SH_DSPSFT 20 193#define OP_MASK_DSPSFT 0x3f 194#define OP_SH_DSPSFT_7 19 195#define OP_MASK_DSPSFT_7 0x7f 196#define OP_SH_SA3 21 197#define OP_MASK_SA3 0x7 198#define OP_SH_SA4 21 199#define OP_MASK_SA4 0xf 200#define OP_SH_IMM8 16 201#define OP_MASK_IMM8 0xff 202#define OP_SH_IMM10 16 203#define OP_MASK_IMM10 0x3ff 204#define OP_SH_WRDSP 11 205#define OP_MASK_WRDSP 0x3f 206#define OP_SH_RDDSP 16 207#define OP_MASK_RDDSP 0x3f 208#define OP_SH_BP 11 209#define OP_MASK_BP 0x3 210 211/* MIPS MT ASE */ 212#define OP_SH_MT_U 5 213#define OP_MASK_MT_U 0x1 214#define OP_SH_MT_H 4 215#define OP_MASK_MT_H 0x1 216#define OP_SH_MTACC_T 18 217#define OP_MASK_MTACC_T 0x3 218#define OP_SH_MTACC_D 13 219#define OP_MASK_MTACC_D 0x3 220 221#define OP_OP_COP0 0x10 222#define OP_OP_COP1 0x11 223#define OP_OP_COP2 0x12 224#define OP_OP_COP3 0x13 225#define OP_OP_LWC1 0x31 226#define OP_OP_LWC2 0x32 227#define OP_OP_LWC3 0x33 /* a.k.a. pref */ 228#define OP_OP_LDC1 0x35 229#define OP_OP_LDC2 0x36 230#define OP_OP_LDC3 0x37 /* a.k.a. ld */ 231#define OP_OP_SWC1 0x39 232#define OP_OP_SWC2 0x3a 233#define OP_OP_SWC3 0x3b 234#define OP_OP_SDC1 0x3d 235#define OP_OP_SDC2 0x3e 236#define OP_OP_SDC3 0x3f /* a.k.a. sd */ 237 238/* Values in the 'VSEL' field. */ 239#define MDMX_FMTSEL_IMM_QH 0x1d 240#define MDMX_FMTSEL_IMM_OB 0x1e 241#define MDMX_FMTSEL_VEC_QH 0x15 242#define MDMX_FMTSEL_VEC_OB 0x16 243 244/* UDI */ 245#define OP_SH_UDI1 6 246#define OP_MASK_UDI1 0x1f 247#define OP_SH_UDI2 6 248#define OP_MASK_UDI2 0x3ff 249#define OP_SH_UDI3 6 250#define OP_MASK_UDI3 0x7fff 251#define OP_SH_UDI4 6 252#define OP_MASK_UDI4 0xfffff 253/* This structure holds information for a particular instruction. */ 254 255struct mips_opcode 256{ 257 /* The name of the instruction. */ 258 const char *name; 259 /* A string describing the arguments for this instruction. */ 260 const char *args; 261 /* The basic opcode for the instruction. When assembling, this 262 opcode is modified by the arguments to produce the actual opcode 263 that is used. If pinfo is INSN_MACRO, then this is 0. */ 264 unsigned long match; 265 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 266 relevant portions of the opcode when disassembling. If the 267 actual opcode anded with the match field equals the opcode field, 268 then we have found the correct instruction. If pinfo is 269 INSN_MACRO, then this field is the macro identifier. */ 270 unsigned long mask; 271 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 272 of bits describing the instruction, notably any relevant hazard 273 information. */ 274 unsigned long pinfo; 275 /* A collection of additional bits describing the instruction. */ 276 unsigned long pinfo2; 277 /* A collection of bits describing the instruction sets of which this 278 instruction or macro is a member. */ 279 unsigned long membership; 280}; 281 282/* These are the characters which may appear in the args field of an 283 instruction. They appear in the order in which the fields appear 284 when the instruction is used. Commas and parentheses in the args 285 string are ignored when assembling, and written into the output 286 when disassembling. 287 288 Each of these characters corresponds to a mask field defined above. 289 290 "<" 5 bit shift amount (OP_*_SHAMT) 291 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 292 "a" 26 bit target address (OP_*_TARGET) 293 "b" 5 bit base register (OP_*_RS) 294 "c" 10 bit breakpoint code (OP_*_CODE) 295 "d" 5 bit destination register specifier (OP_*_RD) 296 "h" 5 bit prefx hint (OP_*_PREFX) 297 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 298 "j" 16 bit signed immediate (OP_*_DELTA) 299 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 300 Also used for immediate operands in vr5400 vector insns. 301 "o" 16 bit signed offset (OP_*_DELTA) 302 "p" 16 bit PC relative branch target address (OP_*_DELTA) 303 "q" 10 bit extra breakpoint code (OP_*_CODE2) 304 "r" 5 bit same register used as both source and target (OP_*_RS) 305 "s" 5 bit source register specifier (OP_*_RS) 306 "t" 5 bit target register (OP_*_RT) 307 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 308 "v" 5 bit same register used as both source and destination (OP_*_RS) 309 "w" 5 bit same register used as both target and destination (OP_*_RT) 310 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 311 (used by clo and clz) 312 "C" 25 bit coprocessor function code (OP_*_COPZ) 313 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 314 "J" 19 bit wait function code (OP_*_CODE19) 315 "x" accept and ignore register name 316 "z" must be zero register 317 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 318 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 319 LSB (OP_*_SHAMT). 320 Enforces: 0 <= pos < 32. 321 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 322 Requires that "+A" or "+E" occur first to set position. 323 Enforces: 0 < (pos+size) <= 32. 324 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 325 Requires that "+A" or "+E" occur first to set position. 326 Enforces: 0 < (pos+size) <= 32. 327 (Also used by "dext" w/ different limits, but limits for 328 that are checked by the M_DEXT macro.) 329 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 330 Enforces: 32 <= pos < 64. 331 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 332 Requires that "+A" or "+E" occur first to set position. 333 Enforces: 32 < (pos+size) <= 64. 334 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 335 Requires that "+A" or "+E" occur first to set position. 336 Enforces: 32 < (pos+size) <= 64. 337 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 338 Requires that "+A" or "+E" occur first to set position. 339 Enforces: 32 < (pos+size) <= 64. 340 341 Floating point instructions: 342 "D" 5 bit destination register (OP_*_FD) 343 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 344 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 345 "S" 5 bit fs source 1 register (OP_*_FS) 346 "T" 5 bit ft source 2 register (OP_*_FT) 347 "R" 5 bit fr source 3 register (OP_*_FR) 348 "V" 5 bit same register used as floating source and destination (OP_*_FS) 349 "W" 5 bit same register used as floating target and destination (OP_*_FT) 350 351 Coprocessor instructions: 352 "E" 5 bit target register (OP_*_RT) 353 "G" 5 bit destination register (OP_*_RD) 354 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 355 "P" 5 bit performance-monitor register (OP_*_PERFREG) 356 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 357 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 358 see also "k" above 359 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 360 for pretty-printing in disassembly only. 361 362 Macro instructions: 363 "A" General 32 bit expression 364 "I" 32 bit immediate (value placed in imm_expr). 365 "+I" 32 bit immediate (value placed in imm2_expr). 366 "F" 64 bit floating point constant in .rdata 367 "L" 64 bit floating point constant in .lit8 368 "f" 32 bit floating point constant 369 "l" 32 bit floating point constant in .lit4 370 371 MDMX instruction operands (note that while these use the FP register 372 fields, they accept both $fN and $vN names for the registers): 373 "O" MDMX alignment offset (OP_*_ALN) 374 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 375 "X" MDMX destination register (OP_*_FD) 376 "Y" MDMX source register (OP_*_FS) 377 "Z" MDMX source register (OP_*_FT) 378 379 DSP ASE usage: 380 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 381 "3" 3 bit unsigned immediate (OP_*_SA3) 382 "4" 4 bit unsigned immediate (OP_*_SA4) 383 "5" 8 bit unsigned immediate (OP_*_IMM8) 384 "6" 5 bit unsigned immediate (OP_*_RS) 385 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 386 "8" 6 bit unsigned immediate (OP_*_WRDSP) 387 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 388 "0" 6 bit signed immediate (OP_*_DSPSFT) 389 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 390 "'" 6 bit unsigned immediate (OP_*_RDDSP) 391 "@" 10 bit signed immediate (OP_*_IMM10) 392 393 MT ASE usage: 394 "!" 1 bit usermode flag (OP_*_MT_U) 395 "$" 1 bit load high flag (OP_*_MT_H) 396 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 397 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 398 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 399 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 400 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 401 402 UDI immediates: 403 "+1" UDI immediate bits 6-10 404 "+2" UDI immediate bits 6-15 405 "+3" UDI immediate bits 6-20 406 "+4" UDI immediate bits 6-25 407 408 Other: 409 "()" parens surrounding optional value 410 "," separates operands 411 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 412 "+" Start of extension sequence. 413 414 Characters used so far, for quick reference when adding more: 415 "234567890" 416 "%[]<>(),+:'@!$*&" 417 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 418 "abcdefghijklopqrstuvwxz" 419 420 Extension character sequences used so far ("+" followed by the 421 following), for quick reference when adding more: 422 "1234" 423 "ABCDEFGHIT" 424 "t" 425*/ 426 427/* These are the bits which may be set in the pinfo field of an 428 instructions, if it is not equal to INSN_MACRO. */ 429 430/* Modifies the general purpose register in OP_*_RD. */ 431#define INSN_WRITE_GPR_D 0x00000001 432/* Modifies the general purpose register in OP_*_RT. */ 433#define INSN_WRITE_GPR_T 0x00000002 434/* Modifies general purpose register 31. */ 435#define INSN_WRITE_GPR_31 0x00000004 436/* Modifies the floating point register in OP_*_FD. */ 437#define INSN_WRITE_FPR_D 0x00000008 438/* Modifies the floating point register in OP_*_FS. */ 439#define INSN_WRITE_FPR_S 0x00000010 440/* Modifies the floating point register in OP_*_FT. */ 441#define INSN_WRITE_FPR_T 0x00000020 442/* Reads the general purpose register in OP_*_RS. */ 443#define INSN_READ_GPR_S 0x00000040 444/* Reads the general purpose register in OP_*_RT. */ 445#define INSN_READ_GPR_T 0x00000080 446/* Reads the floating point register in OP_*_FS. */ 447#define INSN_READ_FPR_S 0x00000100 448/* Reads the floating point register in OP_*_FT. */ 449#define INSN_READ_FPR_T 0x00000200 450/* Reads the floating point register in OP_*_FR. */ 451#define INSN_READ_FPR_R 0x00000400 452/* Modifies coprocessor condition code. */ 453#define INSN_WRITE_COND_CODE 0x00000800 454/* Reads coprocessor condition code. */ 455#define INSN_READ_COND_CODE 0x00001000 456/* TLB operation. */ 457#define INSN_TLB 0x00002000 458/* Reads coprocessor register other than floating point register. */ 459#define INSN_COP 0x00004000 460/* Instruction loads value from memory, requiring delay. */ 461#define INSN_LOAD_MEMORY_DELAY 0x00008000 462/* Instruction loads value from coprocessor, requiring delay. */ 463#define INSN_LOAD_COPROC_DELAY 0x00010000 464/* Instruction has unconditional branch delay slot. */ 465#define INSN_UNCOND_BRANCH_DELAY 0x00020000 466/* Instruction has conditional branch delay slot. */ 467#define INSN_COND_BRANCH_DELAY 0x00040000 468/* Conditional branch likely: if branch not taken, insn nullified. */ 469#define INSN_COND_BRANCH_LIKELY 0x00080000 470/* Moves to coprocessor register, requiring delay. */ 471#define INSN_COPROC_MOVE_DELAY 0x00100000 472/* Loads coprocessor register from memory, requiring delay. */ 473#define INSN_COPROC_MEMORY_DELAY 0x00200000 474/* Reads the HI register. */ 475#define INSN_READ_HI 0x00400000 476/* Reads the LO register. */ 477#define INSN_READ_LO 0x00800000 478/* Modifies the HI register. */ 479#define INSN_WRITE_HI 0x01000000 480/* Modifies the LO register. */ 481#define INSN_WRITE_LO 0x02000000 482/* Takes a trap (easier to keep out of delay slot). */ 483#define INSN_TRAP 0x04000000 484/* Instruction stores value into memory. */ 485#define INSN_STORE_MEMORY 0x08000000 486/* Instruction uses single precision floating point. */ 487#define FP_S 0x10000000 488/* Instruction uses double precision floating point. */ 489#define FP_D 0x20000000 490/* Instruction is part of the tx39's integer multiply family. */ 491#define INSN_MULT 0x40000000 492/* Instruction synchronize shared memory. */ 493#define INSN_SYNC 0x80000000 494 495/* These are the bits which may be set in the pinfo2 field of an 496 instruction. */ 497 498/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 499#define INSN2_ALIAS 0x00000001 500/* Instruction reads MDMX accumulator. */ 501#define INSN2_READ_MDMX_ACC 0x00000002 502/* Instruction writes MDMX accumulator. */ 503#define INSN2_WRITE_MDMX_ACC 0x00000004 504 505/* Instruction is actually a macro. It should be ignored by the 506 disassembler, and requires special treatment by the assembler. */ 507#define INSN_MACRO 0xffffffff 508 509/* Masks used to mark instructions to indicate which MIPS ISA level 510 they were introduced in. ISAs, as defined below, are logical 511 ORs of these bits, indicating that they support the instructions 512 defined at the given level. */ 513 514#define INSN_ISA_MASK 0x00000fff 515#define INSN_ISA1 0x00000001 516#define INSN_ISA2 0x00000002 517#define INSN_ISA3 0x00000004 518#define INSN_ISA4 0x00000008 519#define INSN_ISA5 0x00000010 520#define INSN_ISA32 0x00000020 521#define INSN_ISA64 0x00000040 522#define INSN_ISA32R2 0x00000080 523#define INSN_ISA64R2 0x00000100 524 525/* Masks used for MIPS-defined ASEs. */ 526#define INSN_ASE_MASK 0x0000f000 527 528/* DSP ASE */ 529#define INSN_DSP 0x00001000 530#define INSN_DSP64 0x00002000 531/* MIPS 16 ASE */ 532#define INSN_MIPS16 0x00004000 533/* MIPS-3D ASE */ 534#define INSN_MIPS3D 0x00008000 535 536/* Chip specific instructions. These are bitmasks. */ 537 538/* MIPS R4650 instruction. */ 539#define INSN_4650 0x00010000 540/* LSI R4010 instruction. */ 541#define INSN_4010 0x00020000 542/* NEC VR4100 instruction. */ 543#define INSN_4100 0x00040000 544/* Toshiba R3900 instruction. */ 545#define INSN_3900 0x00080000 546/* MIPS R10000 instruction. */ 547#define INSN_10000 0x00100000 548/* Broadcom SB-1 instruction. */ 549#define INSN_SB1 0x00200000 550/* NEC VR4111/VR4181 instruction. */ 551#define INSN_4111 0x00400000 552/* NEC VR4120 instruction. */ 553#define INSN_4120 0x00800000 554/* NEC VR5400 instruction. */ 555#define INSN_5400 0x01000000 556/* NEC VR5500 instruction. */ 557#define INSN_5500 0x02000000 558 559/* MDMX ASE */ 560#define INSN_MDMX 0x04000000 561/* MT ASE */ 562#define INSN_MT 0x08000000 563/* SmartMIPS ASE */ 564#define INSN_SMARTMIPS 0x10000000 565/* DSP R2 ASE */ 566#define INSN_DSPR2 0x20000000 567 568/* ST Microelectronics Loongson 2E. */ 569#define INSN_LOONGSON_2E 0x40000000 570/* ST Microelectronics Loongson 2F. */ 571#define INSN_LOONGSON_2F 0x80000000 572 573/* MIPS ISA defines, use instead of hardcoding ISA level. */ 574 575#ifndef ISA_MIPS1 576#define ISA_UNKNOWN 0 /* Gas internal use. */ 577#define ISA_MIPS1 (INSN_ISA1) 578#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 579#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 580#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 581#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 582 583#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 584#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 585 586#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 587#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 588#endif // ISA_MIPS1 589 590/* CPU defines, use instead of hardcoding processor number. Keep this 591 in sync with bfd/archures.c in order for machine selection to work. */ 592#define CPU_UNKNOWN 0 /* Gas internal use. */ 593#define CPU_R3000 3000 594#define CPU_R3900 3900 595#define CPU_R4000 4000 596#define CPU_R4010 4010 597#define CPU_VR4100 4100 598#define CPU_R4111 4111 599#define CPU_VR4120 4120 600#define CPU_R4300 4300 601#define CPU_R4400 4400 602#define CPU_R4600 4600 603#define CPU_R4650 4650 604#define CPU_R5000 5000 605#define CPU_VR5400 5400 606#define CPU_VR5500 5500 607#define CPU_R6000 6000 608#define CPU_RM7000 7000 609#define CPU_R8000 8000 610#define CPU_R10000 10000 611#define CPU_R12000 12000 612 613#define CPU_MIPS16 16 614#define CPU_SB1 12310201 /* octal 'SB', 01. */ 615 616#ifndef CPU_MIPS32 617#define CPU_MIPS32 32 618#define CPU_MIPS32R2 33 619#define CPU_MIPS5 5 620#define CPU_MIPS64 64 621#define CPU_MIPS64R2 65 622#endif // !CPU_MIPS32 623 624/* Test for membership in an ISA including chip specific ISAs. INSN 625 is pointer to an element of the opcode table; ISA is the specified 626 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 627 test, or zero if no CPU specific ISA test is desired. */ 628 629#if 0 630#define OPCODE_IS_MEMBER(insn, isa, cpu) \ 631 (((insn)->membership & isa) != 0 \ 632 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 633 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 634 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 635 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 636 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 637 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 638 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 639 && ((insn)->membership & INSN_10000) != 0) \ 640 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 641 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 642 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 643 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 644 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 645 || 0) /* Please keep this term for easier source merging. */ 646#else 647#define OPCODE_IS_MEMBER(insn, isa, cpu) \ 648 (1 != 0) 649#endif 650 651/* This is a list of macro expanded instructions. 652 653 _I appended means immediate 654 _A appended means address 655 _AB appended means address with base register 656 _D appended means 64 bit floating point constant 657 _S appended means 32 bit floating point constant. */ 658 659enum 660{ 661 M_ABS, 662 M_ADD_I, 663 M_ADDU_I, 664 M_AND_I, 665 M_BALIGN, 666 M_BEQ, 667 M_BEQ_I, 668 M_BEQL_I, 669 M_BGE, 670 M_BGEL, 671 M_BGE_I, 672 M_BGEL_I, 673 M_BGEU, 674 M_BGEUL, 675 M_BGEU_I, 676 M_BGEUL_I, 677 M_BGT, 678 M_BGTL, 679 M_BGT_I, 680 M_BGTL_I, 681 M_BGTU, 682 M_BGTUL, 683 M_BGTU_I, 684 M_BGTUL_I, 685 M_BLE, 686 M_BLEL, 687 M_BLE_I, 688 M_BLEL_I, 689 M_BLEU, 690 M_BLEUL, 691 M_BLEU_I, 692 M_BLEUL_I, 693 M_BLT, 694 M_BLTL, 695 M_BLT_I, 696 M_BLTL_I, 697 M_BLTU, 698 M_BLTUL, 699 M_BLTU_I, 700 M_BLTUL_I, 701 M_BNE, 702 M_BNE_I, 703 M_BNEL_I, 704 M_CACHE_AB, 705 M_DABS, 706 M_DADD_I, 707 M_DADDU_I, 708 M_DDIV_3, 709 M_DDIV_3I, 710 M_DDIVU_3, 711 M_DDIVU_3I, 712 M_DEXT, 713 M_DINS, 714 M_DIV_3, 715 M_DIV_3I, 716 M_DIVU_3, 717 M_DIVU_3I, 718 M_DLA_AB, 719 M_DLCA_AB, 720 M_DLI, 721 M_DMUL, 722 M_DMUL_I, 723 M_DMULO, 724 M_DMULO_I, 725 M_DMULOU, 726 M_DMULOU_I, 727 M_DREM_3, 728 M_DREM_3I, 729 M_DREMU_3, 730 M_DREMU_3I, 731 M_DSUB_I, 732 M_DSUBU_I, 733 M_DSUBU_I_2, 734 M_J_A, 735 M_JAL_1, 736 M_JAL_2, 737 M_JAL_A, 738 M_L_DOB, 739 M_L_DAB, 740 M_LA_AB, 741 M_LB_A, 742 M_LB_AB, 743 M_LBU_A, 744 M_LBU_AB, 745 M_LCA_AB, 746 M_LD_A, 747 M_LD_OB, 748 M_LD_AB, 749 M_LDC1_AB, 750 M_LDC2_AB, 751 M_LDC3_AB, 752 M_LDL_AB, 753 M_LDR_AB, 754 M_LH_A, 755 M_LH_AB, 756 M_LHU_A, 757 M_LHU_AB, 758 M_LI, 759 M_LI_D, 760 M_LI_DD, 761 M_LI_S, 762 M_LI_SS, 763 M_LL_AB, 764 M_LLD_AB, 765 M_LS_A, 766 M_LW_A, 767 M_LW_AB, 768 M_LWC0_A, 769 M_LWC0_AB, 770 M_LWC1_A, 771 M_LWC1_AB, 772 M_LWC2_A, 773 M_LWC2_AB, 774 M_LWC3_A, 775 M_LWC3_AB, 776 M_LWL_A, 777 M_LWL_AB, 778 M_LWR_A, 779 M_LWR_AB, 780 M_LWU_AB, 781 M_MOVE, 782 M_MUL, 783 M_MUL_I, 784 M_MULO, 785 M_MULO_I, 786 M_MULOU, 787 M_MULOU_I, 788 M_NOR_I, 789 M_OR_I, 790 M_REM_3, 791 M_REM_3I, 792 M_REMU_3, 793 M_REMU_3I, 794 M_DROL, 795 M_ROL, 796 M_DROL_I, 797 M_ROL_I, 798 M_DROR, 799 M_ROR, 800 M_DROR_I, 801 M_ROR_I, 802 M_S_DA, 803 M_S_DOB, 804 M_S_DAB, 805 M_S_S, 806 M_SC_AB, 807 M_SCD_AB, 808 M_SD_A, 809 M_SD_OB, 810 M_SD_AB, 811 M_SDC1_AB, 812 M_SDC2_AB, 813 M_SDC3_AB, 814 M_SDL_AB, 815 M_SDR_AB, 816 M_SEQ, 817 M_SEQ_I, 818 M_SGE, 819 M_SGE_I, 820 M_SGEU, 821 M_SGEU_I, 822 M_SGT, 823 M_SGT_I, 824 M_SGTU, 825 M_SGTU_I, 826 M_SLE, 827 M_SLE_I, 828 M_SLEU, 829 M_SLEU_I, 830 M_SLT_I, 831 M_SLTU_I, 832 M_SNE, 833 M_SNE_I, 834 M_SB_A, 835 M_SB_AB, 836 M_SH_A, 837 M_SH_AB, 838 M_SW_A, 839 M_SW_AB, 840 M_SWC0_A, 841 M_SWC0_AB, 842 M_SWC1_A, 843 M_SWC1_AB, 844 M_SWC2_A, 845 M_SWC2_AB, 846 M_SWC3_A, 847 M_SWC3_AB, 848 M_SWL_A, 849 M_SWL_AB, 850 M_SWR_A, 851 M_SWR_AB, 852 M_SUB_I, 853 M_SUBU_I, 854 M_SUBU_I_2, 855 M_TEQ_I, 856 M_TGE_I, 857 M_TGEU_I, 858 M_TLT_I, 859 M_TLTU_I, 860 M_TNE_I, 861 M_TRUNCWD, 862 M_TRUNCWS, 863 M_ULD, 864 M_ULD_A, 865 M_ULH, 866 M_ULH_A, 867 M_ULHU, 868 M_ULHU_A, 869 M_ULW, 870 M_ULW_A, 871 M_USH, 872 M_USH_A, 873 M_USW, 874 M_USW_A, 875 M_USD, 876 M_USD_A, 877 M_XOR_I, 878 M_COP0, 879 M_COP1, 880 M_COP2, 881 M_COP3, 882 M_NUM_MACROS 883}; 884 885 886/* The order of overloaded instructions matters. Label arguments and 887 register arguments look the same. Instructions that can have either 888 for arguments must apear in the correct order in this table for the 889 assembler to pick the right one. In other words, entries with 890 immediate operands must apear after the same instruction with 891 registers. 892 893 Many instructions are short hand for other instructions (i.e., The 894 jal <register> instruction is short for jalr <register>). */ 895 896extern const struct mips_opcode mips_builtin_opcodes[]; 897extern const int bfd_mips_num_builtin_opcodes; 898extern struct mips_opcode *mips_opcodes; 899extern int bfd_mips_num_opcodes; 900#define NUMOPCODES bfd_mips_num_opcodes 901 902 903/* The rest of this file adds definitions for the mips16 TinyRISC 904 processor. */ 905 906/* These are the bitmasks and shift counts used for the different 907 fields in the instruction formats. Other than OP, no masks are 908 provided for the fixed portions of an instruction, since they are 909 not needed. 910 911 The I format uses IMM11. 912 913 The RI format uses RX and IMM8. 914 915 The RR format uses RX, and RY. 916 917 The RRI format uses RX, RY, and IMM5. 918 919 The RRR format uses RX, RY, and RZ. 920 921 The RRI_A format uses RX, RY, and IMM4. 922 923 The SHIFT format uses RX, RY, and SHAMT. 924 925 The I8 format uses IMM8. 926 927 The I8_MOVR32 format uses RY and REGR32. 928 929 The IR_MOV32R format uses REG32R and MOV32Z. 930 931 The I64 format uses IMM8. 932 933 The RI64 format uses RY and IMM5. 934 */ 935 936#define MIPS16OP_MASK_OP 0x1f 937#define MIPS16OP_SH_OP 11 938#define MIPS16OP_MASK_IMM11 0x7ff 939#define MIPS16OP_SH_IMM11 0 940#define MIPS16OP_MASK_RX 0x7 941#define MIPS16OP_SH_RX 8 942#define MIPS16OP_MASK_IMM8 0xff 943#define MIPS16OP_SH_IMM8 0 944#define MIPS16OP_MASK_RY 0x7 945#define MIPS16OP_SH_RY 5 946#define MIPS16OP_MASK_IMM5 0x1f 947#define MIPS16OP_SH_IMM5 0 948#define MIPS16OP_MASK_RZ 0x7 949#define MIPS16OP_SH_RZ 2 950#define MIPS16OP_MASK_IMM4 0xf 951#define MIPS16OP_SH_IMM4 0 952#define MIPS16OP_MASK_REGR32 0x1f 953#define MIPS16OP_SH_REGR32 0 954#define MIPS16OP_MASK_REG32R 0x1f 955#define MIPS16OP_SH_REG32R 3 956#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 957#define MIPS16OP_MASK_MOVE32Z 0x7 958#define MIPS16OP_SH_MOVE32Z 0 959#define MIPS16OP_MASK_IMM6 0x3f 960#define MIPS16OP_SH_IMM6 5 961 962/* These are the characters which may appears in the args field of an 963 instruction. They appear in the order in which the fields appear 964 when the instruction is used. Commas and parentheses in the args 965 string are ignored when assembling, and written into the output 966 when disassembling. 967 968 "y" 3 bit register (MIPS16OP_*_RY) 969 "x" 3 bit register (MIPS16OP_*_RX) 970 "z" 3 bit register (MIPS16OP_*_RZ) 971 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 972 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 973 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 974 "0" zero register ($0) 975 "S" stack pointer ($sp or $29) 976 "P" program counter 977 "R" return address register ($ra or $31) 978 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 979 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 980 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 981 "a" 26 bit jump address 982 "e" 11 bit extension value 983 "l" register list for entry instruction 984 "L" register list for exit instruction 985 986 The remaining codes may be extended. Except as otherwise noted, 987 the full extended operand is a 16 bit signed value. 988 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 989 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 990 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 991 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 992 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 993 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 994 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 995 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 996 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 997 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 998 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 999 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1000 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1001 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1002 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1003 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1004 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1005 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1006 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1007 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1008 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1009 */ 1010 1011/* Save/restore encoding for the args field when all 4 registers are 1012 either saved as arguments or saved/restored as statics. */ 1013#define MIPS16_ALL_ARGS 0xe 1014#define MIPS16_ALL_STATICS 0xb 1015 1016/* For the mips16, we use the same opcode table format and a few of 1017 the same flags. However, most of the flags are different. */ 1018 1019/* Modifies the register in MIPS16OP_*_RX. */ 1020#define MIPS16_INSN_WRITE_X 0x00000001 1021/* Modifies the register in MIPS16OP_*_RY. */ 1022#define MIPS16_INSN_WRITE_Y 0x00000002 1023/* Modifies the register in MIPS16OP_*_RZ. */ 1024#define MIPS16_INSN_WRITE_Z 0x00000004 1025/* Modifies the T ($24) register. */ 1026#define MIPS16_INSN_WRITE_T 0x00000008 1027/* Modifies the SP ($29) register. */ 1028#define MIPS16_INSN_WRITE_SP 0x00000010 1029/* Modifies the RA ($31) register. */ 1030#define MIPS16_INSN_WRITE_31 0x00000020 1031/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 1032#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 1033/* Reads the register in MIPS16OP_*_RX. */ 1034#define MIPS16_INSN_READ_X 0x00000080 1035/* Reads the register in MIPS16OP_*_RY. */ 1036#define MIPS16_INSN_READ_Y 0x00000100 1037/* Reads the register in MIPS16OP_*_MOVE32Z. */ 1038#define MIPS16_INSN_READ_Z 0x00000200 1039/* Reads the T ($24) register. */ 1040#define MIPS16_INSN_READ_T 0x00000400 1041/* Reads the SP ($29) register. */ 1042#define MIPS16_INSN_READ_SP 0x00000800 1043/* Reads the RA ($31) register. */ 1044#define MIPS16_INSN_READ_31 0x00001000 1045/* Reads the program counter. */ 1046#define MIPS16_INSN_READ_PC 0x00002000 1047/* Reads the general purpose register in MIPS16OP_*_REGR32. */ 1048#define MIPS16_INSN_READ_GPR_X 0x00004000 1049/* Is a branch insn. */ 1050#define MIPS16_INSN_BRANCH 0x00010000 1051 1052/* The following flags have the same value for the mips16 opcode 1053 table: 1054 INSN_UNCOND_BRANCH_DELAY 1055 INSN_COND_BRANCH_DELAY 1056 INSN_COND_BRANCH_LIKELY (never used) 1057 INSN_READ_HI 1058 INSN_READ_LO 1059 INSN_WRITE_HI 1060 INSN_WRITE_LO 1061 INSN_TRAP 1062 INSN_ISA3 1063 */ 1064 1065extern const struct mips_opcode mips16_opcodes[]; 1066extern const int bfd_mips16_num_opcodes; 1067 1068/* Short hand so the lines aren't too long. */ 1069 1070#define LDD INSN_LOAD_MEMORY_DELAY 1071#define LCD INSN_LOAD_COPROC_DELAY 1072#define UBD INSN_UNCOND_BRANCH_DELAY 1073#define CBD INSN_COND_BRANCH_DELAY 1074#define COD INSN_COPROC_MOVE_DELAY 1075#define CLD INSN_COPROC_MEMORY_DELAY 1076#define CBL INSN_COND_BRANCH_LIKELY 1077#define TRAP INSN_TRAP 1078#define SM INSN_STORE_MEMORY 1079 1080#define WR_d INSN_WRITE_GPR_D 1081#define WR_t INSN_WRITE_GPR_T 1082#define WR_31 INSN_WRITE_GPR_31 1083#define WR_D INSN_WRITE_FPR_D 1084#define WR_T INSN_WRITE_FPR_T 1085#define WR_S INSN_WRITE_FPR_S 1086#define RD_s INSN_READ_GPR_S 1087#define RD_b INSN_READ_GPR_S 1088#define RD_t INSN_READ_GPR_T 1089#define RD_S INSN_READ_FPR_S 1090#define RD_T INSN_READ_FPR_T 1091#define RD_R INSN_READ_FPR_R 1092#define WR_CC INSN_WRITE_COND_CODE 1093#define RD_CC INSN_READ_COND_CODE 1094#define RD_C0 INSN_COP 1095#define RD_C1 INSN_COP 1096#define RD_C2 INSN_COP 1097#define RD_C3 INSN_COP 1098#define WR_C0 INSN_COP 1099#define WR_C1 INSN_COP 1100#define WR_C2 INSN_COP 1101#define WR_C3 INSN_COP 1102 1103#define WR_HI INSN_WRITE_HI 1104#define RD_HI INSN_READ_HI 1105#define MOD_HI WR_HI|RD_HI 1106 1107#define WR_LO INSN_WRITE_LO 1108#define RD_LO INSN_READ_LO 1109#define MOD_LO WR_LO|RD_LO 1110 1111#define WR_HILO WR_HI|WR_LO 1112#define RD_HILO RD_HI|RD_LO 1113#define MOD_HILO WR_HILO|RD_HILO 1114 1115#define IS_M INSN_MULT 1116 1117#define WR_MACC INSN2_WRITE_MDMX_ACC 1118#define RD_MACC INSN2_READ_MDMX_ACC 1119 1120#define I1 INSN_ISA1 1121#define I2 INSN_ISA2 1122#define I3 INSN_ISA3 1123#define I4 INSN_ISA4 1124#define I5 INSN_ISA5 1125#define I32 INSN_ISA32 1126#define I64 INSN_ISA64 1127#define I33 INSN_ISA32R2 1128#define I65 INSN_ISA64R2 1129 1130/* MIPS64 MIPS-3D ASE support. */ 1131#define I16 INSN_MIPS16 1132 1133/* MIPS32 SmartMIPS ASE support. */ 1134#define SMT INSN_SMARTMIPS 1135 1136/* MIPS64 MIPS-3D ASE support. */ 1137#define M3D INSN_MIPS3D 1138 1139/* MIPS64 MDMX ASE support. */ 1140#define MX INSN_MDMX 1141 1142#define IL2E (INSN_LOONGSON_2E) 1143#define IL2F (INSN_LOONGSON_2F) 1144 1145#define P3 INSN_4650 1146#define L1 INSN_4010 1147#define V1 (INSN_4100 | INSN_4111 | INSN_4120) 1148#define T3 INSN_3900 1149#define M1 INSN_10000 1150#define SB1 INSN_SB1 1151#define N411 INSN_4111 1152#define N412 INSN_4120 1153#define N5 (INSN_5400 | INSN_5500) 1154#define N54 INSN_5400 1155#define N55 INSN_5500 1156 1157#define G1 (T3 \ 1158 ) 1159 1160#define G2 (T3 \ 1161 ) 1162 1163#define G3 (I4 \ 1164 ) 1165 1166/* MIPS DSP ASE support. 1167 NOTE: 1168 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair 1169 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have 1170 the same structure as $ac0 (HI + LO). For DSP instructions that write or 1171 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a 1172 (RD_HILO) attributes, such that HILO dependencies are maintained 1173 conservatively. 1174 1175 2. For some mul. instructions that use integer registers as destinations 1176 but destroy HI+LO as side-effect, we add WR_HILO to their attributes. 1177 1178 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields 1179 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write 1180 certain fields of the DSP control register. For simplicity, we decide not 1181 to track dependencies of these fields. 1182 However, "bposge32" is a branch instruction that depends on the "pos" 1183 field. In order to make sure that GAS does not reorder DSP instructions 1184 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) 1185 attribute to those instructions that write the "pos" field. */ 1186 1187#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ 1188#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ 1189#define MOD_a WR_a|RD_a 1190#define DSP_VOLA INSN_TRAP 1191#define D32 INSN_DSP 1192#define D33 INSN_DSPR2 1193#define D64 INSN_DSP64 1194 1195/* MIPS MT ASE support. */ 1196#define MT32 INSN_MT 1197 1198/* The order of overloaded instructions matters. Label arguments and 1199 register arguments look the same. Instructions that can have either 1200 for arguments must apear in the correct order in this table for the 1201 assembler to pick the right one. In other words, entries with 1202 immediate operands must apear after the same instruction with 1203 registers. 1204 1205 Because of the lookup algorithm used, entries with the same opcode 1206 name must be contiguous. 1207 1208 Many instructions are short hand for other instructions (i.e., The 1209 jal <register> instruction is short for jalr <register>). */ 1210 1211const struct mips_opcode mips_builtin_opcodes[] = 1212{ 1213/* These instructions appear first so that the disassembler will find 1214 them first. The assemblers uses a hash table based on the 1215 instruction name anyhow. */ 1216/* name, args, match, mask, pinfo, membership */ 1217{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, 1218{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, 1219{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ 1220{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */ 1221{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ 1222{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ 1223{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ 1224{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, 1225{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, 1226{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ 1227{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ 1228{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ 1229{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ 1230{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ 1231{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ 1232 1233{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, 1234{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1235{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1236{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1237{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1238{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, 1239{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1240{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1241{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1242{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1243{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1244{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1245{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1246{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1247{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1248{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1249{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1250{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1251{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1252{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1253{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 1254{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1255{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, 1256{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1257{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, 1258{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1259{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1260{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, 1261{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, 1262{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1263{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, 1264{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1265{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1266{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1267{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1268{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1269{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1270/* b is at the top of the table. */ 1271/* bal is at the top of the table. */ 1272/* bc0[tf]l? are at the bottom of the table. */ 1273{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1274{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1275{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1276{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1277{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 1278{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 1279{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1280{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 1281{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 1282{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 1283{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1284{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 1285/* bc2* are at the bottom of the table. */ 1286/* bc3* are at the bottom of the table. */ 1287{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1288{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1289{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 1290{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, 1291{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 1292{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, 1293{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, 1294{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, 1295{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, 1296{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, 1297{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, 1298{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, 1299{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, 1300{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, 1301{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1302{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1303{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 1304{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 1305{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, 1306{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, 1307{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, 1308{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, 1309{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, 1310{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, 1311{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, 1312{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, 1313{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1314{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1315{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, 1316{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, 1317{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, 1318{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, 1319{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, 1320{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, 1321{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, 1322{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, 1323{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1324{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1325{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, 1326{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, 1327{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, 1328{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, 1329{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, 1330{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, 1331{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, 1332{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, 1333{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1334{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1335{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 1336{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 1337{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1338{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1339{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 1340{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, 1341{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 1342{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, 1343{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, 1344{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, 1345{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, 1346{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1347{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1348{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1349{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1350{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1351{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1352{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1353{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1354{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1355{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1356{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1357{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1358{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1359{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1360{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1361{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1362{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1363{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1364{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1365{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1366{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1367{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1368{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1369{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1370{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1371{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1372{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1373{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1374{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1375{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1376{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1377{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1378{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1379{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1380{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1381{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1382{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1383{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1384{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1385{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1386{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1387{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1388{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1389{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1390{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1391{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1392{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1393{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1394{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1395{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1396{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1397{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1398{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1399{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1400{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1401{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1402{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1403{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1404{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1405{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1406{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1407{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1408{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1409{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1410{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1411{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1412{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1413{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1414{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1415{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1416{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1417{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1418{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1419{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1420{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1421{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1422{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1423{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1424{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1425{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1426{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1427{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1428{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1429{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1430{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1431{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1432{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1433{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1434{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1435{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1436{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1437{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1438{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1439{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1440{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1441{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1442{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1443{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1444{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1445{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1446{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1447{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1448{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1449{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1450{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1451{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1452{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1453{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1454{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1455{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1456{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1457{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1458{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1459{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1460{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1461{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1462{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1463{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1464{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1465{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1466{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1467{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1468{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1469{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1470{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1471{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1472{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1473{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1474{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1475{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1476{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1477{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1478{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1479{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1480{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1481{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1482{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1483{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1484{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1485{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1486{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1487{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1488{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1489{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1490{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1491{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1492{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1493{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1494{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1495{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1496{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1497{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1498{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1499{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1500{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1501{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1502{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1503{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1504{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1505/* CW4010 instructions which are aliases for the cache instruction. */ 1506{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, 1507{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, 1508{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, 1509{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, 1510{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, 1511{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, 1512{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1513{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1514{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 1515{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 1516{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 1517{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 1518{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 1519/* cfc2 is at the bottom of the table. */ 1520/* cfc3 is at the bottom of the table. */ 1521{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 1522{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 1523{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1524{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 1525{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 1526{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 1527{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 1528{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 1529/* ctc2 is at the bottom of the table. */ 1530/* ctc3 is at the bottom of the table. */ 1531{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 1532{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 1533{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, 1534{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1535{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1536{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1537{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1538{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1539{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1540{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1541{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1542{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 1543{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 1544{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1545{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1546{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 1547{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, 1548{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 1549{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, 1550{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1551{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, 1552{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 1553{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 1554{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1555{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, 1556{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, 1557{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 1558{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 1559/* dctr and dctw are used on the r5000. */ 1560{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, 1561{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, 1562{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, 1563{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, 1564{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1565{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1566{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1567/* For ddiv, see the comments about div. */ 1568{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1569{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, 1570{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, 1571/* For ddivu, see the comments about div. */ 1572{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1573{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, 1574{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, 1575{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1576{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1577{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, 1578{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1579{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1580{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1581/* The MIPS assembler treats the div opcode with two operands as 1582 though the first operand appeared twice (the first operand is both 1583 a source and a destination). To get the div machine instruction, 1584 you must use an explicit destination of $0. */ 1585{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1586{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1587{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, 1588{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, 1589{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1590{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1591{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 1592/* For divu, see the comments about div. */ 1593{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1594{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1595{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, 1596{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, 1597{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, 1598{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, 1599{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ 1600{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ 1601{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, 1602{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1603{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1604{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1605{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1606{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1607{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1608{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1609{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1610{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, 1611{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, 1612{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 1613{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 1614{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, 1615{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1616{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, 1617{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 1618{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 1619{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 1620{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 1621{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 1622{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 1623/* dmfc2 is at the bottom of the table. */ 1624/* dmtc2 is at the bottom of the table. */ 1625/* dmfc3 is at the bottom of the table. */ 1626/* dmtc3 is at the bottom of the table. */ 1627{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, 1628{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, 1629{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, 1630{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, 1631{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, 1632{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, 1633{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1634{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1635{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ 1636{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ 1637{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1638{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, 1639{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, 1640{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1641{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, 1642{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, 1643{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, 1644{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, 1645{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, 1646{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, 1647{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, 1648{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 1649{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, 1650{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 1651{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, 1652{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, 1653{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, 1654{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, 1655{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, 1656{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, 1657{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, 1658{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, 1659{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1660{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1661{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ 1662{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ 1663{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1664{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1665{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1666{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ 1667{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ 1668{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1669{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1670{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1671{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ 1672{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ 1673{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1674{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1675{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, 1676{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1677{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, 1678{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, 1679{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1680{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1681{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1682{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, 1683{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1684{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, 1685{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, 1686{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1687{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, 1688{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1689{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1690{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 1691{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 1692{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, 1693{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, 1694{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, 1695/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with 1696 the same hazard barrier effect. */ 1697{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, 1698{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ 1699/* SVR4 PIC code requires special handling for j, so it must be a 1700 macro. */ 1701{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, 1702/* This form of j is used by the disassembler and internally by the 1703 assembler, but will never match user input (because the line above 1704 will match first). */ 1705{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, 1706{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, 1707{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, 1708/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr 1709 with the same hazard barrier effect. */ 1710{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, 1711{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, 1712/* SVR4 PIC code requires special handling for jal, so it must be a 1713 macro. */ 1714{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, 1715{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, 1716{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, 1717/* This form of jal is used by the disassembler and internally by the 1718 assembler, but will never match user input (because the line above 1719 will match first). */ 1720{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, 1721{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, 1722{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, 1723{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1724{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, 1725{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1726{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, 1727{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, 1728{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, 1729{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, 1730{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, 1731{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 1732{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 1733{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 1734{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 1735{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ 1736{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, 1737{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, 1738{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 1739{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, 1740{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 1741{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, 1742{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 1743{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, 1744{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 1745{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, 1746{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 1747{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1748{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, 1749{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1750{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, 1751/* li is at the start of the table. */ 1752{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, 1753{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, 1754{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, 1755{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, 1756{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, 1757{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, 1758{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 1759{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, 1760{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, 1761{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, 1762{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1763{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, 1764{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1765{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, 1766{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 1767{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 1768{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1769{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1770{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ 1771{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1772{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1773{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, 1774{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1775{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, 1776{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1777{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, 1778{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 1779{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ 1780{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1781{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, 1782{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 1783{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ 1784{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, 1785{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 1786{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, 1787{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 1788{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, 1789{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1790{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1791{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1792{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1793{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1794{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1795{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1796{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1797{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1798{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1799{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1800{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1801{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 1802{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 1803{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1804{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1805{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1806{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1807{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1808{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 1809{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1810{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1811{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 1812{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1813{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1814{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 1815{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1816{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1817{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, 1818{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1819{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1820{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1821{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1822{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1823{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 1824{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 1825{"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1826{"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1827{"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1828{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1829{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1830{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 1831{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 1832{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1833{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, 1834{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 1835{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 1836{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 1837{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1838{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1839{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1840{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1841{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1842{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, 1843{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 1844{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 1845{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 1846{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 1847{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 1848{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 1849{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 1850/* mfc2 is at the bottom of the table. */ 1851/* mfhc2 is at the bottom of the table. */ 1852/* mfc3 is at the bottom of the table. */ 1853{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, 1854{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, 1855{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, 1856{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, 1857{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, 1858{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, 1859{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1860{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1861{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1862{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1863{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1864{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1865{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1866{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1867{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 1868{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 1869{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1870{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1871{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 1872{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 1873{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 1874{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 1875{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 1876{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1877{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1878{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 1879{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 1880{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 1881{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 1882{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1883{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1884{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 1885{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 1886{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 1887{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 1888{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 1889{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1890{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1891{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 1892{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 1893{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1894{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1895{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1896{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1897/* move is at the top of the table. */ 1898{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1899{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1900{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1901{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1902{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1903{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1904{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1905{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1906{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1907{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1908{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 1909{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 1910{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, 1911{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 1912{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 1913{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 1914{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 1915{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 1916{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 1917/* mtc2 is at the bottom of the table. */ 1918/* mthc2 is at the bottom of the table. */ 1919/* mtc3 is at the bottom of the table. */ 1920{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, 1921{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, 1922{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, 1923{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, 1924{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, 1925{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, 1926{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1927{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1928{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1929{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 1930{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 1931{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 1932{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1933{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1934{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, 1935{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 1936{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 1937{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 1938{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 1939{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1940{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1941{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1942{"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1943{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, 1944{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1945{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1946{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1947{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1948{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1949{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1950{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1951{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1952{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, 1953{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, 1954{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, 1955{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, 1956{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1957{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1958{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1959{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1960{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1961{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1962{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1963{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1964{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1965{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1966{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1967{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1968{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, 1969{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, 1970{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, 1971{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, 1972{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 1973{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1974{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1975{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1976{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1977{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1978{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1979{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1980{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1981{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1982{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1983{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1984{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1985{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1986{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1987{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 1988{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 1989{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1990{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 1991{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 1992{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 1993{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1994{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1995{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ 1996{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ 1997{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1998{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1999{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 2000{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2001{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2002{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2003{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2004{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2005{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2006/* nop is at the start of the table. */ 2007{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2008{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, 2009{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2010{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2011{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2012{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2013{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2014{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ 2015{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2016{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, 2017{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2018{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2019{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2020{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2021{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2022{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2023{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2024{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, 2025{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2026{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2027{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2028{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2029{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2030{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2031{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2032{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2033{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2034{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2035{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2036{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2037{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2038 /* pref and prefx are at the start of the table. */ 2039{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2040{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2041{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, 2042{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2043{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2044{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2045{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2046{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2047{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2048{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2049{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 2050{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2051{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2052{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2053{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2054{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2055{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2056{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2057{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2058{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2059{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2060{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2061{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, 2062{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, 2063{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2064{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, 2065{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, 2066{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, 2067{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, 2068{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, 2069{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2070{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2071{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2072{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2073{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2074{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2075{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, 2076{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, 2077{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, 2078{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, 2079{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, 2080{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, 2081{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, 2082{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, 2083{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, 2084{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, 2085{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, 2086{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2087{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2088{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2089{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2090{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2091{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2092{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2093{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2094{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2095{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2096{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2097{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2098{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2099{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2100{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2101{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, 2102{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2103{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2104{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, 2105{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, 2106{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, 2107{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, 2108{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, 2109{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2110{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, 2111{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, 2112{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, 2113{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, 2114{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, 2115{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, 2116{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, 2117{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2118{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2119{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2120{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2121{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, 2122{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, 2123{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, 2124{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, 2125{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2126{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, 2127{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, 2128{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2129{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, 2130{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2131{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, 2132{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 }, 2133{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2134{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2135{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2136{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2137{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, 2138{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, 2139{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, 2140{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, 2141{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, 2142{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, 2143{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, 2144{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, 2145{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, 2146{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, 2147{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2148{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, 2149{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2150{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2151{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2152{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2153{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2154{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2155{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2156{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2157{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2158{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2159{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2160{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2161{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2162{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2163{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, 2164{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, 2165{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, 2166{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, 2167{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2168{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ 2169{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2170{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2171{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2172{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2173{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2174{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2175{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, 2176{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2177{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2178{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2179{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, 2180{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, 2181{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, 2182{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, 2183{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2184{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2185{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2186{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ 2187{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2188{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2189{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2190{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ 2191{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2192{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2193{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2194{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2195{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2196/* ssnop is at the start of the table. */ 2197{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, 2198{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2199{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, 2200{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 2201{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 2202{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2203{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2204{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2205{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2206{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2207{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2208{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2209{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2210{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2211{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2212{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2213{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, 2214{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, 2215{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, 2216{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2217{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, 2218{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, 2219{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, 2220{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2221{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2222{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2223{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2224{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ 2225{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2226{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, 2227{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, 2228{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, 2229{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, 2230{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2231{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, 2232{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2233{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ 2234{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2235{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, 2236{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2237{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ 2238{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 }, 2239{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, 2240{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, 2241{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, 2242{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, 2243{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, 2244{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, 2245{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2246{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2247{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2248{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ 2249{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, 2250{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2251{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2252{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2253{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ 2254{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, 2255{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2256{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2257{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2258{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ 2259{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, 2260{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, 2261{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, 2262{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, 2263{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, 2264{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2265{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2266{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2267{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ 2268{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, 2269{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2270{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2271{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2272{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ 2273{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, 2274{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2275{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2276{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2277{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ 2278{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, 2279{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2280{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2281{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2282{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2283{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, 2284{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2285{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2286{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, 2287{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, 2288{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, 2289{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, 2290{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, 2291{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, 2292{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, 2293{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, 2294{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, 2295{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, 2296{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, 2297{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, 2298{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, 2299{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, 2300{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, 2301{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, 2302{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, 2303{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, 2304{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2305{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, 2306{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2307{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, 2308{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, 2309{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, 2310{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, 2311{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2312{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2313{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, 2314{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2315{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2316{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2317{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2318{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2319{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2320{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, 2321{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, 2322 2323/* User Defined Instruction. */ 2324{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2325{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2326{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2327{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2328{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2329{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2330{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2331{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2332{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2333{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2334{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2335{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2336{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2337{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2338{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2339{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2340{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2341{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2342{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2343{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2344{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2345{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2346{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2347{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2348{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2349{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2350{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2351{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2352{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2353{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2354{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2355{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2356{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2357{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2358{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2359{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2360{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2361{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2362{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2363{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2364{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2365{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2366{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2367{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2368{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2369{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2370{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2371{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2372{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2373{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2374{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2375{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2376{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2377{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2378{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2379{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2380{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2381{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2382{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2383{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2384{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2385{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2386{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2387{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2388 2389/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format 2390 instructions so they are here for the latters to take precedence. */ 2391{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2392{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, 2393{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2394{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, 2395{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2396{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, 2397{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2398{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, 2399{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 2400{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 2401{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, 2402{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, 2403{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, 2404{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, 2405{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 2406{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, 2407{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, 2408{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, 2409{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, 2410{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, 2411{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, 2412{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2413{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2414{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2415 2416/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 2417 instructions, so they are here for the latters to take precedence. */ 2418{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2419{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2420{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2421{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2422{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 2423{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 2424{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, 2425{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, 2426{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 2427{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, 2428{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, 2429{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, 2430 2431/* No hazard protection on coprocessor instructions--they shouldn't 2432 change the state of the processor and if they do it's up to the 2433 user to put in nops as necessary. These are at the end so that the 2434 disassembler recognizes more specific versions first. */ 2435{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, 2436{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, 2437{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, 2438{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, 2439{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, 2440{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, 2441{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, 2442{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, 2443 /* Conflicts with the 4650's "mul" instruction. Nobody's using the 2444 4010 any more, so move this insn out of the way. If the object 2445 format gave us more info, we could do this right. */ 2446{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, 2447/* MIPS DSP ASE */ 2448{"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2449{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2450{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2451{"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2452{"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2453{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2454{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2455{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2456{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2457{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2458{"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2459{"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2460{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2461{"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2462{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2463{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2464{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2465{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2466{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, 2467{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, 2468{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2469{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2470{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2471{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2472{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2473{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2474{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2475{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2476{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2477{"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2478{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2479{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2480{"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2481{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2482{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2483{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2484{"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2485{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2486{"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2487{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2488{"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2489{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, 2490{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, 2491{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2492{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2493{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2494{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2495{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2496{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2497{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2498{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2499{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2500{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2501{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2502{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2503{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2504{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2505{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2506{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2507{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, 2508{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2509{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2510{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2511{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2512{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, 2513{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2514{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2515{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2516{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2517{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2518{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2519{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2520{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2521{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2522{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2523{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2524{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2525{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2526{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2527{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2528{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2529{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, 2530{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, 2531{"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, 2532{"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, 2533{"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2534{"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2535{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2536{"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2537{"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2538{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2539{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2540{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2541{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2542{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2543{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, 2544{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2545{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, 2546{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2547{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2548{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2549{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2550{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2551{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2552{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2553{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2554{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2555{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2556{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2557{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2558{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2559{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2560{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2561{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2562{"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2563{"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, 2564{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2565{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2566{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2567{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2568{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2569{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2570{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2571{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2572{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2573{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2574{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2575{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2576{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2577{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2578{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2579{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2580{"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2581{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2582{"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2583{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2584{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2585{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2586{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2587{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2588{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2589{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2590{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2591{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2592{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2593{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2594{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2595{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2596{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2597{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2598{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2599{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2600{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2601{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2602{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2603{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2604{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2605{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2606{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2607{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2608{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2609{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2610{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2611{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2612{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2613{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2614{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2615{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2616{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2617{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, 2618{"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, 2619{"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, 2620{"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, 2621{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, 2622{"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, 2623{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, 2624{"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, 2625{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, 2626{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2627{"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2628{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2629{"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2630{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2631{"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, 2632{"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, 2633{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, 2634{"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2635{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2636{"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, 2637{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2638{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2639{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2640{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2641{"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 2642{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2643{"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2644{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2645{"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2646{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2647{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2648{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2649{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2650{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2651{"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2652{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2653{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2654{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2655{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2656{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2657{"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 2658{"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2659{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2660{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2661{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2662{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2663{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2664{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2665{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, 2666{"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, 2667{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2668{"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2669{"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2670{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2671{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2672{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2673{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2674{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2675{"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2676{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2677{"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2678{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2679{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2680{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, 2681{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, 2682/* MIPS DSP ASE Rev2 */ 2683{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, 2684{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2685{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2686{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2687{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2688{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2689{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, 2690{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, 2691{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2692{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2693{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2694{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2695{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2696{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2697{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2698{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2699{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2700{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2701{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2702{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2703{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2704{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2705{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2706{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, 2707{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, 2708{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2709{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2710{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, 2711{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2712{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2713{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2714{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2715{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2716{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2717{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2718{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2719{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2720{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2721{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2722{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2723{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2724{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2725{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2726{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2727{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2728{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2729{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2730/* Move bc0* after mftr and mttr to avoid opcode collision. */ 2731{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2732{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2733{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2734{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2735/* ST Microelectronics Loongson-2E and -2F. */ 2736{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2737{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2738{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2739{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2740{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2741{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2742{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2743{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2744{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2745{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2746{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2747{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2748{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2749{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2750{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2751{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2752{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2753{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2754{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2755{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2756{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2757{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2758{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2759{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2760}; 2761 2762#define MIPS_NUM_OPCODES \ 2763 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) 2764const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; 2765 2766/* const removed from the following to allow for dynamic extensions to the 2767 * built-in instruction set. */ 2768struct mips_opcode *mips_opcodes = 2769 (struct mips_opcode *) mips_builtin_opcodes; 2770int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; 2771#undef MIPS_NUM_OPCODES 2772 2773/* Mips instructions are at maximum this many bytes long. */ 2774#define INSNLEN 4 2775 2776 2777/* FIXME: These should be shared with gdb somehow. */ 2778 2779struct mips_cp0sel_name 2780{ 2781 unsigned int cp0reg; 2782 unsigned int sel; 2783 const char * const name; 2784}; 2785 2786/* The mips16 registers. */ 2787static const unsigned int mips16_to_32_reg_map[] = 2788{ 2789 16, 17, 2, 3, 4, 5, 6, 7 2790}; 2791 2792#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] 2793 2794 2795static const char * const mips_gpr_names_numeric[32] = 2796{ 2797 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 2798 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 2799 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 2800 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 2801}; 2802 2803static const char * const mips_gpr_names_oldabi[32] = 2804{ 2805 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 2806 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 2807 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2808 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 2809}; 2810 2811static const char * const mips_gpr_names_newabi[32] = 2812{ 2813 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 2814 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 2815 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2816 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 2817}; 2818 2819static const char * const mips_fpr_names_numeric[32] = 2820{ 2821 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 2822 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 2823 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 2824 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 2825}; 2826 2827static const char * const mips_fpr_names_32[32] = 2828{ 2829 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 2830 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 2831 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 2832 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 2833}; 2834 2835static const char * const mips_fpr_names_n32[32] = 2836{ 2837 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 2838 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 2839 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 2840 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 2841}; 2842 2843static const char * const mips_fpr_names_64[32] = 2844{ 2845 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 2846 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 2847 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 2848 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 2849}; 2850 2851static const char * const mips_cp0_names_numeric[32] = 2852{ 2853 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 2854 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 2855 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 2856 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 2857}; 2858 2859static const char * const mips_cp0_names_mips3264[32] = 2860{ 2861 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 2862 "c0_context", "c0_pagemask", "c0_wired", "$7", 2863 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 2864 "c0_status", "c0_cause", "c0_epc", "c0_prid", 2865 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 2866 "c0_xcontext", "$21", "$22", "c0_debug", 2867 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 2868 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 2869}; 2870 2871static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 2872{ 2873 { 4, 1, "c0_contextconfig" }, 2874 { 0, 1, "c0_mvpcontrol" }, 2875 { 0, 2, "c0_mvpconf0" }, 2876 { 0, 3, "c0_mvpconf1" }, 2877 { 1, 1, "c0_vpecontrol" }, 2878 { 1, 2, "c0_vpeconf0" }, 2879 { 1, 3, "c0_vpeconf1" }, 2880 { 1, 4, "c0_yqmask" }, 2881 { 1, 5, "c0_vpeschedule" }, 2882 { 1, 6, "c0_vpeschefback" }, 2883 { 2, 1, "c0_tcstatus" }, 2884 { 2, 2, "c0_tcbind" }, 2885 { 2, 3, "c0_tcrestart" }, 2886 { 2, 4, "c0_tchalt" }, 2887 { 2, 5, "c0_tccontext" }, 2888 { 2, 6, "c0_tcschedule" }, 2889 { 2, 7, "c0_tcschefback" }, 2890 { 5, 1, "c0_pagegrain" }, 2891 { 6, 1, "c0_srsconf0" }, 2892 { 6, 2, "c0_srsconf1" }, 2893 { 6, 3, "c0_srsconf2" }, 2894 { 6, 4, "c0_srsconf3" }, 2895 { 6, 5, "c0_srsconf4" }, 2896 { 12, 1, "c0_intctl" }, 2897 { 12, 2, "c0_srsctl" }, 2898 { 12, 3, "c0_srsmap" }, 2899 { 15, 1, "c0_ebase" }, 2900 { 16, 1, "c0_config1" }, 2901 { 16, 2, "c0_config2" }, 2902 { 16, 3, "c0_config3" }, 2903 { 18, 1, "c0_watchlo,1" }, 2904 { 18, 2, "c0_watchlo,2" }, 2905 { 18, 3, "c0_watchlo,3" }, 2906 { 18, 4, "c0_watchlo,4" }, 2907 { 18, 5, "c0_watchlo,5" }, 2908 { 18, 6, "c0_watchlo,6" }, 2909 { 18, 7, "c0_watchlo,7" }, 2910 { 19, 1, "c0_watchhi,1" }, 2911 { 19, 2, "c0_watchhi,2" }, 2912 { 19, 3, "c0_watchhi,3" }, 2913 { 19, 4, "c0_watchhi,4" }, 2914 { 19, 5, "c0_watchhi,5" }, 2915 { 19, 6, "c0_watchhi,6" }, 2916 { 19, 7, "c0_watchhi,7" }, 2917 { 23, 1, "c0_tracecontrol" }, 2918 { 23, 2, "c0_tracecontrol2" }, 2919 { 23, 3, "c0_usertracedata" }, 2920 { 23, 4, "c0_tracebpc" }, 2921 { 25, 1, "c0_perfcnt,1" }, 2922 { 25, 2, "c0_perfcnt,2" }, 2923 { 25, 3, "c0_perfcnt,3" }, 2924 { 25, 4, "c0_perfcnt,4" }, 2925 { 25, 5, "c0_perfcnt,5" }, 2926 { 25, 6, "c0_perfcnt,6" }, 2927 { 25, 7, "c0_perfcnt,7" }, 2928 { 27, 1, "c0_cacheerr,1" }, 2929 { 27, 2, "c0_cacheerr,2" }, 2930 { 27, 3, "c0_cacheerr,3" }, 2931 { 28, 1, "c0_datalo" }, 2932 { 28, 2, "c0_taglo1" }, 2933 { 28, 3, "c0_datalo1" }, 2934 { 28, 4, "c0_taglo2" }, 2935 { 28, 5, "c0_datalo2" }, 2936 { 28, 6, "c0_taglo3" }, 2937 { 28, 7, "c0_datalo3" }, 2938 { 29, 1, "c0_datahi" }, 2939 { 29, 2, "c0_taghi1" }, 2940 { 29, 3, "c0_datahi1" }, 2941 { 29, 4, "c0_taghi2" }, 2942 { 29, 5, "c0_datahi2" }, 2943 { 29, 6, "c0_taghi3" }, 2944 { 29, 7, "c0_datahi3" }, 2945}; 2946 2947static const char * const mips_cp0_names_mips3264r2[32] = 2948{ 2949 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 2950 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 2951 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 2952 "c0_status", "c0_cause", "c0_epc", "c0_prid", 2953 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 2954 "c0_xcontext", "$21", "$22", "c0_debug", 2955 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 2956 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 2957}; 2958 2959static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 2960{ 2961 { 4, 1, "c0_contextconfig" }, 2962 { 5, 1, "c0_pagegrain" }, 2963 { 12, 1, "c0_intctl" }, 2964 { 12, 2, "c0_srsctl" }, 2965 { 12, 3, "c0_srsmap" }, 2966 { 15, 1, "c0_ebase" }, 2967 { 16, 1, "c0_config1" }, 2968 { 16, 2, "c0_config2" }, 2969 { 16, 3, "c0_config3" }, 2970 { 18, 1, "c0_watchlo,1" }, 2971 { 18, 2, "c0_watchlo,2" }, 2972 { 18, 3, "c0_watchlo,3" }, 2973 { 18, 4, "c0_watchlo,4" }, 2974 { 18, 5, "c0_watchlo,5" }, 2975 { 18, 6, "c0_watchlo,6" }, 2976 { 18, 7, "c0_watchlo,7" }, 2977 { 19, 1, "c0_watchhi,1" }, 2978 { 19, 2, "c0_watchhi,2" }, 2979 { 19, 3, "c0_watchhi,3" }, 2980 { 19, 4, "c0_watchhi,4" }, 2981 { 19, 5, "c0_watchhi,5" }, 2982 { 19, 6, "c0_watchhi,6" }, 2983 { 19, 7, "c0_watchhi,7" }, 2984 { 23, 1, "c0_tracecontrol" }, 2985 { 23, 2, "c0_tracecontrol2" }, 2986 { 23, 3, "c0_usertracedata" }, 2987 { 23, 4, "c0_tracebpc" }, 2988 { 25, 1, "c0_perfcnt,1" }, 2989 { 25, 2, "c0_perfcnt,2" }, 2990 { 25, 3, "c0_perfcnt,3" }, 2991 { 25, 4, "c0_perfcnt,4" }, 2992 { 25, 5, "c0_perfcnt,5" }, 2993 { 25, 6, "c0_perfcnt,6" }, 2994 { 25, 7, "c0_perfcnt,7" }, 2995 { 27, 1, "c0_cacheerr,1" }, 2996 { 27, 2, "c0_cacheerr,2" }, 2997 { 27, 3, "c0_cacheerr,3" }, 2998 { 28, 1, "c0_datalo" }, 2999 { 28, 2, "c0_taglo1" }, 3000 { 28, 3, "c0_datalo1" }, 3001 { 28, 4, "c0_taglo2" }, 3002 { 28, 5, "c0_datalo2" }, 3003 { 28, 6, "c0_taglo3" }, 3004 { 28, 7, "c0_datalo3" }, 3005 { 29, 1, "c0_datahi" }, 3006 { 29, 2, "c0_taghi1" }, 3007 { 29, 3, "c0_datahi1" }, 3008 { 29, 4, "c0_taghi2" }, 3009 { 29, 5, "c0_datahi2" }, 3010 { 29, 6, "c0_taghi3" }, 3011 { 29, 7, "c0_datahi3" }, 3012}; 3013 3014/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 3015static const char * const mips_cp0_names_sb1[32] = 3016{ 3017 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 3018 "c0_context", "c0_pagemask", "c0_wired", "$7", 3019 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 3020 "c0_status", "c0_cause", "c0_epc", "c0_prid", 3021 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 3022 "c0_xcontext", "$21", "$22", "c0_debug", 3023 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 3024 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 3025}; 3026 3027static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 3028{ 3029 { 16, 1, "c0_config1" }, 3030 { 18, 1, "c0_watchlo,1" }, 3031 { 19, 1, "c0_watchhi,1" }, 3032 { 22, 0, "c0_perftrace" }, 3033 { 23, 3, "c0_edebug" }, 3034 { 25, 1, "c0_perfcnt,1" }, 3035 { 25, 2, "c0_perfcnt,2" }, 3036 { 25, 3, "c0_perfcnt,3" }, 3037 { 25, 4, "c0_perfcnt,4" }, 3038 { 25, 5, "c0_perfcnt,5" }, 3039 { 25, 6, "c0_perfcnt,6" }, 3040 { 25, 7, "c0_perfcnt,7" }, 3041 { 26, 1, "c0_buserr_pa" }, 3042 { 27, 1, "c0_cacheerr_d" }, 3043 { 27, 3, "c0_cacheerr_d_pa" }, 3044 { 28, 1, "c0_datalo_i" }, 3045 { 28, 2, "c0_taglo_d" }, 3046 { 28, 3, "c0_datalo_d" }, 3047 { 29, 1, "c0_datahi_i" }, 3048 { 29, 2, "c0_taghi_d" }, 3049 { 29, 3, "c0_datahi_d" }, 3050}; 3051 3052static const char * const mips_hwr_names_numeric[32] = 3053{ 3054 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3055 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3056 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3057 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3058}; 3059 3060static const char * const mips_hwr_names_mips3264r2[32] = 3061{ 3062 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 3063 "$4", "$5", "$6", "$7", 3064 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3065 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3066 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3067}; 3068 3069struct mips_abi_choice 3070{ 3071 const char *name; 3072 const char * const *gpr_names; 3073 const char * const *fpr_names; 3074}; 3075 3076static struct mips_abi_choice mips_abi_choices[] = 3077{ 3078 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 3079 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 3080 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 3081 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 3082}; 3083 3084struct mips_arch_choice 3085{ 3086 const char *name; 3087 int bfd_mach_valid; 3088 unsigned long bfd_mach; 3089 int processor; 3090 int isa; 3091 const char * const *cp0_names; 3092 const struct mips_cp0sel_name *cp0sel_names; 3093 unsigned int cp0sel_names_len; 3094 const char * const *hwr_names; 3095}; 3096 3097#define bfd_mach_mips3000 3000 3098#define bfd_mach_mips3900 3900 3099#define bfd_mach_mips4000 4000 3100#define bfd_mach_mips4010 4010 3101#define bfd_mach_mips4100 4100 3102#define bfd_mach_mips4111 4111 3103#define bfd_mach_mips4120 4120 3104#define bfd_mach_mips4300 4300 3105#define bfd_mach_mips4400 4400 3106#define bfd_mach_mips4600 4600 3107#define bfd_mach_mips4650 4650 3108#define bfd_mach_mips5000 5000 3109#define bfd_mach_mips5400 5400 3110#define bfd_mach_mips5500 5500 3111#define bfd_mach_mips6000 6000 3112#define bfd_mach_mips7000 7000 3113#define bfd_mach_mips8000 8000 3114#define bfd_mach_mips9000 9000 3115#define bfd_mach_mips10000 10000 3116#define bfd_mach_mips12000 12000 3117#define bfd_mach_mips16 16 3118#define bfd_mach_mips5 5 3119#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ 3120#define bfd_mach_mipsisa32 32 3121#define bfd_mach_mipsisa32r2 33 3122#define bfd_mach_mipsisa64 64 3123#define bfd_mach_mipsisa64r2 65 3124 3125static const struct mips_arch_choice mips_arch_choices[] = 3126{ 3127 { "numeric", 0, 0, 0, 0, 3128 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3129 3130 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 3131 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3132 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 3133 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3134 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 3135 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3136 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 3137 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3138 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 3139 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3140 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 3141 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3142 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 3143 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3144 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 3145 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3146 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 3147 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3148 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 3149 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3150 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 3151 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3152 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 3153 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3154 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 3155 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3156 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 3157 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3158 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 3159 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3160 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3161 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3162 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3163 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3164 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 3165 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3166 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 3167 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3168 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 3169 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3170 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 3171 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3172 3173 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 3174 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 3175 _MIPS32 Architecture For Programmers Volume I: Introduction to the 3176 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 3177 page 1. */ 3178 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 3179 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, 3180 mips_cp0_names_mips3264, 3181 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3182 mips_hwr_names_numeric }, 3183 3184 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 3185 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 3186 | INSN_MIPS3D | INSN_MT), 3187 mips_cp0_names_mips3264r2, 3188 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3189 mips_hwr_names_mips3264r2 }, 3190 3191 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 3192 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 3193 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, 3194 mips_cp0_names_mips3264, 3195 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3196 mips_hwr_names_numeric }, 3197 3198 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 3199 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 3200 | INSN_DSP64 | INSN_MT | INSN_MDMX), 3201 mips_cp0_names_mips3264r2, 3202 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3203 mips_hwr_names_mips3264r2 }, 3204 3205 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 3206 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 3207 mips_cp0_names_sb1, 3208 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 3209 mips_hwr_names_numeric }, 3210 3211 /* This entry, mips16, is here only for ISA/processor selection; do 3212 not print its name. */ 3213 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, 3214 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3215}; 3216 3217/* ISA and processor type to disassemble for, and register names to use. 3218 set_default_mips_dis_options and parse_mips_dis_options fill in these 3219 values. */ 3220static int mips_processor; 3221static int mips_isa; 3222static const char * const *mips_gpr_names; 3223static const char * const *mips_fpr_names; 3224static const char * const *mips_cp0_names; 3225static const struct mips_cp0sel_name *mips_cp0sel_names; 3226static int mips_cp0sel_names_len; 3227static const char * const *mips_hwr_names; 3228 3229/* Other options */ 3230static int no_aliases; /* If set disassemble as most general inst. */ 3231 3232static const struct mips_abi_choice * 3233choose_abi_by_name (const char *name, unsigned int namelen) 3234{ 3235 const struct mips_abi_choice *c; 3236 unsigned int i; 3237 3238 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 3239 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 3240 && strlen (mips_abi_choices[i].name) == namelen) 3241 c = &mips_abi_choices[i]; 3242 3243 return c; 3244} 3245 3246static const struct mips_arch_choice * 3247choose_arch_by_name (const char *name, unsigned int namelen) 3248{ 3249 const struct mips_arch_choice *c = NULL; 3250 unsigned int i; 3251 3252 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 3253 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 3254 && strlen (mips_arch_choices[i].name) == namelen) 3255 c = &mips_arch_choices[i]; 3256 3257 return c; 3258} 3259 3260static const struct mips_arch_choice * 3261choose_arch_by_number (unsigned long mach) 3262{ 3263 static unsigned long hint_bfd_mach; 3264 static const struct mips_arch_choice *hint_arch_choice; 3265 const struct mips_arch_choice *c; 3266 unsigned int i; 3267 3268 /* We optimize this because even if the user specifies no 3269 flags, this will be done for every instruction! */ 3270 if (hint_bfd_mach == mach 3271 && hint_arch_choice != NULL 3272 && hint_arch_choice->bfd_mach == hint_bfd_mach) 3273 return hint_arch_choice; 3274 3275 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 3276 { 3277 if (mips_arch_choices[i].bfd_mach_valid 3278 && mips_arch_choices[i].bfd_mach == mach) 3279 { 3280 c = &mips_arch_choices[i]; 3281 hint_bfd_mach = mach; 3282 hint_arch_choice = c; 3283 } 3284 } 3285 return c; 3286} 3287 3288static void 3289set_default_mips_dis_options (struct disassemble_info *info) 3290{ 3291 const struct mips_arch_choice *chosen_arch; 3292 3293 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, 3294 and numeric FPR, CP0 register, and HWR names. */ 3295 mips_isa = ISA_MIPS3; 3296 mips_processor = CPU_R3000; 3297 mips_gpr_names = mips_gpr_names_oldabi; 3298 mips_fpr_names = mips_fpr_names_numeric; 3299 mips_cp0_names = mips_cp0_names_numeric; 3300 mips_cp0sel_names = NULL; 3301 mips_cp0sel_names_len = 0; 3302 mips_hwr_names = mips_hwr_names_numeric; 3303 no_aliases = 0; 3304 3305 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 3306#if 0 3307 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 3308 { 3309 Elf_Internal_Ehdr *header; 3310 3311 header = elf_elfheader (info->section->owner); 3312 if (is_newabi (header)) 3313 mips_gpr_names = mips_gpr_names_newabi; 3314 } 3315#endif 3316 3317 /* Set ISA, architecture, and cp0 register names as best we can. */ 3318#if !defined(SYMTAB_AVAILABLE) && 0 3319 /* This is running out on a target machine, not in a host tool. 3320 FIXME: Where does mips_target_info come from? */ 3321 target_processor = mips_target_info.processor; 3322 mips_isa = mips_target_info.isa; 3323#else 3324 chosen_arch = choose_arch_by_number (info->mach); 3325 if (chosen_arch != NULL) 3326 { 3327 mips_processor = chosen_arch->processor; 3328 mips_isa = chosen_arch->isa; 3329 mips_cp0_names = chosen_arch->cp0_names; 3330 mips_cp0sel_names = chosen_arch->cp0sel_names; 3331 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3332 mips_hwr_names = chosen_arch->hwr_names; 3333 } 3334#endif 3335} 3336 3337static void 3338parse_mips_dis_option (const char *option, unsigned int len) 3339{ 3340 unsigned int i, optionlen, vallen; 3341 const char *val; 3342 const struct mips_abi_choice *chosen_abi; 3343 const struct mips_arch_choice *chosen_arch; 3344 3345 /* Look for the = that delimits the end of the option name. */ 3346 for (i = 0; i < len; i++) 3347 { 3348 if (option[i] == '=') 3349 break; 3350 } 3351 if (i == 0) /* Invalid option: no name before '='. */ 3352 return; 3353 if (i == len) /* Invalid option: no '='. */ 3354 return; 3355 if (i == (len - 1)) /* Invalid option: no value after '='. */ 3356 return; 3357 3358 optionlen = i; 3359 val = option + (optionlen + 1); 3360 vallen = len - (optionlen + 1); 3361 3362 if (strncmp("gpr-names", option, optionlen) == 0 3363 && strlen("gpr-names") == optionlen) 3364 { 3365 chosen_abi = choose_abi_by_name (val, vallen); 3366 if (chosen_abi != NULL) 3367 mips_gpr_names = chosen_abi->gpr_names; 3368 return; 3369 } 3370 3371 if (strncmp("fpr-names", option, optionlen) == 0 3372 && strlen("fpr-names") == optionlen) 3373 { 3374 chosen_abi = choose_abi_by_name (val, vallen); 3375 if (chosen_abi != NULL) 3376 mips_fpr_names = chosen_abi->fpr_names; 3377 return; 3378 } 3379 3380 if (strncmp("cp0-names", option, optionlen) == 0 3381 && strlen("cp0-names") == optionlen) 3382 { 3383 chosen_arch = choose_arch_by_name (val, vallen); 3384 if (chosen_arch != NULL) 3385 { 3386 mips_cp0_names = chosen_arch->cp0_names; 3387 mips_cp0sel_names = chosen_arch->cp0sel_names; 3388 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3389 } 3390 return; 3391 } 3392 3393 if (strncmp("hwr-names", option, optionlen) == 0 3394 && strlen("hwr-names") == optionlen) 3395 { 3396 chosen_arch = choose_arch_by_name (val, vallen); 3397 if (chosen_arch != NULL) 3398 mips_hwr_names = chosen_arch->hwr_names; 3399 return; 3400 } 3401 3402 if (strncmp("reg-names", option, optionlen) == 0 3403 && strlen("reg-names") == optionlen) 3404 { 3405 /* We check both ABI and ARCH here unconditionally, so 3406 that "numeric" will do the desirable thing: select 3407 numeric register names for all registers. Other than 3408 that, a given name probably won't match both. */ 3409 chosen_abi = choose_abi_by_name (val, vallen); 3410 if (chosen_abi != NULL) 3411 { 3412 mips_gpr_names = chosen_abi->gpr_names; 3413 mips_fpr_names = chosen_abi->fpr_names; 3414 } 3415 chosen_arch = choose_arch_by_name (val, vallen); 3416 if (chosen_arch != NULL) 3417 { 3418 mips_cp0_names = chosen_arch->cp0_names; 3419 mips_cp0sel_names = chosen_arch->cp0sel_names; 3420 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3421 mips_hwr_names = chosen_arch->hwr_names; 3422 } 3423 return; 3424 } 3425 3426 /* Invalid option. */ 3427} 3428 3429static void 3430parse_mips_dis_options (const char *options) 3431{ 3432 const char *option_end; 3433 3434 if (options == NULL) 3435 return; 3436 3437 while (*options != '\0') 3438 { 3439 /* Skip empty options. */ 3440 if (*options == ',') 3441 { 3442 options++; 3443 continue; 3444 } 3445 3446 /* We know that *options is neither NUL or a comma. */ 3447 option_end = options + 1; 3448 while (*option_end != ',' && *option_end != '\0') 3449 option_end++; 3450 3451 parse_mips_dis_option (options, option_end - options); 3452 3453 /* Go on to the next one. If option_end points to a comma, it 3454 will be skipped above. */ 3455 options = option_end; 3456 } 3457} 3458 3459static const struct mips_cp0sel_name * 3460lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 3461 unsigned int len, 3462 unsigned int cp0reg, 3463 unsigned int sel) 3464{ 3465 unsigned int i; 3466 3467 for (i = 0; i < len; i++) 3468 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 3469 return &names[i]; 3470 return NULL; 3471} 3472 3473/* Print insn arguments for 32/64-bit code. */ 3474 3475static void 3476print_insn_args (const char *d, 3477 register unsigned long int l, 3478 bfd_vma pc, 3479 struct disassemble_info *info, 3480 const struct mips_opcode *opp) 3481{ 3482 int op, delta; 3483 unsigned int lsb, msb, msbd; 3484 3485 lsb = 0; 3486 3487 for (; *d != '\0'; d++) 3488 { 3489 switch (*d) 3490 { 3491 case ',': 3492 case '(': 3493 case ')': 3494 case '[': 3495 case ']': 3496 (*info->fprintf_func) (info->stream, "%c", *d); 3497 break; 3498 3499 case '+': 3500 /* Extension character; switch for second char. */ 3501 d++; 3502 switch (*d) 3503 { 3504 case '\0': 3505 /* xgettext:c-format */ 3506 (*info->fprintf_func) (info->stream, 3507 _("# internal error, incomplete extension sequence (+)")); 3508 return; 3509 3510 case 'A': 3511 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; 3512 (*info->fprintf_func) (info->stream, "0x%x", lsb); 3513 break; 3514 3515 case 'B': 3516 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; 3517 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 3518 break; 3519 3520 case '1': 3521 (*info->fprintf_func) (info->stream, "0x%lx", 3522 (l >> OP_SH_UDI1) & OP_MASK_UDI1); 3523 break; 3524 3525 case '2': 3526 (*info->fprintf_func) (info->stream, "0x%lx", 3527 (l >> OP_SH_UDI2) & OP_MASK_UDI2); 3528 break; 3529 3530 case '3': 3531 (*info->fprintf_func) (info->stream, "0x%lx", 3532 (l >> OP_SH_UDI3) & OP_MASK_UDI3); 3533 break; 3534 3535 case '4': 3536 (*info->fprintf_func) (info->stream, "0x%lx", 3537 (l >> OP_SH_UDI4) & OP_MASK_UDI4); 3538 break; 3539 3540 case 'C': 3541 case 'H': 3542 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; 3543 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 3544 break; 3545 3546 case 'D': 3547 { 3548 const struct mips_cp0sel_name *n; 3549 unsigned int cp0reg, sel; 3550 3551 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; 3552 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 3553 3554 /* CP0 register including 'sel' code for mtcN (et al.), to be 3555 printed textually if known. If not known, print both 3556 CP0 register name and sel numerically since CP0 register 3557 with sel 0 may have a name unrelated to register being 3558 printed. */ 3559 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 3560 mips_cp0sel_names_len, cp0reg, sel); 3561 if (n != NULL) 3562 (*info->fprintf_func) (info->stream, "%s", n->name); 3563 else 3564 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 3565 break; 3566 } 3567 3568 case 'E': 3569 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; 3570 (*info->fprintf_func) (info->stream, "0x%x", lsb); 3571 break; 3572 3573 case 'F': 3574 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; 3575 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 3576 break; 3577 3578 case 'G': 3579 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; 3580 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 3581 break; 3582 3583 case 't': /* Coprocessor 0 reg name */ 3584 (*info->fprintf_func) (info->stream, "%s", 3585 mips_cp0_names[(l >> OP_SH_RT) & 3586 OP_MASK_RT]); 3587 break; 3588 3589 case 'T': /* Coprocessor 0 reg name */ 3590 { 3591 const struct mips_cp0sel_name *n; 3592 unsigned int cp0reg, sel; 3593 3594 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; 3595 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 3596 3597 /* CP0 register including 'sel' code for mftc0, to be 3598 printed textually if known. If not known, print both 3599 CP0 register name and sel numerically since CP0 register 3600 with sel 0 may have a name unrelated to register being 3601 printed. */ 3602 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 3603 mips_cp0sel_names_len, cp0reg, sel); 3604 if (n != NULL) 3605 (*info->fprintf_func) (info->stream, "%s", n->name); 3606 else 3607 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 3608 break; 3609 } 3610 3611 default: 3612 /* xgettext:c-format */ 3613 (*info->fprintf_func) (info->stream, 3614 _("# internal error, undefined extension sequence (+%c)"), 3615 *d); 3616 return; 3617 } 3618 break; 3619 3620 case '2': 3621 (*info->fprintf_func) (info->stream, "0x%lx", 3622 (l >> OP_SH_BP) & OP_MASK_BP); 3623 break; 3624 3625 case '3': 3626 (*info->fprintf_func) (info->stream, "0x%lx", 3627 (l >> OP_SH_SA3) & OP_MASK_SA3); 3628 break; 3629 3630 case '4': 3631 (*info->fprintf_func) (info->stream, "0x%lx", 3632 (l >> OP_SH_SA4) & OP_MASK_SA4); 3633 break; 3634 3635 case '5': 3636 (*info->fprintf_func) (info->stream, "0x%lx", 3637 (l >> OP_SH_IMM8) & OP_MASK_IMM8); 3638 break; 3639 3640 case '6': 3641 (*info->fprintf_func) (info->stream, "0x%lx", 3642 (l >> OP_SH_RS) & OP_MASK_RS); 3643 break; 3644 3645 case '7': 3646 (*info->fprintf_func) (info->stream, "$ac%ld", 3647 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); 3648 break; 3649 3650 case '8': 3651 (*info->fprintf_func) (info->stream, "0x%lx", 3652 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); 3653 break; 3654 3655 case '9': 3656 (*info->fprintf_func) (info->stream, "$ac%ld", 3657 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); 3658 break; 3659 3660 case '0': /* dsp 6-bit signed immediate in bit 20 */ 3661 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); 3662 if (delta & 0x20) /* test sign bit */ 3663 delta |= ~OP_MASK_DSPSFT; 3664 (*info->fprintf_func) (info->stream, "%d", delta); 3665 break; 3666 3667 case ':': /* dsp 7-bit signed immediate in bit 19 */ 3668 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); 3669 if (delta & 0x40) /* test sign bit */ 3670 delta |= ~OP_MASK_DSPSFT_7; 3671 (*info->fprintf_func) (info->stream, "%d", delta); 3672 break; 3673 3674 case '\'': 3675 (*info->fprintf_func) (info->stream, "0x%lx", 3676 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); 3677 break; 3678 3679 case '@': /* dsp 10-bit signed immediate in bit 16 */ 3680 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 3681 if (delta & 0x200) /* test sign bit */ 3682 delta |= ~OP_MASK_IMM10; 3683 (*info->fprintf_func) (info->stream, "%d", delta); 3684 break; 3685 3686 case '!': 3687 (*info->fprintf_func) (info->stream, "%ld", 3688 (l >> OP_SH_MT_U) & OP_MASK_MT_U); 3689 break; 3690 3691 case '$': 3692 (*info->fprintf_func) (info->stream, "%ld", 3693 (l >> OP_SH_MT_H) & OP_MASK_MT_H); 3694 break; 3695 3696 case '*': 3697 (*info->fprintf_func) (info->stream, "$ac%ld", 3698 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); 3699 break; 3700 3701 case '&': 3702 (*info->fprintf_func) (info->stream, "$ac%ld", 3703 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); 3704 break; 3705 3706 case 'g': 3707 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 3708 (*info->fprintf_func) (info->stream, "$%ld", 3709 (l >> OP_SH_RD) & OP_MASK_RD); 3710 break; 3711 3712 case 's': 3713 case 'b': 3714 case 'r': 3715 case 'v': 3716 (*info->fprintf_func) (info->stream, "%s", 3717 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); 3718 break; 3719 3720 case 't': 3721 case 'w': 3722 (*info->fprintf_func) (info->stream, "%s", 3723 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3724 break; 3725 3726 case 'i': 3727 case 'u': 3728 (*info->fprintf_func) (info->stream, "0x%lx", 3729 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); 3730 break; 3731 3732 case 'j': /* Same as i, but sign-extended. */ 3733 case 'o': 3734 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 3735 if (delta & 0x8000) 3736 delta |= ~0xffff; 3737 (*info->fprintf_func) (info->stream, "%d", 3738 delta); 3739 break; 3740 3741 case 'h': 3742 (*info->fprintf_func) (info->stream, "0x%x", 3743 (unsigned int) ((l >> OP_SH_PREFX) 3744 & OP_MASK_PREFX)); 3745 break; 3746 3747 case 'k': 3748 (*info->fprintf_func) (info->stream, "0x%x", 3749 (unsigned int) ((l >> OP_SH_CACHE) 3750 & OP_MASK_CACHE)); 3751 break; 3752 3753 case 'a': 3754 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 3755 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); 3756 /* For gdb disassembler, force odd address on jalx. */ 3757 if (info->flavour == bfd_target_unknown_flavour 3758 && strcmp (opp->name, "jalx") == 0) 3759 info->target |= 1; 3760 (*info->print_address_func) (info->target, info); 3761 break; 3762 3763 case 'p': 3764 /* Sign extend the displacement. */ 3765 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 3766 if (delta & 0x8000) 3767 delta |= ~0xffff; 3768 info->target = (delta << 2) + pc + INSNLEN; 3769 (*info->print_address_func) (info->target, info); 3770 break; 3771 3772 case 'd': 3773 (*info->fprintf_func) (info->stream, "%s", 3774 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3775 break; 3776 3777 case 'U': 3778 { 3779 /* First check for both rd and rt being equal. */ 3780 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; 3781 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) 3782 (*info->fprintf_func) (info->stream, "%s", 3783 mips_gpr_names[reg]); 3784 else 3785 { 3786 /* If one is zero use the other. */ 3787 if (reg == 0) 3788 (*info->fprintf_func) (info->stream, "%s", 3789 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3790 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) 3791 (*info->fprintf_func) (info->stream, "%s", 3792 mips_gpr_names[reg]); 3793 else /* Bogus, result depends on processor. */ 3794 (*info->fprintf_func) (info->stream, "%s or %s", 3795 mips_gpr_names[reg], 3796 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3797 } 3798 } 3799 break; 3800 3801 case 'z': 3802 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 3803 break; 3804 3805 case '<': 3806 (*info->fprintf_func) (info->stream, "0x%lx", 3807 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); 3808 break; 3809 3810 case 'c': 3811 (*info->fprintf_func) (info->stream, "0x%lx", 3812 (l >> OP_SH_CODE) & OP_MASK_CODE); 3813 break; 3814 3815 case 'q': 3816 (*info->fprintf_func) (info->stream, "0x%lx", 3817 (l >> OP_SH_CODE2) & OP_MASK_CODE2); 3818 break; 3819 3820 case 'C': 3821 (*info->fprintf_func) (info->stream, "0x%lx", 3822 (l >> OP_SH_COPZ) & OP_MASK_COPZ); 3823 break; 3824 3825 case 'B': 3826 (*info->fprintf_func) (info->stream, "0x%lx", 3827 3828 (l >> OP_SH_CODE20) & OP_MASK_CODE20); 3829 break; 3830 3831 case 'J': 3832 (*info->fprintf_func) (info->stream, "0x%lx", 3833 (l >> OP_SH_CODE19) & OP_MASK_CODE19); 3834 break; 3835 3836 case 'S': 3837 case 'V': 3838 (*info->fprintf_func) (info->stream, "%s", 3839 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 3840 break; 3841 3842 case 'T': 3843 case 'W': 3844 (*info->fprintf_func) (info->stream, "%s", 3845 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 3846 break; 3847 3848 case 'D': 3849 (*info->fprintf_func) (info->stream, "%s", 3850 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 3851 break; 3852 3853 case 'R': 3854 (*info->fprintf_func) (info->stream, "%s", 3855 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); 3856 break; 3857 3858 case 'E': 3859 /* Coprocessor register for lwcN instructions, et al. 3860 3861 Note that there is no load/store cp0 instructions, and 3862 that FPU (cp1) instructions disassemble this field using 3863 'T' format. Therefore, until we gain understanding of 3864 cp2 register names, we can simply print the register 3865 numbers. */ 3866 (*info->fprintf_func) (info->stream, "$%ld", 3867 (l >> OP_SH_RT) & OP_MASK_RT); 3868 break; 3869 3870 case 'G': 3871 /* Coprocessor register for mtcN instructions, et al. Note 3872 that FPU (cp1) instructions disassemble this field using 3873 'S' format. Therefore, we only need to worry about cp0, 3874 cp2, and cp3. */ 3875 op = (l >> OP_SH_OP) & OP_MASK_OP; 3876 if (op == OP_OP_COP0) 3877 (*info->fprintf_func) (info->stream, "%s", 3878 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3879 else 3880 (*info->fprintf_func) (info->stream, "$%ld", 3881 (l >> OP_SH_RD) & OP_MASK_RD); 3882 break; 3883 3884 case 'K': 3885 (*info->fprintf_func) (info->stream, "%s", 3886 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3887 break; 3888 3889 case 'N': 3890 (*info->fprintf_func) (info->stream, 3891 ((opp->pinfo & (FP_D | FP_S)) != 0 3892 ? "$fcc%ld" : "$cc%ld"), 3893 (l >> OP_SH_BCC) & OP_MASK_BCC); 3894 break; 3895 3896 case 'M': 3897 (*info->fprintf_func) (info->stream, "$fcc%ld", 3898 (l >> OP_SH_CCC) & OP_MASK_CCC); 3899 break; 3900 3901 case 'P': 3902 (*info->fprintf_func) (info->stream, "%ld", 3903 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); 3904 break; 3905 3906 case 'e': 3907 (*info->fprintf_func) (info->stream, "%ld", 3908 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); 3909 break; 3910 3911 case '%': 3912 (*info->fprintf_func) (info->stream, "%ld", 3913 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); 3914 break; 3915 3916 case 'H': 3917 (*info->fprintf_func) (info->stream, "%ld", 3918 (l >> OP_SH_SEL) & OP_MASK_SEL); 3919 break; 3920 3921 case 'O': 3922 (*info->fprintf_func) (info->stream, "%ld", 3923 (l >> OP_SH_ALN) & OP_MASK_ALN); 3924 break; 3925 3926 case 'Q': 3927 { 3928 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; 3929 3930 if ((vsel & 0x10) == 0) 3931 { 3932 int fmt; 3933 3934 vsel &= 0x0f; 3935 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 3936 if ((vsel & 1) == 0) 3937 break; 3938 (*info->fprintf_func) (info->stream, "$v%ld[%d]", 3939 (l >> OP_SH_FT) & OP_MASK_FT, 3940 vsel >> 1); 3941 } 3942 else if ((vsel & 0x08) == 0) 3943 { 3944 (*info->fprintf_func) (info->stream, "$v%ld", 3945 (l >> OP_SH_FT) & OP_MASK_FT); 3946 } 3947 else 3948 { 3949 (*info->fprintf_func) (info->stream, "0x%lx", 3950 (l >> OP_SH_FT) & OP_MASK_FT); 3951 } 3952 } 3953 break; 3954 3955 case 'X': 3956 (*info->fprintf_func) (info->stream, "$v%ld", 3957 (l >> OP_SH_FD) & OP_MASK_FD); 3958 break; 3959 3960 case 'Y': 3961 (*info->fprintf_func) (info->stream, "$v%ld", 3962 (l >> OP_SH_FS) & OP_MASK_FS); 3963 break; 3964 3965 case 'Z': 3966 (*info->fprintf_func) (info->stream, "$v%ld", 3967 (l >> OP_SH_FT) & OP_MASK_FT); 3968 break; 3969 3970 default: 3971 /* xgettext:c-format */ 3972 (*info->fprintf_func) (info->stream, 3973 _("# internal error, undefined modifier(%c)"), 3974 *d); 3975 return; 3976 } 3977 } 3978} 3979 3980/* Check if the object uses NewABI conventions. */ 3981#if 0 3982static int 3983is_newabi (header) 3984 Elf_Internal_Ehdr *header; 3985{ 3986 /* There are no old-style ABIs which use 64-bit ELF. */ 3987 if (header->e_ident[EI_CLASS] == ELFCLASS64) 3988 return 1; 3989 3990 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 3991 if ((header->e_flags & EF_MIPS_ABI2) != 0) 3992 return 1; 3993 3994 return 0; 3995} 3996#endif 3997 3998/* Print the mips instruction at address MEMADDR in debugged memory, 3999 on using INFO. Returns length of the instruction, in bytes, which is 4000 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 4001 this is little-endian code. */ 4002 4003static int 4004print_insn_mips (bfd_vma memaddr, 4005 unsigned long int word, 4006 struct disassemble_info *info) 4007{ 4008 const struct mips_opcode *op; 4009 static bfd_boolean init = 0; 4010 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 4011 4012 /* Build a hash table to shorten the search time. */ 4013 if (! init) 4014 { 4015 unsigned int i; 4016 4017 for (i = 0; i <= OP_MASK_OP; i++) 4018 { 4019 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 4020 { 4021 if (op->pinfo == INSN_MACRO 4022 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 4023 continue; 4024 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 4025 { 4026 mips_hash[i] = op; 4027 break; 4028 } 4029 } 4030 } 4031 4032 init = 1; 4033 } 4034 4035 info->bytes_per_chunk = INSNLEN; 4036 info->display_endian = info->endian; 4037 info->insn_info_valid = 1; 4038 info->branch_delay_insns = 0; 4039 info->data_size = 0; 4040 info->insn_type = dis_nonbranch; 4041 info->target = 0; 4042 info->target2 = 0; 4043 4044 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 4045 if (op != NULL) 4046 { 4047 for (; op < &mips_opcodes[NUMOPCODES]; op++) 4048 { 4049 if (op->pinfo != INSN_MACRO 4050 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 4051 && (word & op->mask) == op->match) 4052 { 4053 const char *d; 4054 4055 /* We always allow to disassemble the jalx instruction. */ 4056 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) 4057 && strcmp (op->name, "jalx")) 4058 continue; 4059 4060 /* Figure out instruction type and branch delay information. */ 4061 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 4062 { 4063 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 4064 info->insn_type = dis_jsr; 4065 else 4066 info->insn_type = dis_branch; 4067 info->branch_delay_insns = 1; 4068 } 4069 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 4070 | INSN_COND_BRANCH_LIKELY)) != 0) 4071 { 4072 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 4073 info->insn_type = dis_condjsr; 4074 else 4075 info->insn_type = dis_condbranch; 4076 info->branch_delay_insns = 1; 4077 } 4078 else if ((op->pinfo & (INSN_STORE_MEMORY 4079 | INSN_LOAD_MEMORY_DELAY)) != 0) 4080 info->insn_type = dis_dref; 4081 4082 (*info->fprintf_func) (info->stream, "%s", op->name); 4083 4084 d = op->args; 4085 if (d != NULL && *d != '\0') 4086 { 4087 (*info->fprintf_func) (info->stream, "\t"); 4088 print_insn_args (d, word, memaddr, info, op); 4089 } 4090 4091 return INSNLEN; 4092 } 4093 } 4094 } 4095 4096 /* Handle undefined instructions. */ 4097 info->insn_type = dis_noninsn; 4098 (*info->fprintf_func) (info->stream, "0x%lx", word); 4099 return INSNLEN; 4100} 4101 4102/* In an environment where we do not know the symbol type of the 4103 instruction we are forced to assume that the low order bit of the 4104 instructions' address may mark it as a mips16 instruction. If we 4105 are single stepping, or the pc is within the disassembled function, 4106 this works. Otherwise, we need a clue. Sometimes. */ 4107 4108static int 4109_print_insn_mips (bfd_vma memaddr, 4110 struct disassemble_info *info, 4111 enum bfd_endian endianness) 4112{ 4113 bfd_byte buffer[INSNLEN]; 4114 int status; 4115 4116 set_default_mips_dis_options (info); 4117 parse_mips_dis_options (info->disassembler_options); 4118 4119#if 0 4120#if 1 4121 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ 4122 /* Only a few tools will work this way. */ 4123 if (memaddr & 0x01) 4124 return print_insn_mips16 (memaddr, info); 4125#endif 4126 4127#if SYMTAB_AVAILABLE 4128 if (info->mach == bfd_mach_mips16 4129 || (info->flavour == bfd_target_elf_flavour 4130 && info->symbols != NULL 4131 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other 4132 == STO_MIPS16))) 4133 return print_insn_mips16 (memaddr, info); 4134#endif 4135#endif 4136 4137 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 4138 if (status == 0) 4139 { 4140 unsigned long insn; 4141 4142 if (endianness == BFD_ENDIAN_BIG) 4143 insn = (unsigned long) bfd_getb32 (buffer); 4144 else 4145 insn = (unsigned long) bfd_getl32 (buffer); 4146 4147 return print_insn_mips (memaddr, insn, info); 4148 } 4149 else 4150 { 4151 (*info->memory_error_func) (status, memaddr, info); 4152 return -1; 4153 } 4154} 4155 4156int 4157print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 4158{ 4159 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 4160} 4161 4162int 4163print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 4164{ 4165 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 4166} 4167 4168/* Disassemble mips16 instructions. */ 4169#if 0 4170static int 4171print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 4172{ 4173 int status; 4174 bfd_byte buffer[2]; 4175 int length; 4176 int insn; 4177 bfd_boolean use_extend; 4178 int extend = 0; 4179 const struct mips_opcode *op, *opend; 4180 4181 info->bytes_per_chunk = 2; 4182 info->display_endian = info->endian; 4183 info->insn_info_valid = 1; 4184 info->branch_delay_insns = 0; 4185 info->data_size = 0; 4186 info->insn_type = dis_nonbranch; 4187 info->target = 0; 4188 info->target2 = 0; 4189 4190 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 4191 if (status != 0) 4192 { 4193 (*info->memory_error_func) (status, memaddr, info); 4194 return -1; 4195 } 4196 4197 length = 2; 4198 4199 if (info->endian == BFD_ENDIAN_BIG) 4200 insn = bfd_getb16 (buffer); 4201 else 4202 insn = bfd_getl16 (buffer); 4203 4204 /* Handle the extend opcode specially. */ 4205 use_extend = FALSE; 4206 if ((insn & 0xf800) == 0xf000) 4207 { 4208 use_extend = TRUE; 4209 extend = insn & 0x7ff; 4210 4211 memaddr += 2; 4212 4213 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 4214 if (status != 0) 4215 { 4216 (*info->fprintf_func) (info->stream, "extend 0x%x", 4217 (unsigned int) extend); 4218 (*info->memory_error_func) (status, memaddr, info); 4219 return -1; 4220 } 4221 4222 if (info->endian == BFD_ENDIAN_BIG) 4223 insn = bfd_getb16 (buffer); 4224 else 4225 insn = bfd_getl16 (buffer); 4226 4227 /* Check for an extend opcode followed by an extend opcode. */ 4228 if ((insn & 0xf800) == 0xf000) 4229 { 4230 (*info->fprintf_func) (info->stream, "extend 0x%x", 4231 (unsigned int) extend); 4232 info->insn_type = dis_noninsn; 4233 return length; 4234 } 4235 4236 length += 2; 4237 } 4238 4239 /* FIXME: Should probably use a hash table on the major opcode here. */ 4240 4241 opend = mips16_opcodes + bfd_mips16_num_opcodes; 4242 for (op = mips16_opcodes; op < opend; op++) 4243 { 4244 if (op->pinfo != INSN_MACRO 4245 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 4246 && (insn & op->mask) == op->match) 4247 { 4248 const char *s; 4249 4250 if (strchr (op->args, 'a') != NULL) 4251 { 4252 if (use_extend) 4253 { 4254 (*info->fprintf_func) (info->stream, "extend 0x%x", 4255 (unsigned int) extend); 4256 info->insn_type = dis_noninsn; 4257 return length - 2; 4258 } 4259 4260 use_extend = FALSE; 4261 4262 memaddr += 2; 4263 4264 status = (*info->read_memory_func) (memaddr, buffer, 2, 4265 info); 4266 if (status == 0) 4267 { 4268 use_extend = TRUE; 4269 if (info->endian == BFD_ENDIAN_BIG) 4270 extend = bfd_getb16 (buffer); 4271 else 4272 extend = bfd_getl16 (buffer); 4273 length += 2; 4274 } 4275 } 4276 4277 (*info->fprintf_func) (info->stream, "%s", op->name); 4278 if (op->args[0] != '\0') 4279 (*info->fprintf_func) (info->stream, "\t"); 4280 4281 for (s = op->args; *s != '\0'; s++) 4282 { 4283 if (*s == ',' 4284 && s[1] == 'w' 4285 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) 4286 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) 4287 { 4288 /* Skip the register and the comma. */ 4289 ++s; 4290 continue; 4291 } 4292 if (*s == ',' 4293 && s[1] == 'v' 4294 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) 4295 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) 4296 { 4297 /* Skip the register and the comma. */ 4298 ++s; 4299 continue; 4300 } 4301 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 4302 info); 4303 } 4304 4305 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 4306 { 4307 info->branch_delay_insns = 1; 4308 if (info->insn_type != dis_jsr) 4309 info->insn_type = dis_branch; 4310 } 4311 4312 return length; 4313 } 4314 } 4315 4316 if (use_extend) 4317 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); 4318 (*info->fprintf_func) (info->stream, "0x%x", insn); 4319 info->insn_type = dis_noninsn; 4320 4321 return length; 4322} 4323 4324/* Disassemble an operand for a mips16 instruction. */ 4325 4326static void 4327print_mips16_insn_arg (char type, 4328 const struct mips_opcode *op, 4329 int l, 4330 bfd_boolean use_extend, 4331 int extend, 4332 bfd_vma memaddr, 4333 struct disassemble_info *info) 4334{ 4335 switch (type) 4336 { 4337 case ',': 4338 case '(': 4339 case ')': 4340 (*info->fprintf_func) (info->stream, "%c", type); 4341 break; 4342 4343 case 'y': 4344 case 'w': 4345 (*info->fprintf_func) (info->stream, "%s", 4346 mips16_reg_names(((l >> MIPS16OP_SH_RY) 4347 & MIPS16OP_MASK_RY))); 4348 break; 4349 4350 case 'x': 4351 case 'v': 4352 (*info->fprintf_func) (info->stream, "%s", 4353 mips16_reg_names(((l >> MIPS16OP_SH_RX) 4354 & MIPS16OP_MASK_RX))); 4355 break; 4356 4357 case 'z': 4358 (*info->fprintf_func) (info->stream, "%s", 4359 mips16_reg_names(((l >> MIPS16OP_SH_RZ) 4360 & MIPS16OP_MASK_RZ))); 4361 break; 4362 4363 case 'Z': 4364 (*info->fprintf_func) (info->stream, "%s", 4365 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) 4366 & MIPS16OP_MASK_MOVE32Z))); 4367 break; 4368 4369 case '0': 4370 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 4371 break; 4372 4373 case 'S': 4374 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); 4375 break; 4376 4377 case 'P': 4378 (*info->fprintf_func) (info->stream, "$pc"); 4379 break; 4380 4381 case 'R': 4382 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); 4383 break; 4384 4385 case 'X': 4386 (*info->fprintf_func) (info->stream, "%s", 4387 mips_gpr_names[((l >> MIPS16OP_SH_REGR32) 4388 & MIPS16OP_MASK_REGR32)]); 4389 break; 4390 4391 case 'Y': 4392 (*info->fprintf_func) (info->stream, "%s", 4393 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 4394 break; 4395 4396 case '<': 4397 case '>': 4398 case '[': 4399 case ']': 4400 case '4': 4401 case '5': 4402 case 'H': 4403 case 'W': 4404 case 'D': 4405 case 'j': 4406 case '6': 4407 case '8': 4408 case 'V': 4409 case 'C': 4410 case 'U': 4411 case 'k': 4412 case 'K': 4413 case 'p': 4414 case 'q': 4415 case 'A': 4416 case 'B': 4417 case 'E': 4418 { 4419 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 4420 4421 shift = 0; 4422 signedp = 0; 4423 extbits = 16; 4424 pcrel = 0; 4425 extu = 0; 4426 branch = 0; 4427 switch (type) 4428 { 4429 case '<': 4430 nbits = 3; 4431 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 4432 extbits = 5; 4433 extu = 1; 4434 break; 4435 case '>': 4436 nbits = 3; 4437 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 4438 extbits = 5; 4439 extu = 1; 4440 break; 4441 case '[': 4442 nbits = 3; 4443 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 4444 extbits = 6; 4445 extu = 1; 4446 break; 4447 case ']': 4448 nbits = 3; 4449 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 4450 extbits = 6; 4451 extu = 1; 4452 break; 4453 case '4': 4454 nbits = 4; 4455 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; 4456 signedp = 1; 4457 extbits = 15; 4458 break; 4459 case '5': 4460 nbits = 5; 4461 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4462 info->insn_type = dis_dref; 4463 info->data_size = 1; 4464 break; 4465 case 'H': 4466 nbits = 5; 4467 shift = 1; 4468 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4469 info->insn_type = dis_dref; 4470 info->data_size = 2; 4471 break; 4472 case 'W': 4473 nbits = 5; 4474 shift = 2; 4475 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4476 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 4477 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 4478 { 4479 info->insn_type = dis_dref; 4480 info->data_size = 4; 4481 } 4482 break; 4483 case 'D': 4484 nbits = 5; 4485 shift = 3; 4486 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4487 info->insn_type = dis_dref; 4488 info->data_size = 8; 4489 break; 4490 case 'j': 4491 nbits = 5; 4492 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4493 signedp = 1; 4494 break; 4495 case '6': 4496 nbits = 6; 4497 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 4498 break; 4499 case '8': 4500 nbits = 8; 4501 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4502 break; 4503 case 'V': 4504 nbits = 8; 4505 shift = 2; 4506 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4507 /* FIXME: This might be lw, or it might be addiu to $sp or 4508 $pc. We assume it's load. */ 4509 info->insn_type = dis_dref; 4510 info->data_size = 4; 4511 break; 4512 case 'C': 4513 nbits = 8; 4514 shift = 3; 4515 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4516 info->insn_type = dis_dref; 4517 info->data_size = 8; 4518 break; 4519 case 'U': 4520 nbits = 8; 4521 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4522 extu = 1; 4523 break; 4524 case 'k': 4525 nbits = 8; 4526 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4527 signedp = 1; 4528 break; 4529 case 'K': 4530 nbits = 8; 4531 shift = 3; 4532 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4533 signedp = 1; 4534 break; 4535 case 'p': 4536 nbits = 8; 4537 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4538 signedp = 1; 4539 pcrel = 1; 4540 branch = 1; 4541 info->insn_type = dis_condbranch; 4542 break; 4543 case 'q': 4544 nbits = 11; 4545 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; 4546 signedp = 1; 4547 pcrel = 1; 4548 branch = 1; 4549 info->insn_type = dis_branch; 4550 break; 4551 case 'A': 4552 nbits = 8; 4553 shift = 2; 4554 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4555 pcrel = 1; 4556 /* FIXME: This can be lw or la. We assume it is lw. */ 4557 info->insn_type = dis_dref; 4558 info->data_size = 4; 4559 break; 4560 case 'B': 4561 nbits = 5; 4562 shift = 3; 4563 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4564 pcrel = 1; 4565 info->insn_type = dis_dref; 4566 info->data_size = 8; 4567 break; 4568 case 'E': 4569 nbits = 5; 4570 shift = 2; 4571 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4572 pcrel = 1; 4573 break; 4574 default: 4575 abort (); 4576 } 4577 4578 if (! use_extend) 4579 { 4580 if (signedp && immed >= (1 << (nbits - 1))) 4581 immed -= 1 << nbits; 4582 immed <<= shift; 4583 if ((type == '<' || type == '>' || type == '[' || type == ']') 4584 && immed == 0) 4585 immed = 8; 4586 } 4587 else 4588 { 4589 if (extbits == 16) 4590 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 4591 else if (extbits == 15) 4592 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 4593 else 4594 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 4595 immed &= (1 << extbits) - 1; 4596 if (! extu && immed >= (1 << (extbits - 1))) 4597 immed -= 1 << extbits; 4598 } 4599 4600 if (! pcrel) 4601 (*info->fprintf_func) (info->stream, "%d", immed); 4602 else 4603 { 4604 bfd_vma baseaddr; 4605 4606 if (branch) 4607 { 4608 immed *= 2; 4609 baseaddr = memaddr + 2; 4610 } 4611 else if (use_extend) 4612 baseaddr = memaddr - 2; 4613 else 4614 { 4615 int status; 4616 bfd_byte buffer[2]; 4617 4618 baseaddr = memaddr; 4619 4620 /* If this instruction is in the delay slot of a jr 4621 instruction, the base address is the address of the 4622 jr instruction. If it is in the delay slot of jalr 4623 instruction, the base address is the address of the 4624 jalr instruction. This test is unreliable: we have 4625 no way of knowing whether the previous word is 4626 instruction or data. */ 4627 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 4628 info); 4629 if (status == 0 4630 && (((info->endian == BFD_ENDIAN_BIG 4631 ? bfd_getb16 (buffer) 4632 : bfd_getl16 (buffer)) 4633 & 0xf800) == 0x1800)) 4634 baseaddr = memaddr - 4; 4635 else 4636 { 4637 status = (*info->read_memory_func) (memaddr - 2, buffer, 4638 2, info); 4639 if (status == 0 4640 && (((info->endian == BFD_ENDIAN_BIG 4641 ? bfd_getb16 (buffer) 4642 : bfd_getl16 (buffer)) 4643 & 0xf81f) == 0xe800)) 4644 baseaddr = memaddr - 2; 4645 } 4646 } 4647 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 4648 if (pcrel && branch 4649 && info->flavour == bfd_target_unknown_flavour) 4650 /* For gdb disassembler, maintain odd address. */ 4651 info->target |= 1; 4652 (*info->print_address_func) (info->target, info); 4653 } 4654 } 4655 break; 4656 4657 case 'a': 4658 { 4659 int jalx = l & 0x400; 4660 4661 if (! use_extend) 4662 extend = 0; 4663 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 4664 if (!jalx && info->flavour == bfd_target_unknown_flavour) 4665 /* For gdb disassembler, maintain odd address. */ 4666 l |= 1; 4667 } 4668 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 4669 (*info->print_address_func) (info->target, info); 4670 info->insn_type = dis_jsr; 4671 info->branch_delay_insns = 1; 4672 break; 4673 4674 case 'l': 4675 case 'L': 4676 { 4677 int need_comma, amask, smask; 4678 4679 need_comma = 0; 4680 4681 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 4682 4683 amask = (l >> 3) & 7; 4684 4685 if (amask > 0 && amask < 5) 4686 { 4687 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 4688 if (amask > 1) 4689 (*info->fprintf_func) (info->stream, "-%s", 4690 mips_gpr_names[amask + 3]); 4691 need_comma = 1; 4692 } 4693 4694 smask = (l >> 1) & 3; 4695 if (smask == 3) 4696 { 4697 (*info->fprintf_func) (info->stream, "%s??", 4698 need_comma ? "," : ""); 4699 need_comma = 1; 4700 } 4701 else if (smask > 0) 4702 { 4703 (*info->fprintf_func) (info->stream, "%s%s", 4704 need_comma ? "," : "", 4705 mips_gpr_names[16]); 4706 if (smask > 1) 4707 (*info->fprintf_func) (info->stream, "-%s", 4708 mips_gpr_names[smask + 15]); 4709 need_comma = 1; 4710 } 4711 4712 if (l & 1) 4713 { 4714 (*info->fprintf_func) (info->stream, "%s%s", 4715 need_comma ? "," : "", 4716 mips_gpr_names[31]); 4717 need_comma = 1; 4718 } 4719 4720 if (amask == 5 || amask == 6) 4721 { 4722 (*info->fprintf_func) (info->stream, "%s$f0", 4723 need_comma ? "," : ""); 4724 if (amask == 6) 4725 (*info->fprintf_func) (info->stream, "-$f1"); 4726 } 4727 } 4728 break; 4729 4730 case 'm': 4731 case 'M': 4732 /* MIPS16e save/restore. */ 4733 { 4734 int need_comma = 0; 4735 int amask, args, statics; 4736 int nsreg, smask; 4737 int framesz; 4738 int i, j; 4739 4740 l = l & 0x7f; 4741 if (use_extend) 4742 l |= extend << 16; 4743 4744 amask = (l >> 16) & 0xf; 4745 if (amask == MIPS16_ALL_ARGS) 4746 { 4747 args = 4; 4748 statics = 0; 4749 } 4750 else if (amask == MIPS16_ALL_STATICS) 4751 { 4752 args = 0; 4753 statics = 4; 4754 } 4755 else 4756 { 4757 args = amask >> 2; 4758 statics = amask & 3; 4759 } 4760 4761 if (args > 0) { 4762 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 4763 if (args > 1) 4764 (*info->fprintf_func) (info->stream, "-%s", 4765 mips_gpr_names[4 + args - 1]); 4766 need_comma = 1; 4767 } 4768 4769 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 4770 if (framesz == 0 && !use_extend) 4771 framesz = 128; 4772 4773 (*info->fprintf_func) (info->stream, "%s%d", 4774 need_comma ? "," : "", 4775 framesz); 4776 4777 if (l & 0x40) /* $ra */ 4778 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); 4779 4780 nsreg = (l >> 24) & 0x7; 4781 smask = 0; 4782 if (l & 0x20) /* $s0 */ 4783 smask |= 1 << 0; 4784 if (l & 0x10) /* $s1 */ 4785 smask |= 1 << 1; 4786 if (nsreg > 0) /* $s2-$s8 */ 4787 smask |= ((1 << nsreg) - 1) << 2; 4788 4789 /* Find first set static reg bit. */ 4790 for (i = 0; i < 9; i++) 4791 { 4792 if (smask & (1 << i)) 4793 { 4794 (*info->fprintf_func) (info->stream, ",%s", 4795 mips_gpr_names[i == 8 ? 30 : (16 + i)]); 4796 /* Skip over string of set bits. */ 4797 for (j = i; smask & (2 << j); j++) 4798 continue; 4799 if (j > i) 4800 (*info->fprintf_func) (info->stream, "-%s", 4801 mips_gpr_names[j == 8 ? 30 : (16 + j)]); 4802 i = j + 1; 4803 } 4804 } 4805 4806 /* Statics $ax - $a3. */ 4807 if (statics == 1) 4808 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); 4809 else if (statics > 0) 4810 (*info->fprintf_func) (info->stream, ",%s-%s", 4811 mips_gpr_names[7 - statics + 1], 4812 mips_gpr_names[7]); 4813 } 4814 break; 4815 4816 default: 4817 /* xgettext:c-format */ 4818 (*info->fprintf_func) 4819 (info->stream, 4820 _("# internal disassembler error, unrecognised modifier (%c)"), 4821 type); 4822 abort (); 4823 } 4824} 4825 4826void 4827print_mips_disassembler_options (FILE *stream) 4828{ 4829 unsigned int i; 4830 4831 fprintf (stream, _("\n\ 4832The following MIPS specific disassembler options are supported for use\n\ 4833with the -M switch (multiple options should be separated by commas):\n")); 4834 4835 fprintf (stream, _("\n\ 4836 gpr-names=ABI Print GPR names according to specified ABI.\n\ 4837 Default: based on binary being disassembled.\n")); 4838 4839 fprintf (stream, _("\n\ 4840 fpr-names=ABI Print FPR names according to specified ABI.\n\ 4841 Default: numeric.\n")); 4842 4843 fprintf (stream, _("\n\ 4844 cp0-names=ARCH Print CP0 register names according to\n\ 4845 specified architecture.\n\ 4846 Default: based on binary being disassembled.\n")); 4847 4848 fprintf (stream, _("\n\ 4849 hwr-names=ARCH Print HWR names according to specified\n\ 4850 architecture.\n\ 4851 Default: based on binary being disassembled.\n")); 4852 4853 fprintf (stream, _("\n\ 4854 reg-names=ABI Print GPR and FPR names according to\n\ 4855 specified ABI.\n")); 4856 4857 fprintf (stream, _("\n\ 4858 reg-names=ARCH Print CP0 register and HWR names according to\n\ 4859 specified architecture.\n")); 4860 4861 fprintf (stream, _("\n\ 4862 For the options above, the following values are supported for \"ABI\":\n\ 4863 ")); 4864 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 4865 fprintf (stream, " %s", mips_abi_choices[i].name); 4866 fprintf (stream, _("\n")); 4867 4868 fprintf (stream, _("\n\ 4869 For the options above, The following values are supported for \"ARCH\":\n\ 4870 ")); 4871 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 4872 if (*mips_arch_choices[i].name != '\0') 4873 fprintf (stream, " %s", mips_arch_choices[i].name); 4874 fprintf (stream, _("\n")); 4875 4876 fprintf (stream, _("\n")); 4877} 4878#endif 4879