18abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles)/* mmx.h 28abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 38abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) MultiMedia eXtensions GCC interface library for IA32. 48abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 58abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) To use this library, simply include this header file 68abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) and compile with GCC. You MUST have inlining enabled 78abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) in order for mmx_ok() to work; this can be done by 88abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) simply using -O on the GCC command line. 98abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 108abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) Compiling with -DMMX_TRACE will cause detailed trace 118abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) output to be sent to stderr for each mmx operation. 128abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) This adds lots of code, and obviously slows execution to 138abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) a crawl, but can be very useful for debugging. 148abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 158abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY 168abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT 178abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY 188abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) AND FITNESS FOR ANY PARTICULAR PURPOSE. 198abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 208abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 1997-99 by H. Dietz and R. Fisher 218abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 228abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) Notes: 238abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) It appears that the latest gas has the pand problem fixed, therefore 248abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) I'll undefine BROKEN_PAND by default. 258abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles)*/ 268abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 278abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles)#ifndef _MMX_H 288abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles)#define _MMX_H 299bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 309bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 31e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)/* Warning: at this writing, the version of GAS packaged 32d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) with most Linux distributions does not handle the 33d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) parallel AND operation mnemonic correctly. If the 349bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) symbol BROKEN_PAND is defined, a slower alternative 359bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) coding will be used. If execution of mmxtest results 361e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) in an illegal instruction fault, define this symbol. 37f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles)*/ 38e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)#undef BROKEN_PAND 39d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 40f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) 418abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles)/* The type of an value that fits in an MMX register 428abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) (note that long long constant values MUST be suffixed 435d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) by LL and unsigned long long values by ULL, lest 445d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) they be truncated by the compiler) 455d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles)*/ 465d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles)typedef union { 475d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) long long q; /* Quadword (64-bit) value */ 485d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) unsigned long long uq; /* Unsigned Quadword */ 495d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) int d[2]; /* 2 Doubleword (32-bit) values */ 505d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) unsigned int ud[2]; /* 2 Unsigned Doubleword */ 515d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) short w[4]; /* 4 Word (16-bit) values */ 525d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) unsigned short uw[4]; /* 4 Unsigned Word */ 535d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) char b[8]; /* 8 Byte (8-bit) values */ 545d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) unsigned char ub[8]; /* 8 Unsigned Byte */ 558abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) float s[2]; /* Single-precision (32-bit) value */ 568abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles)} __attribute__ ((aligned (8))) mmx_t; /* On an 8-byte (64-bit) boundary */ 5709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 5809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 5909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)#if 0 6009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)/* Function to test if multimedia instructions are supported... 617242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci*/ 627242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucciinline extern int 637242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tuccimm_support(void) 647242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci{ 6551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) /* Returns 1 if MMX instructions are supported, 6651b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) 3 if Cyrix MMX and Extended MMX instructions are supported 671e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) 5 if AMD MMX and 3DNow! instructions are supported 681e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) 0 if hardware does not support any of these 691e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) */ 708abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) register int rval = 0; 71bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) 7251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) __asm__ __volatile__ ( 7351b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) /* See if CPUID instruction is supported ... */ 7451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) /* ... Get copies of EFLAGS into eax and ecx */ 7551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) "pushf\n\t" 76bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) "popl %%eax\n\t" 77bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) "movl %%eax, %%ecx\n\t" 787242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci 79e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) /* ... Toggle the ID bit in one copy and store */ 80e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) /* to the EFLAGS reg */ 817242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci "xorl $0x200000, %%eax\n\t" 827242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci "push %%eax\n\t" 837242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci "popf\n\t" 847242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci 857242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci /* ... Get the (hopefully modified) EFLAGS */ 86e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) "pushf\n\t" 87e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) "popl %%eax\n\t" 8809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 8951b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) /* ... Compare and test result */ 9009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "xorl %%eax, %%ecx\n\t" 9109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "testl $0x200000, %%ecx\n\t" 92bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) "jz NotSupported1\n\t" /* CPUID not supported */ 93bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) 94bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) 95bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) /* Get standard CPUID information, and 96bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) go to a specific vendor section */ 97bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) "movl $0, %%eax\n\t" 988abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) "cpuid\n\t" 998abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 100f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) /* Check for Intel */ 101f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "cmpl $0x756e6547, %%ebx\n\t" 102f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "jne TryAMD\n\t" 103f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "cmpl $0x49656e69, %%edx\n\t" 104f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "jne TryAMD\n\t" 105f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "cmpl $0x6c65746e, %%ecx\n" 1061e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "jne TryAMD\n\t" 10751b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) "jmp Intel\n\t" 1081e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) 1091e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) /* Check for AMD */ 1101e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "\nTryAMD:\n\t" 1111e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "cmpl $0x68747541, %%ebx\n\t" 1121e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "jne TryCyrix\n\t" 11309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "cmpl $0x69746e65, %%edx\n\t" 1141e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "jne TryCyrix\n\t" 1151e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "cmpl $0x444d4163, %%ecx\n" 1161e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "jne TryCyrix\n\t" 11709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "jmp AMD\n\t" 11851b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) 11909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) /* Check for Cyrix */ 12009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "\nTryCyrix:\n\t" 121f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "cmpl $0x69727943, %%ebx\n\t" 122d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) "jne NotSupported2\n\t" 123d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) "cmpl $0x736e4978, %%edx\n\t" 124f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "jne NotSupported3\n\t" 125f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) "cmpl $0x64616574, %%ecx\n\t" 126d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) "jne NotSupported4\n\t" 127e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) /* Drop through to Cyrix... */ 128f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) 129f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) 13051b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) /* Cyrix Section */ 131e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) /* See if extended CPUID level 80000001 is supported */ 132e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) /* The value of CPUID/80000001 for the 6x86MX is undefined 133a9984bf9ddc3cf73fdae3f29134a2bab379e7029Ben Murdoch according to the Cyrix CPU Detection Guide (Preliminary 134a9984bf9ddc3cf73fdae3f29134a2bab379e7029Ben Murdoch Rev. 1.01 table 1), so we'll check the value of eax for 135a9984bf9ddc3cf73fdae3f29134a2bab379e7029Ben Murdoch CPUID/0 to see if standard CPUID level 2 is supported. 136a9984bf9ddc3cf73fdae3f29134a2bab379e7029Ben Murdoch According to the table, the only CPU which supports level 137a9984bf9ddc3cf73fdae3f29134a2bab379e7029Ben Murdoch 2 is also the only one which supports extended CPUID levels. 1386f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch */ 1396f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch "cmpl $0x2, %%eax\n\t" 14009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "jne MMXtest\n\t" /* Use standard CPUID instead */ 14143e7502580f146aa5b3db8267ba6dbb5c733a489Torne (Richard Coles) 14251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) /* Extended CPUID supported (in theory), so get extended 14351b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) features */ 14451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) "movl $0x80000001, %%eax\n\t" 14551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) "cpuid\n\t" 14651b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) "testl $0x00800000, %%eax\n\t" /* Test for MMX */ 14751b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) "jz NotSupported5\n\t" /* MMX not supported */ 14809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "testl $0x01000000, %%eax\n\t" /* Test for Ext'd MMX */ 14909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "jnz EMMXSupported\n\t" 15009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "movl $1, %0:\n\n\t" /* MMX Supported */ 15109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) "jmp Return\n\n" 1521e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "EMMXSupported:\n\t" 153f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu "movl $3, %0:\n\n\t" /* EMMX and MMX Supported */ 154bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) "jmp Return\n\t" 1558abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 1561e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) 1571e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) /* AMD Section */ 158f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu "AMD:\n\t" 159f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu 160bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) /* See if extended CPUID is supported */ 161f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu "movl $0x80000000, %%eax\n\t" 162f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu "cpuid\n\t" 163bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) "cmpl $0x80000000, %%eax\n\t" 164f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu "jl MMXtest\n\t" /* Use standard CPUID instead */ 165197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch 166f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu /* Extended CPUID supported, so get extended features */ 167f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu "movl $0x80000001, %%eax\n\t" 168f91f5fa1608c2cdd9af1842fb5dadbe78275be2aBo Liu "cpuid\n\t" 1691e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "testl $0x00800000, %%edx\n\t" /* Test for MMX */ 1701e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "jz NotSupported6\n\t" /* MMX not supported */ 1715d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "testl $0x80000000, %%edx\n\t" /* Test for 3DNow! */ 1725d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "jnz ThreeDNowSupported\n\t" 1735d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "movl $1, %0:\n\n\t" /* MMX Supported */ 1745d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "jmp Return\n\n" 1755d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "ThreeDNowSupported:\n\t" 1765d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "movl $5, %0:\n\n\t" /* 3DNow! and MMX Supported */ 1775d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "jmp Return\n\t" 1785d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) 1795d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) 1805d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) /* Intel Section */ 1815d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "Intel:\n\t" 1825d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) 1835d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) /* Check for MMX */ 1845d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "MMXtest:\n\t" 1855d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "movl $1, %%eax\n\t" 1865d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "cpuid\n\t" 1875d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "testl $0x00800000, %%edx\n\t" /* Test for MMX */ 1881e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "jz NotSupported7\n\t" /* MMX Not supported */ 1891e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "movl $1, %0:\n\n\t" /* MMX Supported */ 190d6cdb82654e8f3343a693ca752d5c4cee0324e17Torne (Richard Coles) "jmp Return\n\t" 1915d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) 1921e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) /* Nothing supported */ 193d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) "\nNotSupported1:\n\t" 194d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) "#movl $101, %0:\n\n\t" 1955d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "\nNotSupported2:\n\t" 1961e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "#movl $102, %0:\n\n\t" 1971e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "\nNotSupported3:\n\t" 1981e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "#movl $103, %0:\n\n\t" 1991e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "\nNotSupported4:\n\t" 2001e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "#movl $104, %0:\n\n\t" 2011e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "\nNotSupported5:\n\t" 2021e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "#movl $105, %0:\n\n\t" 2031e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "\nNotSupported6:\n\t" 2045d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) "#movl $106, %0:\n\n\t" 2051e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "\nNotSupported7:\n\t" 2061e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "#movl $107, %0:\n\n\t" 2071e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "movl $0, %0:\n\n\t" 2085d92fedcae5e801a8b224de090094f2d9df0b54aTorne (Richard Coles) 209bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) "Return:\n\t" 2101e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) : "=a" (rval) 2111e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) : /* no input */ 2121e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) : "eax", "ebx", "ecx", "edx" 213bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) ); 2141e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) 2151e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) /* Return */ 2161e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) return(rval); 217e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)} 218e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) 219e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)/* Function to test if mmx instructions are supported... 220e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)*/ 221e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)inline extern int 222e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)mmx_ok(void) 22351b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles){ 22451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) /* Returns 1 if MMX instructions are supported, 0 otherwise */ 22551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) return ( mm_support() & 0x1 ); 2261e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles)} 2277242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci#endif 2288abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 2298abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles)/* Helper functions for the instruction macros that follow... 2301e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) (note that memory-to-register, m2r, instructions are nearly 23151b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) as efficient as register-to-register, r2r, instructions; 23251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) however, memory-to-memory instructions are really simulated 23351b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) as a convenience, and are only 1/3 as efficient) 23451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)*/ 23551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)#ifdef MMX_TRACE 23651b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) 23751b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)/* Include the stuff for printing a trace to stderr... 23851b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)*/ 239e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) 240e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)#define mmx_i2r(op, imm, reg) \ 241e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) { \ 242e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_t mmx_trace; \ 243e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_trace.uq = (imm); \ 244e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) printf(#op "_i2r(" #imm "=0x%08x%08x, ", \ 245e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 246e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) __asm__ __volatile__ ("movq %%" #reg ", %0" \ 247e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : "=y" (mmx_trace) \ 248e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : /* nothing */ ); \ 249e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) printf(#reg "=0x%08x%08x) => ", \ 2507242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci mmx_trace.d[1], mmx_trace.d[0]); \ 251e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) __asm__ __volatile__ (#op " %0, %%" #reg \ 252e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : /* nothing */ \ 253e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : "y" (imm)); \ 254e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) __asm__ __volatile__ ("movq %%" #reg ", %0" \ 255e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : "=y" (mmx_trace) \ 256e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : /* nothing */ ); \ 257e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) printf(#reg "=0x%08x%08x\n", \ 258e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 259e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) } 260e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) 261e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles)#define mmx_m2r(op, mem, reg) \ 262e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) { \ 263e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_t mmx_trace; \ 264e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_trace = (mem); \ 265e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) printf(#op "_m2r(" #mem "=0x%08x%08x, ", \ 266e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 267e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) __asm__ __volatile__ ("movq %%" #reg ", %0" \ 268e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : "=y" (mmx_trace) \ 269e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : /* nothing */ ); \ 270e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) printf(#reg "=0x%08x%08x) => ", \ 271e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 2727242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci __asm__ __volatile__ (#op " %0, %%" #reg \ 273e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : /* nothing */ \ 274e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : "y" (mem)); \ 275e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) __asm__ __volatile__ ("movq %%" #reg ", %0" \ 276e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : "=y" (mmx_trace) \ 277e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) : /* nothing */ ); \ 278e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) printf(#reg "=0x%08x%08x\n", \ 279e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 280e38fbeeb576b5094e34e038ab88d9d6a5c5c2214Torne (Richard Coles) } 2816f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch 2826f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch#define mmx_r2m(op, reg, mem) \ 2836f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch { \ 2846f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch mmx_t mmx_trace; \ 2856f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch __asm__ __volatile__ ("movq %%" #reg ", %0" \ 2866f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch : "=y" (mmx_trace) \ 2876f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch : /* nothing */ ); \ 2886f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch printf(#op "_r2m(" #reg "=0x%08x%08x, ", \ 2896f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch mmx_trace.d[1], mmx_trace.d[0]); \ 2906f543c786fc42989f552b4daa774ca5ff32fa697Ben Murdoch mmx_trace = (mem); \ 29151b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) printf(#mem "=0x%08x%08x) => ", \ 29251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 29351b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) __asm__ __volatile__ (#op " %%" #reg ", %0" \ 29451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) : "=y" (mem) \ 29551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) : /* nothing */ ); \ 29651b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) mmx_trace = (mem); \ 29751b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) printf(#mem "=0x%08x%08x\n", \ 29851b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 29951b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) } 30051b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) 30151b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)#define mmx_r2r(op, regs, regd) \ 30251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) { \ 30351b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) mmx_t mmx_trace; \ 30451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) __asm__ __volatile__ ("movq %%" #regs ", %0" \ 30551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) : "=y" (mmx_trace) \ 3061e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) : /* nothing */ ); \ 3071e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) printf(#op "_r2r(" #regs "=0x%08x%08x, ", \ 308bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 309bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) __asm__ __volatile__ ("movq %%" #regd ", %0" \ 310bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) : "=y" (mmx_trace) \ 311bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) : /* nothing */ ); \ 312bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) printf(#regd "=0x%08x%08x) => ", \ 313bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 314bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) __asm__ __volatile__ (#op " %" #regs ", %" #regd); \ 315bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) __asm__ __volatile__ ("movq %%" #regd ", %0" \ 316bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) : "=y" (mmx_trace) \ 3171e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) : /* nothing */ ); \ 3181e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) printf(#regd "=0x%08x%08x\n", \ 3191e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 3208abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) } 3218abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) 3221e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles)#define mmx_m2m(op, mems, memd) \ 3238abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) { \ 3248abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) mmx_t mmx_trace; \ 3251e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) mmx_trace = (mems); \ 3261e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) printf(#op "_m2m(" #mems "=0x%08x%08x, ", \ 3271e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) mmx_trace.d[1], mmx_trace.d[0]); \ 3281e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) mmx_trace = (memd); \ 3298abfc5808a4e34d6e03867af8bc440dee641886fTorne (Richard Coles) printf(#memd "=0x%08x%08x) => ", \ 330 mmx_trace.d[1], mmx_trace.d[0]); \ 331 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \ 332 #op " %1, %%mm0\n\t" \ 333 "movq %%mm0, %0" \ 334 : "=y" (memd) \ 335 : "y" (mems)); \ 336 mmx_trace = (memd); \ 337 printf(#memd "=0x%08x%08x\n", \ 338 mmx_trace.d[1], mmx_trace.d[0]); \ 339 } 340 341#else 342 343/* These macros are a lot simpler without the tracing... 344*/ 345 346#define mmx_i2r(op, imm, reg) \ 347 __asm__ __volatile__ (#op " %0, %%" #reg \ 348 : /* nothing */ \ 349 : "y" (imm) ) 350 351#define mmx_m2r(op, mem, reg) \ 352 __asm__ __volatile__ (#op " %0, %%" #reg \ 353 : /* nothing */ \ 354 : "m" (mem)) 355 356#define mmx_r2m(op, reg, mem) \ 357 __asm__ __volatile__ (#op " %%" #reg ", %0" \ 358 : "=m" (mem) \ 359 : /* nothing */ ) 360 361#define mmx_r2r(op, regs, regd) \ 362 __asm__ __volatile__ (#op " %" #regs ", %" #regd) 363 364#define mmx_m2m(op, mems, memd) \ 365 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \ 366 #op " %1, %%mm0\n\t" \ 367 "movq %%mm0, %0" \ 368 : "=y" (memd) \ 369 : "y" (mems)) 370 371#endif 372 373 374/* 1x64 MOVe Quadword 375 (this is both a load and a store... 376 in fact, it is the only way to store) 377*/ 378#define movq_m2r(var, reg) mmx_m2r(movq, var, reg) 379#define movq_r2m(reg, var) mmx_r2m(movq, reg, var) 380#define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd) 381#define movq(vars, vard) \ 382 __asm__ __volatile__ ("movq %1, %%mm0\n\t" \ 383 "movq %%mm0, %0" \ 384 : "=y" (vard) \ 385 : "y" (vars)) 386 387 388/* 1x32 MOVe Doubleword 389 (like movq, this is both load and store... 390 but is most useful for moving things between 391 mmx registers and ordinary registers) 392*/ 393#define movd_m2r(var, reg) mmx_m2r(movd, var, reg) 394#define movd_r2m(reg, var) mmx_r2m(movd, reg, var) 395#define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd) 396#define movd(vars, vard) \ 397 __asm__ __volatile__ ("movd %1, %%mm0\n\t" \ 398 "movd %%mm0, %0" \ 399 : "=y" (vard) \ 400 : "y" (vars)) 401 402 403/* 2x32, 4x16, and 8x8 Parallel ADDs 404*/ 405#define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg) 406#define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd) 407#define paddd(vars, vard) mmx_m2m(paddd, vars, vard) 408 409#define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg) 410#define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd) 411#define paddw(vars, vard) mmx_m2m(paddw, vars, vard) 412 413#define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg) 414#define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd) 415#define paddb(vars, vard) mmx_m2m(paddb, vars, vard) 416 417 418/* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic 419*/ 420#define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg) 421#define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd) 422#define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard) 423 424#define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg) 425#define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd) 426#define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard) 427 428 429/* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic 430*/ 431#define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg) 432#define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd) 433#define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard) 434 435#define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg) 436#define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd) 437#define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard) 438 439 440/* 2x32, 4x16, and 8x8 Parallel SUBs 441*/ 442#define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg) 443#define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd) 444#define psubd(vars, vard) mmx_m2m(psubd, vars, vard) 445 446#define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg) 447#define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd) 448#define psubw(vars, vard) mmx_m2m(psubw, vars, vard) 449 450#define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg) 451#define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd) 452#define psubb(vars, vard) mmx_m2m(psubb, vars, vard) 453 454 455/* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic 456*/ 457#define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg) 458#define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd) 459#define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard) 460 461#define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg) 462#define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd) 463#define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard) 464 465 466/* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic 467*/ 468#define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg) 469#define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd) 470#define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard) 471 472#define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg) 473#define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd) 474#define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard) 475 476 477/* 4x16 Parallel MULs giving Low 4x16 portions of results 478*/ 479#define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg) 480#define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd) 481#define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard) 482 483 484/* 4x16 Parallel MULs giving High 4x16 portions of results 485*/ 486#define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg) 487#define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd) 488#define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard) 489 490 491/* 4x16->2x32 Parallel Mul-ADD 492 (muls like pmullw, then adds adjacent 16-bit fields 493 in the multiply result to make the final 2x32 result) 494*/ 495#define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg) 496#define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd) 497#define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard) 498 499 500/* 1x64 bitwise AND 501*/ 502#ifdef BROKEN_PAND 503#define pand_m2r(var, reg) \ 504 { \ 505 mmx_m2r(pandn, (mmx_t) -1LL, reg); \ 506 mmx_m2r(pandn, var, reg); \ 507 } 508#define pand_r2r(regs, regd) \ 509 { \ 510 mmx_m2r(pandn, (mmx_t) -1LL, regd); \ 511 mmx_r2r(pandn, regs, regd) \ 512 } 513#define pand(vars, vard) \ 514 { \ 515 movq_m2r(vard, mm0); \ 516 mmx_m2r(pandn, (mmx_t) -1LL, mm0); \ 517 mmx_m2r(pandn, vars, mm0); \ 518 movq_r2m(mm0, vard); \ 519 } 520#else 521#define pand_m2r(var, reg) mmx_m2r(pand, var, reg) 522#define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd) 523#define pand(vars, vard) mmx_m2m(pand, vars, vard) 524#endif 525 526 527/* 1x64 bitwise AND with Not the destination 528*/ 529#define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg) 530#define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd) 531#define pandn(vars, vard) mmx_m2m(pandn, vars, vard) 532 533 534/* 1x64 bitwise OR 535*/ 536#define por_m2r(var, reg) mmx_m2r(por, var, reg) 537#define por_r2r(regs, regd) mmx_r2r(por, regs, regd) 538#define por(vars, vard) mmx_m2m(por, vars, vard) 539 540 541/* 1x64 bitwise eXclusive OR 542*/ 543#define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg) 544#define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd) 545#define pxor(vars, vard) mmx_m2m(pxor, vars, vard) 546 547 548/* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality 549 (resulting fields are either 0 or -1) 550*/ 551#define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg) 552#define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd) 553#define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard) 554 555#define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg) 556#define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd) 557#define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard) 558 559#define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg) 560#define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd) 561#define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard) 562 563 564/* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than 565 (resulting fields are either 0 or -1) 566*/ 567#define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg) 568#define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd) 569#define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard) 570 571#define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg) 572#define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd) 573#define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard) 574 575#define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg) 576#define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd) 577#define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard) 578 579 580/* 1x64, 2x32, and 4x16 Parallel Shift Left Logical 581*/ 582#define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg) 583#define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg) 584#define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd) 585#define psllq(vars, vard) mmx_m2m(psllq, vars, vard) 586 587#define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg) 588#define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg) 589#define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd) 590#define pslld(vars, vard) mmx_m2m(pslld, vars, vard) 591 592#define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg) 593#define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg) 594#define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd) 595#define psllw(vars, vard) mmx_m2m(psllw, vars, vard) 596 597 598/* 1x64, 2x32, and 4x16 Parallel Shift Right Logical 599*/ 600#define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg) 601#define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg) 602#define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd) 603#define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard) 604 605#define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg) 606#define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg) 607#define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd) 608#define psrld(vars, vard) mmx_m2m(psrld, vars, vard) 609 610#define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg) 611#define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg) 612#define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd) 613#define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard) 614 615 616/* 2x32 and 4x16 Parallel Shift Right Arithmetic 617*/ 618#define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg) 619#define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg) 620#define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd) 621#define psrad(vars, vard) mmx_m2m(psrad, vars, vard) 622 623#define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg) 624#define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg) 625#define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd) 626#define psraw(vars, vard) mmx_m2m(psraw, vars, vard) 627 628 629/* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate 630 (packs source and dest fields into dest in that order) 631*/ 632#define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg) 633#define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd) 634#define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard) 635 636#define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg) 637#define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd) 638#define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard) 639 640 641/* 4x16->8x8 PACK and Unsigned Saturate 642 (packs source and dest fields into dest in that order) 643*/ 644#define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg) 645#define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd) 646#define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard) 647 648 649/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low 650 (interleaves low half of dest with low half of source 651 as padding in each result field) 652*/ 653#define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg) 654#define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd) 655#define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard) 656 657#define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg) 658#define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd) 659#define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard) 660 661#define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg) 662#define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd) 663#define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard) 664 665 666/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High 667 (interleaves high half of dest with high half of source 668 as padding in each result field) 669*/ 670#define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg) 671#define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd) 672#define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard) 673 674#define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg) 675#define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd) 676#define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard) 677 678#define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg) 679#define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd) 680#define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard) 681 682 683/* Empty MMx State 684 (used to clean-up when going from mmx to float use 685 of the registers that are shared by both; note that 686 there is no float-to-mmx operation needed, because 687 only the float tag word info is corruptible) 688*/ 689#ifdef MMX_TRACE 690 691#define emms() \ 692 { \ 693 printf("emms()\n"); \ 694 __asm__ __volatile__ ("emms"); \ 695 } 696 697#else 698 699#define emms() __asm__ __volatile__ ("emms") 700 701#endif 702 703#endif 704 705