1/* -*- mode: C; c-basic-offset: 3; -*- */
2
3#include <stdio.h>    // fprintf
4#include <stdlib.h>   // exit
5#include "vtest.h"
6
7#define DEFOP(op,ukind) op, #op, ukind
8
9/* The opcodes appear in the same order here as in libvex_ir.h
10   That is not necessary but helpful when supporting a new architecture.
11*/
12static irop_t irops[] = {
13  { DEFOP(Iop_Add8,    UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
14  { DEFOP(Iop_Add16,   UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
15  { DEFOP(Iop_Add32,   UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
16  { DEFOP(Iop_Add64,   UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
17  { DEFOP(Iop_Sub8,    UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
18  { DEFOP(Iop_Sub16,   UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
19  { DEFOP(Iop_Sub32,   UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
20  { DEFOP(Iop_Sub64,   UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
21  { DEFOP(Iop_Mul8,    UNDEF_LEFT), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
22  { DEFOP(Iop_Mul16,   UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
23  { DEFOP(Iop_Mul32,   UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
24  { DEFOP(Iop_Mul64,   UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
25  { DEFOP(Iop_Or8,     UNDEF_OR),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
26  { DEFOP(Iop_Or16,    UNDEF_OR),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
27  { DEFOP(Iop_Or32,    UNDEF_OR),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
28  { DEFOP(Iop_Or64,    UNDEF_OR),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
29  { DEFOP(Iop_And8,    UNDEF_AND),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
30  { DEFOP(Iop_And16,   UNDEF_AND),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
31  { DEFOP(Iop_And32,   UNDEF_AND),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
32  { DEFOP(Iop_And64,   UNDEF_AND),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
33  { DEFOP(Iop_Xor8,    UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
34  { DEFOP(Iop_Xor16,   UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
35  { DEFOP(Iop_Xor32,   UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
36  { DEFOP(Iop_Xor64,   UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
37  { DEFOP(Iop_Shl8,    UNDEF_SHL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
38  { DEFOP(Iop_Shl16,   UNDEF_SHL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
39  { DEFOP(Iop_Shl32,   UNDEF_SHL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
40  { DEFOP(Iop_Shl64,   UNDEF_SHL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
41  { DEFOP(Iop_Shr8,    UNDEF_SHR),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
42  { DEFOP(Iop_Shr16,   UNDEF_SHR),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
43  { DEFOP(Iop_Shr32,   UNDEF_SHR),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
44  { DEFOP(Iop_Shr64,   UNDEF_SHR),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
45  { DEFOP(Iop_Sar8,    UNDEF_SAR),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
46  { DEFOP(Iop_Sar16,   UNDEF_SAR),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
47  { DEFOP(Iop_Sar32,   UNDEF_SAR),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
48  { DEFOP(Iop_Sar64,   UNDEF_SAR),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
49  { DEFOP(Iop_CmpEQ8,  UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
50  { DEFOP(Iop_CmpEQ16, UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
51  { DEFOP(Iop_CmpEQ32, UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
52  { DEFOP(Iop_CmpEQ64, UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
53  { DEFOP(Iop_CmpNE8,  UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
54  { DEFOP(Iop_CmpNE16, UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
55  { DEFOP(Iop_CmpNE32, UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
56  { DEFOP(Iop_CmpNE64, UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
57  { DEFOP(Iop_Not8,       UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
58  { DEFOP(Iop_Not16,      UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
59  { DEFOP(Iop_Not32,      UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
60  { DEFOP(Iop_Not64,      UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
61  { DEFOP(Iop_CasCmpEQ8,  UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
62  { DEFOP(Iop_CasCmpEQ16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
63  { DEFOP(Iop_CasCmpEQ32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
64  { DEFOP(Iop_CasCmpEQ64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
65
66  { DEFOP(Iop_CasCmpNE8,  UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
67  { DEFOP(Iop_CasCmpNE16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
68  { DEFOP(Iop_CasCmpNE32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
69  { DEFOP(Iop_CasCmpNE64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
70  { DEFOP(Iop_ExpCmpNE8,  UNDEF_UNKNOWN), }, // exact (expensive) equality
71  { DEFOP(Iop_ExpCmpNE16, UNDEF_UNKNOWN), }, // exact (expensive) equality
72  { DEFOP(Iop_ExpCmpNE32, UNDEF_UNKNOWN), }, // exact (expensive) equality
73  { DEFOP(Iop_ExpCmpNE64, UNDEF_UNKNOWN), }, // exact (expensive) equality
74  { DEFOP(Iop_MullS8,     UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
75  { DEFOP(Iop_MullS16,    UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
76  { DEFOP(Iop_MullS32,    UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
77  // s390 has signed multiplication of 64-bit values but the result
78  // is 64-bit (not 128-bit). So we cannot test this op standalone.
79  { DEFOP(Iop_MullS64,    UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
80  { DEFOP(Iop_MullU8,     UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
81  { DEFOP(Iop_MullU16,    UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
82  { DEFOP(Iop_MullU32,    UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1 }, // mips asserts
83  { DEFOP(Iop_MullU64,    UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
84  { DEFOP(Iop_Clz64,      UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts
85  { DEFOP(Iop_Clz32,      UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
86  { DEFOP(Iop_Ctz64,      UNDEF_ALL),  .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
87  { DEFOP(Iop_Ctz32,      UNDEF_ALL),  .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
88  { DEFOP(Iop_CmpLT32S,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
89  { DEFOP(Iop_CmpLT64S,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
90  { DEFOP(Iop_CmpLE32S,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
91  { DEFOP(Iop_CmpLE64S,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
92  { DEFOP(Iop_CmpLT32U,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
93  { DEFOP(Iop_CmpLT64U,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
94  { DEFOP(Iop_CmpLE32U,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
95  { DEFOP(Iop_CmpLE64U,   UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts
96  { DEFOP(Iop_CmpNEZ8,    UNDEF_ALL), },   // not supported by mc_translate
97  { DEFOP(Iop_CmpNEZ16,   UNDEF_ALL), },   // not supported by mc_translate
98  { DEFOP(Iop_CmpNEZ32,   UNDEF_ALL), },   // not supported by mc_translate
99  { DEFOP(Iop_CmpNEZ64,   UNDEF_ALL), },   // not supported by mc_translate
100  { DEFOP(Iop_CmpwNEZ32,  UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
101  { DEFOP(Iop_CmpwNEZ64,  UNDEF_ALL),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
102  { DEFOP(Iop_Left8,      UNDEF_UNKNOWN), },  // not supported by mc_translate
103  { DEFOP(Iop_Left16,     UNDEF_UNKNOWN), },  // not supported by mc_translate
104  { DEFOP(Iop_Left32,     UNDEF_UNKNOWN), },  // not supported by mc_translate
105  { DEFOP(Iop_Left64,     UNDEF_UNKNOWN), },  // not supported by mc_translate
106  { DEFOP(Iop_Max32U,     UNDEF_UNKNOWN), },  // not supported by mc_translate
107  { DEFOP(Iop_CmpORD32U,  UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
108  { DEFOP(Iop_CmpORD64U,  UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
109  { DEFOP(Iop_CmpORD32S,  UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
110  { DEFOP(Iop_CmpORD64S,  UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
111  { DEFOP(Iop_DivU32,     UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
112  { DEFOP(Iop_DivS32,     UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
113  { DEFOP(Iop_DivU64,     UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
114  { DEFOP(Iop_DivS64,     UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
115  { DEFOP(Iop_DivU64E,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
116  { DEFOP(Iop_DivS64E,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
117  { DEFOP(Iop_DivU32E,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
118  { DEFOP(Iop_DivS32E,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
119  // On s390 the DivMod operations always appear in a certain context
120  // So they cannot be tested in isolation on that platform.
121  { DEFOP(Iop_DivModU64to32,  UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
122  { DEFOP(Iop_DivModS64to32,  UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
123  { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
124  { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
125  { DEFOP(Iop_DivModS64to64,  UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
126  { DEFOP(Iop_8Uto16,    UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
127  { DEFOP(Iop_8Uto32,    UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
128  { DEFOP(Iop_8Uto64,    UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
129  { DEFOP(Iop_16Uto32,   UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
130  { DEFOP(Iop_16Uto64,   UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
131  { DEFOP(Iop_32Uto64,   UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
132  { DEFOP(Iop_8Sto16,    UNDEF_SEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
133  { DEFOP(Iop_8Sto32,    UNDEF_SEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
134  { DEFOP(Iop_8Sto64,    UNDEF_SEXT),   .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
135  { DEFOP(Iop_16Sto32,   UNDEF_SEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
136  { DEFOP(Iop_16Sto64,   UNDEF_SEXT),   .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
137  { DEFOP(Iop_32Sto64,   UNDEF_SEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
138  { DEFOP(Iop_64to8,     UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
139  { DEFOP(Iop_32to8,     UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
140  { DEFOP(Iop_64to16,    UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
141  { DEFOP(Iop_16to8,     UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
142  { DEFOP(Iop_16HIto8,   UNDEF_UPPER),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
143  { DEFOP(Iop_8HLto16,   UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },  // ppc isel
144  { DEFOP(Iop_32to16,    UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
145  { DEFOP(Iop_32HIto16,  UNDEF_UPPER),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
146  { DEFOP(Iop_16HLto32,  UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },  // ppc isel
147  { DEFOP(Iop_64to32,    UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
148  { DEFOP(Iop_64HIto32,  UNDEF_UPPER),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
149  { DEFOP(Iop_32HLto64,  UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
150  { DEFOP(Iop_128to64,   UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
151  { DEFOP(Iop_128HIto64, UNDEF_UPPER),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
152  { DEFOP(Iop_64HLto128, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
153  { DEFOP(Iop_Not1,      UNDEF_ALL),    .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
154  { DEFOP(Iop_32to1,     UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
155  { DEFOP(Iop_64to1,     UNDEF_TRUNC),  .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
156  { DEFOP(Iop_1Uto8,     UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
157  { DEFOP(Iop_1Uto32,    UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
158  { DEFOP(Iop_1Uto64,    UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
159  { DEFOP(Iop_1Sto8,     UNDEF_ALL),    .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
160  { DEFOP(Iop_1Sto16,    UNDEF_ALL), }, // not handled by mc_translate
161  { DEFOP(Iop_1Sto32,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
162  { DEFOP(Iop_1Sto64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
163  { DEFOP(Iop_AddF64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
164  { DEFOP(Iop_SubF64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
165  { DEFOP(Iop_MulF64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
166  { DEFOP(Iop_DivF64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
167  { DEFOP(Iop_AddF32,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
168  { DEFOP(Iop_SubF32,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
169  { DEFOP(Iop_MulF32,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
170  { DEFOP(Iop_DivF32,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
171  { DEFOP(Iop_AddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
172  { DEFOP(Iop_SubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
173  { DEFOP(Iop_MulF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
174  { DEFOP(Iop_DivF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
175  { DEFOP(Iop_NegF64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
176  { DEFOP(Iop_AbsF64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
177  { DEFOP(Iop_NegF32,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
178  { DEFOP(Iop_AbsF32,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
179  { DEFOP(Iop_SqrtF64,   UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
180  { DEFOP(Iop_SqrtF32,   UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
181  { DEFOP(Iop_CmpF64,    UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
182  { DEFOP(Iop_CmpF32,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
183  { DEFOP(Iop_CmpF128,   UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
184  { DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
185  { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
186  { DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
187  { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
188  { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
189  { DEFOP(Iop_I32StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
190  { DEFOP(Iop_I64StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
191  { DEFOP(Iop_I64UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // mips asserts
192  { DEFOP(Iop_I64UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
193  { DEFOP(Iop_I32UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
194  { DEFOP(Iop_I32UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
195  { DEFOP(Iop_F32toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
196  { DEFOP(Iop_F32toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
197  { DEFOP(Iop_F32toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
198  { DEFOP(Iop_F32toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
199  { DEFOP(Iop_I32StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
200  { DEFOP(Iop_I64StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
201  { DEFOP(Iop_F32toF64,  UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
202  { DEFOP(Iop_F64toF32,  UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
203  { DEFOP(Iop_ReinterpF64asI64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
204  { DEFOP(Iop_ReinterpI64asF64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
205  { DEFOP(Iop_ReinterpF32asI32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
206  // ppc requires this op to show up in a specific context. So it cannot be
207  // tested standalone on that platform.
208  { DEFOP(Iop_ReinterpI32asF32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
209  { DEFOP(Iop_F64HLtoF128, UNDEF_CONCAT),    .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
210  { DEFOP(Iop_F128HItoF64, UNDEF_UPPER),     .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
211  { DEFOP(Iop_F128LOtoF64, UNDEF_TRUNC), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
212  { DEFOP(Iop_AddF128,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
213  { DEFOP(Iop_SubF128,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
214  { DEFOP(Iop_MulF128,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
215  { DEFOP(Iop_DivF128,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
216  { DEFOP(Iop_NegF128,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
217  { DEFOP(Iop_AbsF128,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
218  { DEFOP(Iop_SqrtF128,      UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
219  { DEFOP(Iop_I32StoF128,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
220  { DEFOP(Iop_I64StoF128,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
221  { DEFOP(Iop_I32UtoF128,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
222  { DEFOP(Iop_I64UtoF128,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
223  { DEFOP(Iop_F32toF128,     UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
224  { DEFOP(Iop_F64toF128,     UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
225  { DEFOP(Iop_F128toI32S,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
226  { DEFOP(Iop_F128toI64S,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
227  { DEFOP(Iop_F128toI32U,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
228  { DEFOP(Iop_F128toI64U,    UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
229  { DEFOP(Iop_F128toF64,     UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
230  { DEFOP(Iop_F128toF32,     UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
231  { DEFOP(Iop_AtanF64,       UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
232  { DEFOP(Iop_Yl2xF64,       UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
233  { DEFOP(Iop_Yl2xp1F64,     UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
234  { DEFOP(Iop_PRemF64,       UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
235  { DEFOP(Iop_PRemC3210F64,  UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
236  { DEFOP(Iop_PRem1F64,      UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
237  { DEFOP(Iop_PRem1C3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
238  { DEFOP(Iop_ScaleF64,      UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
239  { DEFOP(Iop_SinF64,        UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
240  { DEFOP(Iop_CosF64,        UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
241  { DEFOP(Iop_TanF64,        UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
242  { DEFOP(Iop_2xm1F64,       UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
243  { DEFOP(Iop_RoundF64toInt, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
244  { DEFOP(Iop_RoundF32toInt, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
245  { DEFOP(Iop_MAddF32,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
246  { DEFOP(Iop_MSubF32,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
247  { DEFOP(Iop_MAddF64,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
248  { DEFOP(Iop_MSubF64,       UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
249  { DEFOP(Iop_MAddF64r32,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
250  { DEFOP(Iop_MSubF64r32,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
251  { DEFOP(Iop_Est5FRSqrt,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
252  { DEFOP(Iop_RoundF64toF64_NEAREST, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
253  { DEFOP(Iop_RoundF64toF64_NegINF,  UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
254  { DEFOP(Iop_RoundF64toF64_PosINF,  UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
255  { DEFOP(Iop_RoundF64toF64_ZERO,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
256  { DEFOP(Iop_TruncF64asF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
257  { DEFOP(Iop_RoundF64toF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
258
259  /* ------------------ 32-bit SIMD Integer ------------------ */
260  { DEFOP(Iop_QAdd32S, UNDEF_UNKNOWN), },
261  { DEFOP(Iop_QSub32S, UNDEF_UNKNOWN), },
262  { DEFOP(Iop_Add16x2, UNDEF_UNKNOWN), },
263  { DEFOP(Iop_Sub16x2, UNDEF_UNKNOWN), },
264  { DEFOP(Iop_QAdd16Sx2, UNDEF_UNKNOWN), },
265  { DEFOP(Iop_QAdd16Ux2, UNDEF_UNKNOWN), },
266  { DEFOP(Iop_QSub16Sx2, UNDEF_UNKNOWN), },
267  { DEFOP(Iop_QSub16Ux2, UNDEF_UNKNOWN), },
268  { DEFOP(Iop_HAdd16Ux2, UNDEF_UNKNOWN), },
269  { DEFOP(Iop_HAdd16Sx2, UNDEF_UNKNOWN), },
270  { DEFOP(Iop_HSub16Ux2, UNDEF_UNKNOWN), },
271  { DEFOP(Iop_HSub16Sx2, UNDEF_UNKNOWN), },
272  { DEFOP(Iop_Add8x4, UNDEF_UNKNOWN), },
273  { DEFOP(Iop_Sub8x4, UNDEF_UNKNOWN), },
274  { DEFOP(Iop_QAdd8Sx4, UNDEF_UNKNOWN), },
275  { DEFOP(Iop_QAdd8Ux4, UNDEF_UNKNOWN), },
276  { DEFOP(Iop_QSub8Sx4, UNDEF_UNKNOWN), },
277  { DEFOP(Iop_QSub8Ux4, UNDEF_UNKNOWN), },
278  { DEFOP(Iop_HAdd8Ux4, UNDEF_UNKNOWN), },
279  { DEFOP(Iop_HAdd8Sx4, UNDEF_UNKNOWN), },
280  { DEFOP(Iop_HSub8Ux4, UNDEF_UNKNOWN), },
281  { DEFOP(Iop_HSub8Sx4, UNDEF_UNKNOWN), },
282  { DEFOP(Iop_Sad8Ux4, UNDEF_UNKNOWN), },
283  { DEFOP(Iop_CmpNEZ16x2, UNDEF_UNKNOWN), },
284  { DEFOP(Iop_CmpNEZ8x4, UNDEF_UNKNOWN), },
285  /* ------------------ 64-bit SIMD FP ------------------------ */
286  { DEFOP(Iop_I32UtoFx2, UNDEF_UNKNOWN), },
287  { DEFOP(Iop_I32StoFx2, UNDEF_UNKNOWN), },
288  { DEFOP(Iop_FtoI32Ux2_RZ, UNDEF_UNKNOWN), },
289  { DEFOP(Iop_FtoI32Sx2_RZ, UNDEF_UNKNOWN), },
290  { DEFOP(Iop_F32ToFixed32Ux2_RZ, UNDEF_UNKNOWN), },
291  { DEFOP(Iop_F32ToFixed32Sx2_RZ, UNDEF_UNKNOWN), },
292  { DEFOP(Iop_Fixed32UToF32x2_RN, UNDEF_UNKNOWN), },
293  { DEFOP(Iop_Fixed32SToF32x2_RN, UNDEF_UNKNOWN), },
294  { DEFOP(Iop_Max32Fx2, UNDEF_UNKNOWN), },
295  { DEFOP(Iop_Min32Fx2, UNDEF_UNKNOWN), },
296  { DEFOP(Iop_PwMax32Fx2, UNDEF_UNKNOWN), },
297  { DEFOP(Iop_PwMin32Fx2, UNDEF_UNKNOWN), },
298  { DEFOP(Iop_CmpEQ32Fx2, UNDEF_UNKNOWN), },
299  { DEFOP(Iop_CmpGT32Fx2, UNDEF_UNKNOWN), },
300  { DEFOP(Iop_CmpGE32Fx2, UNDEF_UNKNOWN), },
301  { DEFOP(Iop_Recip32Fx2, UNDEF_UNKNOWN), },
302  { DEFOP(Iop_Recps32Fx2, UNDEF_UNKNOWN), },
303  { DEFOP(Iop_Rsqrte32Fx2, UNDEF_UNKNOWN), },
304  { DEFOP(Iop_Rsqrts32Fx2, UNDEF_UNKNOWN), },
305  { DEFOP(Iop_Neg32Fx2, UNDEF_UNKNOWN), },
306  { DEFOP(Iop_Abs32Fx2, UNDEF_UNKNOWN), },
307  /* ------------------ 64-bit SIMD Integer. ------------------ */
308  { DEFOP(Iop_CmpNEZ8x8, UNDEF_UNKNOWN), },
309  { DEFOP(Iop_CmpNEZ16x4, UNDEF_UNKNOWN), },
310  { DEFOP(Iop_CmpNEZ32x2, UNDEF_UNKNOWN), },
311  { DEFOP(Iop_Add8x8, UNDEF_UNKNOWN), },
312  { DEFOP(Iop_Add16x4, UNDEF_UNKNOWN), },
313  { DEFOP(Iop_Add32x2, UNDEF_UNKNOWN), },
314  { DEFOP(Iop_QAdd8Ux8, UNDEF_UNKNOWN), },
315  { DEFOP(Iop_QAdd16Ux4, UNDEF_UNKNOWN), },
316  { DEFOP(Iop_QAdd32Ux2, UNDEF_UNKNOWN), },
317  { DEFOP(Iop_QAdd64Ux1, UNDEF_UNKNOWN), },
318  { DEFOP(Iop_QAdd8Sx8, UNDEF_UNKNOWN), },
319  { DEFOP(Iop_QAdd16Sx4, UNDEF_UNKNOWN), },
320  { DEFOP(Iop_QAdd32Sx2, UNDEF_UNKNOWN), },
321  { DEFOP(Iop_QAdd64Sx1, UNDEF_UNKNOWN), },
322  { DEFOP(Iop_PwAdd8x8, UNDEF_UNKNOWN), },
323  { DEFOP(Iop_PwAdd16x4, UNDEF_UNKNOWN), },
324  { DEFOP(Iop_PwAdd32x2, UNDEF_UNKNOWN), },
325  { DEFOP(Iop_PwMax8Sx8, UNDEF_UNKNOWN), },
326  { DEFOP(Iop_PwMax16Sx4, UNDEF_UNKNOWN), },
327  { DEFOP(Iop_PwMax32Sx2, UNDEF_UNKNOWN), },
328  { DEFOP(Iop_PwMax8Ux8, UNDEF_UNKNOWN), },
329  { DEFOP(Iop_PwMax16Ux4, UNDEF_UNKNOWN), },
330  { DEFOP(Iop_PwMax32Ux2, UNDEF_UNKNOWN), },
331  { DEFOP(Iop_PwMin8Sx8, UNDEF_UNKNOWN), },
332  { DEFOP(Iop_PwMin16Sx4, UNDEF_UNKNOWN), },
333  { DEFOP(Iop_PwMin32Sx2, UNDEF_UNKNOWN), },
334  { DEFOP(Iop_PwMin8Ux8, UNDEF_UNKNOWN), },
335  { DEFOP(Iop_PwMin16Ux4, UNDEF_UNKNOWN), },
336  { DEFOP(Iop_PwMin32Ux2, UNDEF_UNKNOWN), },
337  { DEFOP(Iop_PwAddL8Ux8, UNDEF_UNKNOWN), },
338  { DEFOP(Iop_PwAddL16Ux4, UNDEF_UNKNOWN), },
339  { DEFOP(Iop_PwAddL32Ux2, UNDEF_UNKNOWN), },
340  { DEFOP(Iop_PwAddL8Sx8, UNDEF_UNKNOWN), },
341  { DEFOP(Iop_PwAddL16Sx4, UNDEF_UNKNOWN), },
342  { DEFOP(Iop_PwAddL32Sx2, UNDEF_UNKNOWN), },
343  { DEFOP(Iop_Sub8x8, UNDEF_UNKNOWN), },
344  { DEFOP(Iop_Sub16x4, UNDEF_UNKNOWN), },
345  { DEFOP(Iop_Sub32x2, UNDEF_UNKNOWN), },
346  { DEFOP(Iop_QSub8Ux8, UNDEF_UNKNOWN), },
347  { DEFOP(Iop_QSub16Ux4, UNDEF_UNKNOWN), },
348  { DEFOP(Iop_QSub32Ux2, UNDEF_UNKNOWN), },
349  { DEFOP(Iop_QSub64Ux1, UNDEF_UNKNOWN), },
350  { DEFOP(Iop_QSub8Sx8, UNDEF_UNKNOWN), },
351  { DEFOP(Iop_QSub16Sx4, UNDEF_UNKNOWN), },
352  { DEFOP(Iop_QSub32Sx2, UNDEF_UNKNOWN), },
353  { DEFOP(Iop_QSub64Sx1, UNDEF_UNKNOWN), },
354  { DEFOP(Iop_Abs8x8, UNDEF_UNKNOWN), },
355  { DEFOP(Iop_Abs16x4, UNDEF_UNKNOWN), },
356  { DEFOP(Iop_Abs32x2, UNDEF_UNKNOWN), },
357  { DEFOP(Iop_Mul8x8, UNDEF_UNKNOWN), },
358  { DEFOP(Iop_Mul16x4, UNDEF_UNKNOWN), },
359  { DEFOP(Iop_Mul32x2, UNDEF_UNKNOWN), },
360  { DEFOP(Iop_Mul32Fx2, UNDEF_UNKNOWN), },
361  { DEFOP(Iop_MulHi16Ux4, UNDEF_UNKNOWN), },
362  { DEFOP(Iop_MulHi16Sx4, UNDEF_UNKNOWN), },
363  { DEFOP(Iop_PolynomialMul8x8, UNDEF_UNKNOWN), },
364  { DEFOP(Iop_QDMulHi16Sx4, UNDEF_UNKNOWN), },
365  { DEFOP(Iop_QDMulHi32Sx2, UNDEF_UNKNOWN), },
366  { DEFOP(Iop_QRDMulHi16Sx4, UNDEF_UNKNOWN), },
367  { DEFOP(Iop_QRDMulHi32Sx2, UNDEF_UNKNOWN), },
368  { DEFOP(Iop_Avg8Ux8, UNDEF_UNKNOWN), },
369  { DEFOP(Iop_Avg16Ux4, UNDEF_UNKNOWN), },
370  { DEFOP(Iop_Max8Sx8, UNDEF_UNKNOWN), },
371  { DEFOP(Iop_Max16Sx4, UNDEF_UNKNOWN), },
372  { DEFOP(Iop_Max32Sx2, UNDEF_UNKNOWN), },
373  { DEFOP(Iop_Max8Ux8, UNDEF_UNKNOWN), },
374  { DEFOP(Iop_Max16Ux4, UNDEF_UNKNOWN), },
375  { DEFOP(Iop_Max32Ux2, UNDEF_UNKNOWN), },
376  { DEFOP(Iop_Min8Sx8, UNDEF_UNKNOWN), },
377  { DEFOP(Iop_Min16Sx4, UNDEF_UNKNOWN), },
378  { DEFOP(Iop_Min32Sx2, UNDEF_UNKNOWN), },
379  { DEFOP(Iop_Min8Ux8, UNDEF_UNKNOWN), },
380  { DEFOP(Iop_Min16Ux4, UNDEF_UNKNOWN), },
381  { DEFOP(Iop_Min32Ux2, UNDEF_UNKNOWN), },
382  { DEFOP(Iop_CmpEQ8x8, UNDEF_UNKNOWN), },
383  { DEFOP(Iop_CmpEQ16x4, UNDEF_UNKNOWN), },
384  { DEFOP(Iop_CmpEQ32x2, UNDEF_UNKNOWN), },
385  { DEFOP(Iop_CmpGT8Ux8, UNDEF_UNKNOWN), },
386  { DEFOP(Iop_CmpGT16Ux4, UNDEF_UNKNOWN), },
387  { DEFOP(Iop_CmpGT32Ux2, UNDEF_UNKNOWN), },
388  { DEFOP(Iop_CmpGT8Sx8, UNDEF_UNKNOWN), },
389  { DEFOP(Iop_CmpGT16Sx4, UNDEF_UNKNOWN), },
390  { DEFOP(Iop_CmpGT32Sx2, UNDEF_UNKNOWN), },
391  { DEFOP(Iop_Cnt8x8, UNDEF_UNKNOWN), },
392  { DEFOP(Iop_Clz8Sx8, UNDEF_UNKNOWN), },
393  { DEFOP(Iop_Clz16Sx4, UNDEF_UNKNOWN), },
394  { DEFOP(Iop_Clz32Sx2, UNDEF_UNKNOWN), },
395  { DEFOP(Iop_Cls8Sx8, UNDEF_UNKNOWN), },
396  { DEFOP(Iop_Cls16Sx4, UNDEF_UNKNOWN), },
397  { DEFOP(Iop_Cls32Sx2, UNDEF_UNKNOWN), },
398  { DEFOP(Iop_Shl8x8, UNDEF_UNKNOWN), },
399  { DEFOP(Iop_Shl16x4, UNDEF_UNKNOWN), },
400  { DEFOP(Iop_Shl32x2, UNDEF_UNKNOWN), },
401  { DEFOP(Iop_Shr8x8, UNDEF_UNKNOWN), },
402  { DEFOP(Iop_Shr16x4, UNDEF_UNKNOWN), },
403  { DEFOP(Iop_Shr32x2, UNDEF_UNKNOWN), },
404  { DEFOP(Iop_Sar8x8, UNDEF_UNKNOWN), },
405  { DEFOP(Iop_Sar16x4, UNDEF_UNKNOWN), },
406  { DEFOP(Iop_Sar32x2, UNDEF_UNKNOWN), },
407  { DEFOP(Iop_Sal8x8, UNDEF_UNKNOWN), },
408  { DEFOP(Iop_Sal16x4, UNDEF_UNKNOWN), },
409  { DEFOP(Iop_Sal32x2, UNDEF_UNKNOWN), },
410  { DEFOP(Iop_Sal64x1, UNDEF_UNKNOWN), },
411  { DEFOP(Iop_ShlN8x8, UNDEF_UNKNOWN), },
412  { DEFOP(Iop_ShlN16x4, UNDEF_UNKNOWN), },
413  { DEFOP(Iop_ShlN32x2, UNDEF_UNKNOWN), },
414  { DEFOP(Iop_ShrN8x8, UNDEF_UNKNOWN), },
415  { DEFOP(Iop_ShrN16x4, UNDEF_UNKNOWN), },
416  { DEFOP(Iop_ShrN32x2, UNDEF_UNKNOWN), },
417  { DEFOP(Iop_SarN8x8, UNDEF_UNKNOWN), },
418  { DEFOP(Iop_SarN16x4, UNDEF_UNKNOWN), },
419  { DEFOP(Iop_SarN32x2, UNDEF_UNKNOWN), },
420  { DEFOP(Iop_QShl8x8, UNDEF_UNKNOWN), },
421  { DEFOP(Iop_QShl16x4, UNDEF_UNKNOWN), },
422  { DEFOP(Iop_QShl32x2, UNDEF_UNKNOWN), },
423  { DEFOP(Iop_QShl64x1, UNDEF_UNKNOWN), },
424  { DEFOP(Iop_QSal8x8, UNDEF_UNKNOWN), },
425  { DEFOP(Iop_QSal16x4, UNDEF_UNKNOWN), },
426  { DEFOP(Iop_QSal32x2, UNDEF_UNKNOWN), },
427  { DEFOP(Iop_QSal64x1, UNDEF_UNKNOWN), },
428  { DEFOP(Iop_QShlN8Sx8, UNDEF_UNKNOWN), },
429  { DEFOP(Iop_QShlN16Sx4, UNDEF_UNKNOWN), },
430  { DEFOP(Iop_QShlN32Sx2, UNDEF_UNKNOWN), },
431  { DEFOP(Iop_QShlN64Sx1, UNDEF_UNKNOWN), },
432  { DEFOP(Iop_QShlN8x8, UNDEF_UNKNOWN), },
433  { DEFOP(Iop_QShlN16x4, UNDEF_UNKNOWN), },
434  { DEFOP(Iop_QShlN32x2, UNDEF_UNKNOWN), },
435  { DEFOP(Iop_QShlN64x1, UNDEF_UNKNOWN), },
436  { DEFOP(Iop_QSalN8x8, UNDEF_UNKNOWN), },
437  { DEFOP(Iop_QSalN16x4, UNDEF_UNKNOWN), },
438  { DEFOP(Iop_QSalN32x2, UNDEF_UNKNOWN), },
439  { DEFOP(Iop_QSalN64x1, UNDEF_UNKNOWN), },
440  { DEFOP(Iop_QNarrowBin16Sto8Ux8, UNDEF_UNKNOWN), },
441  { DEFOP(Iop_QNarrowBin16Sto8Sx8, UNDEF_UNKNOWN), },
442  { DEFOP(Iop_QNarrowBin32Sto16Sx4, UNDEF_UNKNOWN), },
443  { DEFOP(Iop_NarrowBin16to8x8, UNDEF_UNKNOWN), },
444  { DEFOP(Iop_NarrowBin32to16x4, UNDEF_UNKNOWN), },
445  { DEFOP(Iop_InterleaveHI8x8, UNDEF_UNKNOWN), },
446  { DEFOP(Iop_InterleaveHI16x4, UNDEF_UNKNOWN), },
447  { DEFOP(Iop_InterleaveHI32x2, UNDEF_UNKNOWN), },
448  { DEFOP(Iop_InterleaveLO8x8, UNDEF_UNKNOWN), },
449  { DEFOP(Iop_InterleaveLO16x4, UNDEF_UNKNOWN), },
450  { DEFOP(Iop_InterleaveLO32x2, UNDEF_UNKNOWN), },
451  { DEFOP(Iop_InterleaveOddLanes8x8, UNDEF_UNKNOWN), },
452  { DEFOP(Iop_InterleaveEvenLanes8x8, UNDEF_UNKNOWN), },
453  { DEFOP(Iop_InterleaveOddLanes16x4, UNDEF_UNKNOWN), },
454  { DEFOP(Iop_InterleaveEvenLanes16x4, UNDEF_UNKNOWN), },
455  { DEFOP(Iop_CatOddLanes8x8, UNDEF_UNKNOWN), },
456  { DEFOP(Iop_CatOddLanes16x4, UNDEF_UNKNOWN), },
457  { DEFOP(Iop_CatEvenLanes8x8, UNDEF_UNKNOWN), },
458  { DEFOP(Iop_CatEvenLanes16x4, UNDEF_UNKNOWN), },
459  { DEFOP(Iop_GetElem8x8, UNDEF_UNKNOWN), },
460  { DEFOP(Iop_GetElem16x4, UNDEF_UNKNOWN), },
461  { DEFOP(Iop_GetElem32x2, UNDEF_UNKNOWN), },
462  { DEFOP(Iop_SetElem8x8, UNDEF_UNKNOWN), },
463  { DEFOP(Iop_SetElem16x4, UNDEF_UNKNOWN), },
464  { DEFOP(Iop_SetElem32x2, UNDEF_UNKNOWN), },
465  { DEFOP(Iop_Dup8x8, UNDEF_UNKNOWN), },
466  { DEFOP(Iop_Dup16x4, UNDEF_UNKNOWN), },
467  { DEFOP(Iop_Dup32x2, UNDEF_UNKNOWN), },
468  { DEFOP(Iop_Extract64, UNDEF_UNKNOWN), },
469  { DEFOP(Iop_Reverse16_8x8, UNDEF_UNKNOWN), },
470  { DEFOP(Iop_Reverse32_8x8, UNDEF_UNKNOWN), },
471  { DEFOP(Iop_Reverse32_16x4, UNDEF_UNKNOWN), },
472  { DEFOP(Iop_Reverse64_8x8, UNDEF_UNKNOWN), },
473  { DEFOP(Iop_Reverse64_16x4, UNDEF_UNKNOWN), },
474  { DEFOP(Iop_Reverse64_32x2, UNDEF_UNKNOWN), },
475  { DEFOP(Iop_Perm8x8, UNDEF_UNKNOWN), },
476  { DEFOP(Iop_GetMSBs8x8, UNDEF_UNKNOWN), },
477  { DEFOP(Iop_Recip32x2, UNDEF_UNKNOWN), },
478  { DEFOP(Iop_Rsqrte32x2, UNDEF_UNKNOWN), },
479  /* ------------------ Decimal Floating Point ------------------ */
480  { DEFOP(Iop_AddD64,                UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
481  { DEFOP(Iop_SubD64,                UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
482  { DEFOP(Iop_MulD64,                UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
483  { DEFOP(Iop_DivD64,                UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
484  { DEFOP(Iop_AddD128,               UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
485  { DEFOP(Iop_SubD128,               UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
486  { DEFOP(Iop_MulD128,               UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
487  { DEFOP(Iop_DivD128,               UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
488  { DEFOP(Iop_ShlD64,                UNDEF_ALL),  .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
489  { DEFOP(Iop_ShrD64,                UNDEF_ALL),  .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
490  { DEFOP(Iop_ShlD128,               UNDEF_ALL),  .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
491  { DEFOP(Iop_ShrD128,               UNDEF_ALL),  .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
492  { DEFOP(Iop_D32toD64,              UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
493  { DEFOP(Iop_D64toD128,             UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
494  { DEFOP(Iop_I32StoD128,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
495  { DEFOP(Iop_I32UtoD128,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
496  { DEFOP(Iop_I64StoD128,            UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
497  { DEFOP(Iop_I64UtoD128,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
498  { DEFOP(Iop_D64toD32,              UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
499  { DEFOP(Iop_D128toD64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
500  { DEFOP(Iop_I32StoD64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
501  { DEFOP(Iop_I32UtoD64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
502  { DEFOP(Iop_I64StoD64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
503  { DEFOP(Iop_I64UtoD64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
504  { DEFOP(Iop_D64toI32S,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
505  { DEFOP(Iop_D64toI32U,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
506  { DEFOP(Iop_D64toI64S,             UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
507  { DEFOP(Iop_D64toI64U,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
508  { DEFOP(Iop_D128toI64S,            UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
509  { DEFOP(Iop_D128toI64U,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
510  { DEFOP(Iop_D128toI32S,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
511  { DEFOP(Iop_D128toI32U,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
512  { DEFOP(Iop_F32toD32,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
513  { DEFOP(Iop_F32toD64,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
514  { DEFOP(Iop_F32toD128,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
515  { DEFOP(Iop_F64toD32,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
516  { DEFOP(Iop_F64toD64,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
517  { DEFOP(Iop_F64toD128,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
518  { DEFOP(Iop_F128toD32,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
519  { DEFOP(Iop_F128toD64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
520  { DEFOP(Iop_F128toD128,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
521  { DEFOP(Iop_D32toF32,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
522  { DEFOP(Iop_D32toF64,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
523  { DEFOP(Iop_D32toF128,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
524  { DEFOP(Iop_D64toF32,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
525  { DEFOP(Iop_D64toF64,              UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
526  { DEFOP(Iop_D64toF128,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
527  { DEFOP(Iop_D128toF32,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
528  { DEFOP(Iop_D128toF64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
529  { DEFOP(Iop_D128toF128,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
530  { DEFOP(Iop_RoundD64toInt,         UNDEF_ALL),  .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
531  { DEFOP(Iop_RoundD128toInt,        UNDEF_ALL),  .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
532  { DEFOP(Iop_CmpD64,                UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
533  { DEFOP(Iop_CmpD128,               UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
534  { DEFOP(Iop_CmpExpD64,             UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
535  { DEFOP(Iop_CmpExpD128,            UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
536  { DEFOP(Iop_QuantizeD64,           UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
537  { DEFOP(Iop_QuantizeD128,          UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
538  { DEFOP(Iop_SignificanceRoundD64,  UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
539  { DEFOP(Iop_SignificanceRoundD128, UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
540  { DEFOP(Iop_ExtractExpD64,         UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
541  { DEFOP(Iop_ExtractExpD128,        UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
542  { DEFOP(Iop_ExtractSigD64,         UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
543  { DEFOP(Iop_ExtractSigD128,        UNDEF_ALL),  .s390x = 1, .ppc64 = 0, .ppc32 = 0 },
544  { DEFOP(Iop_InsertExpD64,          UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
545  { DEFOP(Iop_InsertExpD128,         UNDEF_ALL),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
546  { DEFOP(Iop_D64HLtoD128,           UNDEF_CONCAT), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
547  { DEFOP(Iop_D128HItoD64,           UNDEF_UPPER),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
548  { DEFOP(Iop_D128LOtoD64,           UNDEF_TRUNC),  .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
549  { DEFOP(Iop_DPBtoBCD,              UNDEF_ALL),    .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
550  { DEFOP(Iop_BCDtoDPB,              UNDEF_ALL),    .s390x = 0, .ppc64 = 1, .ppc32 = 1 },
551  { DEFOP(Iop_ReinterpI64asD64,      UNDEF_SAME),   .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
552  { DEFOP(Iop_ReinterpD64asI64,      UNDEF_SAME),   .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
553  /* ------------------ 128-bit SIMD FP. ------------------ */
554  { DEFOP(Iop_Add32Fx4, UNDEF_UNKNOWN), },
555  { DEFOP(Iop_Sub32Fx4, UNDEF_UNKNOWN), },
556  { DEFOP(Iop_Mul32Fx4, UNDEF_UNKNOWN), },
557  { DEFOP(Iop_Div32Fx4, UNDEF_UNKNOWN), },
558  { DEFOP(Iop_Max32Fx4, UNDEF_UNKNOWN), },
559  { DEFOP(Iop_Min32Fx4, UNDEF_UNKNOWN), },
560  { DEFOP(Iop_Add32Fx2, UNDEF_UNKNOWN), },
561  { DEFOP(Iop_Sub32Fx2, UNDEF_UNKNOWN), },
562  { DEFOP(Iop_CmpEQ32Fx4, UNDEF_UNKNOWN), },
563  { DEFOP(Iop_CmpLT32Fx4, UNDEF_UNKNOWN), },
564  { DEFOP(Iop_CmpLE32Fx4, UNDEF_UNKNOWN), },
565  { DEFOP(Iop_CmpUN32Fx4, UNDEF_UNKNOWN), },
566  { DEFOP(Iop_CmpGT32Fx4, UNDEF_UNKNOWN), },
567  { DEFOP(Iop_CmpGE32Fx4, UNDEF_UNKNOWN), },
568  { DEFOP(Iop_PwMax32Fx4, UNDEF_UNKNOWN), },
569  { DEFOP(Iop_PwMin32Fx4, UNDEF_UNKNOWN), },
570  { DEFOP(Iop_Abs32Fx4, UNDEF_UNKNOWN), },
571  { DEFOP(Iop_Sqrt32Fx4, UNDEF_UNKNOWN), },
572  { DEFOP(Iop_RSqrt32Fx4, UNDEF_UNKNOWN), },
573  { DEFOP(Iop_Neg32Fx4, UNDEF_UNKNOWN), },
574  { DEFOP(Iop_Recip32Fx4, UNDEF_UNKNOWN), },
575  { DEFOP(Iop_Recps32Fx4, UNDEF_UNKNOWN), },
576  { DEFOP(Iop_Rsqrte32Fx4, UNDEF_UNKNOWN), },
577  { DEFOP(Iop_Rsqrts32Fx4, UNDEF_UNKNOWN), },
578  { DEFOP(Iop_I32UtoFx4, UNDEF_UNKNOWN), },
579  { DEFOP(Iop_I32StoFx4, UNDEF_UNKNOWN), },
580  { DEFOP(Iop_FtoI32Ux4_RZ, UNDEF_UNKNOWN), },
581  { DEFOP(Iop_FtoI32Sx4_RZ, UNDEF_UNKNOWN), },
582  { DEFOP(Iop_QFtoI32Ux4_RZ, UNDEF_UNKNOWN), },
583  { DEFOP(Iop_QFtoI32Sx4_RZ, UNDEF_UNKNOWN), },
584  { DEFOP(Iop_RoundF32x4_RM, UNDEF_UNKNOWN), },
585  { DEFOP(Iop_RoundF32x4_RP, UNDEF_UNKNOWN), },
586  { DEFOP(Iop_RoundF32x4_RN, UNDEF_UNKNOWN), },
587  { DEFOP(Iop_RoundF32x4_RZ, UNDEF_UNKNOWN), },
588  { DEFOP(Iop_F32ToFixed32Ux4_RZ, UNDEF_UNKNOWN), },
589  { DEFOP(Iop_F32ToFixed32Sx4_RZ, UNDEF_UNKNOWN), },
590  { DEFOP(Iop_Fixed32UToF32x4_RN, UNDEF_UNKNOWN), },
591  { DEFOP(Iop_Fixed32SToF32x4_RN, UNDEF_UNKNOWN), },
592  { DEFOP(Iop_F32toF16x4, UNDEF_UNKNOWN), },
593  { DEFOP(Iop_F16toF32x4, UNDEF_UNKNOWN), },
594  { DEFOP(Iop_Add32F0x4, UNDEF_UNKNOWN), },
595  { DEFOP(Iop_Sub32F0x4, UNDEF_UNKNOWN), },
596  { DEFOP(Iop_Mul32F0x4, UNDEF_UNKNOWN), },
597  { DEFOP(Iop_Div32F0x4, UNDEF_UNKNOWN), },
598  { DEFOP(Iop_Max32F0x4, UNDEF_UNKNOWN), },
599  { DEFOP(Iop_Min32F0x4, UNDEF_UNKNOWN), },
600  { DEFOP(Iop_CmpEQ32F0x4, UNDEF_UNKNOWN), },
601  { DEFOP(Iop_CmpLT32F0x4, UNDEF_UNKNOWN), },
602  { DEFOP(Iop_CmpLE32F0x4, UNDEF_UNKNOWN), },
603  { DEFOP(Iop_CmpUN32F0x4, UNDEF_UNKNOWN), },
604  { DEFOP(Iop_Recip32F0x4, UNDEF_UNKNOWN), },
605  { DEFOP(Iop_Sqrt32F0x4, UNDEF_UNKNOWN), },
606  { DEFOP(Iop_RSqrt32F0x4, UNDEF_UNKNOWN), },
607  { DEFOP(Iop_Add64Fx2, UNDEF_UNKNOWN), },
608  { DEFOP(Iop_Sub64Fx2, UNDEF_UNKNOWN), },
609  { DEFOP(Iop_Mul64Fx2, UNDEF_UNKNOWN), },
610  { DEFOP(Iop_Div64Fx2, UNDEF_UNKNOWN), },
611  { DEFOP(Iop_Max64Fx2, UNDEF_UNKNOWN), },
612  { DEFOP(Iop_Min64Fx2, UNDEF_UNKNOWN), },
613  { DEFOP(Iop_CmpEQ64Fx2, UNDEF_UNKNOWN), },
614  { DEFOP(Iop_CmpLT64Fx2, UNDEF_UNKNOWN), },
615  { DEFOP(Iop_CmpLE64Fx2, UNDEF_UNKNOWN), },
616  { DEFOP(Iop_CmpUN64Fx2, UNDEF_UNKNOWN), },
617  { DEFOP(Iop_Abs64Fx2, UNDEF_UNKNOWN), },
618  { DEFOP(Iop_Sqrt64Fx2, UNDEF_UNKNOWN), },
619  { DEFOP(Iop_RSqrt64Fx2, UNDEF_UNKNOWN), },
620  { DEFOP(Iop_Neg64Fx2, UNDEF_UNKNOWN), },
621  { DEFOP(Iop_Recip64Fx2, UNDEF_UNKNOWN), },
622  { DEFOP(Iop_Add64F0x2, UNDEF_UNKNOWN), },
623  { DEFOP(Iop_Sub64F0x2, UNDEF_UNKNOWN), },
624  { DEFOP(Iop_Mul64F0x2, UNDEF_UNKNOWN), },
625  { DEFOP(Iop_Div64F0x2, UNDEF_UNKNOWN), },
626  { DEFOP(Iop_Max64F0x2, UNDEF_UNKNOWN), },
627  { DEFOP(Iop_Min64F0x2, UNDEF_UNKNOWN), },
628  { DEFOP(Iop_CmpEQ64F0x2, UNDEF_UNKNOWN), },
629  { DEFOP(Iop_CmpLT64F0x2, UNDEF_UNKNOWN), },
630  { DEFOP(Iop_CmpLE64F0x2, UNDEF_UNKNOWN), },
631  { DEFOP(Iop_CmpUN64F0x2, UNDEF_UNKNOWN), },
632  { DEFOP(Iop_Recip64F0x2, UNDEF_UNKNOWN), },
633  { DEFOP(Iop_Sqrt64F0x2, UNDEF_UNKNOWN), },
634  { DEFOP(Iop_RSqrt64F0x2, UNDEF_UNKNOWN), },
635  { DEFOP(Iop_V128to64, UNDEF_UNKNOWN), },
636  { DEFOP(Iop_V128HIto64, UNDEF_UNKNOWN), },
637  { DEFOP(Iop_64HLtoV128, UNDEF_UNKNOWN), },
638  { DEFOP(Iop_64UtoV128, UNDEF_UNKNOWN), },
639  { DEFOP(Iop_SetV128lo64, UNDEF_UNKNOWN), },
640  { DEFOP(Iop_ZeroHI64ofV128, UNDEF_UNKNOWN) },
641  { DEFOP(Iop_ZeroHI96ofV128, UNDEF_UNKNOWN) },
642  { DEFOP(Iop_ZeroHI112ofV128, UNDEF_UNKNOWN) },
643  { DEFOP(Iop_ZeroHI120ofV128, UNDEF_UNKNOWN) },
644  { DEFOP(Iop_32UtoV128, UNDEF_UNKNOWN), },
645  { DEFOP(Iop_V128to32, UNDEF_UNKNOWN), },
646  { DEFOP(Iop_SetV128lo32, UNDEF_UNKNOWN), },
647  /* ------------------ 128-bit SIMD Integer. ------------------ */
648  { DEFOP(Iop_NotV128, UNDEF_UNKNOWN), },
649  { DEFOP(Iop_AndV128, UNDEF_UNKNOWN), },
650  { DEFOP(Iop_OrV128, UNDEF_UNKNOWN), },
651  { DEFOP(Iop_XorV128, UNDEF_UNKNOWN), },
652  { DEFOP(Iop_ShlV128, UNDEF_UNKNOWN), },
653  { DEFOP(Iop_ShrV128, UNDEF_UNKNOWN), },
654  { DEFOP(Iop_CmpNEZ8x16, UNDEF_UNKNOWN), },
655  { DEFOP(Iop_CmpNEZ16x8, UNDEF_UNKNOWN), },
656  { DEFOP(Iop_CmpNEZ32x4, UNDEF_UNKNOWN), },
657  { DEFOP(Iop_CmpNEZ64x2, UNDEF_UNKNOWN), },
658  { DEFOP(Iop_Add8x16, UNDEF_UNKNOWN), },
659  { DEFOP(Iop_Add16x8, UNDEF_UNKNOWN), },
660  { DEFOP(Iop_Add32x4, UNDEF_UNKNOWN), },
661  { DEFOP(Iop_Add64x2, UNDEF_UNKNOWN), },
662  { DEFOP(Iop_QAdd8Ux16, UNDEF_UNKNOWN), },
663  { DEFOP(Iop_QAdd16Ux8, UNDEF_UNKNOWN), },
664  { DEFOP(Iop_QAdd32Ux4, UNDEF_UNKNOWN), },
665  { DEFOP(Iop_QAdd64Ux2, UNDEF_UNKNOWN), },
666  { DEFOP(Iop_QAdd8Sx16, UNDEF_UNKNOWN), },
667  { DEFOP(Iop_QAdd16Sx8, UNDEF_UNKNOWN), },
668  { DEFOP(Iop_QAdd32Sx4, UNDEF_UNKNOWN), },
669  { DEFOP(Iop_QAdd64Sx2, UNDEF_UNKNOWN), },
670  { DEFOP(Iop_Sub8x16, UNDEF_UNKNOWN), },
671  { DEFOP(Iop_Sub16x8, UNDEF_UNKNOWN), },
672  { DEFOP(Iop_Sub32x4, UNDEF_UNKNOWN), },
673  { DEFOP(Iop_Sub64x2, UNDEF_UNKNOWN), },
674  { DEFOP(Iop_QSub8Ux16, UNDEF_UNKNOWN), },
675  { DEFOP(Iop_QSub16Ux8, UNDEF_UNKNOWN), },
676  { DEFOP(Iop_QSub32Ux4, UNDEF_UNKNOWN), },
677  { DEFOP(Iop_QSub64Ux2, UNDEF_UNKNOWN), },
678  { DEFOP(Iop_QSub8Sx16, UNDEF_UNKNOWN), },
679  { DEFOP(Iop_QSub16Sx8, UNDEF_UNKNOWN), },
680  { DEFOP(Iop_QSub32Sx4, UNDEF_UNKNOWN), },
681  { DEFOP(Iop_QSub64Sx2, UNDEF_UNKNOWN), },
682  { DEFOP(Iop_Mul8x16, UNDEF_UNKNOWN), },
683  { DEFOP(Iop_Mul16x8, UNDEF_UNKNOWN), },
684  { DEFOP(Iop_Mul32x4, UNDEF_UNKNOWN), },
685  { DEFOP(Iop_MulHi16Ux8, UNDEF_UNKNOWN), },
686  { DEFOP(Iop_MulHi32Ux4, UNDEF_UNKNOWN), },
687  { DEFOP(Iop_MulHi16Sx8, UNDEF_UNKNOWN), },
688  { DEFOP(Iop_MulHi32Sx4, UNDEF_UNKNOWN), },
689  { DEFOP(Iop_MullEven8Ux16, UNDEF_UNKNOWN), },
690  { DEFOP(Iop_MullEven16Ux8, UNDEF_UNKNOWN), },
691  { DEFOP(Iop_MullEven32Ux4, UNDEF_UNKNOWN), },
692  { DEFOP(Iop_MullEven8Sx16, UNDEF_UNKNOWN), },
693  { DEFOP(Iop_MullEven16Sx8, UNDEF_UNKNOWN), },
694  { DEFOP(Iop_MullEven32Sx4, UNDEF_UNKNOWN), },
695  { DEFOP(Iop_Mull8Ux8, UNDEF_UNKNOWN), },
696  { DEFOP(Iop_Mull8Sx8, UNDEF_UNKNOWN), },
697  { DEFOP(Iop_Mull16Ux4, UNDEF_UNKNOWN), },
698  { DEFOP(Iop_Mull16Sx4, UNDEF_UNKNOWN), },
699  { DEFOP(Iop_Mull32Ux2, UNDEF_UNKNOWN), },
700  { DEFOP(Iop_Mull32Sx2, UNDEF_UNKNOWN), },
701  { DEFOP(Iop_QDMulHi16Sx8, UNDEF_UNKNOWN), },
702  { DEFOP(Iop_QDMulHi32Sx4, UNDEF_UNKNOWN), },
703  { DEFOP(Iop_QRDMulHi16Sx8, UNDEF_UNKNOWN), },
704  { DEFOP(Iop_QRDMulHi32Sx4, UNDEF_UNKNOWN), },
705  { DEFOP(Iop_QDMulLong16Sx4, UNDEF_UNKNOWN), },
706  { DEFOP(Iop_QDMulLong32Sx2, UNDEF_UNKNOWN), },
707  { DEFOP(Iop_PolynomialMul8x16, UNDEF_UNKNOWN), },
708  { DEFOP(Iop_PolynomialMull8x8, UNDEF_UNKNOWN), },
709  { DEFOP(Iop_PwAdd8x16, UNDEF_UNKNOWN), },
710  { DEFOP(Iop_PwAdd16x8, UNDEF_UNKNOWN), },
711  { DEFOP(Iop_PwAdd32x4, UNDEF_UNKNOWN), },
712  { DEFOP(Iop_PwAdd32Fx2, UNDEF_UNKNOWN), },
713  { DEFOP(Iop_PwAddL8Ux16, UNDEF_UNKNOWN), },
714  { DEFOP(Iop_PwAddL16Ux8, UNDEF_UNKNOWN), },
715  { DEFOP(Iop_PwAddL32Ux4, UNDEF_UNKNOWN), },
716  { DEFOP(Iop_PwAddL8Sx16, UNDEF_UNKNOWN), },
717  { DEFOP(Iop_PwAddL16Sx8, UNDEF_UNKNOWN), },
718  { DEFOP(Iop_PwAddL32Sx4, UNDEF_UNKNOWN), },
719  { DEFOP(Iop_Abs8x16, UNDEF_UNKNOWN), },
720  { DEFOP(Iop_Abs16x8, UNDEF_UNKNOWN), },
721  { DEFOP(Iop_Abs32x4, UNDEF_UNKNOWN), },
722  { DEFOP(Iop_Avg8Ux16, UNDEF_UNKNOWN), },
723  { DEFOP(Iop_Avg16Ux8, UNDEF_UNKNOWN), },
724  { DEFOP(Iop_Avg32Ux4, UNDEF_UNKNOWN), },
725  { DEFOP(Iop_Avg8Sx16, UNDEF_UNKNOWN), },
726  { DEFOP(Iop_Avg16Sx8, UNDEF_UNKNOWN), },
727  { DEFOP(Iop_Avg32Sx4, UNDEF_UNKNOWN), },
728  { DEFOP(Iop_Max8Sx16, UNDEF_UNKNOWN), },
729  { DEFOP(Iop_Max16Sx8, UNDEF_UNKNOWN), },
730  { DEFOP(Iop_Max32Sx4, UNDEF_UNKNOWN), },
731  { DEFOP(Iop_Max64Sx2, UNDEF_UNKNOWN), },
732  { DEFOP(Iop_Max8Ux16, UNDEF_UNKNOWN), },
733  { DEFOP(Iop_Max16Ux8, UNDEF_UNKNOWN), },
734  { DEFOP(Iop_Max32Ux4, UNDEF_UNKNOWN), },
735  { DEFOP(Iop_Max64Ux2, UNDEF_UNKNOWN), },
736  { DEFOP(Iop_Min8Sx16, UNDEF_UNKNOWN), },
737  { DEFOP(Iop_Min16Sx8, UNDEF_UNKNOWN), },
738  { DEFOP(Iop_Min32Sx4, UNDEF_UNKNOWN), },
739  { DEFOP(Iop_Min64Sx2, UNDEF_UNKNOWN), },
740  { DEFOP(Iop_Min8Ux16, UNDEF_UNKNOWN), },
741  { DEFOP(Iop_Min16Ux8, UNDEF_UNKNOWN), },
742  { DEFOP(Iop_Min32Ux4, UNDEF_UNKNOWN), },
743  { DEFOP(Iop_Min64Ux2, UNDEF_UNKNOWN), },
744  { DEFOP(Iop_CmpEQ8x16, UNDEF_UNKNOWN), },
745  { DEFOP(Iop_CmpEQ16x8, UNDEF_UNKNOWN), },
746  { DEFOP(Iop_CmpEQ32x4, UNDEF_UNKNOWN), },
747  { DEFOP(Iop_CmpEQ64x2, UNDEF_UNKNOWN), },
748  { DEFOP(Iop_CmpGT8Sx16, UNDEF_UNKNOWN), },
749  { DEFOP(Iop_CmpGT16Sx8, UNDEF_UNKNOWN), },
750  { DEFOP(Iop_CmpGT32Sx4, UNDEF_UNKNOWN), },
751  { DEFOP(Iop_CmpGT64Sx2, UNDEF_UNKNOWN), },
752  { DEFOP(Iop_CmpGT8Ux16, UNDEF_UNKNOWN), },
753  { DEFOP(Iop_CmpGT16Ux8, UNDEF_UNKNOWN), },
754  { DEFOP(Iop_CmpGT32Ux4, UNDEF_UNKNOWN), },
755  { DEFOP(Iop_CmpGT64Ux2, UNDEF_UNKNOWN), },
756  { DEFOP(Iop_Cnt8x16, UNDEF_UNKNOWN), },
757  { DEFOP(Iop_Clz8Sx16, UNDEF_UNKNOWN), },
758  { DEFOP(Iop_Clz16Sx8, UNDEF_UNKNOWN), },
759  { DEFOP(Iop_Clz32Sx4, UNDEF_UNKNOWN), },
760  { DEFOP(Iop_Clz64x2, UNDEF_UNKNOWN), },
761  { DEFOP(Iop_Cls8Sx16, UNDEF_UNKNOWN), },
762  { DEFOP(Iop_Cls16Sx8, UNDEF_UNKNOWN), },
763  { DEFOP(Iop_Cls32Sx4, UNDEF_UNKNOWN), },
764  { DEFOP(Iop_ShlN8x16, UNDEF_UNKNOWN), },
765  { DEFOP(Iop_ShlN16x8, UNDEF_UNKNOWN), },
766  { DEFOP(Iop_ShlN32x4, UNDEF_UNKNOWN), },
767  { DEFOP(Iop_ShlN64x2, UNDEF_UNKNOWN), },
768  { DEFOP(Iop_ShrN8x16, UNDEF_UNKNOWN), },
769  { DEFOP(Iop_ShrN16x8, UNDEF_UNKNOWN), },
770  { DEFOP(Iop_ShrN32x4, UNDEF_UNKNOWN), },
771  { DEFOP(Iop_ShrN64x2, UNDEF_UNKNOWN), },
772  { DEFOP(Iop_SarN8x16, UNDEF_UNKNOWN), },
773  { DEFOP(Iop_SarN16x8, UNDEF_UNKNOWN), },
774  { DEFOP(Iop_SarN32x4, UNDEF_UNKNOWN), },
775  { DEFOP(Iop_SarN64x2, UNDEF_UNKNOWN), },
776  { DEFOP(Iop_Shl8x16, UNDEF_UNKNOWN), },
777  { DEFOP(Iop_Shl16x8, UNDEF_UNKNOWN), },
778  { DEFOP(Iop_Shl32x4, UNDEF_UNKNOWN), },
779  { DEFOP(Iop_Shl64x2, UNDEF_UNKNOWN), },
780  { DEFOP(Iop_Shr8x16, UNDEF_UNKNOWN), },
781  { DEFOP(Iop_Shr16x8, UNDEF_UNKNOWN), },
782  { DEFOP(Iop_Shr32x4, UNDEF_UNKNOWN), },
783  { DEFOP(Iop_Shr64x2, UNDEF_UNKNOWN), },
784  { DEFOP(Iop_Sar8x16, UNDEF_UNKNOWN), },
785  { DEFOP(Iop_Sar16x8, UNDEF_UNKNOWN), },
786  { DEFOP(Iop_Sar32x4, UNDEF_UNKNOWN), },
787  { DEFOP(Iop_Sar64x2, UNDEF_UNKNOWN), },
788  { DEFOP(Iop_Sal8x16, UNDEF_UNKNOWN), },
789  { DEFOP(Iop_Sal16x8, UNDEF_UNKNOWN), },
790  { DEFOP(Iop_Sal32x4, UNDEF_UNKNOWN), },
791  { DEFOP(Iop_Sal64x2, UNDEF_UNKNOWN), },
792  { DEFOP(Iop_Rol8x16, UNDEF_UNKNOWN), },
793  { DEFOP(Iop_Rol16x8, UNDEF_UNKNOWN), },
794  { DEFOP(Iop_Rol32x4, UNDEF_UNKNOWN), },
795  { DEFOP(Iop_Rol64x2, UNDEF_UNKNOWN), },
796  { DEFOP(Iop_QShl8x16, UNDEF_UNKNOWN), },
797  { DEFOP(Iop_QShl16x8, UNDEF_UNKNOWN), },
798  { DEFOP(Iop_QShl32x4, UNDEF_UNKNOWN), },
799  { DEFOP(Iop_QShl64x2, UNDEF_UNKNOWN), },
800  { DEFOP(Iop_QSal8x16, UNDEF_UNKNOWN), },
801  { DEFOP(Iop_QSal16x8, UNDEF_UNKNOWN), },
802  { DEFOP(Iop_QSal32x4, UNDEF_UNKNOWN), },
803  { DEFOP(Iop_QSal64x2, UNDEF_UNKNOWN), },
804  { DEFOP(Iop_QShlN8Sx16, UNDEF_UNKNOWN), },
805  { DEFOP(Iop_QShlN16Sx8, UNDEF_UNKNOWN), },
806  { DEFOP(Iop_QShlN32Sx4, UNDEF_UNKNOWN), },
807  { DEFOP(Iop_QShlN64Sx2, UNDEF_UNKNOWN), },
808  { DEFOP(Iop_QShlN8x16, UNDEF_UNKNOWN), },
809  { DEFOP(Iop_QShlN16x8, UNDEF_UNKNOWN), },
810  { DEFOP(Iop_QShlN32x4, UNDEF_UNKNOWN), },
811  { DEFOP(Iop_QShlN64x2, UNDEF_UNKNOWN), },
812  { DEFOP(Iop_QSalN8x16, UNDEF_UNKNOWN), },
813  { DEFOP(Iop_QSalN16x8, UNDEF_UNKNOWN), },
814  { DEFOP(Iop_QSalN32x4, UNDEF_UNKNOWN), },
815  { DEFOP(Iop_QSalN64x2, UNDEF_UNKNOWN), },
816  { DEFOP(Iop_QNarrowBin16Sto8Ux16, UNDEF_UNKNOWN), },
817  { DEFOP(Iop_QNarrowBin32Sto16Ux8, UNDEF_UNKNOWN), },
818  { DEFOP(Iop_QNarrowBin16Sto8Sx16, UNDEF_UNKNOWN), },
819  { DEFOP(Iop_QNarrowBin32Sto16Sx8, UNDEF_UNKNOWN), },
820  { DEFOP(Iop_QNarrowBin16Uto8Ux16, UNDEF_UNKNOWN), },
821  { DEFOP(Iop_QNarrowBin32Uto16Ux8, UNDEF_UNKNOWN), },
822  { DEFOP(Iop_NarrowBin16to8x16, UNDEF_UNKNOWN), },
823  { DEFOP(Iop_NarrowBin32to16x8, UNDEF_UNKNOWN), },
824  { DEFOP(Iop_NarrowBin64to32x4, UNDEF_UNKNOWN), },
825  { DEFOP(Iop_NarrowUn16to8x8, UNDEF_UNKNOWN), },
826  { DEFOP(Iop_NarrowUn32to16x4, UNDEF_UNKNOWN), },
827  { DEFOP(Iop_NarrowUn64to32x2, UNDEF_UNKNOWN), },
828  { DEFOP(Iop_QNarrowUn16Sto8Sx8, UNDEF_UNKNOWN), },
829  { DEFOP(Iop_QNarrowUn32Sto16Sx4, UNDEF_UNKNOWN), },
830  { DEFOP(Iop_QNarrowUn64Sto32Sx2, UNDEF_UNKNOWN), },
831  { DEFOP(Iop_QNarrowBin64Sto32Sx4, UNDEF_UNKNOWN), },
832  { DEFOP(Iop_QNarrowUn16Sto8Ux8, UNDEF_UNKNOWN), },
833  { DEFOP(Iop_QNarrowUn32Sto16Ux4, UNDEF_UNKNOWN), },
834  { DEFOP(Iop_QNarrowUn64Sto32Ux2, UNDEF_UNKNOWN), },
835  { DEFOP(Iop_QNarrowBin64Uto32Ux4, UNDEF_UNKNOWN), },
836  { DEFOP(Iop_QNarrowUn16Uto8Ux8, UNDEF_UNKNOWN), },
837  { DEFOP(Iop_QNarrowUn32Uto16Ux4, UNDEF_UNKNOWN), },
838  { DEFOP(Iop_QNarrowUn64Uto32Ux2, UNDEF_UNKNOWN), },
839  { DEFOP(Iop_Widen8Uto16x8, UNDEF_UNKNOWN), },
840  { DEFOP(Iop_Widen16Uto32x4, UNDEF_UNKNOWN), },
841  { DEFOP(Iop_Widen32Uto64x2, UNDEF_UNKNOWN), },
842  { DEFOP(Iop_Widen8Sto16x8, UNDEF_UNKNOWN), },
843  { DEFOP(Iop_Widen16Sto32x4, UNDEF_UNKNOWN), },
844  { DEFOP(Iop_Widen32Sto64x2, UNDEF_UNKNOWN), },
845  { DEFOP(Iop_InterleaveHI8x16, UNDEF_UNKNOWN), },
846  { DEFOP(Iop_InterleaveHI16x8, UNDEF_UNKNOWN), },
847  { DEFOP(Iop_InterleaveHI32x4, UNDEF_UNKNOWN), },
848  { DEFOP(Iop_InterleaveHI64x2, UNDEF_UNKNOWN), },
849  { DEFOP(Iop_InterleaveLO8x16, UNDEF_UNKNOWN), },
850  { DEFOP(Iop_InterleaveLO16x8, UNDEF_UNKNOWN), },
851  { DEFOP(Iop_InterleaveLO32x4, UNDEF_UNKNOWN), },
852  { DEFOP(Iop_InterleaveLO64x2, UNDEF_UNKNOWN), },
853  { DEFOP(Iop_InterleaveOddLanes8x16, UNDEF_UNKNOWN), },
854  { DEFOP(Iop_InterleaveEvenLanes8x16, UNDEF_UNKNOWN), },
855  { DEFOP(Iop_InterleaveOddLanes16x8, UNDEF_UNKNOWN), },
856  { DEFOP(Iop_InterleaveEvenLanes16x8, UNDEF_UNKNOWN), },
857  { DEFOP(Iop_InterleaveOddLanes32x4, UNDEF_UNKNOWN), },
858  { DEFOP(Iop_InterleaveEvenLanes32x4, UNDEF_UNKNOWN), },
859  { DEFOP(Iop_CatOddLanes8x16, UNDEF_UNKNOWN), },
860  { DEFOP(Iop_CatOddLanes16x8, UNDEF_UNKNOWN), },
861  { DEFOP(Iop_CatOddLanes32x4, UNDEF_UNKNOWN), },
862  { DEFOP(Iop_CatEvenLanes8x16, UNDEF_UNKNOWN), },
863  { DEFOP(Iop_CatEvenLanes16x8, UNDEF_UNKNOWN), },
864  { DEFOP(Iop_CatEvenLanes32x4, UNDEF_UNKNOWN), },
865  { DEFOP(Iop_GetElem8x16, UNDEF_UNKNOWN), },
866  { DEFOP(Iop_GetElem16x8, UNDEF_UNKNOWN), },
867  { DEFOP(Iop_GetElem32x4, UNDEF_UNKNOWN), },
868  { DEFOP(Iop_GetElem64x2, UNDEF_UNKNOWN), },
869  { DEFOP(Iop_Dup8x16, UNDEF_UNKNOWN), },
870  { DEFOP(Iop_Dup16x8, UNDEF_UNKNOWN), },
871  { DEFOP(Iop_Dup32x4, UNDEF_UNKNOWN), },
872  { DEFOP(Iop_ExtractV128, UNDEF_UNKNOWN), },
873  { DEFOP(Iop_Reverse16_8x16, UNDEF_UNKNOWN), },
874  { DEFOP(Iop_Reverse32_8x16, UNDEF_UNKNOWN), },
875  { DEFOP(Iop_Reverse32_16x8, UNDEF_UNKNOWN), },
876  { DEFOP(Iop_Reverse64_8x16, UNDEF_UNKNOWN), },
877  { DEFOP(Iop_Reverse64_16x8, UNDEF_UNKNOWN), },
878  { DEFOP(Iop_Reverse64_32x4, UNDEF_UNKNOWN), },
879  { DEFOP(Iop_Perm8x16, UNDEF_UNKNOWN), },
880  { DEFOP(Iop_Perm32x4, UNDEF_UNKNOWN), },
881  { DEFOP(Iop_GetMSBs8x16, UNDEF_UNKNOWN), },
882  { DEFOP(Iop_Recip32x4, UNDEF_UNKNOWN), },
883  { DEFOP(Iop_Rsqrte32x4, UNDEF_UNKNOWN), },
884  /* ------------------ 256-bit SIMD Integer. ------------------ */
885  { DEFOP(Iop_V256to64_0, UNDEF_UNKNOWN), },
886  { DEFOP(Iop_V256to64_1, UNDEF_UNKNOWN), },
887  { DEFOP(Iop_V256to64_2, UNDEF_UNKNOWN), },
888  { DEFOP(Iop_V256to64_3, UNDEF_UNKNOWN), },
889  { DEFOP(Iop_64x4toV256, UNDEF_UNKNOWN), },
890  { DEFOP(Iop_V256toV128_0, UNDEF_UNKNOWN), },
891  { DEFOP(Iop_V256toV128_1, UNDEF_UNKNOWN), },
892  { DEFOP(Iop_V128HLtoV256, UNDEF_UNKNOWN), },
893  { DEFOP(Iop_AndV256, UNDEF_UNKNOWN), },
894  { DEFOP(Iop_OrV256,  UNDEF_UNKNOWN), },
895  { DEFOP(Iop_XorV256, UNDEF_UNKNOWN), },
896  { DEFOP(Iop_NotV256, UNDEF_UNKNOWN), },
897  /* --------------- MISC (vector integer cmp != 0) -------------*/
898  { DEFOP(Iop_CmpNEZ8x32, UNDEF_UNKNOWN), },
899  { DEFOP(Iop_CmpNEZ16x16, UNDEF_UNKNOWN), },
900  { DEFOP(Iop_CmpNEZ32x8, UNDEF_UNKNOWN), },
901  { DEFOP(Iop_CmpNEZ64x4, UNDEF_UNKNOWN), },
902  { DEFOP(Iop_Add8x32, UNDEF_UNKNOWN), },
903  { DEFOP(Iop_Add16x16, UNDEF_UNKNOWN), },
904  { DEFOP(Iop_Add32x8, UNDEF_UNKNOWN), },
905  { DEFOP(Iop_Add64x4, UNDEF_UNKNOWN), },
906  { DEFOP(Iop_Sub8x32, UNDEF_UNKNOWN), },
907  { DEFOP(Iop_Sub16x16, UNDEF_UNKNOWN), },
908  { DEFOP(Iop_Sub32x8, UNDEF_UNKNOWN), },
909  { DEFOP(Iop_Sub64x4, UNDEF_UNKNOWN), },
910  { DEFOP(Iop_CmpEQ8x32, UNDEF_UNKNOWN), },
911  { DEFOP(Iop_CmpEQ16x16, UNDEF_UNKNOWN), },
912  { DEFOP(Iop_CmpEQ32x8, UNDEF_UNKNOWN), },
913  { DEFOP(Iop_CmpEQ64x4, UNDEF_UNKNOWN), },
914  { DEFOP(Iop_CmpGT8Sx32, UNDEF_UNKNOWN), },
915  { DEFOP(Iop_CmpGT16Sx16, UNDEF_UNKNOWN), },
916  { DEFOP(Iop_CmpGT32Sx8, UNDEF_UNKNOWN), },
917  { DEFOP(Iop_CmpGT64Sx4, UNDEF_UNKNOWN), },
918  { DEFOP(Iop_ShlN16x16, UNDEF_UNKNOWN), },
919  { DEFOP(Iop_ShlN32x8, UNDEF_UNKNOWN), },
920  { DEFOP(Iop_ShlN64x4, UNDEF_UNKNOWN), },
921  { DEFOP(Iop_ShrN16x16, UNDEF_UNKNOWN), },
922  { DEFOP(Iop_ShrN32x8, UNDEF_UNKNOWN), },
923  { DEFOP(Iop_ShrN64x4, UNDEF_UNKNOWN), },
924  { DEFOP(Iop_SarN16x16, UNDEF_UNKNOWN), },
925  { DEFOP(Iop_SarN32x8, UNDEF_UNKNOWN), },
926  { DEFOP(Iop_Max8Sx32, UNDEF_UNKNOWN), },
927  { DEFOP(Iop_Max16Sx16, UNDEF_UNKNOWN), },
928  { DEFOP(Iop_Max32Sx8, UNDEF_UNKNOWN), },
929  { DEFOP(Iop_Max8Ux32, UNDEF_UNKNOWN), },
930  { DEFOP(Iop_Max16Ux16, UNDEF_UNKNOWN), },
931  { DEFOP(Iop_Max32Ux8, UNDEF_UNKNOWN), },
932  { DEFOP(Iop_Min8Sx32, UNDEF_UNKNOWN), },
933  { DEFOP(Iop_Min16Sx16, UNDEF_UNKNOWN), },
934  { DEFOP(Iop_Min32Sx8, UNDEF_UNKNOWN), },
935  { DEFOP(Iop_Min8Ux32, UNDEF_UNKNOWN), },
936  { DEFOP(Iop_Min16Ux16, UNDEF_UNKNOWN), },
937  { DEFOP(Iop_Min32Ux8, UNDEF_UNKNOWN), },
938  { DEFOP(Iop_Mul16x16, UNDEF_UNKNOWN), },
939  { DEFOP(Iop_Mul32x8, UNDEF_UNKNOWN), },
940  { DEFOP(Iop_MulHi16Ux16, UNDEF_UNKNOWN), },
941  { DEFOP(Iop_MulHi16Sx16, UNDEF_UNKNOWN), },
942  { DEFOP(Iop_QAdd8Ux32, UNDEF_UNKNOWN), },
943  { DEFOP(Iop_QAdd16Ux16, UNDEF_UNKNOWN), },
944  { DEFOP(Iop_QAdd8Sx32, UNDEF_UNKNOWN), },
945  { DEFOP(Iop_QAdd16Sx16, UNDEF_UNKNOWN), },
946  { DEFOP(Iop_QSub8Ux32, UNDEF_UNKNOWN), },
947  { DEFOP(Iop_QSub16Ux16, UNDEF_UNKNOWN), },
948  { DEFOP(Iop_QSub8Sx32, UNDEF_UNKNOWN), },
949  { DEFOP(Iop_QSub16Sx16, UNDEF_UNKNOWN), },
950  { DEFOP(Iop_Avg8Ux32, UNDEF_UNKNOWN), },
951  { DEFOP(Iop_Avg16Ux16, UNDEF_UNKNOWN), },
952  { DEFOP(Iop_Perm32x8, UNDEF_UNKNOWN), },
953  /* ------------------ 256-bit SIMD FP. ------------------ */
954  { DEFOP(Iop_Add64Fx4, UNDEF_UNKNOWN), },
955  { DEFOP(Iop_Sub64Fx4, UNDEF_UNKNOWN), },
956  { DEFOP(Iop_Mul64Fx4, UNDEF_UNKNOWN), },
957  { DEFOP(Iop_Div64Fx4, UNDEF_UNKNOWN), },
958  { DEFOP(Iop_Add32Fx8, UNDEF_UNKNOWN), },
959  { DEFOP(Iop_Sub32Fx8, UNDEF_UNKNOWN), },
960  { DEFOP(Iop_Mul32Fx8, UNDEF_UNKNOWN), },
961  { DEFOP(Iop_Div32Fx8, UNDEF_UNKNOWN), },
962  { DEFOP(Iop_Sqrt32Fx8, UNDEF_UNKNOWN), },
963  { DEFOP(Iop_Sqrt64Fx4, UNDEF_UNKNOWN), },
964  { DEFOP(Iop_RSqrt32Fx8, UNDEF_UNKNOWN), },
965  { DEFOP(Iop_Recip32Fx8, UNDEF_UNKNOWN), },
966  { DEFOP(Iop_Max32Fx8, UNDEF_UNKNOWN), },
967  { DEFOP(Iop_Min32Fx8, UNDEF_UNKNOWN), },
968  { DEFOP(Iop_Max64Fx4, UNDEF_UNKNOWN), },
969  { DEFOP(Iop_Min64Fx4, UNDEF_UNKNOWN), },
970  { DEFOP(Iop_BCDAdd, UNDEF_UNKNOWN), },
971  { DEFOP(Iop_BCDSub, UNDEF_UNKNOWN), },
972  { DEFOP(Iop_PolynomialMulAdd8x16, UNDEF_UNKNOWN), },
973  { DEFOP(Iop_PolynomialMulAdd16x8, UNDEF_UNKNOWN), },
974  { DEFOP(Iop_PolynomialMulAdd32x4, UNDEF_UNKNOWN), },
975  { DEFOP(Iop_PolynomialMulAdd64x2, UNDEF_UNKNOWN), },
976  { DEFOP(Iop_CipherV128,   UNDEF_UNKNOWN), },
977  { DEFOP(Iop_CipherLV128,  UNDEF_UNKNOWN), },
978  { DEFOP(Iop_CipherSV128,  UNDEF_UNKNOWN), },
979  { DEFOP(Iop_NCipherV128,  UNDEF_UNKNOWN), },
980  { DEFOP(Iop_NCipherLV128, UNDEF_UNKNOWN), },
981  { DEFOP(Iop_SHA512, UNDEF_UNKNOWN), },
982  { DEFOP(Iop_SHA256, UNDEF_UNKNOWN), },
983  { DEFOP(Iop_PwBitMtxXpose64x2, UNDEF_UNKNOWN), },
984};
985
986
987/* Return a descriptor for OP, iff it exists and it is implemented
988   for the current architecture. */
989irop_t *
990get_irop(IROp op)
991{
992   unsigned i;
993
994   for (i = 0; i < sizeof irops / sizeof *irops; ++i) {
995      irop_t *p = irops + i;
996      if (p->op == op) {
997#ifdef __s390x__
998#define S390X_FEATURES "../../../tests/s390x_features"
999         switch (op) {
1000         case Iop_I32StoD64:    // CDFTR
1001         case Iop_I32StoD128:   // CXFTR
1002         case Iop_I32UtoD64:    // CDLFTR
1003         case Iop_I32UtoD128:   // CXLFTR
1004         case Iop_I64UtoD64:    // CDLGTR
1005         case Iop_I64UtoD128:   // CXLGTR
1006         case Iop_D64toI32S:    // CFDTR
1007         case Iop_D128toI32S:   // CFXTR
1008         case Iop_D64toI64U:    // CLGDTR
1009         case Iop_D64toI32U:    // CLFDTR
1010         case Iop_D128toI64U:   // CLGXTR
1011         case Iop_D128toI32U:   // CLFXTR
1012         case Iop_I32UtoF32:
1013         case Iop_I32UtoF64:
1014         case Iop_I32UtoF128:
1015         case Iop_I64UtoF32:
1016         case Iop_I64UtoF64:
1017         case Iop_I64UtoF128:
1018         case Iop_F32toI32U:
1019         case Iop_F32toI64U:
1020         case Iop_F64toI32U:
1021         case Iop_F64toI64U:
1022         case Iop_F128toI32U:
1023         case Iop_F128toI64U: {
1024            int rc;
1025            /* These IROps require the floating point extension facility */
1026            rc = system(S390X_FEATURES " s390x-fpext");
1027            // s390x_features returns 1 if feature does not exist
1028            rc /= 256;
1029            if (rc != 0) return NULL;
1030         }
1031         /* PFPO Iops */
1032         case Iop_F32toD32:
1033         case Iop_F32toD64:
1034         case Iop_F32toD128:
1035         case Iop_F64toD32:
1036         case Iop_F64toD64:
1037         case Iop_F64toD128:
1038         case Iop_F128toD32:
1039         case Iop_F128toD64:
1040         case Iop_F128toD128:
1041         case Iop_D32toF32:
1042         case Iop_D32toF64:
1043         case Iop_D32toF128:
1044         case Iop_D64toF32:
1045         case Iop_D64toF64:
1046         case Iop_D64toF128:
1047         case Iop_D128toF32:
1048         case Iop_D128toF64:
1049         case Iop_D128toF128: {
1050            int rc;
1051            /* These IROps require the Perform Floating Point Operation facility */
1052            rc = system(S390X_FEATURES " s390x-pfpo");
1053            // s390x_features returns 1 if feature does not exist
1054            rc /= 256;
1055            if (rc != 0) return NULL;
1056         }
1057         }
1058         return p->s390x ? p : NULL;
1059#endif
1060#ifdef __x86_64__
1061         return p->amd64 ? p : NULL;
1062#endif
1063#ifdef __powerpc__
1064#ifdef __powerpc64__
1065         return p->ppc64 ? p : NULL;
1066#else
1067         return p->ppc32 ? p : NULL;
1068#endif
1069#endif
1070#ifdef __mips__
1071#if (__mips==64)
1072         return p->mips64 ? p : NULL;
1073#else
1074         return p->mips32 ? p : NULL;
1075#endif
1076#endif
1077#ifdef __arm__
1078         return p->arm ? p : NULL;
1079#endif
1080#ifdef __i386__
1081         return p->x86 ? p : NULL;
1082#endif
1083         return NULL;
1084      }
1085   }
1086
1087   fprintf(stderr, "unknown opcode %d\n", op);
1088   exit(1);
1089}
1090