1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef __LINUX_MFD_TIMPANI_AUDIO_H 20#define __LINUX_MFD_TIMPANI_AUDIO_H 21#define TIMPANI_A_MREF (0x3) 22#define TIMPANI_MREF_RWC "RW" 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#define TIMPANI_MREF_POR 0xe2 25#define TIMPANI_MREF_S 0 26#define TIMPANI_MREF_M 0xFF 27#define TIMPANI_MREF_MREF_BG_EN_S 7 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define TIMPANI_MREF_MREF_BG_EN_M 0x80 30#define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0 31#define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1 32#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40 35#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0 36#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1 37#define TIMPANI_MREF_MREF_200K_MODE_EN_S 5 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20 40#define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0 41#define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1 42#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10 45#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0 46#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1 47#define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8 50#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0 51#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1 52#define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4 55#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0 56#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1 57#define TIMPANI_MREF_MREF_400K_MODE_EN_S 1 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2 60#define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0 61#define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1 62#define TIMPANI_MREF_RESERVED_S 0 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define TIMPANI_MREF_RESERVED_M 0x1 65#define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4) 66#define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW" 67#define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69#define TIMPANI_CDAC_IDAC_REF_CUR_S 0 70#define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF 71#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5 72#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0 75#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1 76#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2 77#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4 80#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5 81#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6 82#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2 85#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C 86#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0 87#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2 90#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3 91#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4 92#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6 95#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7 96#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0 97#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0 100#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1 101#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2 102#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104#define TIMPANI_A_TXADC12_REF_CURR (0x5) 105#define TIMPANI_TXADC12_REF_CURR_RWC "RW" 106#define TIMPANI_TXADC12_REF_CURR_POR 0xa0 107#define TIMPANI_TXADC12_REF_CURR_S 0 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109#define TIMPANI_TXADC12_REF_CURR_M 0xFF 110#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6 111#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0 112#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1 115#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 116#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3 117#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30 120#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0 121#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1 122#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3 125#define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0 126#define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF 127#define TIMPANI_A_TXADC3_EN (0x9) 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129#define TIMPANI_TXADC3_EN_RWC "RW" 130#define TIMPANI_TXADC3_EN_POR 0 131#define TIMPANI_TXADC3_EN_S 0 132#define TIMPANI_TXADC3_EN_M 0xFF 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7 135#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80 136#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0 137#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6 140#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40 141#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 142#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5 145#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20 146#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0 147#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4 150#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10 151#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0 152#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3 155#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8 156#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0 157#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2 160#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4 161#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0 162#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1 165#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2 166#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0 167#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define TIMPANI_TXADC3_EN_RESERVED_S 0 170#define TIMPANI_TXADC3_EN_RESERVED_M 0x1 171#define TIMPANI_A_TXADC4_EN (0xA) 172#define TIMPANI_TXADC4_EN_RWC "RW" 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define TIMPANI_TXADC4_EN_POR 0 175#define TIMPANI_TXADC4_EN_S 0 176#define TIMPANI_TXADC4_EN_M 0xFF 177#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80 180#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0 181#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1 182#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40 185#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 186#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 187#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20 190#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0 191#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1 192#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10 195#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0 196#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1 197#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8 200#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0 201#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1 202#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4 205#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0 206#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1 207#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2 210#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0 211#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1 212#define TIMPANI_TXADC4_EN_RESERVED_S 0 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214#define TIMPANI_TXADC4_EN_RESERVED_M 0x1 215#define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB) 216#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R" 217#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0 220#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF 221#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7 222#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6 225#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40 226#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5 227#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4 230#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10 231#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0 232#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define TIMPANI_A_TXFE1 (0xD) 235#define TIMPANI_TXFE1_RWC "RW" 236#define TIMPANI_TXFE1_POR 0 237#define TIMPANI_TXFE1_S 0 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239#define TIMPANI_TXFE1_M 0xFF 240#define TIMPANI_TXFE1_TXFE1_EN_S 7 241#define TIMPANI_TXFE1_TXFE1_EN_M 0x80 242#define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244#define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1 245#define TIMPANI_TXFE1_TXFE1_GAIN_S 5 246#define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60 247#define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249#define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1 250#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2 251#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3 252#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10 255#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0 256#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1 257#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8 260#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0 261#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1 262#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4 265#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0 266#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1 267#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2 270#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0 271#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1 272#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1 275#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0 276#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1 277#define TIMPANI_A_TXFE2 (0xE) 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define TIMPANI_TXFE2_RWC "RW" 280#define TIMPANI_TXFE2_POR 0 281#define TIMPANI_TXFE2_S 0 282#define TIMPANI_TXFE2_M 0xFF 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284#define TIMPANI_TXFE2_TXFE2_EN_S 7 285#define TIMPANI_TXFE2_TXFE2_EN_M 0x80 286#define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0 287#define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289#define TIMPANI_TXFE2_TXFE2_GAIN_S 5 290#define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60 291#define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0 292#define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2 295#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3 296#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4 297#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0 300#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1 301#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3 302#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0 305#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1 306#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2 307#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0 310#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1 311#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1 312#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0 315#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1 316#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0 317#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0 320#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1 321#define TIMPANI_A_TXFE12_ATEST (0xF) 322#define TIMPANI_TXFE12_ATEST_RWC "RW" 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324#define TIMPANI_TXFE12_ATEST_POR 0 325#define TIMPANI_TXFE12_ATEST_S 0 326#define TIMPANI_TXFE12_ATEST_M 0xFF 327#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80 330#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 331#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 332#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40 335#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0 336#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1 337#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20 340#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0 341#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1 342#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10 345#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0 346#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1 347#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8 350#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 351#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 352#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4 355#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0 356#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1 357#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2 360#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0 361#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1 362#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1 365#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0 366#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1 367#define TIMPANI_A_TXFE_CLT (0x10) 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369#define TIMPANI_TXFE_CLT_RWC "RW" 370#define TIMPANI_TXFE_CLT_POR 0x68 371#define TIMPANI_TXFE_CLT_S 0 372#define TIMPANI_TXFE_CLT_M 0xFF 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5 375#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0 376#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0 377#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2 380#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3 381#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4 382#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6 385#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7 386#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3 387#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0 390#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1 391#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2 392#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394#define TIMPANI_TXFE_CLT_RESERVED_S 0 395#define TIMPANI_TXFE_CLT_RESERVED_M 0x7 396#define TIMPANI_A_TXADC1_EN (0x11) 397#define TIMPANI_TXADC1_EN_RWC "RW" 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399#define TIMPANI_TXADC1_EN_POR 0 400#define TIMPANI_TXADC1_EN_S 0 401#define TIMPANI_TXADC1_EN_M 0xFF 402#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80 405#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0 406#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1 407#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40 410#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 411#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 412#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20 415#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0 416#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1 417#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10 420#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0 421#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1 422#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8 425#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0 426#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1 427#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4 430#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0 431#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1 432#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2 435#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0 436#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1 437#define TIMPANI_TXADC1_EN_RESERVED_S 0 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439#define TIMPANI_TXADC1_EN_RESERVED_M 0x1 440#define TIMPANI_A_TXADC2_EN (0x12) 441#define TIMPANI_TXADC2_EN_RWC "RW" 442#define TIMPANI_TXADC2_EN_POR 0 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define TIMPANI_TXADC2_EN_S 0 445#define TIMPANI_TXADC2_EN_M 0xFF 446#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7 447#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0 450#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1 451#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6 452#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 455#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 456#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5 457#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0 460#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1 461#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4 462#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0 465#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1 466#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3 467#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0 470#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1 471#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2 472#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0 475#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1 476#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1 477#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0 480#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1 481#define TIMPANI_TXADC2_EN_RESERVED_S 0 482#define TIMPANI_TXADC2_EN_RESERVED_M 0x1 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484#define TIMPANI_A_TXADC_CTL (0x13) 485#define TIMPANI_TXADC_CTL_RWC "RW" 486#define TIMPANI_TXADC_CTL_POR 0x58 487#define TIMPANI_TXADC_CTL_S 0 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489#define TIMPANI_TXADC_CTL_M 0xFF 490#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6 491#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0 492#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1 495#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2 496#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3 497#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30 500#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0 501#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1 502#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3 505#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2 506#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC 507#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1 510#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2 511#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3 512#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0 513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3 515#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0 516#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1 517#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2 518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3 520#define TIMPANI_A_TXADC_CTL2 (0x14) 521#define TIMPANI_TXADC_CTL2_RWC "RW" 522#define TIMPANI_TXADC_CTL2_POR 0x64 523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524#define TIMPANI_TXADC_CTL2_S 0 525#define TIMPANI_TXADC_CTL2_M 0xFF 526#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6 527#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0 528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0 530#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1 531#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2 532#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3 533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4 535#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30 536#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0 537#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1 538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2 540#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3 541#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2 542#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC 543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0 545#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1 546#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2 547#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3 548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1 550#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2 551#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0 552#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1 553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0 555#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1 556#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0 557#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1 558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559#define TIMPANI_A_TXADC_CTL3 (0x15) 560#define TIMPANI_TXADC_CTL3_RWC "RW" 561#define TIMPANI_TXADC_CTL3_POR 0x64 562#define TIMPANI_TXADC_CTL3_S 0 563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564#define TIMPANI_TXADC_CTL3_M 0xFF 565#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6 566#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0 567#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0 568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1 570#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2 571#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3 572#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4 573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30 575#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0 576#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1 577#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2 578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3 580#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2 581#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC 582#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0 583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1 585#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2 586#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3 587#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1 588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2 590#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0 591#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1 592#define TIMPANI_TXADC_CTL3_RESERVED_S 0 593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594#define TIMPANI_TXADC_CTL3_RESERVED_M 0x1 595#define TIMPANI_A_TXADC_CHOP_CTL (0x16) 596#define TIMPANI_TXADC_CHOP_CTL_RWC "RW" 597#define TIMPANI_TXADC_CHOP_CTL_POR 0 598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599#define TIMPANI_TXADC_CHOP_CTL_S 0 600#define TIMPANI_TXADC_CHOP_CTL_M 0xFF 601#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7 602#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80 603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0 605#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1 606#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4 607#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70 608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0 610#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1 611#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2 612#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3 613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4 615#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5 616#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6 617#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7 618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3 620#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8 621#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0 622#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1 623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2 625#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4 626#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0 627#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1 628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629#define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0 630#define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3 631#define TIMPANI_A_TXFE3 (0x18) 632#define TIMPANI_TXFE3_RWC "RW" 633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634#define TIMPANI_TXFE3_POR 0 635#define TIMPANI_TXFE3_S 0 636#define TIMPANI_TXFE3_M 0xFF 637#define TIMPANI_TXFE3_TXFE3_EN_S 7 638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639#define TIMPANI_TXFE3_TXFE3_EN_M 0x80 640#define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0 641#define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1 642#define TIMPANI_TXFE3_TXFE3_GAIN_S 5 643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644#define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60 645#define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0 646#define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1 647#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2 648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3 650#define TIMPANI_TXFE3_RESERVED_1_S 2 651#define TIMPANI_TXFE3_RESERVED_1_M 0x1C 652#define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1 653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654#define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2 655#define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0 656#define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1 657#define TIMPANI_TXFE3_RESERVED_2_S 0 658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659#define TIMPANI_TXFE3_RESERVED_2_M 0x1 660#define TIMPANI_A_TXFE4 (0x19) 661#define TIMPANI_TXFE4_RWC "RW" 662#define TIMPANI_TXFE4_POR 0 663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664#define TIMPANI_TXFE4_S 0 665#define TIMPANI_TXFE4_M 0xFF 666#define TIMPANI_TXFE4_TXFE4_EN_S 7 667#define TIMPANI_TXFE4_TXFE4_EN_M 0x80 668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669#define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0 670#define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1 671#define TIMPANI_TXFE4_TXFE4_GAIN_S 5 672#define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60 673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674#define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0 675#define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1 676#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2 677#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3 678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679#define TIMPANI_TXFE4_RESERVED_1_S 2 680#define TIMPANI_TXFE4_RESERVED_1_M 0x1C 681#define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1 682#define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2 683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684#define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0 685#define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1 686#define TIMPANI_TXFE4_RESERVED_2_S 0 687#define TIMPANI_TXFE4_RESERVED_2_M 0x1 688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689#define TIMPANI_A_TXFE3_ATEST (0x1A) 690#define TIMPANI_TXFE3_ATEST_RWC "RW" 691#define TIMPANI_TXFE3_ATEST_POR 0 692#define TIMPANI_TXFE3_ATEST_S 0 693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694#define TIMPANI_TXFE3_ATEST_M 0xFF 695#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7 696#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80 697#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 700#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6 701#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40 702#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0 703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1 705#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5 706#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20 707#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0 708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1 710#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4 711#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10 712#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0 713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1 715#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3 716#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8 717#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 720#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2 721#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4 722#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0 723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1 725#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1 726#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2 727#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0 728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1 730#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0 731#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1 732#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0 733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1 735#define TIMPANI_A_TXFE_DIFF_SE (0x1B) 736#define TIMPANI_TXFE_DIFF_SE_RWC "RW" 737#define TIMPANI_TXFE_DIFF_SE_POR 0 738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739#define TIMPANI_TXFE_DIFF_SE_S 0 740#define TIMPANI_TXFE_DIFF_SE_M 0xFF 741#define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4 742#define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0 743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3 745#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8 746#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0 747#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1 748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2 750#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4 751#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0 752#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1 753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1 755#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2 756#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0 757#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1 758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0 760#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1 761#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0 762#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1 763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764#define TIMPANI_A_CDAC_RX_CLK_CTL (0x20) 765#define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW" 766#define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98 767#define TIMPANI_CDAC_RX_CLK_CTL_S 0 768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769#define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF 770#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7 771#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80 772#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0 773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1 775#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6 776#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40 777#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0 778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1 780#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2 781#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C 782#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0 783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1 785#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2 786#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3 787#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4 788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5 790#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6 791#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7 792#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8 793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9 795#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA 796#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB 797#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC 798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD 800#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE 801#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF 802#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1 803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2 805#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1 806#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0 807#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0 808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1 810#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0 811#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1 812#define TIMPANI_A_CDAC_BUFF_CTL (0x21) 813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814#define TIMPANI_CDAC_BUFF_CTL_RWC "RW" 815#define TIMPANI_CDAC_BUFF_CTL_POR 0x60 816#define TIMPANI_CDAC_BUFF_CTL_S 0 817#define TIMPANI_CDAC_BUFF_CTL_M 0xFF 818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5 820#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0 821#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0 822#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1 823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2 825#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3 826#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4 827#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5 828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6 830#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7 831#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3 832#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18 833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0 835#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1 836#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2 837#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3 838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1 840#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6 841#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0 842#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1 843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2 845#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3 846#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0 847#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1 848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0 850#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1 851#define TIMPANI_A_CDAC_REF_CTL1 (0x22) 852#define TIMPANI_CDAC_REF_CTL1_RWC "RW" 853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854#define TIMPANI_CDAC_REF_CTL1_POR 0xe1 855#define TIMPANI_CDAC_REF_CTL1_S 0 856#define TIMPANI_CDAC_REF_CTL1_M 0xFF 857#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5 858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0 860#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0 861#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1 862#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2 863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3 865#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4 866#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5 867#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6 868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7 870#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2 871#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C 872#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0 873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1 875#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2 876#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3 877#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4 878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5 880#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6 881#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7 882#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0 883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3 885#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0 886#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1 887#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2 888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3 890#define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23) 891#define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW" 892#define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28 893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894#define TIMPANI_IDAC_DWA_FIR_CTL_S 0 895#define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF 896#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7 897#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80 898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0 900#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1 901#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4 902#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70 903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0 905#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1 906#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2 907#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3 908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4 910#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3 911#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8 912#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1 913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0 915#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0 916#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7 917#define TIMPANI_A_CDAC_REF_CTL2 (0x24) 918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919#define TIMPANI_CDAC_REF_CTL2_RWC "RW" 920#define TIMPANI_CDAC_REF_CTL2_POR 0xc 921#define TIMPANI_CDAC_REF_CTL2_S 0 922#define TIMPANI_CDAC_REF_CTL2_M 0xFF 923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7 925#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80 926#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6 927#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40 928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0 930#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1 931#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5 932#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20 933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0 935#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1 936#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4 937#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10 938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2 940#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC 941#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1 942#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3 943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0 945#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3 946#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0 947#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1 948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3 950#define TIMPANI_A_CDAC_CTL1 (0x25) 951#define TIMPANI_CDAC_CTL1_RWC "RW" 952#define TIMPANI_CDAC_CTL1_POR 0xb 953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954#define TIMPANI_CDAC_CTL1_S 0 955#define TIMPANI_CDAC_CTL1_M 0xFF 956#define TIMPANI_CDAC_CTL1_RESERVED_S 6 957#define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0 958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5 960#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20 961#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0 962#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1 963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4 965#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10 966#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0 967#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1 968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2 970#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC 971#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0 972#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1 973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2 975#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3 976#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1 977#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2 978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0 980#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1 981#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0 982#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1 983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1 985#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0 986#define TIMPANI_A_CDAC_CTL2 (0x26) 987#define TIMPANI_CDAC_CTL2_RWC "RW" 988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989#define TIMPANI_CDAC_CTL2_POR 0xd0 990#define TIMPANI_CDAC_CTL2_S 0 991#define TIMPANI_CDAC_CTL2_M 0xFF 992#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5 993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0 995#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0 996#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1 997#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2 998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3 1000#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4 1001#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5 1002#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6 1003/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1004#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7 1005#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2 1006#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C 1007#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0 1008/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1009#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1 1010#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2 1011#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3 1012#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4 1013/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1014#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5 1015#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6 1016#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7 1017#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0 1018/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1019#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3 1020#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0 1021#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1 1022#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2 1023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1024#define TIMPANI_A_IDAC_L_CTL (0x28) 1025#define TIMPANI_IDAC_L_CTL_RWC "RW" 1026#define TIMPANI_IDAC_L_CTL_POR 0xe 1027#define TIMPANI_IDAC_L_CTL_S 0 1028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1029#define TIMPANI_IDAC_L_CTL_M 0xFF 1030#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7 1031#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80 1032#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0 1033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1034#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1 1035#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5 1036#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60 1037#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0 1038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1039#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1 1040#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 1041#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3 1042#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3 1043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1044#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18 1045#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0 1046#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1 1047#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2 1048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1049#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3 1050#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2 1051#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4 1052#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0 1053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1054#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 1055#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1 1056#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2 1057#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0 1058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1059#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1 1060#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0 1061#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1 1062#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 1063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1064#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 1065#define TIMPANI_A_IDAC_R_CTL (0x29) 1066#define TIMPANI_IDAC_R_CTL_RWC "RW" 1067#define TIMPANI_IDAC_R_CTL_POR 0xe 1068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1069#define TIMPANI_IDAC_R_CTL_S 0 1070#define TIMPANI_IDAC_R_CTL_M 0xFF 1071#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7 1072#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80 1073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1074#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0 1075#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1 1076#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5 1077#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60 1078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1079#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0 1080#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1 1081#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 1082#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3 1083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1084#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3 1085#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18 1086#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0 1087#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1 1088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1089#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2 1090#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3 1091#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2 1092#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4 1093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1094#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0 1095#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 1096#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1 1097#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2 1098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1099#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0 1100#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1 1101#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0 1102#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1 1103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1104#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 1105#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 1106#define TIMPANI_A_PA_MASTER_BIAS (0x2D) 1107#define TIMPANI_PA_MASTER_BIAS_RWC "RW" 1108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1109#define TIMPANI_PA_MASTER_BIAS_POR 0x6f 1110#define TIMPANI_PA_MASTER_BIAS_S 0 1111#define TIMPANI_PA_MASTER_BIAS_M 0xFF 1112#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5 1113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1114#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0 1115#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0 1116#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1 1117#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2 1118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1119#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3 1120#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4 1121#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5 1122#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6 1123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1124#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7 1125#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2 1126#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C 1127#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0 1128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1129#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1 1130#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2 1131#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3 1132#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4 1133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1134#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5 1135#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6 1136#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7 1137#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0 1138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1139#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3 1140#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0 1141#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1 1142#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2 1143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1144#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3 1145#define TIMPANI_A_PA_CLASSD_BIAS (0x2E) 1146#define TIMPANI_PA_CLASSD_BIAS_RWC "RW" 1147#define TIMPANI_PA_CLASSD_BIAS_POR 0x55 1148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1149#define TIMPANI_PA_CLASSD_BIAS_S 0 1150#define TIMPANI_PA_CLASSD_BIAS_M 0xFF 1151#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6 1152#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0 1153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1154#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0 1155#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1 1156#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2 1157#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3 1158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1159#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4 1160#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30 1161#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0 1162#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1 1163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1164#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2 1165#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3 1166#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2 1167#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC 1168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1169#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0 1170#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1 1171#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2 1172#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3 1173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1174#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0 1175#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3 1176#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0 1177#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1 1178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1179#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2 1180#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3 1181#define TIMPANI_A_AUXPGA_CUR (0x2F) 1182#define TIMPANI_AUXPGA_CUR_RWC "RW" 1183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1184#define TIMPANI_AUXPGA_CUR_POR 0x44 1185#define TIMPANI_AUXPGA_CUR_S 0 1186#define TIMPANI_AUXPGA_CUR_M 0xFF 1187#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4 1188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1189#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0 1190#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0 1191#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1 1192#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2 1193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1194#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3 1195#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4 1196#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5 1197#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6 1198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1199#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7 1200#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8 1201#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9 1202#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA 1203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1204#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB 1205#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC 1206#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD 1207#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE 1208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1209#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF 1210#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0 1211#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF 1212#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0 1213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1214#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1 1215#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2 1216#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3 1217#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4 1218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1219#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5 1220#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6 1221#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7 1222#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8 1223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1224#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9 1225#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA 1226#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB 1227#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC 1228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1229#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD 1230#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE 1231#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF 1232#define TIMPANI_A_AUXPGA_CM (0x30) 1233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1234#define TIMPANI_AUXPGA_CM_RWC "RW" 1235#define TIMPANI_AUXPGA_CM_POR 0x92 1236#define TIMPANI_AUXPGA_CM_S 0 1237#define TIMPANI_AUXPGA_CM_M 0xFF 1238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1239#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5 1240#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0 1241#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 1242#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 1243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1244#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 1245#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 1246#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 1247#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 1248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1249#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 1250#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 1251#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2 1252#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C 1253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1254#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 1255#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 1256#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 1257#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 1258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1259#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 1260#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 1261#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 1262#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 1263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1264#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1 1265#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2 1266#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1 1267#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0 1268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1269#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0 1270#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1 1271#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1 1272#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0 1273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1274#define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31) 1275#define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW" 1276#define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4 1277#define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0 1278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1279#define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF 1280#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7 1281#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80 1282#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1 1283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1284#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0 1285#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6 1286#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40 1287#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1 1288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1289#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0 1290#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5 1291#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20 1292#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1 1293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1294#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0 1295#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4 1296#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10 1297#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1 1298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1299#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0 1300#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3 1301#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8 1302#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1 1303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1304#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0 1305#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2 1306#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4 1307#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1 1308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1309#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0 1310#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1 1311#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2 1312#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1 1313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1314#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0 1315#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0 1316#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1 1317#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1 1318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1319#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0 1320#define TIMPANI_A_PA_LINE_AUXO_EN (0x32) 1321#define TIMPANI_PA_LINE_AUXO_EN_RWC "RW" 1322#define TIMPANI_PA_LINE_AUXO_EN_POR 0 1323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1324#define TIMPANI_PA_LINE_AUXO_EN_S 0 1325#define TIMPANI_PA_LINE_AUXO_EN_M 0xFF 1326#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7 1327#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80 1328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1329#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1 1330#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0 1331#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6 1332#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40 1333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1334#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1 1335#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0 1336#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5 1337#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20 1338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1339#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1 1340#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0 1341#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4 1342#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10 1343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1344#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1 1345#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0 1346#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3 1347#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8 1348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1349#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1 1350#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0 1351#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2 1352#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4 1353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1354#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1 1355#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0 1356#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1 1357#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2 1358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1359#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1 1360#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0 1361#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0 1362#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1 1363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1364#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1 1365#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0 1366#define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33) 1367#define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW" 1368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1369#define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0 1370#define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0 1371#define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF 1372#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7 1373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1374#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80 1375#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1 1376#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0 1377#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6 1378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1379#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40 1380#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1 1381#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0 1382#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5 1383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1384#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20 1385#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0 1386#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1 1387#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4 1388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1389#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10 1390#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0 1391#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1 1392#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3 1393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1394#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8 1395#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0 1396#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1 1397#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2 1398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1399#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4 1400#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0 1401#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1 1402#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1 1403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1404#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2 1405#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0 1406#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1 1407#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0 1408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1409#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1 1410#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0 1411#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1 1412#define TIMPANI_A_PA_LINE_L_GAIN (0x34) 1413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1414#define TIMPANI_PA_LINE_L_GAIN_RWC "RW" 1415#define TIMPANI_PA_LINE_L_GAIN_POR 0xac 1416#define TIMPANI_PA_LINE_L_GAIN_S 0 1417#define TIMPANI_PA_LINE_L_GAIN_M 0xFF 1418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1419#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2 1420#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC 1421#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0 1422#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1 1423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1424#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2 1425#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3 1426#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4 1427#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5 1428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1429#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6 1430#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7 1431#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8 1432#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9 1433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1434#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA 1435#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB 1436#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC 1437#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD 1438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1439#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE 1440#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF 1441#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10 1442#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11 1443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1444#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12 1445#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13 1446#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14 1447#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15 1448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1449#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16 1450#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17 1451#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18 1452#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19 1453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1454#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A 1455#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B 1456#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C 1457#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D 1458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1459#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E 1460#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F 1461#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20 1462#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21 1463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1464#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22 1465#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23 1466#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24 1467#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25 1468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1469#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26 1470#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27 1471#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28 1472#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29 1473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1474#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A 1475#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B 1476#define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0 1477#define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3 1478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1479#define TIMPANI_A_PA_LINE_R_GAIN (0x35) 1480#define TIMPANI_PA_LINE_R_GAIN_RWC "RW" 1481#define TIMPANI_PA_LINE_R_GAIN_POR 0xac 1482#define TIMPANI_PA_LINE_R_GAIN_S 0 1483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1484#define TIMPANI_PA_LINE_R_GAIN_M 0xFF 1485#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2 1486#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC 1487#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0 1488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1489#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1 1490#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2 1491#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3 1492#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4 1493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1494#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5 1495#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6 1496#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7 1497#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8 1498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1499#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9 1500#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA 1501#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB 1502#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC 1503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1504#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD 1505#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE 1506#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF 1507#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10 1508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1509#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11 1510#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12 1511#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13 1512#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14 1513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1514#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15 1515#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16 1516#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17 1517#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18 1518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1519#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19 1520#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A 1521#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B 1522#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C 1523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1524#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D 1525#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E 1526#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F 1527#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20 1528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1529#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21 1530#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22 1531#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23 1532#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24 1533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1534#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25 1535#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26 1536#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27 1537#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28 1538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1539#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29 1540#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A 1541#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B 1542#define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0 1543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1544#define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3 1545#define TIMPANI_A_PA_HPH_L_GAIN (0x36) 1546#define TIMPANI_PA_HPH_L_GAIN_RWC "RW" 1547#define TIMPANI_PA_HPH_L_GAIN_POR 0xae 1548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1549#define TIMPANI_PA_HPH_L_GAIN_S 0 1550#define TIMPANI_PA_HPH_L_GAIN_M 0xFF 1551#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2 1552#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC 1553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1554#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0 1555#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1 1556#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2 1557#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3 1558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1559#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4 1560#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5 1561#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6 1562#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7 1563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1564#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8 1565#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9 1566#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA 1567#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB 1568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1569#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC 1570#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD 1571#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE 1572#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF 1573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1574#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10 1575#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11 1576#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12 1577#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13 1578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1579#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14 1580#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15 1581#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16 1582#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17 1583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1584#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18 1585#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19 1586#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A 1587#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B 1588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1589#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C 1590#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D 1591#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E 1592#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F 1593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1594#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20 1595#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21 1596#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22 1597#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23 1598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1599#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24 1600#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25 1601#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26 1602#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27 1603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1604#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28 1605#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29 1606#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A 1607#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B 1608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1609#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1 1610#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2 1611#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1 1612#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0 1613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1614#define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0 1615#define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1 1616#define TIMPANI_A_PA_HPH_R_GAIN (0x37) 1617#define TIMPANI_PA_HPH_R_GAIN_RWC "RW" 1618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1619#define TIMPANI_PA_HPH_R_GAIN_POR 0xae 1620#define TIMPANI_PA_HPH_R_GAIN_S 0 1621#define TIMPANI_PA_HPH_R_GAIN_M 0xFF 1622#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2 1623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1624#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC 1625#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0 1626#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1 1627#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2 1628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1629#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3 1630#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4 1631#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5 1632#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6 1633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1634#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7 1635#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8 1636#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9 1637#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA 1638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1639#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB 1640#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC 1641#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD 1642#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE 1643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1644#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF 1645#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10 1646#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11 1647#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12 1648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1649#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13 1650#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14 1651#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15 1652#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16 1653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1654#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17 1655#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18 1656#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19 1657#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A 1658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1659#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B 1660#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C 1661#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D 1662#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E 1663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1664#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F 1665#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20 1666#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21 1667#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22 1668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1669#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23 1670#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24 1671#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25 1672#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26 1673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1674#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27 1675#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28 1676#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29 1677#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A 1678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1679#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B 1680#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1 1681#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2 1682#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1 1683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1684#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0 1685#define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0 1686#define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1 1687#define TIMPANI_A_AUXPGA_LR_GAIN (0x38) 1688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1689#define TIMPANI_AUXPGA_LR_GAIN_RWC "RW" 1690#define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa 1691#define TIMPANI_AUXPGA_LR_GAIN_S 0 1692#define TIMPANI_AUXPGA_LR_GAIN_M 0xFF 1693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1694#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4 1695#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0 1696#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0 1697#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1 1698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1699#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2 1700#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3 1701#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4 1702#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5 1703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1704#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6 1705#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7 1706#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8 1707#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9 1708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1709#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA 1710#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB 1711#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC 1712#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD 1713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1714#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE 1715#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF 1716#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0 1717#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF 1718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1719#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0 1720#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1 1721#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2 1722#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3 1723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1724#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4 1725#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5 1726#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6 1727#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7 1728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1729#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8 1730#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9 1731#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA 1732#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB 1733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1734#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC 1735#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD 1736#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE 1737#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF 1738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1739#define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39) 1740#define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW" 1741#define TIMPANI_PA_AUXO_EARPA_CONN_POR 0 1742#define TIMPANI_PA_AUXO_EARPA_CONN_S 0 1743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1744#define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF 1745#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7 1746#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80 1747#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0 1748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1749#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1 1750#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6 1751#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40 1752#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0 1753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1754#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1 1755#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5 1756#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20 1757#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0 1758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1759#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1 1760#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4 1761#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10 1762#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3 1763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1764#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8 1765#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1 1766#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0 1767#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2 1768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1769#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4 1770#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0 1771#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1 1772#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1 1773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1774#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2 1775#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0 1776#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1 1777#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0 1778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1779#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1 1780#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0 1781#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1 1782#define TIMPANI_A_PA_LINE_ST_CONN (0x3A) 1783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1784#define TIMPANI_PA_LINE_ST_CONN_RWC "RW" 1785#define TIMPANI_PA_LINE_ST_CONN_POR 0 1786#define TIMPANI_PA_LINE_ST_CONN_S 0 1787#define TIMPANI_PA_LINE_ST_CONN_M 0xFF 1788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1789#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7 1790#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80 1791#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0 1792#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1 1793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1794#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6 1795#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40 1796#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0 1797#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1 1798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1799#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5 1800#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20 1801#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0 1802#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1 1803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1804#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4 1805#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10 1806#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0 1807#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1 1808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1809#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3 1810#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8 1811#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0 1812#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1 1813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1814#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2 1815#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4 1816#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0 1817#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1 1818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1819#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0 1820#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3 1821#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0 1822#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1 1823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1824#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2 1825#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3 1826#define TIMPANI_A_PA_LINE_MONO_CONN (0x3B) 1827#define TIMPANI_PA_LINE_MONO_CONN_RWC "RW" 1828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1829#define TIMPANI_PA_LINE_MONO_CONN_POR 0 1830#define TIMPANI_PA_LINE_MONO_CONN_S 0 1831#define TIMPANI_PA_LINE_MONO_CONN_M 0xFF 1832#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7 1833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1834#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80 1835#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0 1836#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1 1837#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6 1838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1839#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40 1840#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0 1841#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1 1842#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5 1843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1844#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20 1845#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0 1846#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1 1847#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4 1848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1849#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10 1850#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 1851#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1 1852#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3 1853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1854#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8 1855#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 1856#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1 1857#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2 1858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1859#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4 1860#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 1861#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1 1862#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0 1863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1864#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3 1865#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0 1866#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1 1867#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2 1868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1869#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3 1870#define TIMPANI_A_PA_HPH_ST_CONN (0x3C) 1871#define TIMPANI_PA_HPH_ST_CONN_RWC "RW" 1872#define TIMPANI_PA_HPH_ST_CONN_POR 0 1873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1874#define TIMPANI_PA_HPH_ST_CONN_S 0 1875#define TIMPANI_PA_HPH_ST_CONN_M 0xFF 1876#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7 1877#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80 1878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1879#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0 1880#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1 1881#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6 1882#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40 1883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1884#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0 1885#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1 1886#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5 1887#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20 1888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1889#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0 1890#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1 1891#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4 1892#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10 1893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1894#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0 1895#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1 1896#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3 1897#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8 1898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1899#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0 1900#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1 1901#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2 1902#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4 1903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1904#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0 1905#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1 1906#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1 1907#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2 1908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1909#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1 1910#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0 1911#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0 1912#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1 1913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1914#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1 1915#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0 1916#define TIMPANI_A_PA_HPH_MONO_CONN (0x3D) 1917#define TIMPANI_PA_HPH_MONO_CONN_RWC "RW" 1918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1919#define TIMPANI_PA_HPH_MONO_CONN_POR 0 1920#define TIMPANI_PA_HPH_MONO_CONN_S 0 1921#define TIMPANI_PA_HPH_MONO_CONN_M 0xFF 1922#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7 1923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1924#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80 1925#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0 1926#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1 1927#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6 1928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1929#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40 1930#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0 1931#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1 1932#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5 1933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1934#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20 1935#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0 1936#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1 1937#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4 1938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1939#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10 1940#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 1941#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1 1942#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3 1943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1944#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8 1945#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 1946#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1 1947#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2 1948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1949#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4 1950#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 1951#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1 1952#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0 1953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1954#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3 1955#define TIMPANI_A_PA_CLASSD_CONN (0x3E) 1956#define TIMPANI_PA_CLASSD_CONN_RWC "RW" 1957#define TIMPANI_PA_CLASSD_CONN_POR 0 1958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1959#define TIMPANI_PA_CLASSD_CONN_S 0 1960#define TIMPANI_PA_CLASSD_CONN_M 0xFF 1961#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7 1962#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80 1963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1964#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0 1965#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1 1966#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6 1967#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40 1968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1969#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0 1970#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1 1971#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5 1972#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20 1973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1974#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0 1975#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1 1976#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4 1977#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10 1978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1979#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1 1980#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0 1981#define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0 1982#define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF 1983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1984#define TIMPANI_A_PA_CNP_CTL (0x3F) 1985#define TIMPANI_PA_CNP_CTL_RWC "RW" 1986#define TIMPANI_PA_CNP_CTL_POR 0x07 1987#define TIMPANI_PA_CNP_CTL_S 0 1988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1989#define TIMPANI_PA_CNP_CTL_M 0xFF 1990#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6 1991#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0 1992#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0 1993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1994#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1 1995#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2 1996#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3 1997#define TIMPANI_PA_CNP_CTL_RESERVED_S 4 1998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1999#define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30 2000#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3 2001#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8 2002#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0 2003/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2004#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1 2005#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0 2006#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7 2007#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0 2008/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2009#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1 2010#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2 2011#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3 2012#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4 2013/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2014#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5 2015#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6 2016#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7 2017#define TIMPANI_A_PA_CLASSD_L_CTL (0x40) 2018/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2019#define TIMPANI_PA_CLASSD_L_CTL_RWC "RW" 2020#define TIMPANI_PA_CLASSD_L_CTL_POR 0x08 2021#define TIMPANI_PA_CLASSD_L_CTL_S 0 2022#define TIMPANI_PA_CLASSD_L_CTL_M 0xFF 2023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2024#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6 2025#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0 2026#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5 2027#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20 2028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2029#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0 2030#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1 2031#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4 2032#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10 2033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2034#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0 2035#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1 2036#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2 2037#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC 2038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2039#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0 2040#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1 2041#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2 2042#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3 2043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2044#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1 2045#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2 2046#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0 2047#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1 2048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2049#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0 2050#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1 2051#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0 2052#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1 2053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2054#define TIMPANI_A_PA_CLASSD_R_CTL (0x41) 2055#define TIMPANI_PA_CLASSD_R_CTL_RWC "RW" 2056#define TIMPANI_PA_CLASSD_R_CTL_POR 0x08 2057#define TIMPANI_PA_CLASSD_R_CTL_S 0 2058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2059#define TIMPANI_PA_CLASSD_R_CTL_M 0xFF 2060#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6 2061#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0 2062#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5 2063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2064#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20 2065#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0 2066#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1 2067#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4 2068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2069#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10 2070#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0 2071#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1 2072#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2 2073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2074#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC 2075#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0 2076#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1 2077#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2 2078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2079#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3 2080#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1 2081#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2 2082#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0 2083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2084#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1 2085#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0 2086#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1 2087#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0 2088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2089#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1 2090#define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42) 2091#define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW" 2092#define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0 2093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2094#define TIMPANI_PA_CLASSD_INT2_CTL_S 0 2095#define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF 2096#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6 2097#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0 2098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2099#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0 2100#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1 2101#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2 2102#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3 2103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2104#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4 2105#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30 2106#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0 2107#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1 2108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2109#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2 2110#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3 2111#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2 2112#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC 2113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2114#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0 2115#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1 2116#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2 2117#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3 2118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2119#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0 2120#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3 2121#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0 2122#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1 2123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2124#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2 2125#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3 2126#define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43) 2127#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW" 2128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2129#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2 2130#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0 2131#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF 2132#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7 2133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2134#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80 2135#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 2136#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 2137#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6 2138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2139#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40 2140#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 2141#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 2142#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4 2143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2144#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 2145#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 2146#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 2147#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 2148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2149#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 2150#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3 2151#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8 2152#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1 2153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2154#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0 2155#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2 2156#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4 2157#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1 2158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2159#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0 2160#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0 2161#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3 2162#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 2163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2164#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 2165#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 2166#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 2167#define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44) 2168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2169#define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW" 2170#define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37 2171#define TIMPANI_PA_CLASSD_L_SW_CTL_S 0 2172#define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF 2173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2174#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6 2175#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0 2176#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 2177#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 2178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2179#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 2180#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 2181#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4 2182#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30 2183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2184#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 2185#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 2186#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 2187#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 2188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2189#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3 2190#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8 2191#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2 2192#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4 2193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2194#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0 2195#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1 2196#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1 2197#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2 2198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2199#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0 2200#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1 2201#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0 2202#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1 2203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2204#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0 2205#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 2206#define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45) 2207#define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW" 2208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2209#define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff 2210#define TIMPANI_PA_CLASSD_L_OCP1_S 0 2211#define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF 2212#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7 2213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2214#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80 2215#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0 2216#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1 2217#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6 2218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2219#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40 2220#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0 2221#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1 2222#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4 2223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2224#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30 2225#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 2226#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 2227#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 2228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2229#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 2230#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0 2231#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF 2232#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 2233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2234#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 2235#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 2236#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 2237#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 2238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2239#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 2240#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 2241#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 2242#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 2243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2244#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA 2245#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB 2246#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC 2247#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD 2248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2249#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE 2250#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF 2251#define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46) 2252#define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW" 2253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2254#define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77 2255#define TIMPANI_PA_CLASSD_L_OCP2_S 0 2256#define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF 2257#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4 2258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2259#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0 2260#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0 2261#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1 2262#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2 2263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2264#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3 2265#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4 2266#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5 2267#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6 2268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2269#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7 2270#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8 2271#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9 2272#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA 2273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2274#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB 2275#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC 2276#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD 2277#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE 2278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2279#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF 2280#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0 2281#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF 2282#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0 2283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2284#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1 2285#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2 2286#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3 2287#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4 2288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2289#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5 2290#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6 2291#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7 2292#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8 2293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2294#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9 2295#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA 2296#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB 2297#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC 2298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2299#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD 2300#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE 2301#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF 2302#define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47) 2303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2304#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW" 2305#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2 2306#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0 2307#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF 2308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2309#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7 2310#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80 2311#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 2312#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 2313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2314#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6 2315#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40 2316#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 2317#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 2318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2319#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4 2320#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 2321#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 2322#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 2323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2324#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 2325#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 2326#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3 2327#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8 2328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2329#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1 2330#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0 2331#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2 2332#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4 2333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2334#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1 2335#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0 2336#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0 2337#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3 2338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2339#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 2340#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 2341#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 2342#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 2343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2344#define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48) 2345#define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW" 2346#define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37 2347#define TIMPANI_PA_CLASSD_R_SW_CTL_S 0 2348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2349#define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF 2350#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6 2351#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0 2352#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 2353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2354#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 2355#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 2356#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 2357#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4 2358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2359#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30 2360#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 2361#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 2362#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 2363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2364#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 2365#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3 2366#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8 2367#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2 2368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2369#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4 2370#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0 2371#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1 2372#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1 2373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2374#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2 2375#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0 2376#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1 2377#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0 2378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2379#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1 2380#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0 2381#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 2382#define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49) 2383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2384#define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW" 2385#define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff 2386#define TIMPANI_PA_CLASSD_R_OCP1_S 0 2387#define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF 2388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2389#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7 2390#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80 2391#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0 2392#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1 2393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2394#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6 2395#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40 2396#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0 2397#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1 2398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2399#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4 2400#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30 2401#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 2402#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 2403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2404#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 2405#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 2406#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0 2407#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF 2408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2409#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 2410#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 2411#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 2412#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 2413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2414#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 2415#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 2416#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 2417#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 2418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2419#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 2420#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA 2421#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB 2422#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC 2423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2424#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD 2425#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE 2426#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF 2427#define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A) 2428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2429#define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW" 2430#define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77 2431#define TIMPANI_PA_CLASSD_R_OCP2_S 0 2432#define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF 2433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2434#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4 2435#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0 2436#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0 2437#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1 2438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2439#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2 2440#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3 2441#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4 2442#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5 2443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2444#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6 2445#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7 2446#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8 2447#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9 2448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2449#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA 2450#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB 2451#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC 2452#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD 2453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2454#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE 2455#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF 2456#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0 2457#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF 2458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2459#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0 2460#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1 2461#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2 2462#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3 2463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2464#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4 2465#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5 2466#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6 2467#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7 2468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2469#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8 2470#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9 2471#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA 2472#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB 2473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2474#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC 2475#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD 2476#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE 2477#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF 2478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2479#define TIMPANI_A_PA_HPH_CTL1 (0x4B) 2480#define TIMPANI_PA_HPH_CTL1_RWC "RW" 2481#define TIMPANI_PA_HPH_CTL1_POR 0x44 2482#define TIMPANI_PA_HPH_CTL1_S 0 2483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2484#define TIMPANI_PA_HPH_CTL1_M 0xFF 2485#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4 2486#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0 2487#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1 2488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2489#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2 2490#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3 2491#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4 2492#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6 2493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2494#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8 2495#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC 2496#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3 2497#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8 2498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2499#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0 2500#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1 2501#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0 2502#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7 2503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2504#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0 2505#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2 2506#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3 2507#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4 2508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2509#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6 2510#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7 2511#define TIMPANI_A_PA_HPH_CTL2 (0x4C) 2512#define TIMPANI_PA_HPH_CTL2_RWC "RW" 2513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2514#define TIMPANI_PA_HPH_CTL2_POR 0xC8 2515#define TIMPANI_PA_HPH_CTL2_S 0 2516#define TIMPANI_PA_HPH_CTL2_M 0xFF 2517#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7 2518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2519#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80 2520#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1 2521#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0 2522#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6 2523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2524#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40 2525#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1 2526#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0 2527#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5 2528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2529#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20 2530#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1 2531#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0 2532#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4 2533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2534#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10 2535#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1 2536#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0 2537#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2 2538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2539#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC 2540#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0 2541#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1 2542#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2 2543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2544#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3 2545#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1 2546#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2 2547#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0 2548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2549#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1 2550#define TIMPANI_PA_HPH_CTL2_RESERVED_S 0 2551#define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1 2552#define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D) 2553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2554#define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW" 2555#define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2 2556#define TIMPANI_PA_LINE_AUXO_CTL_S 0 2557#define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF 2558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2559#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6 2560#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0 2561#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0 2562#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1 2563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2564#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2 2565#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3 2566#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4 2567#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30 2568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2569#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0 2570#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1 2571#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2 2572#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3 2573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2574#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2 2575#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC 2576#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0 2577#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1 2578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2579#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2 2580#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3 2581#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0 2582#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3 2583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2584#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0 2585#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2 2586#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3 2587#define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E) 2588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2589#define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW" 2590#define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe 2591#define TIMPANI_PA_AUXO_EARPA_CTL_S 0 2592#define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF 2593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2594#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6 2595#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0 2596#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4 2597#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30 2598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2599#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0 2600#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1 2601#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2 2602#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3 2603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2604#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3 2605#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8 2606#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1 2607#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0 2608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2609#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1 2610#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6 2611#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0 2612#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1 2613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2614#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2 2615#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3 2616#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0 2617#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1 2618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2619#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1 2620#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0 2621#define TIMPANI_A_PA_EARO_CTL (0x4F) 2622#define TIMPANI_PA_EARO_CTL_RWC "RW" 2623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2624#define TIMPANI_PA_EARO_CTL_POR 0x0 2625#define TIMPANI_PA_EARO_CTL_S 0 2626#define TIMPANI_PA_EARO_CTL_M 0xFF 2627#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7 2628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2629#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80 2630#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0 2631#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1 2632#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6 2633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2634#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40 2635#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0 2636#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1 2637#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3 2638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2639#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38 2640#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0 2641#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1 2642#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2 2643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2644#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3 2645#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4 2646#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5 2647#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6 2648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2649#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7 2650#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0 2651#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7 2652#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0 2653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2654#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1 2655#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2 2656#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3 2657#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4 2658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2659#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5 2660#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6 2661#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7 2662#define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50) 2663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2664#define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW" 2665#define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea 2666#define TIMPANI_PA_MASTER_BIAS_CUR_S 0 2667#define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF 2668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2669#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7 2670#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80 2671#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1 2672#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0 2673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2674#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5 2675#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60 2676#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0 2677#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1 2678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2679#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2 2680#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3 2681#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3 2682#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18 2683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2684#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 2685#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 2686#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 2687#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 2688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2689#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1 2690#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6 2691#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 2692#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 2693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2694#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 2695#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 2696#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0 2697#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1 2698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2699#define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51) 2700#define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R" 2701#define TIMPANI_PA_CLASSD_SC_STATUS_POR 0 2702#define TIMPANI_PA_CLASSD_SC_STATUS_S 0 2703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2704#define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF 2705#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7 2706#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80 2707#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0 2708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2709#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1 2710#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6 2711#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40 2712#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0 2713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2714#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 2715#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4 2716#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30 2717#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3 2718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2719#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8 2720#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0 2721#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1 2722#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2 2723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2724#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4 2725#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0 2726#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 2727#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1 2728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2729#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2 2730#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0 2731#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1 2732#define TIMPANI_A_PA_HPH_SC_STATUS (0x52) 2733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2734#define TIMPANI_PA_HPH_SC_STATUS_RWC "R" 2735#define TIMPANI_PA_HPH_SC_STATUS_POR 0 2736#define TIMPANI_PA_HPH_SC_STATUS_S 0 2737#define TIMPANI_PA_HPH_SC_STATUS_M 0xFF 2738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2739#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7 2740#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80 2741#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0 2742#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1 2743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2744#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4 2745#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70 2746#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3 2747#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8 2748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2749#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0 2750#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1 2751#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2 2752#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4 2753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2754#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0 2755#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3 2756#define TIMPANI_A_ATEST_EN (0x53) 2757#define TIMPANI_ATEST_EN_RWC "RW" 2758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2759#define TIMPANI_ATEST_EN_POR 0 2760#define TIMPANI_ATEST_EN_S 0 2761#define TIMPANI_ATEST_EN_M 0xFF 2762#define TIMPANI_ATEST_EN_ATEST_EN_S 7 2763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2764#define TIMPANI_ATEST_EN_ATEST_EN_M 0x80 2765#define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0 2766#define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1 2767#define TIMPANI_ATEST_EN_RESERVED_S 0 2768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2769#define TIMPANI_ATEST_EN_RESERVED_M 0x7F 2770#define TIMPANI_A_ATEST_TSHKADC (0x54) 2771#define TIMPANI_ATEST_TSHKADC_RWC "RW" 2772#define TIMPANI_ATEST_TSHKADC_POR 0 2773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2774#define TIMPANI_ATEST_TSHKADC_S 0 2775#define TIMPANI_ATEST_TSHKADC_M 0xFF 2776#define TIMPANI_ATEST_TSHKADC_RESERVED_S 4 2777#define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0 2778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2779#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2 2780#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC 2781#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0 2782#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1 2783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2784#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2 2785#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3 2786#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0 2787#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3 2788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2789#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0 2790#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1 2791#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2 2792#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3 2793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2794#define TIMPANI_A_ATEST_TXADC13 (0x55) 2795#define TIMPANI_ATEST_TXADC13_RWC "RW" 2796#define TIMPANI_ATEST_TXADC13_POR 0 2797#define TIMPANI_ATEST_TXADC13_S 0 2798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2799#define TIMPANI_ATEST_TXADC13_M 0xFF 2800#define TIMPANI_ATEST_TXADC13_RESERVED_S 7 2801#define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80 2802#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6 2803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2804#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40 2805#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0 2806#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1 2807#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3 2808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2809#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38 2810#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0 2811#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1 2812#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2 2813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2814#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3 2815#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4 2816#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5 2817#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6 2818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2819#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0 2820#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7 2821#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0 2822#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1 2823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2824#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2 2825#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3 2826#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4 2827#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5 2828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2829#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6 2830#define TIMPANI_A_ATEST_TXADC24 (0x56) 2831#define TIMPANI_ATEST_TXADC24_RWC "RW" 2832#define TIMPANI_ATEST_TXADC24_POR 0 2833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2834#define TIMPANI_ATEST_TXADC24_S 0 2835#define TIMPANI_ATEST_TXADC24_M 0xFF 2836#define TIMPANI_ATEST_TXADC24_RESERVED_S 7 2837#define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80 2838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2839#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6 2840#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40 2841#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0 2842#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1 2843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2844#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3 2845#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38 2846#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0 2847#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1 2848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2849#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2 2850#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3 2851#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4 2852#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5 2853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2854#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6 2855#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0 2856#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7 2857#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0 2858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2859#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1 2860#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2 2861#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3 2862#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4 2863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2864#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5 2865#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6 2866#define TIMPANI_A_ATEST_AUXPGA (0x57) 2867#define TIMPANI_ATEST_AUXPGA_RWC "RW" 2868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2869#define TIMPANI_ATEST_AUXPGA_POR 0 2870#define TIMPANI_ATEST_AUXPGA_S 0 2871#define TIMPANI_ATEST_AUXPGA_M 0xFF 2872#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7 2873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2874#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80 2875#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0 2876#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1 2877#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6 2878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2879#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40 2880#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0 2881#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1 2882#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5 2883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2884#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20 2885#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0 2886#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1 2887#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4 2888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2889#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10 2890#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0 2891#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1 2892#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3 2893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2894#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8 2895#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0 2896#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1 2897#define TIMPANI_ATEST_AUXPGA_RESERVED_S 0 2898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2899#define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7 2900#define TIMPANI_A_ATEST_CDAC (0x58) 2901#define TIMPANI_ATEST_CDAC_RWC "RW" 2902#define TIMPANI_ATEST_CDAC_POR 0 2903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2904#define TIMPANI_ATEST_CDAC_S 0 2905#define TIMPANI_ATEST_CDAC_M 0xFF 2906#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7 2907#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80 2908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2909#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0 2910#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1 2911#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6 2912#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40 2913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2914#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0 2915#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1 2916#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5 2917#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20 2918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2919#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0 2920#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1 2921#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4 2922#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10 2923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2924#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0 2925#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1 2926#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2 2927#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC 2928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2929#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0 2930#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1 2931#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2 2932#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3 2933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2934#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0 2935#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3 2936#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0 2937#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1 2938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2939#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2 2940#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3 2941#define TIMPANI_A_ATEST_IDAC (0x59) 2942#define TIMPANI_ATEST_IDAC_RWC "RW" 2943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2944#define TIMPANI_ATEST_IDAC_POR 0 2945#define TIMPANI_ATEST_IDAC_S 0 2946#define TIMPANI_ATEST_IDAC_M 0xFF 2947#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7 2948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2949#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80 2950#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1 2951#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0 2952#define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4 2953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2954#define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70 2955#define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7 2956#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6 2957#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5 2958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2959#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4 2960#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3 2961#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2 2962#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1 2963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2964#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0 2965#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3 2966#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8 2967#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1 2968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2969#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0 2970#define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0 2971#define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7 2972#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7 2973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2974#define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6 2975#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5 2976#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4 2977#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3 2978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2979#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2 2980#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1 2981#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0 2982#define TIMPANI_A_ATEST_PA1 (0x5A) 2983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2984#define TIMPANI_ATEST_PA1_RWC "RW" 2985#define TIMPANI_ATEST_PA1_POR 0 2986#define TIMPANI_ATEST_PA1_S 0 2987#define TIMPANI_ATEST_PA1_M 0xFF 2988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2989#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7 2990#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80 2991#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0 2992#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1 2993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2994#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6 2995#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40 2996#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0 2997#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1 2998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2999#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5 3000#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20 3001#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0 3002#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1 3003/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3004#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4 3005#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10 3006#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0 3007#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1 3008/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3009#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3 3010#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8 3011#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0 3012#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1 3013/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3014#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2 3015#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4 3016#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0 3017#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1 3018/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3019#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1 3020#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2 3021#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0 3022#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1 3023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3024#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0 3025#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1 3026#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0 3027#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1 3028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3029#define TIMPANI_A_ATEST_CLASSD (0x5B) 3030#define TIMPANI_ATEST_CLASSD_RWC "RW" 3031#define TIMPANI_ATEST_CLASSD_POR 0 3032#define TIMPANI_ATEST_CLASSD_S 0 3033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3034#define TIMPANI_ATEST_CLASSD_M 0xFF 3035#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4 3036#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0 3037#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0 3038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3039#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1 3040#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2 3041#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3 3042#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4 3043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3044#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5 3045#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6 3046#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7 3047#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8 3048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3049#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9 3050#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA 3051#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB 3052#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC 3053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3054#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD 3055#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE 3056#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF 3057#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0 3058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3059#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF 3060#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0 3061#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1 3062#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2 3063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3064#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3 3065#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4 3066#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5 3067#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6 3068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3069#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7 3070#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8 3071#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9 3072#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA 3073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3074#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB 3075#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC 3076#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD 3077#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE 3078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3079#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF 3080#define TIMPANI_A_ATEST_LINEO_AUXO (0x5C) 3081#define TIMPANI_ATEST_LINEO_AUXO_RWC "RW" 3082#define TIMPANI_ATEST_LINEO_AUXO_POR 0 3083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3084#define TIMPANI_ATEST_LINEO_AUXO_S 0 3085#define TIMPANI_ATEST_LINEO_AUXO_M 0xFF 3086#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7 3087#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80 3088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3089#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0 3090#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1 3091#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6 3092#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40 3093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3094#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0 3095#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1 3096#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5 3097#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20 3098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3099#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 3100#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1 3101#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4 3102#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10 3103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3104#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0 3105#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01 3106#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3 3107#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8 3108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3109#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 3110#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01 3111#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2 3112#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4 3113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3114#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0 3115#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1 3116#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1 3117#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2 3118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3119#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0 3120#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1 3121#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0 3122#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1 3123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3124#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0 3125#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1 3126#define TIMPANI_A_CDC_RESET_CTL (0x80) 3127#define TIMPANI_CDC_RESET_CTL_RWC "RW" 3128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3129#define TIMPANI_CDC_RESET_CTL_POR 0 3130#define TIMPANI_CDC_RESET_CTL_S 0 3131#define TIMPANI_CDC_RESET_CTL_M 0x7F 3132#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6 3133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3134#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40 3135#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5 3136#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20 3137#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4 3138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3139#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10 3140#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3 3141#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8 3142#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2 3143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3144#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4 3145#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1 3146#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2 3147#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0 3148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3149#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1 3150#define TIMPANI_A_CDC_RX1_CTL (0x81) 3151#define TIMPANI_CDC_RX1_CTL_RWC "RW" 3152#define TIMPANI_CDC_RX1_CTL_POR 0xc 3153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3154#define TIMPANI_CDC_RX1_CTL_S 0 3155#define TIMPANI_CDC_RX1_CTL_M 0x3F 3156#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5 3157#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20 3158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3159#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4 3160#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10 3161#define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2 3162#define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC 3163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3164#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3 3165#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1 3166#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0 3167#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1 3168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3169#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2 3170#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1 3171#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0 3172#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0 3173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3174#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1 3175#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1 3176#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0 3177#define TIMPANI_A_CDC_TX_I2S_CTL (0x82) 3178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3179#define TIMPANI_CDC_TX_I2S_CTL_RWC "RW" 3180#define TIMPANI_CDC_TX_I2S_CTL_POR 0xc 3181#define TIMPANI_CDC_TX_I2S_CTL_S 0 3182#define TIMPANI_CDC_TX_I2S_CTL_M 0x3F 3183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3184#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5 3185#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20 3186#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4 3187#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10 3188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3189#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2 3190#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC 3191#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3 3192#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1 3193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3194#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0 3195#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1 3196#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2 3197#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1 3198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3199#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0 3200#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0 3201#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1 3202#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1 3203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3204#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0 3205#define TIMPANI_A_CDC_CH_CTL (0x83) 3206#define TIMPANI_CDC_CH_CTL_RWC "RW" 3207#define TIMPANI_CDC_CH_CTL_POR 0 3208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3209#define TIMPANI_CDC_CH_CTL_S 0 3210#define TIMPANI_CDC_CH_CTL_M 0xFF 3211#define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7 3212#define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80 3213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3214#define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6 3215#define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40 3216#define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5 3217#define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20 3218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3219#define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4 3220#define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10 3221#define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3 3222#define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8 3223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3224#define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2 3225#define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4 3226#define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1 3227#define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2 3228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3229#define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0 3230#define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1 3231#define TIMPANI_A_CDC_RX1LG (0x84) 3232#define TIMPANI_CDC_RX1LG_RWC "RW" 3233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3234#define TIMPANI_CDC_RX1LG_POR 0xac 3235#define TIMPANI_CDC_RX1LG_S 0 3236#define TIMPANI_CDC_RX1LG_M 0xFF 3237#define TIMPANI_CDC_RX1LG_GAIN_S 0 3238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3239#define TIMPANI_CDC_RX1LG_GAIN_M 0xFF 3240#define TIMPANI_A_CDC_RX1RG (0x85) 3241#define TIMPANI_CDC_RX1RG_RWC "RW" 3242#define TIMPANI_CDC_RX1RG_POR 0xac 3243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3244#define TIMPANI_CDC_RX1RG_S 0 3245#define TIMPANI_CDC_RX1RG_M 0xFF 3246#define TIMPANI_CDC_RX1RG_GAIN_S 0 3247#define TIMPANI_CDC_RX1RG_GAIN_M 0xFF 3248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3249#define TIMPANI_A_CDC_TX1LG (0x86) 3250#define TIMPANI_CDC_TX1LG_RWC "RW" 3251#define TIMPANI_CDC_TX1LG_POR 0xac 3252#define TIMPANI_CDC_TX1LG_S 0 3253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3254#define TIMPANI_CDC_TX1LG_M 0xFF 3255#define TIMPANI_CDC_TX1LG_GAIN_S 0 3256#define TIMPANI_CDC_TX1LG_GAIN_M 0xFF 3257#define TIMPANI_A_CDC_TX1RG (0x87) 3258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3259#define TIMPANI_CDC_TX1RG_RWC "RW" 3260#define TIMPANI_CDC_TX1RG_POR 0xac 3261#define TIMPANI_CDC_TX1RG_S 0 3262#define TIMPANI_CDC_TX1RG_M 0xFF 3263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3264#define TIMPANI_CDC_TX1RG_GAIN_S 0 3265#define TIMPANI_CDC_TX1RG_GAIN_M 0xFF 3266#define TIMPANI_A_CDC_RX_PGA_TIMER (0x88) 3267#define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW" 3268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3269#define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff 3270#define TIMPANI_CDC_RX_PGA_TIMER_S 0 3271#define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF 3272#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0 3273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3274#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF 3275#define TIMPANI_A_CDC_TX_PGA_TIMER (0x89) 3276#define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW" 3277#define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff 3278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3279#define TIMPANI_CDC_TX_PGA_TIMER_S 0 3280#define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF 3281#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0 3282#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF 3283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3284#define TIMPANI_A_CDC_GCTL1 (0x8A) 3285#define TIMPANI_CDC_GCTL1_RWC "RW" 3286#define TIMPANI_CDC_GCTL1_POR 0x33 3287#define TIMPANI_CDC_GCTL1_S 0 3288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3289#define TIMPANI_CDC_GCTL1_M 0xFF 3290#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7 3291#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80 3292#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6 3293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3294#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40 3295#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5 3296#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20 3297#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4 3298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3299#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10 3300#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3 3301#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8 3302#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2 3303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3304#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4 3305#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1 3306#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2 3307#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0 3308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3309#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1 3310#define TIMPANI_A_CDC_TX1L_STG (0x8B) 3311#define TIMPANI_CDC_TX1L_STG_RWC "RW" 3312#define TIMPANI_CDC_TX1L_STG_POR 0xac 3313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3314#define TIMPANI_CDC_TX1L_STG_S 0 3315#define TIMPANI_CDC_TX1L_STG_M 0xFF 3316#define TIMPANI_CDC_TX1L_STG_GAIN_S 0 3317#define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF 3318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3319#define TIMPANI_A_CDC_ST_CTL (0x8C) 3320#define TIMPANI_CDC_ST_CTL_RWC "RW" 3321#define TIMPANI_CDC_ST_CTL_POR 0x55 3322#define TIMPANI_CDC_ST_CTL_S 0 3323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3324#define TIMPANI_CDC_ST_CTL_M 0xFF 3325#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7 3326#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80 3327#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6 3328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3329#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40 3330#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5 3331#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20 3332#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4 3333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3334#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10 3335#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3 3336#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8 3337#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2 3338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3339#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4 3340#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1 3341#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2 3342#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0 3343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3344#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1 3345#define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D) 3346#define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW" 3347#define TIMPANI_CDC_RX1L_DCOFFSET_POR 0 3348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3349#define TIMPANI_CDC_RX1L_DCOFFSET_S 0 3350#define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF 3351#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0 3352#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF 3353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3354#define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E) 3355#define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW" 3356#define TIMPANI_CDC_RX1R_DCOFFSET_POR 0 3357#define TIMPANI_CDC_RX1R_DCOFFSET_S 0 3358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3359#define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF 3360#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0 3361#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF 3362#define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F) 3363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3364#define TIMPANI_CDC_BYPASS_CTL1_RWC "RW" 3365#define TIMPANI_CDC_BYPASS_CTL1_POR 0x2 3366#define TIMPANI_CDC_BYPASS_CTL1_S 0 3367#define TIMPANI_CDC_BYPASS_CTL1_M 0xF 3368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3369#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3 3370#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8 3371#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2 3372#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4 3373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3374#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1 3375#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2 3376#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0 3377#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1 3378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3379#define TIMPANI_A_CDC_PDM_CONFIG (0x90) 3380#define TIMPANI_CDC_PDM_CONFIG_RWC "RW" 3381#define TIMPANI_CDC_PDM_CONFIG_POR 0 3382#define TIMPANI_CDC_PDM_CONFIG_S 0 3383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3384#define TIMPANI_CDC_PDM_CONFIG_M 0xF 3385#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0 3386#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF 3387#define TIMPANI_A_CDC_TESTMODE1 (0x91) 3388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3389#define TIMPANI_CDC_TESTMODE1_RWC "RW" 3390#define TIMPANI_CDC_TESTMODE1_POR 0 3391#define TIMPANI_CDC_TESTMODE1_S 0 3392#define TIMPANI_CDC_TESTMODE1_M 0x3F 3393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3394#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5 3395#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20 3396#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4 3397#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10 3398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3399#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3 3400#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8 3401#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2 3402#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4 3403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3404#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1 3405#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2 3406#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0 3407#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1 3408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3409#define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92) 3410#define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW" 3411#define TIMPANI_CDC_DMIC_CLK_CTL_POR 0 3412#define TIMPANI_CDC_DMIC_CLK_CTL_S 0 3413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3414#define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F 3415#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3 3416#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38 3417#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4 3418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3419#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3 3420#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2 3421#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1 3422#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0 3423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3424#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1 3425#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6 3426#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2 3427#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1 3428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3429#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0 3430#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0 3431#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1 3432#define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93) 3433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3434#define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW" 3435#define TIMPANI_CDC_ADC12_CLK_CTL_POR 0 3436#define TIMPANI_CDC_ADC12_CLK_CTL_S 0 3437#define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF 3438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3439#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6 3440#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0 3441#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2 3442#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1 3443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3444#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0 3445#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3 3446#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38 3447#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4 3448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3449#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3 3450#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2 3451#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1 3452#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0 3453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3454#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0 3455#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7 3456#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4 3457#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3 3458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3459#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2 3460#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1 3461#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0 3462#define TIMPANI_A_CDC_TX1_CTL (0x94) 3463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3464#define TIMPANI_CDC_TX1_CTL_RWC "RW" 3465#define TIMPANI_CDC_TX1_CTL_POR 0x1b 3466#define TIMPANI_CDC_TX1_CTL_S 0 3467#define TIMPANI_CDC_TX1_CTL_M 0x3F 3468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3469#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5 3470#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20 3471#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3 3472#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18 3473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3474#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3 3475#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1 3476#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0 3477#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2 3478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3479#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4 3480#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0 3481#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3 3482#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3 3483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3484#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1 3485#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0 3486#define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95) 3487#define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW" 3488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3489#define TIMPANI_CDC_ADC34_CLK_CTL_POR 0 3490#define TIMPANI_CDC_ADC34_CLK_CTL_S 0 3491#define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF 3492#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6 3493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3494#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0 3495#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2 3496#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1 3497#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0 3498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3499#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3 3500#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38 3501#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4 3502#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3 3503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3504#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2 3505#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1 3506#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0 3507#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0 3508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3509#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7 3510#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4 3511#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3 3512#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2 3513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3514#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1 3515#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0 3516#define TIMPANI_A_CDC_TX2_CTL (0x96) 3517#define TIMPANI_CDC_TX2_CTL_RWC "RW" 3518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3519#define TIMPANI_CDC_TX2_CTL_POR 0x1b 3520#define TIMPANI_CDC_TX2_CTL_S 0 3521#define TIMPANI_CDC_TX2_CTL_M 0x3F 3522#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5 3523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3524#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20 3525#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3 3526#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18 3527#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3 3528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3529#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1 3530#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0 3531#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2 3532#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4 3533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3534#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0 3535#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3 3536#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3 3537#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1 3538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3539#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0 3540#define TIMPANI_A_CDC_RX1_CLK_CTL (0x97) 3541#define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW" 3542#define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1 3543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3544#define TIMPANI_CDC_RX1_CLK_CTL_S 0 3545#define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F 3546#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2 3547#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C 3548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3549#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4 3550#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3 3551#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2 3552#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1 3553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3554#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0 3555#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0 3556#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3 3557#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2 3558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3559#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1 3560#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0 3561#define TIMPANI_A_CDC_RX2_CLK_CTL (0x98) 3562#define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW" 3563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3564#define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2 3565#define TIMPANI_CDC_RX2_CLK_CTL_S 0 3566#define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F 3567#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2 3568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3569#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C 3570#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4 3571#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3 3572#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2 3573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3574#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1 3575#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0 3576#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0 3577#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3 3578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3579#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2 3580#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1 3581#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0 3582#define TIMPANI_A_CDC_DEC_ADC_SEL (0x99) 3583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3584#define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW" 3585#define TIMPANI_CDC_DEC_ADC_SEL_POR 0 3586#define TIMPANI_CDC_DEC_ADC_SEL_S 0 3587#define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF 3588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3589#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6 3590#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0 3591#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3 3592#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2 3593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3594#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1 3595#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0 3596#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4 3597#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30 3598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3599#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3 3600#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2 3601#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1 3602#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0 3603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3604#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2 3605#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC 3606#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3 3607#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2 3608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3609#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1 3610#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0 3611#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0 3612#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3 3613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3614#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3 3615#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2 3616#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1 3617#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0 3618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3619#define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A) 3620#define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW" 3621#define TIMPANI_CDC_ANC_INPUT_MUX_POR 0 3622#define TIMPANI_CDC_ANC_INPUT_MUX_S 0 3623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3624#define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF 3625#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6 3626#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0 3627#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3 3628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3629#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2 3630#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1 3631#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0 3632#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4 3633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3634#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30 3635#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3 3636#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2 3637#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1 3638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3639#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0 3640#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2 3641#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC 3642#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3 3643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3644#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2 3645#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1 3646#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0 3647#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0 3648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3649#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3 3650#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3 3651#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2 3652#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1 3653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3654#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0 3655#define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B) 3656#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW" 3657#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0 3658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3659#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0 3660#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1 3661#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0 3662#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1 3663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3664#define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C) 3665#define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW" 3666#define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0 3667#define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0 3668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3669#define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3 3670#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1 3671#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2 3672#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1 3673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3674#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0 3675#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0 3676#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1 3677#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1 3678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3679#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0 3680#define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E) 3681#define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW" 3682#define TIMPANI_CLK_DIV_SYNC_CTL_POR 0 3683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3684#define TIMPANI_CLK_DIV_SYNC_CTL_S 0 3685#define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3 3686#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1 3687#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2 3688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3689#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0 3690#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1 3691#define TIMPANI_A_CDC_ADC_CLK_EN (0x9F) 3692#define TIMPANI_CDC_ADC_CLK_EN_RWC "RW" 3693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3694#define TIMPANI_CDC_ADC_CLK_EN_POR 0 3695#define TIMPANI_CDC_ADC_CLK_EN_S 0 3696#define TIMPANI_CDC_ADC_CLK_EN_M 0xF 3697#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3 3698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3699#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8 3700#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2 3701#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4 3702#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1 3703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3704#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2 3705#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0 3706#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1 3707#define TIMPANI_A_CDC_ST_MIXING (0xA0) 3708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3709#define TIMPANI_CDC_ST_MIXING_RWC "RW" 3710#define TIMPANI_CDC_ST_MIXING_POR 0 3711#define TIMPANI_CDC_ST_MIXING_S 0 3712#define TIMPANI_CDC_ST_MIXING_M 0xF 3713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3714#define TIMPANI_CDC_ST_MIXING_TX2_R_S 3 3715#define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8 3716#define TIMPANI_CDC_ST_MIXING_TX2_L_S 2 3717#define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4 3718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3719#define TIMPANI_CDC_ST_MIXING_TX1_R_S 1 3720#define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2 3721#define TIMPANI_CDC_ST_MIXING_TX1_L_S 0 3722#define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1 3723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3724#define TIMPANI_A_CDC_RX2_CTL (0xA1) 3725#define TIMPANI_CDC_RX2_CTL_RWC "RW" 3726#define TIMPANI_CDC_RX2_CTL_POR 0xc 3727#define TIMPANI_CDC_RX2_CTL_S 0 3728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3729#define TIMPANI_CDC_RX2_CTL_M 0x3F 3730#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5 3731#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20 3732#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4 3733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3734#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10 3735#define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2 3736#define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC 3737#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3 3738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3739#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1 3740#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0 3741#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1 3742#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2 3743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3744#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1 3745#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0 3746#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0 3747#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1 3748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3749#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1 3750#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0 3751#define TIMPANI_A_CDC_ARB_CLK_EN (0xA2) 3752#define TIMPANI_CDC_ARB_CLK_EN_RWC "RW" 3753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3754#define TIMPANI_CDC_ARB_CLK_EN_POR 0 3755#define TIMPANI_CDC_ARB_CLK_EN_S 0 3756#define TIMPANI_CDC_ARB_CLK_EN_M 0x1 3757#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0 3758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3759#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1 3760#define TIMPANI_A_CDC_I2S_CTL2 (0xA3) 3761#define TIMPANI_CDC_I2S_CTL2_RWC "RW" 3762#define TIMPANI_CDC_I2S_CTL2_POR 0 3763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3764#define TIMPANI_CDC_I2S_CTL2_S 0 3765#define TIMPANI_CDC_I2S_CTL2_M 0x3F 3766#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3 3767#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38 3768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3769#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4 3770#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3 3771#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2 3772#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1 3773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3774#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0 3775#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2 3776#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4 3777#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1 3778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3779#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2 3780#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0 3781#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1 3782#define TIMPANI_A_CDC_RX2LG (0xA4) 3783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3784#define TIMPANI_CDC_RX2LG_RWC "RW" 3785#define TIMPANI_CDC_RX2LG_POR 0xac 3786#define TIMPANI_CDC_RX2LG_S 0 3787#define TIMPANI_CDC_RX2LG_M 0xFF 3788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3789#define TIMPANI_CDC_RX2LG_GAIN_S 0 3790#define TIMPANI_CDC_RX2LG_GAIN_M 0xFF 3791#define TIMPANI_A_CDC_RX2RG (0xA5) 3792#define TIMPANI_CDC_RX2RG_RWC "RW" 3793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3794#define TIMPANI_CDC_RX2RG_POR 0xac 3795#define TIMPANI_CDC_RX2RG_S 0 3796#define TIMPANI_CDC_RX2RG_M 0xFF 3797#define TIMPANI_CDC_RX2RG_GAIN_S 0 3798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3799#define TIMPANI_CDC_RX2RG_GAIN_M 0xFF 3800#define TIMPANI_A_CDC_TX2LG (0xA6) 3801#define TIMPANI_CDC_TX2LG_RWC "RW" 3802#define TIMPANI_CDC_TX2LG_POR 0xac 3803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3804#define TIMPANI_CDC_TX2LG_S 0 3805#define TIMPANI_CDC_TX2LG_M 0xFF 3806#define TIMPANI_CDC_TX2LG_GAIN_S 0 3807#define TIMPANI_CDC_TX2LG_GAIN_M 0xFF 3808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3809#define TIMPANI_A_CDC_TX2RG (0xA7) 3810#define TIMPANI_CDC_TX2RG_RWC "RW" 3811#define TIMPANI_CDC_TX2RG_POR 0xac 3812#define TIMPANI_CDC_TX2RG_S 0 3813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3814#define TIMPANI_CDC_TX2RG_M 0xFF 3815#define TIMPANI_CDC_TX2RG_GAIN_S 0 3816#define TIMPANI_CDC_TX2RG_GAIN_M 0xFF 3817#define TIMPANI_A_CDC_DMIC_MUX (0xA8) 3818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3819#define TIMPANI_CDC_DMIC_MUX_RWC "RW" 3820#define TIMPANI_CDC_DMIC_MUX_POR 0 3821#define TIMPANI_CDC_DMIC_MUX_S 0 3822#define TIMPANI_CDC_DMIC_MUX_M 0xFF 3823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3824#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6 3825#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0 3826#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 3827#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 3828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3829#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 3830#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 3831#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4 3832#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30 3833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3834#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 3835#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 3836#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 3837#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 3838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3839#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2 3840#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC 3841#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 3842#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 3843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3844#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 3845#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 3846#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0 3847#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3 3848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3849#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 3850#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 3851#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 3852#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 3853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3854#define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9) 3855#define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW" 3856#define TIMPANI_CDC_ARB_CLK_CTL_POR 0 3857#define TIMPANI_CDC_ARB_CLK_CTL_S 0 3858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3859#define TIMPANI_CDC_ARB_CLK_CTL_M 0x3 3860#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0 3861#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3 3862#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0 3863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3864#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1 3865#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2 3866#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3 3867#define TIMPANI_A_CDC_GCTL2 (0xAA) 3868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3869#define TIMPANI_CDC_GCTL2_RWC "RW" 3870#define TIMPANI_CDC_GCTL2_POR 0x33 3871#define TIMPANI_CDC_GCTL2_S 0 3872#define TIMPANI_CDC_GCTL2_M 0xFF 3873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3874#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7 3875#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80 3876#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6 3877#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40 3878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3879#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5 3880#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20 3881#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4 3882#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10 3883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3884#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3 3885#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8 3886#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2 3887#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4 3888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3889#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1 3890#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2 3891#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0 3892#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1 3893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3894#define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB) 3895#define TIMPANI_CDC_BYPASS_CTL2_RWC "RW" 3896#define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D 3897#define TIMPANI_CDC_BYPASS_CTL2_S 0 3898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3899#define TIMPANI_CDC_BYPASS_CTL2_M 0x3F 3900#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5 3901#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20 3902#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4 3903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3904#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10 3905#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3 3906#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8 3907#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2 3908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3909#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4 3910#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1 3911#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2 3912#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0 3913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3914#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1 3915#define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC) 3916#define TIMPANI_CDC_BYPASS_CTL3_RWC "RW" 3917#define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D 3918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3919#define TIMPANI_CDC_BYPASS_CTL3_S 0 3920#define TIMPANI_CDC_BYPASS_CTL3_M 0x3F 3921#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5 3922#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20 3923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3924#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4 3925#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10 3926#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3 3927#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8 3928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3929#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2 3930#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4 3931#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1 3932#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2 3933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3934#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0 3935#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1 3936#define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD) 3937#define TIMPANI_CDC_BYPASS_CTL4_RWC "RW" 3938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3939#define TIMPANI_CDC_BYPASS_CTL4_POR 0x2 3940#define TIMPANI_CDC_BYPASS_CTL4_S 0 3941#define TIMPANI_CDC_BYPASS_CTL4_M 0xF 3942#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3 3943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3944#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8 3945#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2 3946#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4 3947#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1 3948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3949#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2 3950#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0 3951#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1 3952#define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE) 3953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3954#define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW" 3955#define TIMPANI_CDC_RX2L_DCOFFSET_POR 0 3956#define TIMPANI_CDC_RX2L_DCOFFSET_S 0 3957#define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF 3958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3959#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0 3960#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF 3961#define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF) 3962#define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW" 3963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3964#define TIMPANI_CDC_RX2R_DCOFFSET_POR 0 3965#define TIMPANI_CDC_RX2R_DCOFFSET_S 0 3966#define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF 3967#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0 3968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3969#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF 3970#define TIMPANI_A_CDC_RX_MIX_CTL (0xB0) 3971#define TIMPANI_CDC_RX_MIX_CTL_RWC "RW" 3972#define TIMPANI_CDC_RX_MIX_CTL_POR 0 3973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3974#define TIMPANI_CDC_RX_MIX_CTL_S 0 3975#define TIMPANI_CDC_RX_MIX_CTL_M 0x3 3976#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1 3977#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2 3978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3979#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0 3980#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1 3981#define TIMPANI_A_CDC_SPARE_CTL (0xB1) 3982#define TIMPANI_CDC_SPARE_CTL_RWC "RW" 3983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3984#define TIMPANI_CDC_SPARE_CTL_POR 0 3985#define TIMPANI_CDC_SPARE_CTL_S 0 3986#define TIMPANI_CDC_SPARE_CTL_M 0xFF 3987#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0 3988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3989#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF 3990#define TIMPANI_A_CDC_TESTMODE2 (0xB2) 3991#define TIMPANI_CDC_TESTMODE2_RWC "RW" 3992#define TIMPANI_CDC_TESTMODE2_POR 0 3993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3994#define TIMPANI_CDC_TESTMODE2_S 0 3995#define TIMPANI_CDC_TESTMODE2_M 0x1F 3996#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4 3997#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10 3998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3999#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3 4000#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8 4001#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2 4002#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4 4003/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4004#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1 4005#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2 4006#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0 4007#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1 4008/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4009#define TIMPANI_A_CDC_PDM_OE (0xB3) 4010#define TIMPANI_CDC_PDM_OE_RWC "RW" 4011#define TIMPANI_CDC_PDM_OE_POR 0 4012#define TIMPANI_CDC_PDM_OE_S 0 4013/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4014#define TIMPANI_CDC_PDM_OE_M 0x3F 4015#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5 4016#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20 4017#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4 4018/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4019#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10 4020#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3 4021#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8 4022#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2 4023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4024#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4 4025#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1 4026#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2 4027#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0 4028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4029#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1 4030#define TIMPANI_A_CDC_TX1R_STG (0xB4) 4031#define TIMPANI_CDC_TX1R_STG_RWC "RW" 4032#define TIMPANI_CDC_TX1R_STG_POR 0xac 4033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4034#define TIMPANI_CDC_TX1R_STG_S 0 4035#define TIMPANI_CDC_TX1R_STG_M 0xFF 4036#define TIMPANI_CDC_TX1R_STG_GAIN_S 0 4037#define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF 4038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4039#define TIMPANI_A_CDC_TX2L_STG (0xB5) 4040#define TIMPANI_CDC_TX2L_STG_RWC "RW" 4041#define TIMPANI_CDC_TX2L_STG_POR 0xac 4042#define TIMPANI_CDC_TX2L_STG_S 0 4043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4044#define TIMPANI_CDC_TX2L_STG_M 0xFF 4045#define TIMPANI_CDC_TX2L_STG_GAIN_S 0 4046#define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF 4047#define TIMPANI_A_CDC_TX2R_STG (0xB6) 4048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4049#define TIMPANI_CDC_TX2R_STG_RWC "RW" 4050#define TIMPANI_CDC_TX2R_STG_POR 0xac 4051#define TIMPANI_CDC_TX2R_STG_S 0 4052#define TIMPANI_CDC_TX2R_STG_M 0xFF 4053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4054#define TIMPANI_CDC_TX2R_STG_GAIN_S 0 4055#define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF 4056#define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7) 4057#define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW" 4058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4059#define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0 4060#define TIMPANI_CDC_ARB_BYPASS_CTL_S 0 4061#define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1 4062#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0 4063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4064#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1 4065#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1 4066#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0 4067#define TIMPANI_A_CDC_ANC1_CTL1 (0xC0) 4068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4069#define TIMPANI_CDC_ANC1_CTL1_RWC "RW" 4070#define TIMPANI_CDC_ANC1_CTL1_POR 0 4071#define TIMPANI_CDC_ANC1_CTL1_S 0 4072#define TIMPANI_CDC_ANC1_CTL1_M 0x3F 4073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4074#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5 4075#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20 4076#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1 4077#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0 4078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4079#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4 4080#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10 4081#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1 4082#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0 4083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4084#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3 4085#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8 4086#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1 4087#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0 4088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4089#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2 4090#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4 4091#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1 4092#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0 4093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4094#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1 4095#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2 4096#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1 4097#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0 4098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4099#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0 4100#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1 4101#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1 4102#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0 4103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4104#define TIMPANI_A_CDC_ANC1_CTL2 (0xC1) 4105#define TIMPANI_CDC_ANC1_CTL2_RWC "RW" 4106#define TIMPANI_CDC_ANC1_CTL2_POR 0 4107#define TIMPANI_CDC_ANC1_CTL2_S 0 4108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4109#define TIMPANI_CDC_ANC1_CTL2_M 0x1F 4110#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0 4111#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F 4112#define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2) 4113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4114#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW" 4115#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0 4116#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0 4117#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF 4118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4119#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4 4120#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0 4121#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0 4122#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF 4123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4124#define TIMPANI_A_CDC_ANC1_RX_NS (0xC3) 4125#define TIMPANI_CDC_ANC1_RX_NS_RWC "RW" 4126#define TIMPANI_CDC_ANC1_RX_NS_POR 0x1 4127#define TIMPANI_CDC_ANC1_RX_NS_S 0 4128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4129#define TIMPANI_CDC_ANC1_RX_NS_M 0x7 4130#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2 4131#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4 4132#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1 4133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4134#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2 4135#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0 4136#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1 4137#define TIMPANI_A_CDC_ANC1_SPARE (0xC4) 4138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4139#define TIMPANI_CDC_ANC1_SPARE_RWC "RW" 4140#define TIMPANI_CDC_ANC1_SPARE_POR 0 4141#define TIMPANI_CDC_ANC1_SPARE_S 0 4142#define TIMPANI_CDC_ANC1_SPARE_M 0xFF 4143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4144#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0 4145#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF 4146#define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5) 4147#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW" 4148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4149#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0 4150#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0 4151#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F 4152#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0 4153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4154#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F 4155#define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6) 4156#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW" 4157#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0 4158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4159#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0 4160#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1 4161#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0 4162#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1 4163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4164#define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7) 4165#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW" 4166#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0 4167#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0 4168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4169#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF 4170#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0 4171#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF 4172#define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8) 4173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4174#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW" 4175#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0 4176#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0 4177#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3 4178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4179#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1 4180#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2 4181#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 4182#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 4183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4184#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0 4185#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1 4186#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1 4187#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0 4188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4189#define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9) 4190#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW" 4191#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0 4192#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0 4193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4194#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF 4195#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0 4196#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF 4197#define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA) 4198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4199#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW" 4200#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0 4201#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0 4202#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF 4203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4204#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0 4205#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF 4206#define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB) 4207#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW" 4208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4209#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0 4210#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0 4211#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF 4212#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0 4213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4214#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF 4215#define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC) 4216#define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW" 4217#define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0 4218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4219#define TIMPANI_CDC_ANC1_SCALE_PTR_S 0 4220#define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7 4221#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0 4222#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7 4223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4224#define TIMPANI_A_CDC_ANC1_SCALE (0xCD) 4225#define TIMPANI_CDC_ANC1_SCALE_RWC "RW" 4226#define TIMPANI_CDC_ANC1_SCALE_POR 0 4227#define TIMPANI_CDC_ANC1_SCALE_S 0 4228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4229#define TIMPANI_CDC_ANC1_SCALE_M 0xFF 4230#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0 4231#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF 4232#define TIMPANI_A_CDC_ANC1_DEBUG (0xCE) 4233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4234#define TIMPANI_CDC_ANC1_DEBUG_RWC "RW" 4235#define TIMPANI_CDC_ANC1_DEBUG_POR 0 4236#define TIMPANI_CDC_ANC1_DEBUG_S 0 4237#define TIMPANI_CDC_ANC1_DEBUG_M 0xF 4238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4239#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0 4240#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF 4241#define TIMPANI_A_CDC_ANC2_CTL1 (0xD0) 4242#define TIMPANI_CDC_ANC2_CTL1_RWC "RW" 4243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4244#define TIMPANI_CDC_ANC2_CTL1_POR 0 4245#define TIMPANI_CDC_ANC2_CTL1_S 0 4246#define TIMPANI_CDC_ANC2_CTL1_M 0x3F 4247#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5 4248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4249#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20 4250#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1 4251#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0 4252#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4 4253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4254#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10 4255#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1 4256#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0 4257#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3 4258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4259#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8 4260#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1 4261#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0 4262#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2 4263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4264#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4 4265#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1 4266#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0 4267#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1 4268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4269#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2 4270#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1 4271#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0 4272#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0 4273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4274#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1 4275#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1 4276#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0 4277#define TIMPANI_A_CDC_ANC2_CTL2 (0xD1) 4278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4279#define TIMPANI_CDC_ANC2_CTL2_RWC "RW" 4280#define TIMPANI_CDC_ANC2_CTL2_POR 0 4281#define TIMPANI_CDC_ANC2_CTL2_S 0 4282#define TIMPANI_CDC_ANC2_CTL2_M 0x1F 4283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4284#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0 4285#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F 4286#define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2) 4287#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW" 4288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4289#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0 4290#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0 4291#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF 4292#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4 4293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4294#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0 4295#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0 4296#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF 4297#define TIMPANI_A_CDC_ANC2_RX_NS (0xD3) 4298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4299#define TIMPANI_CDC_ANC2_RX_NS_RWC "RW" 4300#define TIMPANI_CDC_ANC2_RX_NS_POR 0x1 4301#define TIMPANI_CDC_ANC2_RX_NS_S 0 4302#define TIMPANI_CDC_ANC2_RX_NS_M 0x7 4303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4304#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2 4305#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4 4306#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1 4307#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2 4308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4309#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0 4310#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1 4311#define TIMPANI_A_CDC_ANC2_SPARE (0xD4) 4312#define TIMPANI_CDC_ANC2_SPARE_RWC "RW" 4313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4314#define TIMPANI_CDC_ANC2_SPARE_POR 0 4315#define TIMPANI_CDC_ANC2_SPARE_S 0 4316#define TIMPANI_CDC_ANC2_SPARE_M 0xFF 4317#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0 4318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4319#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF 4320#define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5) 4321#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW" 4322#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0 4323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4324#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0 4325#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F 4326#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0 4327#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F 4328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4329#define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6) 4330#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW" 4331#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0 4332#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0 4333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4334#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1 4335#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0 4336#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1 4337#define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7) 4338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4339#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW" 4340#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0 4341#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0 4342#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF 4343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4344#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0 4345#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF 4346#define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8) 4347#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW" 4348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4349#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0 4350#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0 4351#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3 4352#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1 4353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4354#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2 4355#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 4356#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 4357#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0 4358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4359#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1 4360#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1 4361#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0 4362#define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9) 4363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4364#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW" 4365#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0 4366#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0 4367#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF 4368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4369#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0 4370#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF 4371#define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA) 4372#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW" 4373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4374#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0 4375#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0 4376#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF 4377#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0 4378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4379#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF 4380#define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB) 4381#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW" 4382#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0 4383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4384#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0 4385#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF 4386#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0 4387#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF 4388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4389#define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC) 4390#define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW" 4391#define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0 4392#define TIMPANI_CDC_ANC2_SCALE_PTR_S 0 4393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4394#define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7 4395#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0 4396#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7 4397#define TIMPANI_A_CDC_ANC2_SCALE (0xDD) 4398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4399#define TIMPANI_CDC_ANC2_SCALE_RWC "RW" 4400#define TIMPANI_CDC_ANC2_SCALE_POR 0 4401#define TIMPANI_CDC_ANC2_SCALE_S 0 4402#define TIMPANI_CDC_ANC2_SCALE_M 0xFF 4403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4404#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0 4405#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF 4406#define TIMPANI_A_CDC_ANC2_DEBUG (0xDE) 4407#define TIMPANI_CDC_ANC2_DEBUG_RWC "RW" 4408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4409#define TIMPANI_CDC_ANC2_DEBUG_POR 0 4410#define TIMPANI_CDC_ANC2_DEBUG_S 0 4411#define TIMPANI_CDC_ANC2_DEBUG_M 0xF 4412#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0 4413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4414#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF 4415#define TIMPANI_A_CDC_LINE_L_AVOL (0xE0) 4416#define TIMPANI_CDC_LINE_L_AVOL_RWC "RW" 4417#define TIMPANI_CDC_LINE_L_AVOL_POR 0xac 4418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4419#define TIMPANI_CDC_LINE_L_AVOL_S 0 4420#define TIMPANI_CDC_LINE_L_AVOL_M 0xFF 4421#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2 4422#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC 4423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4424#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0 4425#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3 4426#define TIMPANI_A_CDC_LINE_R_AVOL (0xE1) 4427#define TIMPANI_CDC_LINE_R_AVOL_RWC "RW" 4428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4429#define TIMPANI_CDC_LINE_R_AVOL_POR 0xac 4430#define TIMPANI_CDC_LINE_R_AVOL_S 0 4431#define TIMPANI_CDC_LINE_R_AVOL_M 0xFF 4432#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2 4433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4434#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC 4435#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0 4436#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3 4437#define TIMPANI_A_CDC_HPH_L_AVOL (0xE2) 4438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4439#define TIMPANI_CDC_HPH_L_AVOL_RWC "RW" 4440#define TIMPANI_CDC_HPH_L_AVOL_POR 0xae 4441#define TIMPANI_CDC_HPH_L_AVOL_S 0 4442#define TIMPANI_CDC_HPH_L_AVOL_M 0xFF 4443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4444#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2 4445#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC 4446#define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1 4447#define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2 4448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4449#define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1 4450#define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0 4451#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0 4452#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1 4453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4454#define TIMPANI_A_CDC_HPH_R_AVOL (0xE3) 4455#define TIMPANI_CDC_HPH_R_AVOL_RWC "RW" 4456#define TIMPANI_CDC_HPH_R_AVOL_POR 0xae 4457#define TIMPANI_CDC_HPH_R_AVOL_S 0 4458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4459#define TIMPANI_CDC_HPH_R_AVOL_M 0xFF 4460#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2 4461#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC 4462#define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1 4463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4464#define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2 4465#define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1 4466#define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0 4467#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0 4468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4469#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1 4470#define TIMPANI_A_CDC_COMP_CTL1 (0xE4) 4471#define TIMPANI_CDC_COMP_CTL1_RWC "RW" 4472#define TIMPANI_CDC_COMP_CTL1_POR 0 4473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4474#define TIMPANI_CDC_COMP_CTL1_S 0 4475#define TIMPANI_CDC_COMP_CTL1_M 0xFF 4476#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7 4477#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80 4478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4479#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6 4480#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40 4481#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5 4482#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20 4483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4484#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4 4485#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10 4486#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3 4487#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8 4488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4489#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2 4490#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4 4491#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1 4492#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2 4493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4494#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0 4495#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1 4496#define TIMPANI_A_CDC_COMP_CTL2 (0xE5) 4497#define TIMPANI_CDC_COMP_CTL2_RWC "RW" 4498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4499#define TIMPANI_CDC_COMP_CTL2_POR 0xe 4500#define TIMPANI_CDC_COMP_CTL2_S 0 4501#define TIMPANI_CDC_COMP_CTL2_M 0xF 4502#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2 4503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4504#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC 4505#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0 4506#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3 4507#define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6) 4508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4509#define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW" 4510#define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9 4511#define TIMPANI_CDC_COMP_PEAK_METER_S 0 4512#define TIMPANI_CDC_COMP_PEAK_METER_M 0xF 4513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4514#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0 4515#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF 4516#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7) 4517#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW" 4518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4519#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7 4520#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0 4521#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF 4522#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0 4523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4524#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF 4525#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8) 4526#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW" 4527#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28 4528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4529#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0 4530#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF 4531#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0 4532#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF 4533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4534#define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9) 4535#define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW" 4536#define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b 4537#define TIMPANI_CDC_COMP_ZONE_SELECT_S 0 4538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4539#define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F 4540#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3 4541#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78 4542#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0 4543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4544#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7 4545#define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA) 4546#define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW" 4547#define TIMPANI_CDC_COMP_ZC_MSB_POR 0 4548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4549#define TIMPANI_CDC_COMP_ZC_MSB_S 0 4550#define TIMPANI_CDC_COMP_ZC_MSB_M 0x7 4551#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0 4552#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7 4553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4554#define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB) 4555#define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW" 4556#define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f 4557#define TIMPANI_CDC_COMP_ZC_LSB_S 0 4558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4559#define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF 4560#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0 4561#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF 4562#define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC) 4563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4564#define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW" 4565#define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b 4566#define TIMPANI_CDC_COMP_SHUT_DOWN_S 0 4567#define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F 4568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4569#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3 4570#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38 4571#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0 4572#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7 4573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4574#define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED) 4575#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW" 4576#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0 4577#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0 4578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4579#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF 4580#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3 4581#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8 4582#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2 4583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4584#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4 4585#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1 4586#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2 4587#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0 4588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4589#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1 4590#define TIMPANI_A_CDC_COMP_HALT (0xEE) 4591#define TIMPANI_CDC_COMP_HALT_RWC "RW" 4592#define TIMPANI_CDC_COMP_HALT_POR 0 4593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4594#define TIMPANI_CDC_COMP_HALT_S 0 4595#define TIMPANI_CDC_COMP_HALT_M 0x1 4596#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0 4597#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1 4598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4599#endif 4600