| ebc56bd68743dfffcfeb04f938181b18efaed85c |
|
20-Aug-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix Arm64 inline locking code
The Arm64 monitor enter code was incorrectly comparing the
thread ID to zero rather than the lock value to determine if the
inline fast path was doable. As a result, we ended up always
using the out-of-line case.
This fix delivers a 6% improvement to DeltaBlue.
b/16707253
Change-Id: I499530da84beecf1f3f5c5ebb666e3eb12599ac0
|
| 03c9785a8a6d712775cf406c4371d0227c44148f |
|
14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Reduce stack usage for overflow checks""
Fixes stack protection issue.
Fixes mac build issue.
This reverts commit 83b1940e6482b9d8feba5c492507735686650ea5.
Change-Id: I7ba17252882b23a740bcda2ea94aacf398255406
|
| ab9a0dbf3b63d517da5278b8298e6cd316e09f68 |
|
14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Reduce stack usage for overflow checks"
This reverts commit 63c051a540e6dfc806f656b88ac3a63e99395429.
Change-Id: I282a048994fcd130fe73842b16c21680053c592f
|
| 63c051a540e6dfc806f656b88ac3a63e99395429 |
|
26-Jul-2014 |
Dave Allison <dallison@google.com> |
Reduce stack usage for overflow checks
This reduces the stack space reserved for overflow checks to 12K, split
into an 8K gap and a 4K protected region. GC needs over 8K when running
in a stack overflow situation.
Also prevents signal runaway by detecting a signal inside code that
resulted from a signal handler invokation. And adds a max signal count to
the SignalTest to prevent it running forever.
Also reduces the number of iterations for the InterfaceTest as this was
taking (almost) forever with the --trace option on run-test.
Bug: 15435566
Change-Id: Id4fd46f22d52d42a9eb431ca07948673e8fda694
Conflicts:
compiler/optimizing/code_generator_x86_64.cc
runtime/arch/x86/fault_handler_x86.cc
runtime/arch/x86_64/quick_entrypoints_x86_64.S
|
| 83b1940e6482b9d8feba5c492507735686650ea5 |
|
14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Reduce stack usage for overflow checks"
This reverts commit 63c051a540e6dfc806f656b88ac3a63e99395429.
Change-Id: I282a048994fcd130fe73842b16c21680053c592f
|
| 8c18c2aaedb171f9b03ec49c94b0e33449dc411b |
|
06-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Generate chained compare-and-branch for short switches
Refactor Mir2Lir to generate chained compare-and-branch sequences
for short switches on all architectures.
Bug: 16241558
(cherry picked from commit 48971b3242e5126bcd800cc9c68df64596b43d13)
Change-Id: I0bb3071b8676523e90e0258e9b0e3fd69c1237f4
|
| 7204c04dd86ae8ce05690e38737b2abf017a0a69 |
|
11-Jun-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
AArch64: Implicit StackOverflow/NPE/Suspend checks.
This implements implicit stack overflow checks and null pointer exceptions
for AArch64. Suspend checks are implemented but not switched on yet.
Bug: 16256184
Change-Id: I2eb076f2c0c9d94793d5a898fea49cf409b4eb66
Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
|
| f29ecd69af2743a425314baa4abd6c44d8d88649 |
|
29-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework ARM64 entry sequence
Try to fold one sub of SP in the ARM64 entry sequence. When the
framesize is small, generate a sub over the full frame-size, and
adjust the spill offsets accordingly. If the framesize is too
large, use a pre-indexed store and fill upwards from there.
Change-Id: I1c15ac6276fb62b8164372de02fd92437f605938
|
| b551fdcda9eb128c80de37c4fb978968bec6d4b3 |
|
25-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Clean up CalleeSaveMethod frame and the use of temp registers.
CalleeSaveMethod frame size changes :
SaveAll : 368 -> 176
RefOnly : 176 -> 96
RefsAndArgs : 304 -> 224
JNI register spill size changes :
160 -> 88
In the transition assembly, use registers following the rules:
1. x0-x7 as temp/argument registers.
2. IP0, IP1 as scratch registers.
3. After correct type of callee-save-frame has been setup, all registers
are scratch-able(probably except xSELF and xSUSPEND).
4. When restore callee-save-frame, IP0 and IP1 should be untouched.
5. From C to managed code, we assume all callee save register in AAPCS
will be restored by managed code except x19(SUSPEND).
In quick compiler:
1. Use IP0, IP1 as scratch register.
2. Use IP1 as hidden argument register(IP0 will be scratched by
trampoline.)
Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
|
| 0f45f22eb3c52f0ece4c56989180e79c6680d825 |
|
15-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Throw StackOverflowError in native code
Initialize stack-overflow errors in native code to be able to reduce
the preserved area size of the stack.
Includes a refactoring away from constexpr in instruction_set.h to allow
for easy changing of the values.
Bug: 16256184
(cherry picked from commit 7ea6f79bbddd69d5db86a8656a31aaaf64ae2582)
Change-Id: I117cc8485f43da5f0a470f0f5e5b3dc3b5a06246
|
| 7ea6f79bbddd69d5db86a8656a31aaaf64ae2582 |
|
15-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Throw StackOverflowError in native code
Initialize stack-overflow errors in native code to be able to reduce
the preserved area size of the stack.
Includes a refactoring away from constexpr in instruction_set.h to allow
for easy changing of the values.
Change-Id: I117cc8485f43da5f0a470f0f5e5b3dc3b5a06246
|
| 147eb41b53729ec8d5c188d1cac90964a51afb8a |
|
11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86""""
This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1.
Bug: 16256184
Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73
Conflicts:
compiler/dex/quick/arm64/target_arm64.cc
compiler/image_test.cc
runtime/fault_handler.cc
|
| 69dfe51b684dd9d510dbcb63295fe180f998efde |
|
11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86""""
This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1.
Bug: 16256184
Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73
|
| 48f5c47907654350ce30a8dfdda0e977f5d3d39f |
|
27-Jun-2014 |
Hans Boehm <hboehm@google.com> |
Replace memory barriers to better reflect Java needs.
Replaces barriers that enforce ordering of one access type
(e.g. Load) with respect to another (e.g. store) with more general
ones that better reflect both Java requirements and actual hardware
barrier/fence instructions. The old code was inconsistent and
unclear about which barriers implied which others. Sometimes
multiple barriers were generated and then eliminated;
sometimes it was assumed that certain barriers implied others.
The new barriers closely parallel those in C++11, though, for now,
we use something closer to the old naming.
Bug: 14685856
Change-Id: Ie1c80afe3470057fc6f2b693a9831dfe83add831
|
| ccc60264229ac96d798528d2cb7dbbdd0deca993 |
|
05-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework TargetReg(symbolic_reg, wide)
Make the standard implementation in Mir2Lir and the specialized one
in the x86 backend return a pair when wide = "true". Introduce
WideKind enumeration to improve code readability. Simplify generic
code based on this implementation.
Change-Id: I670d45aa2572eedfdc77ac763e6486c83f8e26b4
|
| 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e |
|
10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Add implicit null and stack checks for x86""
Fixes x86_64 cross compile issue. Removes command line options
and property to set implicit checks - this is hard coded now.
This reverts commit 3d14eb620716e92c21c4d2c2d11a95be53319791.
Change-Id: I5404473b5aaf1a9c68b7181f5952cb174d93a90d
|
| 0025a86411145eb7cd4971f9234fc21c7b4aced1 |
|
11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Revert "Add implicit null and stack checks for x86"""
Broke the build.
This reverts commit 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e.
Change-Id: I9df0e7446ff0913a0e1276a558b2ccf6c8f4c949
|
| b5860fb459f1ed71f39d8a87b45bee6727d79fe8 |
|
22-Jun-2014 |
buzbee <buzbee@google.com> |
Register promotion support for 64-bit targets
Not sufficiently tested for 64-bit targets, but should be
fairly close.
A significant amount of refactoring could stil be done, (in
later CLs).
With this change we are not making any changes to the vmap
scheme. As a result, it is a requirement that if a vreg
is promoted to both a 32-bit view and the low half of a
64-bit view it must share the same physical register. We
may change this restriction later on to allow for more flexibility
for 32-bit Arm.
For example, if v4, v5, v4/v5 and v5/v6 are all hot enough to
promote, we'd end up with something like:
v4 (as an int) -> r10
v4/v5 (as a long) -> r10
v5 (as an int) -> r11
v5/v6 (as a long) -> r11
Fix a couple of ARM64 bugs on the way...
Change-Id: I6a152b9c164d9f1a053622266e165428045362f3
|
| 4b537a851b686402513a7c4a4e60f5457bb8d7c1 |
|
01-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Quick compiler: More size checks, add TargetReg variants
Add variants for TargetReg for requesting specific register usage,
e.g., wide and ref. More register size checks.
With code adapted from https://android-review.googlesource.com/#/c/98605/.
Change-Id: I852d3be509d4dcd242c7283da702a2a76357278d
|
| baa7c88a34fdfd230a2a383c2e388945f4d907b6 |
|
30-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Rename A64_/A32_ register prefix to x/w.
A64/A32 look like architecture name, but they are all for arm64.
Use lower-case to name the registers defined in "ARM ARM" which can
also be directly used in assembly file.
Use upper-case to name the registers which are other aliases.
Change-Id: I0ac38ed75f977fdc362288b01179b84feaee5614
|
| 949cd973513f1ae29280fcde7953b0f7e70172a7 |
|
23-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Enable GenSpecialCase.
With the following fixes:
1. Map reference register to 64-bit argument register.
2. Set max_mapped_in_ to the index of last in. (Originally it was the
low part of the wide register)
Change-Id: If41de654a004a0561396e349d1f150517a72ab2f
|
| de68676b24f61a55adc0b22fe828f036a5925c41 |
|
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"
This reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d.
Breaks the build.
Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
|
| 3c12c512faf6837844d5465b23b9410889e5eb11 |
|
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
This reverts commit de68676b24f61a55adc0b22fe828f036a5925c41.
Fixes an API comment, and differentiates between inserting and appending.
Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
|
| 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d |
|
23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Split out more cases of Load/StoreRef, volatile as parameter
Splits out more cases of ref registers being loaded or stored. For
code clarity, adds volatile as a flag parameter instead of a separate
method.
On ARM64, continue cleanup. Add flags to print/fatal on size mismatches.
Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
|
| 5655e84e8d71697d8ef3ea901a0b853af42c559e |
|
18-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Implicit checks in the compiler are independent from Runtime
When cross-compiling, those flags are independent. This is an
initial CL that helps bypass fatal failures when cross-compiling,
as not all architectures support (and have turned on) implicit
checks.
The actual transport for the target architecture when it is
different from the runtime needs to be implemented in a follow-up
CL.
Bug: 15703710
Change-Id: Idc881a9a4abfd38643b862a491a5af9b8841f693
|
| 7cd26f355ba83be75b72ed628ed5ee84a3245c4f |
|
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Target-dependent stack overflow, less check elision
Refactor the separate stack overflow reserved sizes from thread.h
into instruction_set.h and make sure they're used in the compiler.
Refactor the decision on when to elide stack overflow checks:
especially with large interpreter stack frames, it is not a good
idea to elide checks when the frame size is even close to the
reserved size. Currently enforce checks when the frame size is
>= 2KB, but make sure that frame sizes 1KB and below will elide
the checks (number from experience).
Bug: 15728765
Change-Id: I016bfd3d8218170cbccbd123ed5e2203db167c06
|
| 47b31aa855379471c06735b738396fa76e7c1988 |
|
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Start implementation of OpRegRegRegExtend for ARM64
We need a sign-extending add for packed-switch and sparse-switch,
as the 32b values are signed offsets. This starts an implementation
that is sufficient for the use cases.
Change-Id: Ib5bae24b902077346a97d5e9e061533f9cdfcdb0
|
| 33ae5583bdd69847a7316ab38a8fa8ccd63093ef |
|
12-Jun-2014 |
buzbee <buzbee@google.com> |
Arm64 hard-float
Basic enabling of hard-float for Arm64. In future CLs we'll
consolidate the various targets - there is a lot of overlap.
Compilation remains turned off in this CL, but I expect
to enable a subset shortly. With compilation fully enabled
(including the EXPERIMENTAL opcodes with the exception of
REM and THROW), we get the following run-test results:
003-omnibus-opcode failures:
Classes.checkCast
Classes.arrayInstance
UnresTest2
Haven't gone deep, but these appear to be related to throw/catch and/or
stacktrace.
For REM, the generated code looks reasonable to me - my guess is that
we've got something wrong on the transition to the runtime. Haven't
looked deeper yet, though.
The bulk of the other failure also appear to be related to transitioning
to the runtime system, or handling try/catch.
run-test status:
Status with optimizations disabled, REM_FLOAT/DOUBLE and THROW disabled:
succeeded tests: 94
failed tests: 22
failed: 003-omnibus-opcodes
failed: 004-annotations
failed: 009-instanceof2
failed: 024-illegal-access
failed: 025-access-controller
failed: 031-class-attributes
failed: 044-proxy
failed: 045-reflect-array
failed: 046-reflect
failed: 058-enum-order
failed: 062-character-encodings
failed: 063-process-manager
failed: 064-field-access
failed: 068-classloader
failed: 071-dexfile
failed: 083-compiler-regressions
failed: 084-class-init
failed: 086-null-super
failed: 087-gc-after-link
failed: 100-reflect2
failed: 107-int-math2
failed: 201-built-in-exception-detail-messages
Change-Id: Ib66209285cad8998d77a14781de300af02a96b15
|
| f8ec48e8eff0050de1451fc8e9c3a71c26d5ce7e |
|
06-Jun-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
ART: arm64 explicit stack overflow checks
Implement only the explicit checks for the quick backend for arm64.
Implicit checks require fault handlers, which are currently unimplemented.
CMN + CMP have extended versions implemented for comparisons against the
stack pointer. More extended opcode implementations will need to follow.
Change-Id: I8db297aec73df818b20fe410297800c886701c76
|
| fd2e291297463a3d5bdb18adc2a1eacbe2759152 |
|
06-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fix MarkGCCard, enabling more MIR opcodes.
Fixing register usage in MarkGCCard. Also enabling more MIR opcodes in
the compiler filter.
Change-Id: I877250f8deaefc69115e861344ca47cc5ccea8ff
|
| 5acc8b0e23b12b481a9e97f84d084b79cd544319 |
|
05-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fix and enable sparse- and packed-switch.
Changed implementation of sparse- and packed-switch to use w and x
registers appropriately. Also added a couple of utilities to obtain a
w/s register corresponding to a given x/d register and viceversa.
Change-Id: I485a110f6e91b09227d9e2a0b8b14224a10bca90
|
| 576ca0cd692c0b6ae70e776de91015b8ff000a08 |
|
07-Jun-2014 |
Ian Rogers <irogers@google.com> |
Reduce header files including header files.
Main focus is getting heap.h out of runtime.h.
Change-Id: I8d13dce8512816db2820a27b24f5866cc871a04b
|
| a0cd2d701f29e0bc6275f1b13c0edfd4ec391879 |
|
01-Jun-2014 |
buzbee <buzbee@google.com> |
Quick compiler: reference cleanup
For 32-bit targets, object references are 32 bits wide both in
Dalvik virtual registers and in core physical registers. Because of
this, object references and non-floating point values were both
handled as if they had the same register class (kCoreReg).
However, for 64-bit systems, references are 32 bits in Dalvik vregs, but
64 bits in physical registers. Although the same underlying physical
core registers will still be used for object reference and non-float
values, different register class views will be used to represent them.
For example, an object reference in arm64 might be held in x3 at some
point, while the same underlying physical register, w3, would be used
to hold a 32-bit int.
This CL breaks apart the handling of object reference and non-float values
to allow the proper register class (or register view) to be used. A
new register class, kRefReg, is introduced which will map to a 32-bit
core register on 32-bit targets, and 64-bit core registers on 64-bit
targets. From this point on, object references should be allocated
registers in the kRefReg class rather than kCoreReg.
Change-Id: I6166827daa8a0ea3af326940d56a6a14874f5810
|
| ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
|
03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE
Merge ART from AOSP to lmp-preview-dev.
Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
|
| ed65c5e982705defdb597d94d1aa3f2997239c9b |
|
22-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable LONG_* and INT_* opcodes.
This patch fixes some of the issues with LONG and INT opcodes. The patch
has been tested and passes all the dalvik tests except for 018 and 107.
Change-Id: Idd1923ed935ee8236ab0c7e5fa969eaefeea8708
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
|
| bc6d197cdb02eeac0c98ec4ed37f530b003a4e7a |
|
13-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixes in A64 code generation.
- Disabled special method compilation, as it requires hard-float ABI,
- Disabled suspend checks, as runtime is not yet ready (e.g. trampolines
are not setting the suspend register, etc),
- Changing definition of zero register (the zero register has now 0x3f
as its register number),
- Fixing some issues with handling of cmp instructions in the assembler:
we now use the shift-register rather than the extended-register variant
of cmp and cmn,
- Partially fixing register setup (register sN is now mapped to dN),
- Fixing and completing implementation of register spills/unspills,
- Fixing LoadBaseDispBody() and StoreBaseDispBody().
Change-Id: Ia49ba48b6ca0f782380066345b7a198cb6c1dc1d
|
| c830430ed65497c2268649d8e78121364e31b184 |
|
15-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix quick compiler monitor implementation.
Also with some small fixes :
1. Enable some dex byte code to compile.
2. Copy the register definition from runtime.cc.
3. A quick fix for "cmp Wn, Wm" in the assembler.
4. Optimise GenMoveException a bit by using xzr.
5. Fix improper use of StoreValueWide() on 32-bit value in FlushIns().
6. Fix one debug assert in the assembler.
It can pass all cases in run-all-test, except 044 which also fails with
the interpreter.
Change-Id: I9cc0253f1039c78d5100640235ac33e884b02560
|
| b14329f90f725af0f67c45dfcb94933a426d63ce |
|
15-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix MonitorExit code on ARM
We do not emit barriers on non-SMP systems. But on ARM, we have
places that need to conditionally execute, which is done through
an IT instruction. The guide of said instruction thus changes
between SMP and non-SMP systems.
To cleanly approach this, change the API so that GenMemBarrier
returns whether it generated an instruction. ARM will have to
query the result and update any dependent IT.
Throw a build system error if TARGET_CPU_SMP is not set.
Fix runtime/Android.mk to work with new multilib host.
Bug: 14989275
Change-Id: I9e611b770e8a1cd4ca19367d7dae0573ec08dc61
|
| 2f244e9faccfcca68af3c5484c397a01a1c3a342 |
|
08-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add more ThreadOffset in Mir2Lir and backends
This duplicates all methods with ThreadOffset parameters, so that
both ThreadOffset<4> and ThreadOffset<8> can be handled. Dynamic
checks against the compilation unit's instruction set determine
which pointer size to use and therefore which methods to call.
Methods with unsupported pointer sizes should fatally fail, as
this indicates an issue during method selection.
Change-Id: Ifdb445b3732d3dc5e6a220db57374a55e91e1bf6
|
| e45fb9e7976c8462b94a58ad60b006b0eacec49f |
|
06-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Change arm64 backend to produce A64 code.
The arm backend clone is changed to produce A64 code. At the moment
this backend can only compile simple methods (both leaf and non-leaf).
Most of the work on the assembler (assembler_arm64.cc) has been done.
Some work on the LIR generation layer (functions such as OpRegRegImm
& friends) is still necessary. The register allocator still needs to
be adapted to the A64 instruction set (it is mostly unchanged from
the arm backend). Offsets for helpers in gen_invoke.cc still need to
be changed to work on 64-bit.
Change-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921
|
| 43ec8737d8356dbff0a90bee521fb0e73438da47 |
|
31-Mar-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Added arm64 quick backend as an arm clone.
Created a new directory arm64 under compiler/dex/quick which contains
a copy of the 32-bit arm backend. In following CLs, this code will
be replaced/modified to support Aarch64.
Change-Id: I06c468db8d588e339eecf4d7d85276d5e334a17a
|