4439596b00c91f565370bf0813cc2f9165093693 |
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13-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Hide unreachable basic blocks in the compiler Unreachable blocks are not handled uniformly in the optimization passes. Uniformly hide them to avoid initialization errors. Bug: 15573463 Change-Id: Ia9e89fa357d5672a6cd8389f28a06ff618fe60ee
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c9360ce1f1dabb4075b09dd6db49ee6d4212a6fc |
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05-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Use ScopedArenaVector instead of std::vector in SSA transformation. Change-Id: Ibf8471274f2d5e11fcc185044745434c3c82ed74
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ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE Merge ART from AOSP to lmp-preview-dev. Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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2469e60e6ff08c2a0b4cd1e209246c5d91027679 |
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07-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Setting up cleanup - Moved code around to actually have the clean-up code in a PassDriver format. This allows us to better control what is being called after an optimization It also allows the use of a centralized pass system for both optimizations and cleanup. Change-Id: I9d21e9bb9ee663739722f440d82adf04f73e380c Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Yixin Shou <yixin.shou@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
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4896d7b6fb75add25f2d6ba84346ac83d8ba9d51 |
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02-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Better SSA Allocation when recreating SSA The SSA calculation is not allocation friendly. This makes the SSARepresentation remember how much is allocated and not reallocate if SSA should be recalculated. Also added some allocation friendly code for the dominance code. Change-Id: Icd5586b7e2fefae8e1535975ab400b1ca95b500f Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
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d4750f202170a448119c1813a964574bfea0dded |
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24-May-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "ART: Better SSA Allocation when recreating SSA" Temporarily reverting until memory footprint cost of adding a vreg to ssa entrance map on every applicable MIR node can be assessed.. This reverts commit cb73fb35e5f7c575ed491c0c8e2d2b1a0a22ea2e. Change-Id: Ia9c03bfc5d365ad8d8b949e870f1e3bcda7f9a54
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a5b8fde2d2bc3167078694fad417fddfe442a6fd |
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23-May-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite BitVector index iterator. The BitVector::Iterator was not iterating over the bits but rather over indexes of the set bits. Therefore, we rename it to IndexIterator and provide a BitVector::Indexes() to get a container-style interface with begin() and end() for range based for loops. Also, simplify InsertPhiNodes where the tmp_blocks isn't needed since the phi_nodes and input_blocks cannot lose any blocks in subsequent iterations, so we can do the Union() directly in those bit vectors and we need to repeat the loop only if we have new input_blocks, rather than on phi_nodes change. And move the temporary bit vectors to scoped arena. Change-Id: I6cb87a2f60724eeef67c6aaa34b36ed5acde6d43
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3aa57730e2aec451bb836918d936c6862598d8d6 |
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17-Apr-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: MIR, SSARepresentation, and BasicBlock Additional API Adding the API calls to the MIR structure to help with higher level code. Some code has been added to BasicBlock as well for the removal. Some code has also been added to SSARepresentation. A constructor has been added to DecodedInstruction. Change-Id: Ie65948d53d83fd8250545c94c88b442a68d702c7 Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Yixin Shou <yixin.shou@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
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700a402244a1a423da4f3ba8032459f4b65fa18f |
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20-May-2014 |
Ian Rogers <irogers@google.com> |
Now we have a proper C++ library, use std::unique_ptr. Also remove the Android.libcxx.mk and other bits of stlport compatibility mechanics. Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
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cb73fb35e5f7c575ed491c0c8e2d2b1a0a22ea2e |
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02-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Better SSA Allocation when recreating SSA The SSA calculation is not allocation friendly. This makes the SSARepresentation remember how much is allocated and not reallocate if SSA should be recalculated. Also added some allocation friendly code for the dominance code. Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Change-Id: I6418b402434bd850b45771c75b7631b7b84a8f66
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5d47447e1d0cd18cf91a189f7a08e65c8d43ea5a |
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21-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Move saved SSA map to ScopedArenaAllocator to save memory. Bug: 13564922 Change-Id: I917d451267ca6fceb2f6b2ff33b872ee8c209893
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cdacac4a8196bdc620185079ec9e886329606f3d |
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13-Mar-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: API changes - Moved AppendMIR to BasicBlock - Moved PrependMIR to BasicBlock - Moved InsertMIRAfter to BasicBlock - Moved GetNextUnconditionalMir to BasicBlock Change-Id: Id261434e9f7d5d93f1bce0c87c9276a20077c483 Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
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bfea9c29e809e04bde4a46591fea64c5a7b922fb |
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17-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Class initialization check elimination. Also, move null check elimination temporaries to the ScopedArenaAllocator and reuse the same variables in the class initialization check elimination. Change-Id: Ic746f95427065506fa6016d4931e4cb8b34937af
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83cc7ae96d4176533dd0391a1591d321b0a87f4f |
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12-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Create a scoped arena allocator and use that for LVN. This saves more than 0.5s of boot.oat compilation time on Nexus 5. TODO: Move other stuff to the scoped allocator. This CL alone increases the peak memory allocation. By reusing the memory for other parts of the compilation we should reduce this overhead. Change-Id: Ifbc00aab4f3afd0000da818dfe68b96713824a08
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0e33643519b68a343a7466dcaba12b8567777cc3 |
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26-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Move arena_bit_vector.h/cc to compiler/utils. Also move MIR's BasicBlock related code from arena_bit_vector.h to bit_vector_block_iterator.cc. Change-Id: I85c224b387d31cf57a1ef1f1a36eaadf22f1c85d
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f7a82b422fa0428fb5678d91804610d56398b478 |
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11-Feb-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
Implements a BasicBlock iterator using the ArenaBitVector. Added the implementation of a BasicBlock iterator using the ArenaBitVector. This patch only adds the implementation of the iterator and does not yet use it everywhere it could be. Added one example in ssa_transformation.cc of its use. Change-Id: Ia85d58320c80c48a43609265ea5318a416c71f18 Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
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4e97c539408f47145526f0062c1c06df99146a73 |
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07-Jan-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
Added pass framework The patch adds a Middle-End pass system and normalizes the current passes into the pass framework. Passes have: - A start, work, and end functions. - A gate to determine to apply the pass. - Can provide a CFG dump folder. mir_dataflow.cc, mir_graph.cc, mir_optimization.cc, ssa_transformation.cc: - Changed due to moving code into bb_optimizations.cc. - Moved certain functions from private to public due to needed from the passes. pass.cc, pass.h: - Pass base class pass_driver.cc, pass_driver.h: - The pass driver implementation. frontend.cc: - Replace the function calls to the passes with the pass driver. Change-Id: I88cd82efbf6499df9e6c7f135d7e294dd724a079 Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
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0b1191cfece83f6f8d4101575a06555a2d13387a |
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28-Oct-2013 |
Bill Buzbee <buzbee@google.com> |
Revert "Revert "Null check elimination improvement"" This reverts commit 31aa97cfec5ee76b2f2496464e1b6f9e11d21a29. ..and thereby brings back change 380165, which was reverted because it was buggy. Three problems with the original CL: 1. The author ran the pre-submit tests, but used -j24 and failed to search the output for fail messages. 2. The new null check analysis pass uses an interative approach to identify whether a null check is needed. It is possible that the null-check-required state may oscillate, and a logic error caused it to stick in the "no check needed" state. 3. Our old nemesis Dalvik untyped constants, in which 0 values can be used both as object reference and non-object references. This CL conservatively treats all CONST definitions as potential object definitions for the purposes of null check elimination. Change-Id: I3c1744e44318276e42989502a314585e56ac57a0
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31aa97cfec5ee76b2f2496464e1b6f9e11d21a29 |
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26-Oct-2013 |
Ian Rogers <irogers@google.com> |
Revert "Null check elimination improvement" This reverts commit 4db179d1821a9e78819d5adc8057a72f49e2aed8. Change-Id: I059c15c85860c6c9f235b5dabaaef2edebaf1de2
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413e89f277ec6ba1bdf2040f5b5611f29a27a447 |
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22-Oct-2013 |
Brian Carlstrom <bdc@google.com> |
Refactor ArenaBitVector to create more general BitVector Change-Id: Ib26f2884de9ce7d620048bdf5ed6dec639622e41
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4db179d1821a9e78819d5adc8057a72f49e2aed8 |
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23-Oct-2013 |
buzbee <buzbee@google.com> |
Null check elimination improvement See b/10862777 Improves the null check elimination pass by tracking visibility of object definitions, rather than successful uses of object dereferences. For boot class path, increases static null check elimination success rate from 98.4% to 98.6%. Reduces size of boot.oat by ~300K bytes. Fixes loop nesting depth computation, which is used by register promotion, and tweaked the heuristics. Fixes a bug in verbose listing output in which a basic block id is directly dereferenced, rather than first being converted to a pointer. Change-Id: Id01c20b533cdb12ea8fc4be576438407d0a34cec
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0d82948094d9a198e01aa95f64012bdedd5b6fc9 |
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12-Oct-2013 |
buzbee <buzbee@google.com> |
64-bit prep Preparation for 64-bit roll. o Eliminated storing pointers in 32-bit int slots in LIR. o General size reductions of common structures to reduce impact of doubled pointer sizes: - BasicBlock struct was 72 bytes, now is 48. - MIR struct was 72 bytes, now is 64. - RegLocation was 12 bytes, now is 8. o Generally replaced uses of BasicBlock* pointers with 16-bit Ids. o Replaced several doubly-linked lists with singly-linked to save one stored pointer per node. o We had quite a few uses of uintptr_t's that were a holdover from the JIT (which used pointers to mapped dex & actual code cache addresses rather than trace-relative offsets). Replaced those with uint32_t's. o Clean up handling of embedded data for switch tables and array data. o Miscellaneous cleanup. I anticipate one or two additional CLs to reduce the size of MIR and LIR structs. Change-Id: I58e426d3f8e5efe64c1146b2823453da99451230
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74e256b8e442417d4ba2054c771c1e4f41062768 |
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04-Oct-2013 |
Sebastien Hertz <shertz@google.com> |
Add missing references. This mainly avoids implicit copies when extracting an object from a container. Change-Id: If4d0e6153e8c2b48345fde5bb546b4c65649fcf3
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56c717860df2d71d66fb77aa77f29dd346e559d3 |
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06-Sep-2013 |
buzbee <buzbee@google.com> |
Compile-time tuning Specialized the dataflow iterators and did a few other minor tweaks. Showing ~5% compile-time improvement in a single-threaded environment; less in multi-threaded (presumably because we're blocked by something else). Change-Id: I2e2ed58d881414b9fc97e04cd0623e188259afd2
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f6c4b3ba3825de1dbb3e747a68b809c6cc8eb4db |
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25-Aug-2013 |
Mathieu Chartier <mathieuc@google.com> |
New arena memory allocator. Before we were creating arenas for each method. The issue with doing this is that we needed to memset each memory allocation. This can be improved if you start out with arenas that contain all zeroed memory and recycle them for each method. When you give memory back to the arena pool you do a single memset to zero out all of the memory that you used. Always inlined the fast path of the allocation code. Removed the "zero" parameter since the new arena allocator always returns zeroed memory. Host dex2oat time on target oat apks (2 samples each). Before: real 1m11.958s user 4m34.020s sys 1m28.570s After: real 1m9.690s user 4m17.670s sys 1m23.960s Target device dex2oat samples (Mako, Thinkfree.apk): Without new arena allocator: 0m26.47s real 0m54.60s user 0m25.85s system 0m25.91s real 0m54.39s user 0m26.69s system 0m26.61s real 0m53.77s user 0m27.35s system 0m26.33s real 0m54.90s user 0m25.30s system 0m26.34s real 0m53.94s user 0m27.23s system With new arena allocator: 0m25.02s real 0m54.46s user 0m19.94s system 0m25.17s real 0m55.06s user 0m20.72s system 0m24.85s real 0m55.14s user 0m19.30s system 0m24.59s real 0m54.02s user 0m20.07s system 0m25.06s real 0m55.00s user 0m20.42s system Correctness of Thinkfree.apk.oat verified by diffing both of the oat files. Change-Id: I5ff7b85ffe86c57d3434294ca7a621a695bf57a9
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7934ac288acfb2552bb0b06ec1f61e5820d924a4 |
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26-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/comments issues Change-Id: Iae286862c85fb8fd8901eae1204cd6d271d69496
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df62950e7a32031b82360c407d46a37b94188fbb |
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18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/parens issues Change-Id: Ifc678d59a8bed24ffddde5a0e543620b17b0aba9
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0cd7ec2dcd8d7ba30bf3ca420b40dac52849876c |
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18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/blank_line issues Change-Id: Ice937e95e23dd622c17054551d4ae4cebd0ef8a2
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2ce745c06271d5223d57dbf08117b20d5b60694a |
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18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/braces issues Change-Id: Ide80939faf8e8690d8842dde8133902ac725ed1a
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7940e44f4517de5e2634a7e07d58d0fb26160513 |
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12-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Create separate Android.mk for main build targets The runtime, compiler, dex2oat, and oatdump now are in seperate trees to prevent dependency creep. They can now be individually built without rebuilding the rest of the art projects. dalvikvm and jdwpspy were already this way. Builds in the art directory should behave as before, building everything including tests. Change-Id: Ic6b1151e5ed0f823c3dd301afd2b13eb2d8feb81
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