History log of /external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
9f71b97c0cd7ff930164fafe8d6d5b5a9b871c86 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195456:
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r195456 | dsanders | 2013-11-22 05:22:52 -0800 (Fri, 22 Nov 2013) | 4 lines

Fix typo in a comment added in r195455.

Credit to Matheus Almeida for spotting it.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
876f8f123e9a52bf8e970f9e04b93700380b5dbf 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195444:
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r195444 | dsanders | 2013-11-22 03:24:50 -0800 (Fri, 22 Nov 2013) | 4 lines

[mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.

Fixes an instruction selection failure detected by llvm-stress.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
1184bebd31edac189a2c129ba93795b66cf4876d 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195364:
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r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines

[mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.

Mask == ~InvMask asserts if the width of Mask and InvMask differ.
The combine isn't valid (with two exceptions, see below) if the widths differ
so test for this before testing Mask == ~InvMask.

In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and
InvMask=~0, the combine is still valid. However, there are more appropriate
combines that could be used in these cases such as folding x & 0 to 0, or
x & ~0 to x.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
9148c5d5495a25e8479f6a58e57f7058da1b4871 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195343:
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r195343 | dsanders | 2013-11-21 03:40:14 -0800 (Thu, 21 Nov 2013) | 5 lines

[mips][msa/dsp] Only do DSP combines if DSP is enabled.

Fixes a crash (null pointer dereferenced) when MSA is enabled.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
cb85ded9980644fc6a3ff7d8e4dc56351adcc114 15-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of using a long-winded equivalent.

Now that getConstant(-1, MVT::v2i64) works correctly on MIPS32 we can use
SelectionDAG::getNOT() to produce the bitmask.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ea28aafa83fc2b6dd632041278c9a18e5a2b2b41 15-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 type

Summary:
When getConstant() is called for an expanded vector type, it is split into
multiple scalar constants which are then combined using appropriate build_vector
and bitcast operations.

In addition to the usual big/little endian differences, the case where the
element-order of the vector does not have the same endianness as the elements
themselves is also accounted for. For example, for v4i32 on big-endian MIPS,
the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is
<0123,4567,89AB,CDEF>.
Handling this case turns out to be a nop since getConstant() returns a splatted
vector (so reversing the element order doesn't change the value)

This fixes a number of cases in MIPS MSA where calling getConstant() during
operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF
into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger
differences between illegal and legal types such as legalizing v2i64 into v8i16.

lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling
getConstant() so this function has been updated in the same patch.

For the sake of transparency, the steps I've taken since the review are:
* Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed
that the MIPS tests were falsely passing because a polymorphic function was
not actually polymorphic in the reviewed patch.
* Fixed the tests that were now failing. This involved deleting the code to
handle the MIPS MSA element-order (which was previously doing an byte-order
swap instead of an element-order swap). This left
isVectorEltOrderLittleEndian() unused and it was deleted.
* Fixed build failures caused by rebasing beyond r194467-r194472. These build
failures involved the bset, bneg, and bclr instructions added in these commits
using lowerMSASplatImm() in a way that was no longer valid after this patch.
Some of these were fixed by calling SelectionDAG::getConstant() instead,
others were fixed by a new function getBuildVectorSplat() that provided the
removed functionality of lowerMSASplatImm() in a more sensible way.

Reviewers: bkramer

Reviewed By: bkramer

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
92e94a2ee44aefda151125fdb62bf9d5b54edfb2 12-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Fix buildbot failures caused by an unused variable when assertions are disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
bb47fd04c9b1616c0371eb2c488c5f0f665c25f8 12-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
aee7825762830536956b9e634fd7ffd59396984d 12-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
75ac8df380e2bad6b7e0798641b8b1805a393339 30-Oct-2013 Hans Wennborg <hans@hanshq.net> Add #include of raw_ostream.h to MipsSEISelLowering.cpp

Fixing this Windows build error:

..\lib\Target\Mips\MipsSEISelLowering.cpp(997) : error C2027: use of undefined type 'llvm::raw_ostream'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
c385709d8397ca1535481c04564b67d07c66c619 30-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)

Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).

These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.

bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
values is an uimm8, rather than when the condition is a uimm8 (which is
covered by bmnzi.b)

compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
is the same operation (see MSA.txt).

i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
distinguishable from bmnzi.b.

vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
MSA.txt).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
6ff1ef9931b50763a40e9ae8696cfab9e25cf4de 30-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)

This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
a7c3cac87118c3e409a7fc889090c5ffe242985e 30-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECT

(or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b).
where $mask is a constant splat. This allows bitwise operations to make use
of bsel.

It's also a stepping stone towards matching bins[lr], and bins[lr]i from
normal IR.

Two sets of similar tests have been added in this commit. The bsel_* functions
test the case where binsri cannot be used. The binsr_*_i functions will
start to use the binsri instruction in the next commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
aed9334acfdd8fa7548dc540fe865a5a641cb208 30-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips] MipsSETargetLowering now reports DAGCombiner changes when using -debug-only=mips-isel

No test since -debug output is intended for developers and not end-users.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
57cd3bc4064bd71eb6572d3cba5e23471ab25863 30-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics)

splat.d is implemented but this subtest is currently disabled. This is because
it is difficult to match the appropriate IR on MIPS32. There is a patch under
review that should help with this so I hope to enable the subtest soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
09c7f4026afa46ca7ca67d47179013a340a5e944 23-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
52244da7f2b3def646900520668b859343b84a33 17-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added lsa instruction



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
db8a16252b9d29bd7a3442d5c3bad0398dd85908 17-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Removed ldx.[bhwd] and stx.[bhwd].

These were present in a previous version of the MSA spec but are not
present in the published version. There is no hardware that uses these
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
62e87cb2415b305ca9b888a2338a6af59e74005d 15-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for build_vector for v4f32 and v2f64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
adb1297d49dd345821d7aa91057a0b22e6209a16 15-Oct-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename isel nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
b6ed641c719e3f370b0e9120823b349993c3494b 15-Oct-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Delete unnecessary code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
a6e253ddd0f757101fe97105d60a1e098ca5f33c 11-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
4fa2c32220405ac32838e45d91392a83fae70bb0 11-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
c879eabcc25c4099a50939ed0bca86471201b183 11-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
b9bee10b2158253e222eb8dd5f0ae0452740ace3 11-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
243702b95a471ffb7d2374dfad3d7f8b11bee7e7 07-Oct-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo.

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
7f768e03684514ea9ebabed93694521f9ffab28f 01-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
4d835f1cbe5d8c5f6cea4040bea9b180927a1c05 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Implemented insert.d intrinsic.

This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
9f30d43122dce961ae1625c2c429bf74bf292324 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Implemented fill.d intrinsic.

This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
e8eafdb67685d4f5d52ab0dce2339c37e39cdc44 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Implemented copy_[us].d intrinsic.

This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
37469a132988eb0c888f6a8a205b2aca510e14f8 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.

For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
b4691b495d867a863aa12de57d45bc6a93e4df78 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64

For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
c8a1fa77a73e7c885035421712ceba951f9024cb 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)

Updated some of the vshf since they (correctly) emit splati's now



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ba616ef0236a11239a0a2c174627dcdc4ab63434 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Tidy up

lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr,
and lowerMSAUnaryIntr were trivially small functions. Inlined them into
their callers.

lowerMSASplat now takes its callers SDLoc instead of making a new one.

No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
d2a31a124f3bebbdfc4d886afe33a116893aa689 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
86f309b4d1426b54f23d6ba53d3f5c8a1aa3985b 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added missing check in performSRACombine

Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
3706eda52c4565016959902a3f5aaf7271516286 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
f515964d36834ec918fe831029bc72ccdcec34d3 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
93d995719e2459a6e9ccdb2c93a8ede8fa88c899 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
7e0df9aa2966d0462e34511524a4958e226b74ee 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.

Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp

This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).

There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.

compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ad16ddeb8e07a259d17ef203c9f443f816f6ae7b 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations.

The resulting code is the same length, but doesnt cause memory traffic or latency.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
421dcc59212a73b82141caa2c94ea340a7b34deb 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics)

This covers the case where fmax_a can be used to implement ISD::FABS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
c998bc98439e21bc8c3838d6353475eacfb8494e 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
89d13c1b380218d381be035eb5e4d83dcbc391cc 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
38a10ff063971c2f7f7384cceba3253bca32e27a 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics)

This required correcting the definition of the bsel and bseli intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ae1fb8fc19dcfd2f0e33a36f40d687b08dcc9a6b 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics)

MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
cfb1e1703130809043a7b020b4cdfa04b59fa8ec 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
e0187e51a17f2081d6a72a57e0fbba8ce38d9410 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
9a1aaeb012e593fba977015c5d8b6b1aa41a908c 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)

Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
operation and implemented the DAG combines necessary to fold sign/zero
extends into the extract.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
a399d698a84ffd22c7d1f121c24cbc147c6f4e06 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
915432ca1306d10453c9eb523cbc4b257642f62a 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
4e812c1f4a723f0fa0e8714610e08be593c759b8 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
57ebcb28a63d8646fd8fd69cfd9e6766066e342f 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> Partially revert r191192: Fix -Wunused-variable error when assertions are disabled and -Werror is in use.

An unrelated change crept in because 'svn revert' isn't recursive by default.
The unrelated changes have been reverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
912fde24089094a953dfb802c69f4b0d83c7925c 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> Fix -Wunused-variable error when assertions are disabled and -Werror is in use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
da521cc1cc733ee1c27b00e4c0e365c8b702e2e0 23-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)

Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).

Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
f2eb1e4286bf397d60a37e6f288ac81e644a3258 11-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
2ac128292150c7ebb469d137877eaa3c6d26a8bb 11-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ece929d6234b73ea248b7a5e89f915613ad748ea 11-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
68831cbd417b7e4c47b565038a4fe9a1269d5d50 11-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)

The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ddfbd5805478cf108156bb0159b7495d2b236f7e 11-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Separate the configuration of int/float vector types since they will diverge soon

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
2dd3afc5e600b4585e4c2cd08f9a35fd1cf0df61 09-Sep-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] When double precision loads and stores are split into two i32 loads and
stores, make sure the load or store that accesses the higher half does not have
an alignment that is larger than the offset from the original address.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 07-Sep-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
c673f9c6fecb0f828845ada7ea5458f66f896283 30-Aug-2013 Reed Kotler <rkotler@mips.com> Fix a problem with dual mips16/mips32 mode. When the underlying processor
has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
3c380d5e28f86984b147fcd424736c498773f37e 28-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v

These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
2fd3e67dc6438cee5e32e0d7d7d42891df7edd96 28-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added load/store intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
c73488a38ecb26340604706003e84cff7bd48ddf 23-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Split MSA128 regset into size-specific sets containing the same registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ad341d48f0fc131d1c31a0c824736e70c34e0476 21-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.

Test case will be added when support for mfhc1 and mthc1 is added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
e2a9376b1bd2204ea6f56a35b762e28e0ef4e35a 15-Aug-2013 Jack Carter <jack.carter@imgtec.com> [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)

Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
7d6355226c60cd5ac7e1c916b17fee1a2b30a871 14-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename DSPRegs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
3f70e908c3d9de7acea462719ebf36dca1560f9c 13-Aug-2013 Jack Carter <jack.carter@imgtec.com> [Mips][msa] Added initial MSA support.

* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
1858786285139b87961d9ca08de91dcd59364afb 07-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename register classes CPURegs and CPU64Regs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
5e795097b081390a7172beeffad7e65c5150214f 02-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Expand vector truncating stores and extending loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
9a308df027b60057d0fe3ba7a3ee9648f6677879 26-Jun-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Improve code generation for constant multiplication using shifts, adds and
subs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
ac6d9bec671252dd1e596fa71180ff6b39d06b5d 25-May-2013 Andrew Trick <atrick@apple.com> Track IR ordering of SelectionDAG nodes 2/4.

Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
cd6c57917db22a3913a2cdbadfa79fed3547bdec 01-May-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Instruction selection patterns for DSP-ASE vector select and compare
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
e311b00a912b9f1a1e8fc1d28b2e58a015d250ec 23-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Compare splat value with element size instead of calling isUIntN.

No intended changes in functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
b109ea8245e2948ea6d06a6e6cbab7c6788da211 22-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> 80 columns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
d597263b9442923bacc24f26a8510fb69f992864 22-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] In performDSPShiftCombine, check that all elements in the vector are
shifted by the same amount and the shift amount is smaller than the element
size.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
6265d5c91a18b2fb6499eb581c488315880c044d 20-Apr-2013 Tim Northover <Tim.Northover@arm.com> Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
97a62bf2a4a2d141aad8af3531c3b69934f134c1 20-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Instruction selection patterns for DSP-ASE vector shifts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
4e0980af2e9eda80cbd82895167e650d83ffe087 13-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and
lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
3d60241c3e86973be281660bc5971c3a46cfdc47 13-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Reapply r179420 and r179421.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
d35d5bdfc41ff401f938e49e844d707462405428 13-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> Revert r179420 and r179421.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
9367b8d4f254d9e5cccb15334cc1a969c5be0d31 13-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
fc82e4db13b46b2f14f5895d2a0b33524d55d06a 11-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selects
multiply instructions in MipsSEDAGToDAGISel.

This patch was supposed to be part of r178403.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
a430cb613b6e93c05f128b04323c57acfd08686d 09-Apr-2013 Reed Kotler <rkotler@mips.com> This patch enables llvm to switch between compiling for mips32/mips64
and mips16 on a per function basis.

Because this patch is somewhat involved I have provide an overview of the
key pieces of it.

The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.

Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info,
instruction info and instruction selection classes.

Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).

When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.

When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.

In addition, MipsAsmPrinter needs to be reset on a function basis.

The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
7e287bfb58e63c4e1068e49e8e1b714f3b9703bc 30-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> Remove unused variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
d593a77b4cf3b81cd657e351e47cad25ee037ce1 30-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.

We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
f5926fd844a84adcf1ae4f193146f2877997b82c 30-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.

The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
042b79625f315da6378d06b5480b15894d6b06b1 14-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix filename in comment and delete unnecessary lines of code.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
5ac065a79767cc112eba63136183b7103765d0d3 13-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for
mips16 and MipsSETargetLowering is for mips32/64.

No functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.cpp